1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
52 #include "lib/eq.h"
53 #include "fs_core.h"
54 #include "lib/mpfs.h"
55 #include "eswitch.h"
56 #include "devlink.h"
57 #include "fw_reset.h"
58 #include "lib/mlx5.h"
59 #include "lib/tout.h"
60 #include "fpga/core.h"
61 #include "en_accel/ipsec.h"
62 #include "lib/clock.h"
63 #include "lib/vxlan.h"
64 #include "lib/geneve.h"
65 #include "lib/devcom.h"
66 #include "lib/pci_vsc.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69 #include "lib/hv_vhca.h"
70 #include "diag/rsc_dump.h"
71 #include "sf/vhca_event.h"
72 #include "sf/dev/dev.h"
73 #include "sf/sf.h"
74 #include "mlx5_irq.h"
75 #include "hwmon.h"
76 #include "lag/lag.h"
77
78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
79 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 unsigned int mlx5_core_debug_mask;
83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
92 static DEFINE_IDA(sw_vhca_ida);
93
94 enum {
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 };
98
99 #define LOG_MAX_SUPPORTED_QPS 0xff
100
101 static struct mlx5_profile profile[] = {
102 [0] = {
103 .mask = 0,
104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
110
111 },
112 [2] = {
113 .mask = MLX5_PROF_MASK_QP_SIZE |
114 MLX5_PROF_MASK_MR_CACHE,
115 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
117 .mr_cache[0] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[1] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[2] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[3] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[4] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[5] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[6] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[7] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[8] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[9] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[10] = {
158 .size = 500,
159 .limit = 250
160 },
161 .mr_cache[11] = {
162 .size = 500,
163 .limit = 250
164 },
165 .mr_cache[12] = {
166 .size = 64,
167 .limit = 32
168 },
169 .mr_cache[13] = {
170 .size = 32,
171 .limit = 16
172 },
173 .mr_cache[14] = {
174 .size = 16,
175 .limit = 8
176 },
177 .mr_cache[15] = {
178 .size = 8,
179 .limit = 4
180 },
181 },
182 [3] = {
183 .mask = MLX5_PROF_MASK_QP_SIZE,
184 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
185 .num_cmd_caches = 0,
186 },
187 };
188
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili,const char * init_state)189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 u32 warn_time_mili, const char *init_state)
191 {
192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 u32 fw_initializing;
195
196 do {
197 fw_initializing = ioread32be(&dev->iseg->initializing);
198 if (!(fw_initializing >> 31))
199 break;
200 if (time_after(jiffies, end)) {
201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n",
202 max_wait_mili, init_state);
203 return -ETIMEDOUT;
204 }
205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n",
207 init_state);
208 return -ENODEV;
209 }
210 if (warn_time_mili && time_after(jiffies, warn)) {
211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n",
212 init_state, jiffies_to_msecs(end - warn) / 1000,
213 fw_initializing);
214 warn = jiffies + msecs_to_jiffies(warn_time_mili);
215 }
216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
217 } while (true);
218
219 return 0;
220 }
221
mlx5_set_driver_version(struct mlx5_core_dev * dev)222 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
223 {
224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
225 driver_version);
226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
227 char *string;
228
229 if (!MLX5_CAP_GEN(dev, driver_version))
230 return;
231
232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
233
234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u",
235 KBUILD_MODNAME, LINUX_VERSION_MAJOR,
236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
260 return err;
261 }
262
mlx5_pci_enable_device(struct mlx5_core_dev * dev)263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
264 {
265 struct pci_dev *pdev = dev->pdev;
266 int err = 0;
267
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
271 if (!err)
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
273 }
274 mutex_unlock(&dev->pci_status_mutex);
275
276 return err;
277 }
278
mlx5_pci_disable_device(struct mlx5_core_dev * dev)279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
287 }
288 mutex_unlock(&dev->pci_status_mutex);
289 }
290
request_bar(struct pci_dev * pdev)291 static int request_bar(struct pci_dev *pdev)
292 {
293 int err = 0;
294
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
297 return -ENODEV;
298 }
299
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
301 if (err)
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
303
304 return err;
305 }
306
release_bar(struct pci_dev * pdev)307 static void release_bar(struct pci_dev *pdev)
308 {
309 pci_release_regions(pdev);
310 }
311
312 struct mlx5_reg_host_endianness {
313 u8 he;
314 u8 rsvd[15];
315 };
316
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
318 {
319 switch (size) {
320 case 128:
321 return 0;
322 case 256:
323 return 1;
324 case 512:
325 return 2;
326 case 1024:
327 return 3;
328 case 2048:
329 return 4;
330 case 4096:
331 return 5;
332 default:
333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
334 return 0;
335 }
336 }
337
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)338 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
339 {
340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
341 dev->mlx5e_res.uplink_netdev = netdev;
342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
343 netdev);
344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
345 }
346
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)347 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
348 {
349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
351 dev->mlx5e_res.uplink_netdev);
352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
353 }
354 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
355
mlx5_core_mp_event_replay(struct mlx5_core_dev * dev,u32 event,void * data)356 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data)
357 {
358 mlx5_blocking_notifier_call_chain(dev, event, data);
359 }
360 EXPORT_SYMBOL(mlx5_core_mp_event_replay);
361
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)362 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
363 enum mlx5_cap_mode cap_mode)
364 {
365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
367 void *out, *hca_caps;
368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369 int err;
370
371 if (WARN_ON(!dev->caps.hca[cap_type]))
372 /* this cap_type must be added to mlx5_hca_caps_alloc() */
373 return -EINVAL;
374
375 memset(in, 0, sizeof(in));
376 out = kzalloc(out_sz, GFP_KERNEL);
377 if (!out)
378 return -ENOMEM;
379
380 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
381 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
382 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
383 if (err) {
384 mlx5_core_warn(dev,
385 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
386 cap_type, cap_mode, err);
387 goto query_ex;
388 }
389
390 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
391
392 switch (cap_mode) {
393 case HCA_CAP_OPMOD_GET_MAX:
394 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
395 MLX5_UN_SZ_BYTES(hca_cap_union));
396 break;
397 case HCA_CAP_OPMOD_GET_CUR:
398 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
399 MLX5_UN_SZ_BYTES(hca_cap_union));
400 break;
401 default:
402 mlx5_core_warn(dev,
403 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
404 cap_type, cap_mode);
405 err = -EINVAL;
406 break;
407 }
408 query_ex:
409 kfree(out);
410 return err;
411 }
412
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)413 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
414 {
415 int ret;
416
417 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
418 if (ret)
419 return ret;
420 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
421 }
422
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)423 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
424 {
425 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
426 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
427 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
428 }
429
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)430 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
431 {
432 void *set_hca_cap;
433 int req_endianness;
434 int err;
435
436 if (!MLX5_CAP_GEN(dev, atomic))
437 return 0;
438
439 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
440 if (err)
441 return err;
442
443 req_endianness =
444 MLX5_CAP_ATOMIC(dev,
445 supported_atomic_req_8B_endianness_mode_1);
446
447 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
448 return 0;
449
450 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
451
452 /* Set requestor to host endianness */
453 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
454 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
455
456 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
457 }
458
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)459 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
460 {
461 bool do_set = false, mem_page_fault = false;
462 void *set_hca_cap;
463 int err;
464
465 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
466 !MLX5_CAP_GEN(dev, pg))
467 return 0;
468
469 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
470 if (err)
471 return err;
472
473 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
474 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
475 MLX5_ST_SZ_BYTES(odp_cap));
476
477 /* For best performance, enable memory scheme ODP only when
478 * it has page prefetch enabled.
479 */
480 if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) &&
481 MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) {
482 mem_page_fault = true;
483 do_set = true;
484 MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault);
485 goto set;
486 }
487
488 #define ODP_CAP_SET_MAX(dev, field) \
489 do { \
490 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
491 if (_res) { \
492 do_set = true; \
493 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
494 } \
495 } while (0)
496
497 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.ud_odp_caps.srq_receive);
498 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.rc_odp_caps.srq_receive);
499 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.srq_receive);
500 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.send);
501 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.receive);
502 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.write);
503 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.read);
504 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.atomic);
505 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.srq_receive);
506 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.send);
507 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.receive);
508 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.write);
509 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read);
510 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic);
511
512 set:
513 if (do_set)
514 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
515
516 mlx5_core_dbg(dev, "Using ODP %s scheme\n",
517 mem_page_fault ? "memory" : "transport");
518 return err;
519 }
520
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)521 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
522 {
523 struct devlink *devlink = priv_to_devlink(dev);
524 union devlink_param_value val;
525 int err;
526
527 err = devl_param_driverinit_value_get(devlink,
528 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
529 &val);
530 if (!err)
531 return val.vu32;
532 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
533 return err;
534 }
535
mlx5_is_roce_on(struct mlx5_core_dev * dev)536 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
537 {
538 struct devlink *devlink = priv_to_devlink(dev);
539 union devlink_param_value val;
540 int err;
541
542 err = devl_param_driverinit_value_get(devlink,
543 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
544 &val);
545
546 if (!err)
547 return val.vbool;
548
549 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
550 return MLX5_CAP_GEN(dev, roce);
551 }
552 EXPORT_SYMBOL(mlx5_is_roce_on);
553
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)554 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
555 {
556 bool do_set = false;
557 void *set_hca_cap;
558 int err;
559
560 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
561 return 0;
562
563 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
564 if (err)
565 return err;
566
567 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
568 capability);
569 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
570 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
571
572 if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) &&
573 dev->priv.sw_vhca_id > 0) {
574 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
575 do_set = true;
576 }
577
578 if (MLX5_CAP_GEN_2_MAX(dev, lag_per_mp_group)) {
579 MLX5_SET(cmd_hca_cap_2, set_hca_cap, lag_per_mp_group, 1);
580 do_set = true;
581 }
582
583 /* some FW versions that support querying MLX5_CAP_GENERAL_2
584 * capabilities but don't support setting them.
585 * Skip unnecessary update to hca_cap_2 when no changes were introduced
586 */
587 return do_set ? set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2) : 0;
588 }
589
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)590 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
591 {
592 struct mlx5_profile *prof = &dev->profile;
593 void *set_hca_cap;
594 int max_uc_list;
595 int err;
596
597 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
598 if (err)
599 return err;
600
601 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
602 capability);
603 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
604 MLX5_ST_SZ_BYTES(cmd_hca_cap));
605
606 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
607 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
608 128);
609 /* we limit the size of the pkey table to 128 entries for now */
610 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
611 to_fw_pkey_sz(dev, 128));
612
613 /* Check log_max_qp from HCA caps to set in current profile */
614 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
615 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
616 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
617 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
618 prof->log_max_qp,
619 MLX5_CAP_GEN_MAX(dev, log_max_qp));
620 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
621 }
622 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
623 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
624 prof->log_max_qp);
625
626 /* disable cmdif checksum */
627 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
628
629 /* Enable 4K UAR only when HCA supports it and page size is bigger
630 * than 4K.
631 */
632 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
633 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
634
635 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
636
637 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
638 MLX5_SET(cmd_hca_cap,
639 set_hca_cap,
640 cache_line_128byte,
641 cache_line_size() >= 128 ? 1 : 0);
642
643 if (MLX5_CAP_GEN_MAX(dev, dct))
644 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
645
646 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
647 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
648 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload))
649 MLX5_SET(cmd_hca_cap, set_hca_cap,
650 pci_sync_for_fw_update_with_driver_unload, 1);
651 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method))
652 MLX5_SET(cmd_hca_cap, set_hca_cap,
653 pcie_reset_using_hotreset_method, 1);
654
655 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
656 MLX5_SET(cmd_hca_cap,
657 set_hca_cap,
658 num_vhca_ports,
659 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
660
661 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
662 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
663
664 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
665 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
666
667 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
668
669 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
670 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
671 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
672
673 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
674 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
675 mlx5_is_roce_on(dev));
676
677 max_uc_list = max_uc_list_get_devlink_param(dev);
678 if (max_uc_list > 0)
679 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
680 ilog2(max_uc_list));
681
682 /* enable absolute native port num */
683 if (MLX5_CAP_GEN_MAX(dev, abs_native_port_num))
684 MLX5_SET(cmd_hca_cap, set_hca_cap, abs_native_port_num, 1);
685
686 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
687 }
688
689 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
690 * boot process.
691 * In case RoCE cap is writable in FW and user/devlink requested to change the
692 * cap, we are yet to query the final state of the above cap.
693 * Hence, the need for this function.
694 *
695 * Returns
696 * True:
697 * 1) RoCE cap is read only in FW and already disabled
698 * OR:
699 * 2) RoCE cap is writable in FW and user/devlink requested it off.
700 *
701 * In any other case, return False.
702 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)703 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
704 {
705 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
706 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
707 }
708
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)709 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
710 {
711 void *set_hca_cap;
712 int err;
713
714 if (is_roce_fw_disabled(dev))
715 return 0;
716
717 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
718 if (err)
719 return err;
720
721 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
722 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
723 return 0;
724
725 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
726 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
727 MLX5_ST_SZ_BYTES(roce_cap));
728 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
729
730 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default))
731 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
732
733 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
734 return err;
735 }
736
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)737 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
738 void *set_ctx)
739 {
740 void *set_hca_cap;
741 int err;
742
743 if (!MLX5_CAP_GEN(dev, port_selection_cap))
744 return 0;
745
746 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
747 if (err)
748 return err;
749
750 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
751 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
752 return 0;
753
754 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
755 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
756 MLX5_ST_SZ_BYTES(port_selection_cap));
757 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
758
759 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
760
761 return err;
762 }
763
set_hca_cap(struct mlx5_core_dev * dev)764 static int set_hca_cap(struct mlx5_core_dev *dev)
765 {
766 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
767 void *set_ctx;
768 int err;
769
770 set_ctx = kzalloc(set_sz, GFP_KERNEL);
771 if (!set_ctx)
772 return -ENOMEM;
773
774 err = handle_hca_cap(dev, set_ctx);
775 if (err) {
776 mlx5_core_err(dev, "handle_hca_cap failed\n");
777 goto out;
778 }
779
780 memset(set_ctx, 0, set_sz);
781 err = handle_hca_cap_atomic(dev, set_ctx);
782 if (err) {
783 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
784 goto out;
785 }
786
787 memset(set_ctx, 0, set_sz);
788 err = handle_hca_cap_odp(dev, set_ctx);
789 if (err) {
790 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
791 goto out;
792 }
793
794 memset(set_ctx, 0, set_sz);
795 err = handle_hca_cap_roce(dev, set_ctx);
796 if (err) {
797 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
798 goto out;
799 }
800
801 memset(set_ctx, 0, set_sz);
802 err = handle_hca_cap_2(dev, set_ctx);
803 if (err) {
804 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
805 goto out;
806 }
807
808 memset(set_ctx, 0, set_sz);
809 err = handle_hca_cap_port_selection(dev, set_ctx);
810 if (err) {
811 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
812 goto out;
813 }
814
815 out:
816 kfree(set_ctx);
817 return err;
818 }
819
set_hca_ctrl(struct mlx5_core_dev * dev)820 static int set_hca_ctrl(struct mlx5_core_dev *dev)
821 {
822 struct mlx5_reg_host_endianness he_in;
823 struct mlx5_reg_host_endianness he_out;
824 int err;
825
826 if (!mlx5_core_is_pf(dev))
827 return 0;
828
829 memset(&he_in, 0, sizeof(he_in));
830 he_in.he = MLX5_SET_HOST_ENDIANNESS;
831 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
832 &he_out, sizeof(he_out),
833 MLX5_REG_HOST_ENDIANNESS, 0, 1);
834 return err;
835 }
836
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)837 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
838 {
839 int ret = 0;
840
841 /* Disable local_lb by default */
842 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
843 ret = mlx5_nic_vport_update_local_lb(dev, false);
844
845 return ret;
846 }
847
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)848 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
849 {
850 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
851
852 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
853 MLX5_SET(enable_hca_in, in, function_id, func_id);
854 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
855 dev->caps.embedded_cpu);
856 return mlx5_cmd_exec_in(dev, enable_hca, in);
857 }
858
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)859 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
860 {
861 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
862
863 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
864 MLX5_SET(disable_hca_in, in, function_id, func_id);
865 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
866 dev->caps.embedded_cpu);
867 return mlx5_cmd_exec_in(dev, disable_hca, in);
868 }
869
mlx5_core_set_issi(struct mlx5_core_dev * dev)870 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
871 {
872 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
873 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
874 u32 sup_issi;
875 int err;
876
877 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
878 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
879 if (err) {
880 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
881 u8 status = MLX5_GET(query_issi_out, query_out, status);
882
883 if (!status || syndrome == MLX5_DRIVER_SYND) {
884 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
885 err, status, syndrome);
886 return err;
887 }
888
889 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
890 dev->issi = 0;
891 return 0;
892 }
893
894 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
895
896 if (sup_issi & (1 << 1)) {
897 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
898
899 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
900 MLX5_SET(set_issi_in, set_in, current_issi, 1);
901 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
902 if (err) {
903 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
904 err);
905 return err;
906 }
907
908 dev->issi = 1;
909
910 return 0;
911 } else if (sup_issi & (1 << 0) || !sup_issi) {
912 return 0;
913 }
914
915 return -EOPNOTSUPP;
916 }
917
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)918 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
919 const struct pci_device_id *id)
920 {
921 int err = 0;
922
923 mutex_init(&dev->pci_status_mutex);
924 pci_set_drvdata(dev->pdev, dev);
925
926 dev->bar_addr = pci_resource_start(pdev, 0);
927
928 err = mlx5_pci_enable_device(dev);
929 if (err) {
930 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
931 return err;
932 }
933
934 err = request_bar(pdev);
935 if (err) {
936 mlx5_core_err(dev, "error requesting BARs, aborting\n");
937 goto err_disable;
938 }
939
940 pci_set_master(pdev);
941
942 err = set_dma_caps(pdev);
943 if (err) {
944 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
945 goto err_clr_master;
946 }
947
948 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
949 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
950 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
951 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
952
953 dev->iseg_base = dev->bar_addr;
954 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
955 if (!dev->iseg) {
956 err = -ENOMEM;
957 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
958 goto err_clr_master;
959 }
960
961 mlx5_pci_vsc_init(dev);
962
963 pci_enable_ptm(pdev, NULL);
964
965 return 0;
966
967 err_clr_master:
968 release_bar(dev->pdev);
969 err_disable:
970 mlx5_pci_disable_device(dev);
971 return err;
972 }
973
mlx5_pci_close(struct mlx5_core_dev * dev)974 static void mlx5_pci_close(struct mlx5_core_dev *dev)
975 {
976 /* health work might still be active, and it needs pci bar in
977 * order to know the NIC state. Therefore, drain the health WQ
978 * before removing the pci bars
979 */
980 mlx5_drain_health_wq(dev);
981 pci_disable_ptm(dev->pdev);
982 iounmap(dev->iseg);
983 release_bar(dev->pdev);
984 mlx5_pci_disable_device(dev);
985 }
986
mlx5_init_once(struct mlx5_core_dev * dev)987 static int mlx5_init_once(struct mlx5_core_dev *dev)
988 {
989 int err;
990
991 dev->priv.devc = mlx5_devcom_register_device(dev);
992 if (!dev->priv.devc)
993 mlx5_core_warn(dev, "failed to register devcom device\n");
994
995 err = mlx5_query_board_id(dev);
996 if (err) {
997 mlx5_core_err(dev, "query board id failed\n");
998 goto err_devcom;
999 }
1000
1001 err = mlx5_irq_table_init(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "failed to initialize irq table\n");
1004 goto err_devcom;
1005 }
1006
1007 err = mlx5_eq_table_init(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "failed to initialize eq\n");
1010 goto err_irq_cleanup;
1011 }
1012
1013 err = mlx5_fw_reset_init(dev);
1014 if (err) {
1015 mlx5_core_err(dev, "failed to initialize fw reset events\n");
1016 goto err_eq_cleanup;
1017 }
1018
1019 mlx5_cq_debugfs_init(dev);
1020
1021 mlx5_init_reserved_gids(dev);
1022
1023 err = mlx5_init_clock(dev);
1024 if (err) {
1025 mlx5_core_err(dev, "failed to initialize hardware clock\n");
1026 goto err_tables_cleanup;
1027 }
1028
1029 dev->vxlan = mlx5_vxlan_create(dev);
1030 dev->geneve = mlx5_geneve_create(dev);
1031
1032 err = mlx5_init_rl_table(dev);
1033 if (err) {
1034 mlx5_core_err(dev, "Failed to init rate limiting\n");
1035 goto err_clock_cleanup;
1036 }
1037
1038 err = mlx5_mpfs_init(dev);
1039 if (err) {
1040 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1041 goto err_rl_cleanup;
1042 }
1043
1044 err = mlx5_sriov_init(dev);
1045 if (err) {
1046 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1047 goto err_mpfs_cleanup;
1048 }
1049
1050 err = mlx5_eswitch_init(dev);
1051 if (err) {
1052 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1053 goto err_sriov_cleanup;
1054 }
1055
1056 err = mlx5_fpga_init(dev);
1057 if (err) {
1058 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1059 goto err_eswitch_cleanup;
1060 }
1061
1062 err = mlx5_vhca_event_init(dev);
1063 if (err) {
1064 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1065 goto err_fpga_cleanup;
1066 }
1067
1068 err = mlx5_sf_hw_table_init(dev);
1069 if (err) {
1070 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1071 goto err_sf_hw_table_cleanup;
1072 }
1073
1074 err = mlx5_sf_table_init(dev);
1075 if (err) {
1076 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1077 goto err_sf_table_cleanup;
1078 }
1079
1080 err = mlx5_fs_core_alloc(dev);
1081 if (err) {
1082 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1083 goto err_fs;
1084 }
1085
1086 dev->dm = mlx5_dm_create(dev);
1087 dev->st = mlx5_st_create(dev);
1088 dev->tracer = mlx5_fw_tracer_create(dev);
1089 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1090 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1091
1092 return 0;
1093
1094 err_fs:
1095 mlx5_sf_table_cleanup(dev);
1096 err_sf_table_cleanup:
1097 mlx5_sf_hw_table_cleanup(dev);
1098 err_sf_hw_table_cleanup:
1099 mlx5_vhca_event_cleanup(dev);
1100 err_fpga_cleanup:
1101 mlx5_fpga_cleanup(dev);
1102 err_eswitch_cleanup:
1103 mlx5_eswitch_cleanup(dev->priv.eswitch);
1104 err_sriov_cleanup:
1105 mlx5_sriov_cleanup(dev);
1106 err_mpfs_cleanup:
1107 mlx5_mpfs_cleanup(dev);
1108 err_rl_cleanup:
1109 mlx5_cleanup_rl_table(dev);
1110 err_clock_cleanup:
1111 mlx5_geneve_destroy(dev->geneve);
1112 mlx5_vxlan_destroy(dev->vxlan);
1113 mlx5_cleanup_clock(dev);
1114 err_tables_cleanup:
1115 mlx5_cleanup_reserved_gids(dev);
1116 mlx5_cq_debugfs_cleanup(dev);
1117 mlx5_fw_reset_cleanup(dev);
1118 err_eq_cleanup:
1119 mlx5_eq_table_cleanup(dev);
1120 err_irq_cleanup:
1121 mlx5_irq_table_cleanup(dev);
1122 err_devcom:
1123 mlx5_devcom_unregister_device(dev->priv.devc);
1124
1125 return err;
1126 }
1127
mlx5_cleanup_once(struct mlx5_core_dev * dev)1128 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1129 {
1130 mlx5_rsc_dump_destroy(dev);
1131 mlx5_hv_vhca_destroy(dev->hv_vhca);
1132 mlx5_fw_tracer_destroy(dev->tracer);
1133 mlx5_st_destroy(dev);
1134 mlx5_dm_cleanup(dev);
1135 mlx5_fs_core_free(dev);
1136 mlx5_sf_table_cleanup(dev);
1137 mlx5_sf_hw_table_cleanup(dev);
1138 mlx5_vhca_event_cleanup(dev);
1139 mlx5_fpga_cleanup(dev);
1140 mlx5_eswitch_cleanup(dev->priv.eswitch);
1141 mlx5_sriov_cleanup(dev);
1142 mlx5_mpfs_cleanup(dev);
1143 mlx5_cleanup_rl_table(dev);
1144 mlx5_geneve_destroy(dev->geneve);
1145 mlx5_vxlan_destroy(dev->vxlan);
1146 mlx5_cleanup_clock(dev);
1147 mlx5_cleanup_reserved_gids(dev);
1148 mlx5_cq_debugfs_cleanup(dev);
1149 mlx5_fw_reset_cleanup(dev);
1150 mlx5_eq_table_cleanup(dev);
1151 mlx5_irq_table_cleanup(dev);
1152 mlx5_devcom_unregister_device(dev->priv.devc);
1153 }
1154
mlx5_function_enable(struct mlx5_core_dev * dev,bool boot,u64 timeout)1155 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1156 {
1157 int err;
1158
1159 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1160 fw_rev_min(dev), fw_rev_sub(dev));
1161
1162 /* Only PFs hold the relevant PCIe information for this query */
1163 if (mlx5_core_is_pf(dev))
1164 pcie_print_link_status(dev->pdev);
1165
1166 /* wait for firmware to accept initialization segments configurations
1167 */
1168 err = wait_fw_init(dev, timeout,
1169 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL),
1170 "pre-initializing");
1171 if (err)
1172 return err;
1173
1174 err = mlx5_cmd_enable(dev);
1175 if (err) {
1176 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1177 return err;
1178 }
1179
1180 mlx5_tout_query_iseg(dev);
1181
1182 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing");
1183 if (err)
1184 goto err_cmd_cleanup;
1185
1186 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1187 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1188
1189 err = mlx5_core_enable_hca(dev, 0);
1190 if (err) {
1191 mlx5_core_err(dev, "enable hca failed\n");
1192 goto err_cmd_cleanup;
1193 }
1194
1195 mlx5_start_health_poll(dev);
1196
1197 err = mlx5_core_set_issi(dev);
1198 if (err) {
1199 mlx5_core_err(dev, "failed to set issi\n");
1200 goto stop_health_poll;
1201 }
1202
1203 err = mlx5_satisfy_startup_pages(dev, 1);
1204 if (err) {
1205 mlx5_core_err(dev, "failed to allocate boot pages\n");
1206 goto stop_health_poll;
1207 }
1208
1209 err = mlx5_tout_query_dtor(dev);
1210 if (err) {
1211 mlx5_core_err(dev, "failed to read dtor\n");
1212 goto reclaim_boot_pages;
1213 }
1214
1215 return 0;
1216
1217 reclaim_boot_pages:
1218 mlx5_reclaim_startup_pages(dev);
1219 stop_health_poll:
1220 mlx5_stop_health_poll(dev, boot);
1221 mlx5_core_disable_hca(dev, 0);
1222 err_cmd_cleanup:
1223 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1224 mlx5_cmd_disable(dev);
1225
1226 return err;
1227 }
1228
mlx5_function_disable(struct mlx5_core_dev * dev,bool boot)1229 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot)
1230 {
1231 mlx5_reclaim_startup_pages(dev);
1232 mlx5_stop_health_poll(dev, boot);
1233 mlx5_core_disable_hca(dev, 0);
1234 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1235 mlx5_cmd_disable(dev);
1236 }
1237
mlx5_function_open(struct mlx5_core_dev * dev)1238 static int mlx5_function_open(struct mlx5_core_dev *dev)
1239 {
1240 int err;
1241
1242 err = set_hca_ctrl(dev);
1243 if (err) {
1244 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1245 return err;
1246 }
1247
1248 err = set_hca_cap(dev);
1249 if (err) {
1250 mlx5_core_err(dev, "set_hca_cap failed\n");
1251 return err;
1252 }
1253
1254 err = mlx5_satisfy_startup_pages(dev, 0);
1255 if (err) {
1256 mlx5_core_err(dev, "failed to allocate init pages\n");
1257 return err;
1258 }
1259
1260 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1261 if (err) {
1262 mlx5_core_err(dev, "init hca failed\n");
1263 return err;
1264 }
1265
1266 mlx5_set_driver_version(dev);
1267
1268 err = mlx5_query_hca_caps(dev);
1269 if (err) {
1270 mlx5_core_err(dev, "query hca failed\n");
1271 return err;
1272 }
1273 mlx5_start_health_fw_log_up(dev);
1274 return 0;
1275 }
1276
mlx5_function_close(struct mlx5_core_dev * dev)1277 static int mlx5_function_close(struct mlx5_core_dev *dev)
1278 {
1279 int err;
1280
1281 err = mlx5_cmd_teardown_hca(dev);
1282 if (err) {
1283 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1284 return err;
1285 }
1286
1287 return 0;
1288 }
1289
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1290 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1291 {
1292 int err;
1293
1294 err = mlx5_function_enable(dev, boot, timeout);
1295 if (err)
1296 return err;
1297
1298 err = mlx5_function_open(dev);
1299 if (err)
1300 mlx5_function_disable(dev, boot);
1301 return err;
1302 }
1303
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1304 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1305 {
1306 int err = mlx5_function_close(dev);
1307
1308 if (!err)
1309 mlx5_function_disable(dev, boot);
1310 else
1311 mlx5_stop_health_poll(dev, boot);
1312
1313 return err;
1314 }
1315
mlx5_load(struct mlx5_core_dev * dev)1316 static int mlx5_load(struct mlx5_core_dev *dev)
1317 {
1318 int err;
1319
1320 err = mlx5_alloc_bfreg(dev, &dev->priv.bfreg, false, false);
1321 if (err) {
1322 mlx5_core_err(dev, "Failed allocating bfreg, %d\n", err);
1323 return err;
1324 }
1325
1326 mlx5_events_start(dev);
1327 mlx5_pagealloc_start(dev);
1328
1329 err = mlx5_irq_table_create(dev);
1330 if (err) {
1331 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1332 goto err_irq_table;
1333 }
1334
1335 err = mlx5_eq_table_create(dev);
1336 if (err) {
1337 mlx5_core_err(dev, "Failed to create EQs\n");
1338 goto err_eq_table;
1339 }
1340
1341 mlx5_clock_load(dev);
1342
1343 err = mlx5_fw_tracer_init(dev->tracer);
1344 if (err) {
1345 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1346 mlx5_fw_tracer_destroy(dev->tracer);
1347 dev->tracer = NULL;
1348 }
1349
1350 mlx5_fw_reset_events_start(dev);
1351 mlx5_hv_vhca_init(dev->hv_vhca);
1352
1353 err = mlx5_rsc_dump_init(dev);
1354 if (err) {
1355 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1356 mlx5_rsc_dump_destroy(dev);
1357 dev->rsc_dump = NULL;
1358 }
1359
1360 err = mlx5_fpga_device_start(dev);
1361 if (err) {
1362 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1363 goto err_fpga_start;
1364 }
1365
1366 err = mlx5_fs_core_init(dev);
1367 if (err) {
1368 mlx5_core_err(dev, "Failed to init flow steering\n");
1369 goto err_fs;
1370 }
1371
1372 err = mlx5_core_set_hca_defaults(dev);
1373 if (err) {
1374 mlx5_core_err(dev, "Failed to set hca defaults\n");
1375 goto err_set_hca;
1376 }
1377
1378 mlx5_vhca_event_start(dev);
1379
1380 err = mlx5_ec_init(dev);
1381 if (err) {
1382 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1383 goto err_ec;
1384 }
1385
1386 mlx5_lag_add_mdev(dev);
1387 err = mlx5_sriov_attach(dev);
1388 if (err) {
1389 mlx5_core_err(dev, "sriov init failed %d\n", err);
1390 goto err_sriov;
1391 }
1392
1393 mlx5_sf_dev_table_create(dev);
1394
1395 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1396 if (err)
1397 goto err_traps_reg;
1398
1399 return 0;
1400
1401 err_traps_reg:
1402 mlx5_sf_dev_table_destroy(dev);
1403 mlx5_sriov_detach(dev);
1404 err_sriov:
1405 mlx5_lag_remove_mdev(dev);
1406 mlx5_ec_cleanup(dev);
1407 err_ec:
1408 mlx5_vhca_event_stop(dev);
1409 err_set_hca:
1410 mlx5_fs_core_cleanup(dev);
1411 err_fs:
1412 mlx5_fpga_device_stop(dev);
1413 err_fpga_start:
1414 mlx5_rsc_dump_cleanup(dev);
1415 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1416 mlx5_fw_reset_events_stop(dev);
1417 mlx5_fw_tracer_cleanup(dev->tracer);
1418 mlx5_clock_unload(dev);
1419 mlx5_eq_table_destroy(dev);
1420 err_eq_table:
1421 mlx5_irq_table_destroy(dev);
1422 err_irq_table:
1423 mlx5_pagealloc_stop(dev);
1424 mlx5_events_stop(dev);
1425 mlx5_free_bfreg(dev, &dev->priv.bfreg);
1426 return err;
1427 }
1428
mlx5_unload(struct mlx5_core_dev * dev)1429 static void mlx5_unload(struct mlx5_core_dev *dev)
1430 {
1431 mlx5_eswitch_disable(dev->priv.eswitch);
1432 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1433 mlx5_vhca_event_stop(dev);
1434 mlx5_sf_dev_table_destroy(dev);
1435 mlx5_sriov_detach(dev);
1436 mlx5_lag_remove_mdev(dev);
1437 mlx5_ec_cleanup(dev);
1438 mlx5_sf_hw_table_destroy(dev);
1439 mlx5_fs_core_cleanup(dev);
1440 mlx5_fpga_device_stop(dev);
1441 mlx5_rsc_dump_cleanup(dev);
1442 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1443 mlx5_fw_reset_events_stop(dev);
1444 mlx5_fw_tracer_cleanup(dev->tracer);
1445 mlx5_clock_unload(dev);
1446 mlx5_eq_table_destroy(dev);
1447 mlx5_irq_table_destroy(dev);
1448 mlx5_pagealloc_stop(dev);
1449 mlx5_events_stop(dev);
1450 mlx5_free_bfreg(dev, &dev->priv.bfreg);
1451 }
1452
mlx5_init_one_devl_locked(struct mlx5_core_dev * dev)1453 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev)
1454 {
1455 bool light_probe = mlx5_dev_is_lightweight(dev);
1456 int err = 0;
1457
1458 mutex_lock(&dev->intf_state_mutex);
1459 dev->state = MLX5_DEVICE_STATE_UP;
1460
1461 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1462 if (err)
1463 goto err_function;
1464
1465 err = mlx5_init_once(dev);
1466 if (err) {
1467 mlx5_core_err(dev, "sw objs init failed\n");
1468 goto function_teardown;
1469 }
1470
1471 /* In case of light_probe, mlx5_devlink is already registered.
1472 * Hence, don't register devlink again.
1473 */
1474 if (!light_probe) {
1475 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1476 if (err)
1477 goto err_devlink_params_reg;
1478 }
1479
1480 err = mlx5_load(dev);
1481 if (err)
1482 goto err_load;
1483
1484 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1485
1486 err = mlx5_register_device(dev);
1487 if (err)
1488 goto err_register;
1489
1490 err = mlx5_crdump_enable(dev);
1491 if (err)
1492 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err);
1493
1494 err = mlx5_hwmon_dev_register(dev);
1495 if (err)
1496 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err);
1497
1498 mutex_unlock(&dev->intf_state_mutex);
1499 return 0;
1500
1501 err_register:
1502 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1503 mlx5_unload(dev);
1504 err_load:
1505 if (!light_probe)
1506 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1507 err_devlink_params_reg:
1508 mlx5_cleanup_once(dev);
1509 function_teardown:
1510 mlx5_function_teardown(dev, true);
1511 err_function:
1512 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1513 mutex_unlock(&dev->intf_state_mutex);
1514 return err;
1515 }
1516
mlx5_init_one(struct mlx5_core_dev * dev)1517 int mlx5_init_one(struct mlx5_core_dev *dev)
1518 {
1519 struct devlink *devlink = priv_to_devlink(dev);
1520 int err;
1521
1522 devl_lock(devlink);
1523 devl_register(devlink);
1524 err = mlx5_init_one_devl_locked(dev);
1525 if (err)
1526 devl_unregister(devlink);
1527 devl_unlock(devlink);
1528 return err;
1529 }
1530
mlx5_uninit_one(struct mlx5_core_dev * dev)1531 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1532 {
1533 struct devlink *devlink = priv_to_devlink(dev);
1534
1535 devl_lock(devlink);
1536 mutex_lock(&dev->intf_state_mutex);
1537
1538 mlx5_hwmon_dev_unregister(dev);
1539 mlx5_crdump_disable(dev);
1540 mlx5_unregister_device(dev);
1541
1542 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1543 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1544 __func__);
1545 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1546 mlx5_cleanup_once(dev);
1547 goto out;
1548 }
1549
1550 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1551 mlx5_unload(dev);
1552 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1553 mlx5_cleanup_once(dev);
1554 mlx5_function_teardown(dev, true);
1555 out:
1556 mutex_unlock(&dev->intf_state_mutex);
1557 devl_unregister(devlink);
1558 devl_unlock(devlink);
1559 }
1560
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1561 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1562 {
1563 int err = 0;
1564 u64 timeout;
1565
1566 devl_assert_locked(priv_to_devlink(dev));
1567 mutex_lock(&dev->intf_state_mutex);
1568 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1569 mlx5_core_warn(dev, "interface is up, NOP\n");
1570 goto out;
1571 }
1572 /* remove any previous indication of internal error */
1573 dev->state = MLX5_DEVICE_STATE_UP;
1574
1575 if (recovery)
1576 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1577 else
1578 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1579 err = mlx5_function_setup(dev, false, timeout);
1580 if (err)
1581 goto err_function;
1582
1583 err = mlx5_load(dev);
1584 if (err)
1585 goto err_load;
1586
1587 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1588
1589 err = mlx5_attach_device(dev);
1590 if (err)
1591 goto err_attach;
1592
1593 mutex_unlock(&dev->intf_state_mutex);
1594 return 0;
1595
1596 err_attach:
1597 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1598 mlx5_unload(dev);
1599 err_load:
1600 mlx5_function_teardown(dev, false);
1601 err_function:
1602 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1603 out:
1604 mutex_unlock(&dev->intf_state_mutex);
1605 return err;
1606 }
1607
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1608 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1609 {
1610 struct devlink *devlink = priv_to_devlink(dev);
1611 int ret;
1612
1613 devl_lock(devlink);
1614 ret = mlx5_load_one_devl_locked(dev, recovery);
1615 devl_unlock(devlink);
1616 return ret;
1617 }
1618
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1619 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1620 {
1621 devl_assert_locked(priv_to_devlink(dev));
1622 mutex_lock(&dev->intf_state_mutex);
1623
1624 mlx5_detach_device(dev, suspend);
1625
1626 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1627 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1628 __func__);
1629 goto out;
1630 }
1631
1632 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1633 mlx5_unload(dev);
1634 mlx5_function_teardown(dev, false);
1635 out:
1636 mutex_unlock(&dev->intf_state_mutex);
1637 }
1638
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1639 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1640 {
1641 struct devlink *devlink = priv_to_devlink(dev);
1642
1643 devl_lock(devlink);
1644 mlx5_unload_one_devl_locked(dev, suspend);
1645 devl_unlock(devlink);
1646 }
1647
1648 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps.
1649 * A full query of hca_caps will be done when the device will reload.
1650 */
mlx5_query_hca_caps_light(struct mlx5_core_dev * dev)1651 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev)
1652 {
1653 int err;
1654
1655 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
1656 if (err)
1657 return err;
1658
1659 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
1660 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
1661 HCA_CAP_OPMOD_GET_CUR);
1662 if (err)
1663 return err;
1664 }
1665
1666 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
1667 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
1668 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE,
1669 HCA_CAP_OPMOD_GET_CUR);
1670 if (err)
1671 return err;
1672 }
1673
1674 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
1675 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
1676 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION,
1677 HCA_CAP_OPMOD_GET_CUR);
1678 if (err)
1679 return err;
1680 }
1681
1682 return 0;
1683 }
1684
mlx5_init_one_light(struct mlx5_core_dev * dev)1685 int mlx5_init_one_light(struct mlx5_core_dev *dev)
1686 {
1687 struct devlink *devlink = priv_to_devlink(dev);
1688 int err;
1689
1690 devl_lock(devlink);
1691 devl_register(devlink);
1692 dev->state = MLX5_DEVICE_STATE_UP;
1693 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1694 if (err) {
1695 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err);
1696 goto out;
1697 }
1698
1699 err = mlx5_query_hca_caps_light(dev);
1700 if (err) {
1701 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err);
1702 goto query_hca_caps_err;
1703 }
1704
1705 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1706 if (err) {
1707 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err);
1708 goto query_hca_caps_err;
1709 }
1710
1711 devl_unlock(devlink);
1712 return 0;
1713
1714 query_hca_caps_err:
1715 mlx5_function_disable(dev, true);
1716 out:
1717 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1718 devl_unregister(devlink);
1719 devl_unlock(devlink);
1720 return err;
1721 }
1722
mlx5_uninit_one_light(struct mlx5_core_dev * dev)1723 void mlx5_uninit_one_light(struct mlx5_core_dev *dev)
1724 {
1725 struct devlink *devlink = priv_to_devlink(dev);
1726
1727 devl_lock(devlink);
1728 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1729 devl_unregister(devlink);
1730 devl_unlock(devlink);
1731 if (dev->state != MLX5_DEVICE_STATE_UP)
1732 return;
1733 mlx5_function_disable(dev, true);
1734 }
1735
1736 /* xxx_light() function are used in order to configure the device without full
1737 * init (light init). e.g.: There isn't a point in reload a device to light state.
1738 * Hence, mlx5_load_one_light() isn't needed.
1739 */
1740
mlx5_unload_one_light(struct mlx5_core_dev * dev)1741 void mlx5_unload_one_light(struct mlx5_core_dev *dev)
1742 {
1743 if (dev->state != MLX5_DEVICE_STATE_UP)
1744 return;
1745 mlx5_function_disable(dev, false);
1746 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1747 }
1748
1749 static const int types[] = {
1750 MLX5_CAP_GENERAL,
1751 MLX5_CAP_GENERAL_2,
1752 MLX5_CAP_ETHERNET_OFFLOADS,
1753 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1754 MLX5_CAP_ODP,
1755 MLX5_CAP_ATOMIC,
1756 MLX5_CAP_ROCE,
1757 MLX5_CAP_IPOIB_OFFLOADS,
1758 MLX5_CAP_FLOW_TABLE,
1759 MLX5_CAP_ESWITCH_FLOW_TABLE,
1760 MLX5_CAP_ESWITCH,
1761 MLX5_CAP_QOS,
1762 MLX5_CAP_DEBUG,
1763 MLX5_CAP_DEV_MEM,
1764 MLX5_CAP_DEV_EVENT,
1765 MLX5_CAP_TLS,
1766 MLX5_CAP_VDPA_EMULATION,
1767 MLX5_CAP_IPSEC,
1768 MLX5_CAP_PORT_SELECTION,
1769 MLX5_CAP_PSP,
1770 MLX5_CAP_MACSEC,
1771 MLX5_CAP_ADV_VIRTUALIZATION,
1772 MLX5_CAP_CRYPTO,
1773 MLX5_CAP_SHAMPO,
1774 MLX5_CAP_ADV_RDMA,
1775 };
1776
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1777 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1778 {
1779 int type;
1780 int i;
1781
1782 for (i = 0; i < ARRAY_SIZE(types); i++) {
1783 type = types[i];
1784 kfree(dev->caps.hca[type]);
1785 }
1786 }
1787
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1788 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1789 {
1790 struct mlx5_hca_cap *cap;
1791 int type;
1792 int i;
1793
1794 for (i = 0; i < ARRAY_SIZE(types); i++) {
1795 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1796 if (!cap)
1797 goto err;
1798 type = types[i];
1799 dev->caps.hca[type] = cap;
1800 }
1801
1802 return 0;
1803
1804 err:
1805 mlx5_hca_caps_free(dev);
1806 return -ENOMEM;
1807 }
1808
vhca_id_show(struct seq_file * file,void * priv)1809 static int vhca_id_show(struct seq_file *file, void *priv)
1810 {
1811 struct mlx5_core_dev *dev = file->private;
1812
1813 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1814 return 0;
1815 }
1816
1817 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1818
mlx5_notifiers_init(struct mlx5_core_dev * dev)1819 static int mlx5_notifiers_init(struct mlx5_core_dev *dev)
1820 {
1821 int err;
1822
1823 err = mlx5_events_init(dev);
1824 if (err) {
1825 mlx5_core_err(dev, "failed to initialize events\n");
1826 return err;
1827 }
1828
1829 BLOCKING_INIT_NOTIFIER_HEAD(&dev->priv.esw_n_head);
1830 mlx5_vhca_state_notifier_init(dev);
1831
1832 err = mlx5_sf_hw_notifier_init(dev);
1833 if (err)
1834 goto err_sf_hw_notifier;
1835
1836 err = mlx5_sf_notifiers_init(dev);
1837 if (err)
1838 goto err_sf_notifiers;
1839
1840 err = mlx5_sf_dev_notifier_init(dev);
1841 if (err)
1842 goto err_sf_dev_notifier;
1843
1844 return 0;
1845
1846 err_sf_dev_notifier:
1847 mlx5_sf_notifiers_cleanup(dev);
1848 err_sf_notifiers:
1849 mlx5_sf_hw_notifier_cleanup(dev);
1850 err_sf_hw_notifier:
1851 mlx5_events_cleanup(dev);
1852 return err;
1853 }
1854
mlx5_notifiers_cleanup(struct mlx5_core_dev * dev)1855 static void mlx5_notifiers_cleanup(struct mlx5_core_dev *dev)
1856 {
1857 mlx5_sf_dev_notifier_cleanup(dev);
1858 mlx5_sf_notifiers_cleanup(dev);
1859 mlx5_sf_hw_notifier_cleanup(dev);
1860 mlx5_events_cleanup(dev);
1861 }
1862
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1863 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1864 {
1865 struct mlx5_priv *priv = &dev->priv;
1866 int err;
1867
1868 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1869 lockdep_register_key(&dev->lock_key);
1870 mutex_init(&dev->intf_state_mutex);
1871 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1872 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1873 mutex_init(&dev->wc_state_lock);
1874
1875 mutex_init(&priv->bfregs.reg_head.lock);
1876 mutex_init(&priv->bfregs.wc_head.lock);
1877 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1878 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1879
1880 mutex_init(&priv->alloc_mutex);
1881 mutex_init(&priv->pgdir_mutex);
1882 INIT_LIST_HEAD(&priv->pgdir_list);
1883
1884 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1885 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1886 mlx5_debugfs_root);
1887 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1888 INIT_LIST_HEAD(&priv->traps);
1889
1890 err = mlx5_cmd_init(dev);
1891 if (err) {
1892 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n");
1893 goto err_cmd_init;
1894 }
1895
1896 err = mlx5_tout_init(dev);
1897 if (err) {
1898 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1899 goto err_timeout_init;
1900 }
1901
1902 err = mlx5_health_init(dev);
1903 if (err)
1904 goto err_health_init;
1905
1906 err = mlx5_pagealloc_init(dev);
1907 if (err)
1908 goto err_pagealloc_init;
1909
1910 err = mlx5_adev_init(dev);
1911 if (err)
1912 goto err_adev_init;
1913
1914 err = mlx5_hca_caps_alloc(dev);
1915 if (err)
1916 goto err_hca_caps;
1917
1918 err = mlx5_notifiers_init(dev);
1919 if (err)
1920 goto err_hca_caps;
1921
1922 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1923 * unique id per function which uses mlx5_core.
1924 * Those values are supplied to FW as part of the init HCA command to
1925 * be used by both driver and FW when it's applicable.
1926 */
1927 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1928 MAX_SW_VHCA_ID,
1929 GFP_KERNEL);
1930 if (dev->priv.sw_vhca_id < 0)
1931 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1932 dev->priv.sw_vhca_id);
1933
1934 return 0;
1935
1936 err_hca_caps:
1937 mlx5_adev_cleanup(dev);
1938 err_adev_init:
1939 mlx5_pagealloc_cleanup(dev);
1940 err_pagealloc_init:
1941 mlx5_health_cleanup(dev);
1942 err_health_init:
1943 mlx5_tout_cleanup(dev);
1944 err_timeout_init:
1945 mlx5_cmd_cleanup(dev);
1946 err_cmd_init:
1947 debugfs_remove(dev->priv.dbg.dbg_root);
1948 mutex_destroy(&priv->pgdir_mutex);
1949 mutex_destroy(&priv->alloc_mutex);
1950 mutex_destroy(&priv->bfregs.wc_head.lock);
1951 mutex_destroy(&priv->bfregs.reg_head.lock);
1952 mutex_destroy(&dev->intf_state_mutex);
1953 lockdep_unregister_key(&dev->lock_key);
1954 return err;
1955 }
1956
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1957 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1958 {
1959 struct mlx5_priv *priv = &dev->priv;
1960
1961 if (priv->sw_vhca_id > 0)
1962 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1963
1964 mlx5_notifiers_cleanup(dev);
1965 mlx5_hca_caps_free(dev);
1966 mlx5_adev_cleanup(dev);
1967 mlx5_pagealloc_cleanup(dev);
1968 mlx5_health_cleanup(dev);
1969 mlx5_tout_cleanup(dev);
1970 mlx5_cmd_cleanup(dev);
1971 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1972 mutex_destroy(&priv->pgdir_mutex);
1973 mutex_destroy(&priv->alloc_mutex);
1974 mutex_destroy(&priv->bfregs.wc_head.lock);
1975 mutex_destroy(&priv->bfregs.reg_head.lock);
1976 mutex_destroy(&dev->wc_state_lock);
1977 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1978 mutex_destroy(&dev->intf_state_mutex);
1979 lockdep_unregister_key(&dev->lock_key);
1980 }
1981
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1982 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1983 {
1984 struct mlx5_core_dev *dev;
1985 struct devlink *devlink;
1986 int err;
1987
1988 devlink = mlx5_devlink_alloc(&pdev->dev);
1989 if (!devlink) {
1990 dev_err(&pdev->dev, "devlink alloc failed\n");
1991 return -ENOMEM;
1992 }
1993
1994 dev = devlink_priv(devlink);
1995 dev->device = &pdev->dev;
1996 dev->pdev = pdev;
1997
1998 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1999 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
2000
2001 dev->priv.adev_idx = mlx5_adev_idx_alloc();
2002 if (dev->priv.adev_idx < 0) {
2003 err = dev->priv.adev_idx;
2004 goto adev_init_err;
2005 }
2006
2007 err = mlx5_mdev_init(dev, prof_sel);
2008 if (err)
2009 goto mdev_init_err;
2010
2011 err = mlx5_pci_init(dev, pdev, id);
2012 if (err) {
2013 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
2014 err);
2015 goto pci_init_err;
2016 }
2017
2018 err = mlx5_init_one(dev);
2019 if (err) {
2020 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
2021 err);
2022 goto err_init_one;
2023 }
2024
2025 pci_save_state(pdev);
2026 return 0;
2027
2028 err_init_one:
2029 mlx5_pci_close(dev);
2030 pci_init_err:
2031 mlx5_mdev_uninit(dev);
2032 mdev_init_err:
2033 mlx5_adev_idx_free(dev->priv.adev_idx);
2034 adev_init_err:
2035 mlx5_devlink_free(devlink);
2036
2037 return err;
2038 }
2039
remove_one(struct pci_dev * pdev)2040 static void remove_one(struct pci_dev *pdev)
2041 {
2042 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2043 struct devlink *devlink = priv_to_devlink(dev);
2044
2045 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2046 mlx5_drain_fw_reset(dev);
2047 mlx5_drain_health_wq(dev);
2048 mlx5_sriov_disable(pdev, false);
2049 mlx5_uninit_one(dev);
2050 mlx5_pci_close(dev);
2051 mlx5_mdev_uninit(dev);
2052 mlx5_adev_idx_free(dev->priv.adev_idx);
2053 mlx5_devlink_free(devlink);
2054 }
2055
2056 #define mlx5_pci_trace(dev, fmt, ...) ({ \
2057 struct mlx5_core_dev *__dev = (dev); \
2058 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
2059 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
2060 __dev->pci_status, ##__VA_ARGS__); \
2061 })
2062
result2str(enum pci_ers_result result)2063 static const char *result2str(enum pci_ers_result result)
2064 {
2065 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
2066 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
2067 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
2068 "unknown";
2069 }
2070
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2071 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
2072 pci_channel_state_t state)
2073 {
2074 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2075 enum pci_ers_result res;
2076
2077 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
2078
2079 mlx5_enter_error_state(dev, false);
2080 mlx5_error_sw_reset(dev);
2081 mlx5_unload_one(dev, false);
2082 mlx5_drain_health_wq(dev);
2083 mlx5_pci_disable_device(dev);
2084
2085 res = state == pci_channel_io_perm_failure ?
2086 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2087
2088 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
2089 __func__, dev->state, dev->pci_status, res, result2str(res));
2090 return res;
2091 }
2092
2093 /* wait for the device to show vital signs by waiting
2094 * for the health counter to start counting.
2095 */
wait_vital(struct pci_dev * pdev)2096 static int wait_vital(struct pci_dev *pdev)
2097 {
2098 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2099 struct mlx5_core_health *health = &dev->priv.health;
2100 const int niter = 100;
2101 u32 last_count = 0;
2102 u32 count;
2103 int i;
2104
2105 for (i = 0; i < niter; i++) {
2106 count = ioread32be(health->health_counter);
2107 if (count && count != 0xffffffff) {
2108 if (last_count && last_count != count) {
2109 mlx5_core_info(dev,
2110 "wait vital counter value 0x%x after %d iterations\n",
2111 count, i);
2112 return 0;
2113 }
2114 last_count = count;
2115 }
2116 msleep(50);
2117 }
2118
2119 return -ETIMEDOUT;
2120 }
2121
mlx5_pci_slot_reset(struct pci_dev * pdev)2122 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
2123 {
2124 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
2125 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2126 int err;
2127
2128 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
2129 __func__, dev->state, dev->pci_status);
2130
2131 err = mlx5_pci_enable_device(dev);
2132 if (err) {
2133 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
2134 __func__, err);
2135 goto out;
2136 }
2137
2138 pci_set_master(pdev);
2139 pci_restore_state(pdev);
2140
2141 err = wait_vital(pdev);
2142 if (err) {
2143 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
2144 __func__, err);
2145 goto out;
2146 }
2147
2148 res = PCI_ERS_RESULT_RECOVERED;
2149 out:
2150 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
2151 __func__, dev->state, dev->pci_status, err, res, result2str(res));
2152 return res;
2153 }
2154
mlx5_pci_resume(struct pci_dev * pdev)2155 static void mlx5_pci_resume(struct pci_dev *pdev)
2156 {
2157 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2158 int err;
2159
2160 mlx5_pci_trace(dev, "Enter, loading driver..\n");
2161
2162 err = mlx5_load_one(dev, false);
2163
2164 if (!err)
2165 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
2166 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2167
2168 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
2169 !err ? "recovered" : "Failed");
2170 }
2171
2172 static const struct pci_error_handlers mlx5_err_handler = {
2173 .error_detected = mlx5_pci_err_detected,
2174 .slot_reset = mlx5_pci_slot_reset,
2175 .resume = mlx5_pci_resume
2176 };
2177
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2178 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2179 {
2180 bool fast_teardown = false, force_teardown = false;
2181 int ret = 1;
2182
2183 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2184 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2185
2186 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2187 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2188
2189 if (!fast_teardown && !force_teardown)
2190 return -EOPNOTSUPP;
2191
2192 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2193 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2194 return -EAGAIN;
2195 }
2196
2197 /* Panic tear down fw command will stop the PCI bus communication
2198 * with the HCA, so the health poll is no longer needed.
2199 */
2200 mlx5_stop_health_poll(dev, false);
2201
2202 ret = mlx5_cmd_fast_teardown_hca(dev);
2203 if (!ret)
2204 goto succeed;
2205
2206 ret = mlx5_cmd_force_teardown_hca(dev);
2207 if (!ret)
2208 goto succeed;
2209
2210 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
2211 mlx5_start_health_poll(dev);
2212 return ret;
2213
2214 succeed:
2215 mlx5_enter_error_state(dev, true);
2216
2217 /* Some platforms requiring freeing the IRQ's in the shutdown
2218 * flow. If they aren't freed they can't be allocated after
2219 * kexec. There is no need to cleanup the mlx5_core software
2220 * contexts.
2221 */
2222 mlx5_core_eq_free_irqs(dev);
2223
2224 return 0;
2225 }
2226
shutdown(struct pci_dev * pdev)2227 static void shutdown(struct pci_dev *pdev)
2228 {
2229 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2230 int err;
2231
2232 mlx5_core_info(dev, "Shutdown was called\n");
2233 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2234 mlx5_drain_health_wq(dev);
2235 err = mlx5_try_fast_unload(dev);
2236 if (err)
2237 mlx5_unload_one(dev, false);
2238 mlx5_pci_disable_device(dev);
2239 }
2240
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)2241 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2242 {
2243 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2244
2245 mlx5_unload_one(dev, true);
2246
2247 return 0;
2248 }
2249
mlx5_resume(struct pci_dev * pdev)2250 static int mlx5_resume(struct pci_dev *pdev)
2251 {
2252 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2253
2254 return mlx5_load_one(dev, false);
2255 }
2256
2257 static const struct pci_device_id mlx5_core_pci_table[] = {
2258 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2259 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2260 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2261 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2262 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2263 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2264 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2265 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2266 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2267 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2268 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2269 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2270 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2271 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2272 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2273 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2274 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2275 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2276 { PCI_VDEVICE(MELLANOX, 0x1027) }, /* ConnectX-10 */
2277 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2278 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2279 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2280 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2281 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2282 { 0, }
2283 };
2284
2285 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2286
mlx5_disable_device(struct mlx5_core_dev * dev)2287 void mlx5_disable_device(struct mlx5_core_dev *dev)
2288 {
2289 mlx5_error_sw_reset(dev);
2290 mlx5_unload_one_devl_locked(dev, false);
2291 }
2292
mlx5_recover_device(struct mlx5_core_dev * dev)2293 int mlx5_recover_device(struct mlx5_core_dev *dev)
2294 {
2295 if (!mlx5_core_is_sf(dev)) {
2296 mlx5_pci_disable_device(dev);
2297 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2298 return -EIO;
2299 }
2300
2301 return mlx5_load_one_devl_locked(dev, true);
2302 }
2303
2304 static struct pci_driver mlx5_core_driver = {
2305 .name = KBUILD_MODNAME,
2306 .id_table = mlx5_core_pci_table,
2307 .probe = probe_one,
2308 .remove = remove_one,
2309 .suspend = mlx5_suspend,
2310 .resume = mlx5_resume,
2311 .shutdown = shutdown,
2312 .err_handler = &mlx5_err_handler,
2313 .sriov_configure = mlx5_core_sriov_configure,
2314 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2315 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2316 };
2317
2318 /**
2319 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2320 * mlx5_core is its driver.
2321 * @pdev: The associated PCI device.
2322 *
2323 * Upon return the interface state lock stay held to let caller uses it safely.
2324 * Caller must ensure to use the returned mlx5 device for a narrow window
2325 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2326 *
2327 * Return: Pointer to the associated mlx5_core_dev or NULL.
2328 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2329 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2330 {
2331 struct mlx5_core_dev *mdev;
2332
2333 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2334 if (IS_ERR(mdev))
2335 return NULL;
2336
2337 mutex_lock(&mdev->intf_state_mutex);
2338 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2339 mutex_unlock(&mdev->intf_state_mutex);
2340 return NULL;
2341 }
2342
2343 return mdev;
2344 }
2345 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2346
2347 /**
2348 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2349 * @mdev: The mlx5 core device.
2350 *
2351 * Upon return the interface state lock is unlocked and caller should not
2352 * access the mdev any more.
2353 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2354 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2355 {
2356 mutex_unlock(&mdev->intf_state_mutex);
2357 }
2358 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2359
mlx5_core_verify_params(void)2360 static void mlx5_core_verify_params(void)
2361 {
2362 if (prof_sel >= ARRAY_SIZE(profile)) {
2363 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2364 prof_sel,
2365 ARRAY_SIZE(profile) - 1,
2366 MLX5_DEFAULT_PROF);
2367 prof_sel = MLX5_DEFAULT_PROF;
2368 }
2369 }
2370
mlx5_init(void)2371 static int __init mlx5_init(void)
2372 {
2373 int err;
2374
2375 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2376 "mlx5_core name not in sync with kernel module name");
2377
2378 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2379
2380 mlx5_core_verify_params();
2381 mlx5_register_debugfs();
2382
2383 err = mlx5e_init();
2384 if (err)
2385 goto err_debug;
2386
2387 err = mlx5_sf_driver_register();
2388 if (err)
2389 goto err_sf;
2390
2391 err = pci_register_driver(&mlx5_core_driver);
2392 if (err)
2393 goto err_pci;
2394
2395 return 0;
2396
2397 err_pci:
2398 mlx5_sf_driver_unregister();
2399 err_sf:
2400 mlx5e_cleanup();
2401 err_debug:
2402 mlx5_unregister_debugfs();
2403 return err;
2404 }
2405
mlx5_cleanup(void)2406 static void __exit mlx5_cleanup(void)
2407 {
2408 pci_unregister_driver(&mlx5_core_driver);
2409 mlx5_sf_driver_unregister();
2410 mlx5e_cleanup();
2411 mlx5_unregister_debugfs();
2412 }
2413
2414 module_init(mlx5_init);
2415 module_exit(mlx5_cleanup);
2416