1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/delay.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/debugfs.h>
46 #include <linux/kmod.h>
47 #include <linux/mlx5/mlx5_ifc.h>
48 #include <linux/mlx5/vport.h>
49 #include <linux/version.h>
50 #include <net/devlink.h>
51 #include "mlx5_core.h"
52 #include "lib/eq.h"
53 #include "fs_core.h"
54 #include "lib/mpfs.h"
55 #include "eswitch.h"
56 #include "devlink.h"
57 #include "fw_reset.h"
58 #include "lib/mlx5.h"
59 #include "lib/tout.h"
60 #include "fpga/core.h"
61 #include "en_accel/ipsec.h"
62 #include "lib/clock.h"
63 #include "lib/vxlan.h"
64 #include "lib/geneve.h"
65 #include "lib/devcom.h"
66 #include "lib/pci_vsc.h"
67 #include "diag/fw_tracer.h"
68 #include "ecpf.h"
69 #include "lib/hv_vhca.h"
70 #include "diag/rsc_dump.h"
71 #include "sf/vhca_event.h"
72 #include "sf/dev/dev.h"
73 #include "sf/sf.h"
74 #include "mlx5_irq.h"
75 #include "hwmon.h"
76 #include "lag/lag.h"
77
78 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
79 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
80 MODULE_LICENSE("Dual BSD/GPL");
81
82 unsigned int mlx5_core_debug_mask;
83 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
84 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
85
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
92 static DEFINE_IDA(sw_vhca_ida);
93
94 enum {
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
97 };
98
99 #define LOG_MAX_SUPPORTED_QPS 0xff
100
101 static struct mlx5_profile profile[] = {
102 [0] = {
103 .mask = 0,
104 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
110
111 },
112 [2] = {
113 .mask = MLX5_PROF_MASK_QP_SIZE |
114 MLX5_PROF_MASK_MR_CACHE,
115 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
116 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
117 .mr_cache[0] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[1] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[2] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[3] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[4] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[5] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[6] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[7] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[8] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[9] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[10] = {
158 .size = 500,
159 .limit = 250
160 },
161 .mr_cache[11] = {
162 .size = 500,
163 .limit = 250
164 },
165 .mr_cache[12] = {
166 .size = 64,
167 .limit = 32
168 },
169 .mr_cache[13] = {
170 .size = 32,
171 .limit = 16
172 },
173 .mr_cache[14] = {
174 .size = 16,
175 .limit = 8
176 },
177 .mr_cache[15] = {
178 .size = 8,
179 .limit = 4
180 },
181 },
182 [3] = {
183 .mask = MLX5_PROF_MASK_QP_SIZE,
184 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
185 .num_cmd_caches = 0,
186 },
187 };
188
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili,const char * init_state)189 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
190 u32 warn_time_mili, const char *init_state)
191 {
192 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
193 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
194 u32 fw_initializing;
195
196 do {
197 fw_initializing = ioread32be(&dev->iseg->initializing);
198 if (!(fw_initializing >> 31))
199 break;
200 if (time_after(jiffies, end)) {
201 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n",
202 max_wait_mili, init_state);
203 return -ETIMEDOUT;
204 }
205 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) {
206 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n",
207 init_state);
208 return -ENODEV;
209 }
210 if (warn_time_mili && time_after(jiffies, warn)) {
211 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n",
212 init_state, jiffies_to_msecs(end - warn) / 1000,
213 fw_initializing);
214 warn = jiffies + msecs_to_jiffies(warn_time_mili);
215 }
216 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
217 } while (true);
218
219 return 0;
220 }
221
mlx5_set_driver_version(struct mlx5_core_dev * dev)222 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
223 {
224 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
225 driver_version);
226 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
227 char *string;
228
229 if (!MLX5_CAP_GEN(dev, driver_version))
230 return;
231
232 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
233
234 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u",
235 KBUILD_MODNAME, LINUX_VERSION_MAJOR,
236 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
260 return err;
261 }
262
mlx5_pci_enable_device(struct mlx5_core_dev * dev)263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
264 {
265 struct pci_dev *pdev = dev->pdev;
266 int err = 0;
267
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
271 if (!err)
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
273 }
274 mutex_unlock(&dev->pci_status_mutex);
275
276 return err;
277 }
278
mlx5_pci_disable_device(struct mlx5_core_dev * dev)279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
287 }
288 mutex_unlock(&dev->pci_status_mutex);
289 }
290
request_bar(struct pci_dev * pdev)291 static int request_bar(struct pci_dev *pdev)
292 {
293 int err = 0;
294
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
297 return -ENODEV;
298 }
299
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
301 if (err)
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
303
304 return err;
305 }
306
release_bar(struct pci_dev * pdev)307 static void release_bar(struct pci_dev *pdev)
308 {
309 pci_release_regions(pdev);
310 }
311
312 struct mlx5_reg_host_endianness {
313 u8 he;
314 u8 rsvd[15];
315 };
316
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)317 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
318 {
319 switch (size) {
320 case 128:
321 return 0;
322 case 256:
323 return 1;
324 case 512:
325 return 2;
326 case 1024:
327 return 3;
328 case 2048:
329 return 4;
330 case 4096:
331 return 5;
332 default:
333 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
334 return 0;
335 }
336 }
337
mlx5_core_uplink_netdev_set(struct mlx5_core_dev * dev,struct net_device * netdev)338 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev)
339 {
340 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
341 dev->mlx5e_res.uplink_netdev = netdev;
342 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
343 netdev);
344 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
345 }
346
mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev * dev)347 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev)
348 {
349 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock);
350 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV,
351 dev->mlx5e_res.uplink_netdev);
352 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock);
353 }
354 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay);
355
mlx5_core_mp_event_replay(struct mlx5_core_dev * dev,u32 event,void * data)356 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data)
357 {
358 mlx5_blocking_notifier_call_chain(dev, event, data);
359 }
360 EXPORT_SYMBOL(mlx5_core_mp_event_replay);
361
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)362 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
363 enum mlx5_cap_mode cap_mode)
364 {
365 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
366 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
367 void *out, *hca_caps;
368 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369 int err;
370
371 if (WARN_ON(!dev->caps.hca[cap_type]))
372 /* this cap_type must be added to mlx5_hca_caps_alloc() */
373 return -EINVAL;
374
375 memset(in, 0, sizeof(in));
376 out = kzalloc(out_sz, GFP_KERNEL);
377 if (!out)
378 return -ENOMEM;
379
380 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
381 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
382 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
383 if (err) {
384 mlx5_core_warn(dev,
385 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
386 cap_type, cap_mode, err);
387 goto query_ex;
388 }
389
390 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
391
392 switch (cap_mode) {
393 case HCA_CAP_OPMOD_GET_MAX:
394 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
395 MLX5_UN_SZ_BYTES(hca_cap_union));
396 break;
397 case HCA_CAP_OPMOD_GET_CUR:
398 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
399 MLX5_UN_SZ_BYTES(hca_cap_union));
400 break;
401 default:
402 mlx5_core_warn(dev,
403 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
404 cap_type, cap_mode);
405 err = -EINVAL;
406 break;
407 }
408 query_ex:
409 kfree(out);
410 return err;
411 }
412
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)413 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
414 {
415 int ret;
416
417 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
418 if (ret)
419 return ret;
420 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
421 }
422
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)423 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
424 {
425 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
426 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
427 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
428 }
429
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)430 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
431 {
432 void *set_hca_cap;
433 int req_endianness;
434 int err;
435
436 if (!MLX5_CAP_GEN(dev, atomic))
437 return 0;
438
439 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
440 if (err)
441 return err;
442
443 req_endianness =
444 MLX5_CAP_ATOMIC(dev,
445 supported_atomic_req_8B_endianness_mode_1);
446
447 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
448 return 0;
449
450 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
451
452 /* Set requestor to host endianness */
453 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
454 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
455
456 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
457 }
458
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)459 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
460 {
461 bool do_set = false, mem_page_fault = false;
462 void *set_hca_cap;
463 int err;
464
465 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
466 !MLX5_CAP_GEN(dev, pg))
467 return 0;
468
469 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
470 if (err)
471 return err;
472
473 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
474 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
475 MLX5_ST_SZ_BYTES(odp_cap));
476
477 /* For best performance, enable memory scheme ODP only when
478 * it has page prefetch enabled.
479 */
480 if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) &&
481 MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) {
482 mem_page_fault = true;
483 do_set = true;
484 MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault);
485 goto set;
486 }
487
488 #define ODP_CAP_SET_MAX(dev, field) \
489 do { \
490 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
491 if (_res) { \
492 do_set = true; \
493 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
494 } \
495 } while (0)
496
497 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.ud_odp_caps.srq_receive);
498 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.rc_odp_caps.srq_receive);
499 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.srq_receive);
500 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.send);
501 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.receive);
502 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.write);
503 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.read);
504 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.atomic);
505 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.srq_receive);
506 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.send);
507 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.receive);
508 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.write);
509 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read);
510 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic);
511
512 set:
513 if (do_set)
514 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
515
516 mlx5_core_dbg(dev, "Using ODP %s scheme\n",
517 mem_page_fault ? "memory" : "transport");
518 return err;
519 }
520
max_uc_list_get_devlink_param(struct mlx5_core_dev * dev)521 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
522 {
523 struct devlink *devlink = priv_to_devlink(dev);
524 union devlink_param_value val;
525 int err;
526
527 err = devl_param_driverinit_value_get(devlink,
528 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
529 &val);
530 if (!err)
531 return val.vu32;
532 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
533 return err;
534 }
535
mlx5_is_roce_on(struct mlx5_core_dev * dev)536 bool mlx5_is_roce_on(struct mlx5_core_dev *dev)
537 {
538 struct devlink *devlink = priv_to_devlink(dev);
539 union devlink_param_value val;
540 int err;
541
542 err = devl_param_driverinit_value_get(devlink,
543 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
544 &val);
545
546 if (!err)
547 return val.vbool;
548
549 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
550 return MLX5_CAP_GEN(dev, roce);
551 }
552 EXPORT_SYMBOL(mlx5_is_roce_on);
553
handle_hca_cap_2(struct mlx5_core_dev * dev,void * set_ctx)554 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx)
555 {
556 void *set_hca_cap;
557 int err;
558
559 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2))
560 return 0;
561
562 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
563 if (err)
564 return err;
565
566 if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) ||
567 !(dev->priv.sw_vhca_id > 0))
568 return 0;
569
570 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
571 capability);
572 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur,
573 MLX5_ST_SZ_BYTES(cmd_hca_cap_2));
574 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1);
575
576 return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2);
577 }
578
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)579 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
580 {
581 struct mlx5_profile *prof = &dev->profile;
582 void *set_hca_cap;
583 int max_uc_list;
584 int err;
585
586 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
587 if (err)
588 return err;
589
590 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
591 capability);
592 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
593 MLX5_ST_SZ_BYTES(cmd_hca_cap));
594
595 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
596 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
597 128);
598 /* we limit the size of the pkey table to 128 entries for now */
599 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
600 to_fw_pkey_sz(dev, 128));
601
602 /* Check log_max_qp from HCA caps to set in current profile */
603 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
604 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
605 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
606 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
607 prof->log_max_qp,
608 MLX5_CAP_GEN_MAX(dev, log_max_qp));
609 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
610 }
611 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
612 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
613 prof->log_max_qp);
614
615 /* disable cmdif checksum */
616 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
617
618 /* Enable 4K UAR only when HCA supports it and page size is bigger
619 * than 4K.
620 */
621 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
622 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
623
624 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
625
626 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
627 MLX5_SET(cmd_hca_cap,
628 set_hca_cap,
629 cache_line_128byte,
630 cache_line_size() >= 128 ? 1 : 0);
631
632 if (MLX5_CAP_GEN_MAX(dev, dct))
633 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
634
635 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
636 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
637 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload))
638 MLX5_SET(cmd_hca_cap, set_hca_cap,
639 pci_sync_for_fw_update_with_driver_unload, 1);
640 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method))
641 MLX5_SET(cmd_hca_cap, set_hca_cap,
642 pcie_reset_using_hotreset_method, 1);
643
644 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
645 MLX5_SET(cmd_hca_cap,
646 set_hca_cap,
647 num_vhca_ports,
648 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
649
650 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
651 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
652
653 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
654 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
655
656 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
657
658 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
659 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
660 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
661
662 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))
663 MLX5_SET(cmd_hca_cap, set_hca_cap, roce,
664 mlx5_is_roce_on(dev));
665
666 max_uc_list = max_uc_list_get_devlink_param(dev);
667 if (max_uc_list > 0)
668 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
669 ilog2(max_uc_list));
670
671 /* enable absolute native port num */
672 if (MLX5_CAP_GEN_MAX(dev, abs_native_port_num))
673 MLX5_SET(cmd_hca_cap, set_hca_cap, abs_native_port_num, 1);
674
675 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
676 }
677
678 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
679 * boot process.
680 * In case RoCE cap is writable in FW and user/devlink requested to change the
681 * cap, we are yet to query the final state of the above cap.
682 * Hence, the need for this function.
683 *
684 * Returns
685 * True:
686 * 1) RoCE cap is read only in FW and already disabled
687 * OR:
688 * 2) RoCE cap is writable in FW and user/devlink requested it off.
689 *
690 * In any other case, return False.
691 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)692 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
693 {
694 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) ||
695 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
696 }
697
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)698 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
699 {
700 void *set_hca_cap;
701 int err;
702
703 if (is_roce_fw_disabled(dev))
704 return 0;
705
706 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
707 if (err)
708 return err;
709
710 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
711 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
712 return 0;
713
714 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
715 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
716 MLX5_ST_SZ_BYTES(roce_cap));
717 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
718
719 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default))
720 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1);
721
722 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
723 return err;
724 }
725
handle_hca_cap_port_selection(struct mlx5_core_dev * dev,void * set_ctx)726 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev,
727 void *set_ctx)
728 {
729 void *set_hca_cap;
730 int err;
731
732 if (!MLX5_CAP_GEN(dev, port_selection_cap))
733 return 0;
734
735 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION);
736 if (err)
737 return err;
738
739 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) ||
740 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass))
741 return 0;
742
743 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
744 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur,
745 MLX5_ST_SZ_BYTES(port_selection_cap));
746 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1);
747
748 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION);
749
750 return err;
751 }
752
set_hca_cap(struct mlx5_core_dev * dev)753 static int set_hca_cap(struct mlx5_core_dev *dev)
754 {
755 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
756 void *set_ctx;
757 int err;
758
759 set_ctx = kzalloc(set_sz, GFP_KERNEL);
760 if (!set_ctx)
761 return -ENOMEM;
762
763 err = handle_hca_cap(dev, set_ctx);
764 if (err) {
765 mlx5_core_err(dev, "handle_hca_cap failed\n");
766 goto out;
767 }
768
769 memset(set_ctx, 0, set_sz);
770 err = handle_hca_cap_atomic(dev, set_ctx);
771 if (err) {
772 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
773 goto out;
774 }
775
776 memset(set_ctx, 0, set_sz);
777 err = handle_hca_cap_odp(dev, set_ctx);
778 if (err) {
779 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
780 goto out;
781 }
782
783 memset(set_ctx, 0, set_sz);
784 err = handle_hca_cap_roce(dev, set_ctx);
785 if (err) {
786 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
787 goto out;
788 }
789
790 memset(set_ctx, 0, set_sz);
791 err = handle_hca_cap_2(dev, set_ctx);
792 if (err) {
793 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
794 goto out;
795 }
796
797 memset(set_ctx, 0, set_sz);
798 err = handle_hca_cap_port_selection(dev, set_ctx);
799 if (err) {
800 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n");
801 goto out;
802 }
803
804 out:
805 kfree(set_ctx);
806 return err;
807 }
808
set_hca_ctrl(struct mlx5_core_dev * dev)809 static int set_hca_ctrl(struct mlx5_core_dev *dev)
810 {
811 struct mlx5_reg_host_endianness he_in;
812 struct mlx5_reg_host_endianness he_out;
813 int err;
814
815 if (!mlx5_core_is_pf(dev))
816 return 0;
817
818 memset(&he_in, 0, sizeof(he_in));
819 he_in.he = MLX5_SET_HOST_ENDIANNESS;
820 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
821 &he_out, sizeof(he_out),
822 MLX5_REG_HOST_ENDIANNESS, 0, 1);
823 return err;
824 }
825
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)826 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
827 {
828 int ret = 0;
829
830 /* Disable local_lb by default */
831 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
832 ret = mlx5_nic_vport_update_local_lb(dev, false);
833
834 return ret;
835 }
836
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)837 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
838 {
839 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
840
841 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
842 MLX5_SET(enable_hca_in, in, function_id, func_id);
843 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
844 dev->caps.embedded_cpu);
845 return mlx5_cmd_exec_in(dev, enable_hca, in);
846 }
847
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)848 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
849 {
850 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
851
852 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
853 MLX5_SET(disable_hca_in, in, function_id, func_id);
854 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
855 dev->caps.embedded_cpu);
856 return mlx5_cmd_exec_in(dev, disable_hca, in);
857 }
858
mlx5_core_set_issi(struct mlx5_core_dev * dev)859 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
860 {
861 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
862 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
863 u32 sup_issi;
864 int err;
865
866 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
867 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
868 if (err) {
869 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
870 u8 status = MLX5_GET(query_issi_out, query_out, status);
871
872 if (!status || syndrome == MLX5_DRIVER_SYND) {
873 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
874 err, status, syndrome);
875 return err;
876 }
877
878 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
879 dev->issi = 0;
880 return 0;
881 }
882
883 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
884
885 if (sup_issi & (1 << 1)) {
886 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
887
888 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
889 MLX5_SET(set_issi_in, set_in, current_issi, 1);
890 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
891 if (err) {
892 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
893 err);
894 return err;
895 }
896
897 dev->issi = 1;
898
899 return 0;
900 } else if (sup_issi & (1 << 0) || !sup_issi) {
901 return 0;
902 }
903
904 return -EOPNOTSUPP;
905 }
906
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)907 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
908 const struct pci_device_id *id)
909 {
910 int err = 0;
911
912 mutex_init(&dev->pci_status_mutex);
913 pci_set_drvdata(dev->pdev, dev);
914
915 dev->bar_addr = pci_resource_start(pdev, 0);
916
917 err = mlx5_pci_enable_device(dev);
918 if (err) {
919 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
920 return err;
921 }
922
923 err = request_bar(pdev);
924 if (err) {
925 mlx5_core_err(dev, "error requesting BARs, aborting\n");
926 goto err_disable;
927 }
928
929 pci_set_master(pdev);
930
931 err = set_dma_caps(pdev);
932 if (err) {
933 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
934 goto err_clr_master;
935 }
936
937 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
938 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
939 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
940 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
941
942 dev->iseg_base = dev->bar_addr;
943 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
944 if (!dev->iseg) {
945 err = -ENOMEM;
946 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
947 goto err_clr_master;
948 }
949
950 mlx5_pci_vsc_init(dev);
951
952 pci_enable_ptm(pdev, NULL);
953
954 return 0;
955
956 err_clr_master:
957 release_bar(dev->pdev);
958 err_disable:
959 mlx5_pci_disable_device(dev);
960 return err;
961 }
962
mlx5_pci_close(struct mlx5_core_dev * dev)963 static void mlx5_pci_close(struct mlx5_core_dev *dev)
964 {
965 /* health work might still be active, and it needs pci bar in
966 * order to know the NIC state. Therefore, drain the health WQ
967 * before removing the pci bars
968 */
969 mlx5_drain_health_wq(dev);
970 pci_disable_ptm(dev->pdev);
971 iounmap(dev->iseg);
972 release_bar(dev->pdev);
973 mlx5_pci_disable_device(dev);
974 }
975
mlx5_init_once(struct mlx5_core_dev * dev)976 static int mlx5_init_once(struct mlx5_core_dev *dev)
977 {
978 int err;
979
980 dev->priv.devc = mlx5_devcom_register_device(dev);
981 if (!dev->priv.devc)
982 mlx5_core_warn(dev, "failed to register devcom device\n");
983
984 err = mlx5_query_board_id(dev);
985 if (err) {
986 mlx5_core_err(dev, "query board id failed\n");
987 goto err_devcom;
988 }
989
990 err = mlx5_irq_table_init(dev);
991 if (err) {
992 mlx5_core_err(dev, "failed to initialize irq table\n");
993 goto err_devcom;
994 }
995
996 err = mlx5_eq_table_init(dev);
997 if (err) {
998 mlx5_core_err(dev, "failed to initialize eq\n");
999 goto err_irq_cleanup;
1000 }
1001
1002 err = mlx5_events_init(dev);
1003 if (err) {
1004 mlx5_core_err(dev, "failed to initialize events\n");
1005 goto err_eq_cleanup;
1006 }
1007
1008 err = mlx5_fw_reset_init(dev);
1009 if (err) {
1010 mlx5_core_err(dev, "failed to initialize fw reset events\n");
1011 goto err_events_cleanup;
1012 }
1013
1014 mlx5_cq_debugfs_init(dev);
1015
1016 mlx5_init_reserved_gids(dev);
1017
1018 err = mlx5_init_clock(dev);
1019 if (err) {
1020 mlx5_core_err(dev, "failed to initialize hardware clock\n");
1021 goto err_tables_cleanup;
1022 }
1023
1024 dev->vxlan = mlx5_vxlan_create(dev);
1025 dev->geneve = mlx5_geneve_create(dev);
1026
1027 err = mlx5_init_rl_table(dev);
1028 if (err) {
1029 mlx5_core_err(dev, "Failed to init rate limiting\n");
1030 goto err_clock_cleanup;
1031 }
1032
1033 err = mlx5_mpfs_init(dev);
1034 if (err) {
1035 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
1036 goto err_rl_cleanup;
1037 }
1038
1039 err = mlx5_sriov_init(dev);
1040 if (err) {
1041 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
1042 goto err_mpfs_cleanup;
1043 }
1044
1045 err = mlx5_eswitch_init(dev);
1046 if (err) {
1047 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
1048 goto err_sriov_cleanup;
1049 }
1050
1051 err = mlx5_fpga_init(dev);
1052 if (err) {
1053 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
1054 goto err_eswitch_cleanup;
1055 }
1056
1057 err = mlx5_vhca_event_init(dev);
1058 if (err) {
1059 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
1060 goto err_fpga_cleanup;
1061 }
1062
1063 err = mlx5_sf_hw_table_init(dev);
1064 if (err) {
1065 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
1066 goto err_sf_hw_table_cleanup;
1067 }
1068
1069 err = mlx5_sf_table_init(dev);
1070 if (err) {
1071 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
1072 goto err_sf_table_cleanup;
1073 }
1074
1075 err = mlx5_fs_core_alloc(dev);
1076 if (err) {
1077 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1078 goto err_fs;
1079 }
1080
1081 dev->dm = mlx5_dm_create(dev);
1082 dev->st = mlx5_st_create(dev);
1083 dev->tracer = mlx5_fw_tracer_create(dev);
1084 dev->hv_vhca = mlx5_hv_vhca_create(dev);
1085 dev->rsc_dump = mlx5_rsc_dump_create(dev);
1086
1087 return 0;
1088
1089 err_fs:
1090 mlx5_sf_table_cleanup(dev);
1091 err_sf_table_cleanup:
1092 mlx5_sf_hw_table_cleanup(dev);
1093 err_sf_hw_table_cleanup:
1094 mlx5_vhca_event_cleanup(dev);
1095 err_fpga_cleanup:
1096 mlx5_fpga_cleanup(dev);
1097 err_eswitch_cleanup:
1098 mlx5_eswitch_cleanup(dev->priv.eswitch);
1099 err_sriov_cleanup:
1100 mlx5_sriov_cleanup(dev);
1101 err_mpfs_cleanup:
1102 mlx5_mpfs_cleanup(dev);
1103 err_rl_cleanup:
1104 mlx5_cleanup_rl_table(dev);
1105 err_clock_cleanup:
1106 mlx5_geneve_destroy(dev->geneve);
1107 mlx5_vxlan_destroy(dev->vxlan);
1108 mlx5_cleanup_clock(dev);
1109 err_tables_cleanup:
1110 mlx5_cleanup_reserved_gids(dev);
1111 mlx5_cq_debugfs_cleanup(dev);
1112 mlx5_fw_reset_cleanup(dev);
1113 err_events_cleanup:
1114 mlx5_events_cleanup(dev);
1115 err_eq_cleanup:
1116 mlx5_eq_table_cleanup(dev);
1117 err_irq_cleanup:
1118 mlx5_irq_table_cleanup(dev);
1119 err_devcom:
1120 mlx5_devcom_unregister_device(dev->priv.devc);
1121
1122 return err;
1123 }
1124
mlx5_cleanup_once(struct mlx5_core_dev * dev)1125 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1126 {
1127 mlx5_rsc_dump_destroy(dev);
1128 mlx5_hv_vhca_destroy(dev->hv_vhca);
1129 mlx5_fw_tracer_destroy(dev->tracer);
1130 mlx5_st_destroy(dev);
1131 mlx5_dm_cleanup(dev);
1132 mlx5_fs_core_free(dev);
1133 mlx5_sf_table_cleanup(dev);
1134 mlx5_sf_hw_table_cleanup(dev);
1135 mlx5_vhca_event_cleanup(dev);
1136 mlx5_fpga_cleanup(dev);
1137 mlx5_eswitch_cleanup(dev->priv.eswitch);
1138 mlx5_sriov_cleanup(dev);
1139 mlx5_mpfs_cleanup(dev);
1140 mlx5_cleanup_rl_table(dev);
1141 mlx5_geneve_destroy(dev->geneve);
1142 mlx5_vxlan_destroy(dev->vxlan);
1143 mlx5_cleanup_clock(dev);
1144 mlx5_cleanup_reserved_gids(dev);
1145 mlx5_cq_debugfs_cleanup(dev);
1146 mlx5_fw_reset_cleanup(dev);
1147 mlx5_events_cleanup(dev);
1148 mlx5_eq_table_cleanup(dev);
1149 mlx5_irq_table_cleanup(dev);
1150 mlx5_devcom_unregister_device(dev->priv.devc);
1151 }
1152
mlx5_function_enable(struct mlx5_core_dev * dev,bool boot,u64 timeout)1153 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1154 {
1155 int err;
1156
1157 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1158 fw_rev_min(dev), fw_rev_sub(dev));
1159
1160 /* Only PFs hold the relevant PCIe information for this query */
1161 if (mlx5_core_is_pf(dev))
1162 pcie_print_link_status(dev->pdev);
1163
1164 /* wait for firmware to accept initialization segments configurations
1165 */
1166 err = wait_fw_init(dev, timeout,
1167 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL),
1168 "pre-initializing");
1169 if (err)
1170 return err;
1171
1172 err = mlx5_cmd_enable(dev);
1173 if (err) {
1174 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1175 return err;
1176 }
1177
1178 mlx5_tout_query_iseg(dev);
1179
1180 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing");
1181 if (err)
1182 goto err_cmd_cleanup;
1183
1184 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1185 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1186
1187 err = mlx5_core_enable_hca(dev, 0);
1188 if (err) {
1189 mlx5_core_err(dev, "enable hca failed\n");
1190 goto err_cmd_cleanup;
1191 }
1192
1193 mlx5_start_health_poll(dev);
1194
1195 err = mlx5_core_set_issi(dev);
1196 if (err) {
1197 mlx5_core_err(dev, "failed to set issi\n");
1198 goto stop_health_poll;
1199 }
1200
1201 err = mlx5_satisfy_startup_pages(dev, 1);
1202 if (err) {
1203 mlx5_core_err(dev, "failed to allocate boot pages\n");
1204 goto stop_health_poll;
1205 }
1206
1207 err = mlx5_tout_query_dtor(dev);
1208 if (err) {
1209 mlx5_core_err(dev, "failed to read dtor\n");
1210 goto reclaim_boot_pages;
1211 }
1212
1213 return 0;
1214
1215 reclaim_boot_pages:
1216 mlx5_reclaim_startup_pages(dev);
1217 stop_health_poll:
1218 mlx5_stop_health_poll(dev, boot);
1219 mlx5_core_disable_hca(dev, 0);
1220 err_cmd_cleanup:
1221 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1222 mlx5_cmd_disable(dev);
1223
1224 return err;
1225 }
1226
mlx5_function_disable(struct mlx5_core_dev * dev,bool boot)1227 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot)
1228 {
1229 mlx5_reclaim_startup_pages(dev);
1230 mlx5_stop_health_poll(dev, boot);
1231 mlx5_core_disable_hca(dev, 0);
1232 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1233 mlx5_cmd_disable(dev);
1234 }
1235
mlx5_function_open(struct mlx5_core_dev * dev)1236 static int mlx5_function_open(struct mlx5_core_dev *dev)
1237 {
1238 int err;
1239
1240 err = set_hca_ctrl(dev);
1241 if (err) {
1242 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1243 return err;
1244 }
1245
1246 err = set_hca_cap(dev);
1247 if (err) {
1248 mlx5_core_err(dev, "set_hca_cap failed\n");
1249 return err;
1250 }
1251
1252 err = mlx5_satisfy_startup_pages(dev, 0);
1253 if (err) {
1254 mlx5_core_err(dev, "failed to allocate init pages\n");
1255 return err;
1256 }
1257
1258 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1259 if (err) {
1260 mlx5_core_err(dev, "init hca failed\n");
1261 return err;
1262 }
1263
1264 mlx5_set_driver_version(dev);
1265
1266 err = mlx5_query_hca_caps(dev);
1267 if (err) {
1268 mlx5_core_err(dev, "query hca failed\n");
1269 return err;
1270 }
1271 mlx5_start_health_fw_log_up(dev);
1272 return 0;
1273 }
1274
mlx5_function_close(struct mlx5_core_dev * dev)1275 static int mlx5_function_close(struct mlx5_core_dev *dev)
1276 {
1277 int err;
1278
1279 err = mlx5_cmd_teardown_hca(dev);
1280 if (err) {
1281 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1282 return err;
1283 }
1284
1285 return 0;
1286 }
1287
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot,u64 timeout)1288 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout)
1289 {
1290 int err;
1291
1292 err = mlx5_function_enable(dev, boot, timeout);
1293 if (err)
1294 return err;
1295
1296 err = mlx5_function_open(dev);
1297 if (err)
1298 mlx5_function_disable(dev, boot);
1299 return err;
1300 }
1301
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1302 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1303 {
1304 int err = mlx5_function_close(dev);
1305
1306 if (!err)
1307 mlx5_function_disable(dev, boot);
1308 else
1309 mlx5_stop_health_poll(dev, boot);
1310
1311 return err;
1312 }
1313
mlx5_load(struct mlx5_core_dev * dev)1314 static int mlx5_load(struct mlx5_core_dev *dev)
1315 {
1316 int err;
1317
1318 err = mlx5_alloc_bfreg(dev, &dev->priv.bfreg, false, false);
1319 if (err) {
1320 mlx5_core_err(dev, "Failed allocating bfreg, %d\n", err);
1321 return err;
1322 }
1323
1324 mlx5_events_start(dev);
1325 mlx5_pagealloc_start(dev);
1326
1327 err = mlx5_irq_table_create(dev);
1328 if (err) {
1329 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1330 goto err_irq_table;
1331 }
1332
1333 err = mlx5_eq_table_create(dev);
1334 if (err) {
1335 mlx5_core_err(dev, "Failed to create EQs\n");
1336 goto err_eq_table;
1337 }
1338
1339 mlx5_clock_load(dev);
1340
1341 err = mlx5_fw_tracer_init(dev->tracer);
1342 if (err) {
1343 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1344 mlx5_fw_tracer_destroy(dev->tracer);
1345 dev->tracer = NULL;
1346 }
1347
1348 mlx5_fw_reset_events_start(dev);
1349 mlx5_hv_vhca_init(dev->hv_vhca);
1350
1351 err = mlx5_rsc_dump_init(dev);
1352 if (err) {
1353 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1354 mlx5_rsc_dump_destroy(dev);
1355 dev->rsc_dump = NULL;
1356 }
1357
1358 err = mlx5_fpga_device_start(dev);
1359 if (err) {
1360 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1361 goto err_fpga_start;
1362 }
1363
1364 err = mlx5_fs_core_init(dev);
1365 if (err) {
1366 mlx5_core_err(dev, "Failed to init flow steering\n");
1367 goto err_fs;
1368 }
1369
1370 err = mlx5_core_set_hca_defaults(dev);
1371 if (err) {
1372 mlx5_core_err(dev, "Failed to set hca defaults\n");
1373 goto err_set_hca;
1374 }
1375
1376 mlx5_vhca_event_start(dev);
1377
1378 err = mlx5_sf_hw_table_create(dev);
1379 if (err) {
1380 mlx5_core_err(dev, "sf table create failed %d\n", err);
1381 goto err_vhca;
1382 }
1383
1384 err = mlx5_ec_init(dev);
1385 if (err) {
1386 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1387 goto err_ec;
1388 }
1389
1390 mlx5_lag_add_mdev(dev);
1391 err = mlx5_sriov_attach(dev);
1392 if (err) {
1393 mlx5_core_err(dev, "sriov init failed %d\n", err);
1394 goto err_sriov;
1395 }
1396
1397 mlx5_sf_dev_table_create(dev);
1398
1399 err = mlx5_devlink_traps_register(priv_to_devlink(dev));
1400 if (err)
1401 goto err_traps_reg;
1402
1403 return 0;
1404
1405 err_traps_reg:
1406 mlx5_sf_dev_table_destroy(dev);
1407 mlx5_sriov_detach(dev);
1408 err_sriov:
1409 mlx5_lag_remove_mdev(dev);
1410 mlx5_ec_cleanup(dev);
1411 err_ec:
1412 mlx5_sf_hw_table_destroy(dev);
1413 err_vhca:
1414 mlx5_vhca_event_stop(dev);
1415 err_set_hca:
1416 mlx5_fs_core_cleanup(dev);
1417 err_fs:
1418 mlx5_fpga_device_stop(dev);
1419 err_fpga_start:
1420 mlx5_rsc_dump_cleanup(dev);
1421 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1422 mlx5_fw_reset_events_stop(dev);
1423 mlx5_fw_tracer_cleanup(dev->tracer);
1424 mlx5_clock_unload(dev);
1425 mlx5_eq_table_destroy(dev);
1426 err_eq_table:
1427 mlx5_irq_table_destroy(dev);
1428 err_irq_table:
1429 mlx5_pagealloc_stop(dev);
1430 mlx5_events_stop(dev);
1431 mlx5_free_bfreg(dev, &dev->priv.bfreg);
1432 return err;
1433 }
1434
mlx5_unload(struct mlx5_core_dev * dev)1435 static void mlx5_unload(struct mlx5_core_dev *dev)
1436 {
1437 mlx5_eswitch_disable(dev->priv.eswitch);
1438 mlx5_devlink_traps_unregister(priv_to_devlink(dev));
1439 mlx5_sf_dev_table_destroy(dev);
1440 mlx5_sriov_detach(dev);
1441 mlx5_lag_remove_mdev(dev);
1442 mlx5_ec_cleanup(dev);
1443 mlx5_sf_hw_table_destroy(dev);
1444 mlx5_vhca_event_stop(dev);
1445 mlx5_fs_core_cleanup(dev);
1446 mlx5_fpga_device_stop(dev);
1447 mlx5_rsc_dump_cleanup(dev);
1448 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1449 mlx5_fw_reset_events_stop(dev);
1450 mlx5_fw_tracer_cleanup(dev->tracer);
1451 mlx5_clock_unload(dev);
1452 mlx5_eq_table_destroy(dev);
1453 mlx5_irq_table_destroy(dev);
1454 mlx5_pagealloc_stop(dev);
1455 mlx5_events_stop(dev);
1456 mlx5_free_bfreg(dev, &dev->priv.bfreg);
1457 }
1458
mlx5_init_one_devl_locked(struct mlx5_core_dev * dev)1459 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev)
1460 {
1461 bool light_probe = mlx5_dev_is_lightweight(dev);
1462 int err = 0;
1463
1464 mutex_lock(&dev->intf_state_mutex);
1465 dev->state = MLX5_DEVICE_STATE_UP;
1466
1467 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1468 if (err)
1469 goto err_function;
1470
1471 err = mlx5_init_once(dev);
1472 if (err) {
1473 mlx5_core_err(dev, "sw objs init failed\n");
1474 goto function_teardown;
1475 }
1476
1477 /* In case of light_probe, mlx5_devlink is already registered.
1478 * Hence, don't register devlink again.
1479 */
1480 if (!light_probe) {
1481 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1482 if (err)
1483 goto err_devlink_params_reg;
1484 }
1485
1486 err = mlx5_load(dev);
1487 if (err)
1488 goto err_load;
1489
1490 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1491
1492 err = mlx5_register_device(dev);
1493 if (err)
1494 goto err_register;
1495
1496 err = mlx5_crdump_enable(dev);
1497 if (err)
1498 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err);
1499
1500 err = mlx5_hwmon_dev_register(dev);
1501 if (err)
1502 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err);
1503
1504 mutex_unlock(&dev->intf_state_mutex);
1505 return 0;
1506
1507 err_register:
1508 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1509 mlx5_unload(dev);
1510 err_load:
1511 if (!light_probe)
1512 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1513 err_devlink_params_reg:
1514 mlx5_cleanup_once(dev);
1515 function_teardown:
1516 mlx5_function_teardown(dev, true);
1517 err_function:
1518 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1519 mutex_unlock(&dev->intf_state_mutex);
1520 return err;
1521 }
1522
mlx5_init_one(struct mlx5_core_dev * dev)1523 int mlx5_init_one(struct mlx5_core_dev *dev)
1524 {
1525 struct devlink *devlink = priv_to_devlink(dev);
1526 int err;
1527
1528 devl_lock(devlink);
1529 devl_register(devlink);
1530 err = mlx5_init_one_devl_locked(dev);
1531 if (err)
1532 devl_unregister(devlink);
1533 devl_unlock(devlink);
1534 return err;
1535 }
1536
mlx5_uninit_one(struct mlx5_core_dev * dev)1537 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1538 {
1539 struct devlink *devlink = priv_to_devlink(dev);
1540
1541 devl_lock(devlink);
1542 mutex_lock(&dev->intf_state_mutex);
1543
1544 mlx5_hwmon_dev_unregister(dev);
1545 mlx5_crdump_disable(dev);
1546 mlx5_unregister_device(dev);
1547
1548 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1549 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1550 __func__);
1551 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1552 mlx5_cleanup_once(dev);
1553 goto out;
1554 }
1555
1556 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1557 mlx5_unload(dev);
1558 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1559 mlx5_cleanup_once(dev);
1560 mlx5_function_teardown(dev, true);
1561 out:
1562 mutex_unlock(&dev->intf_state_mutex);
1563 devl_unregister(devlink);
1564 devl_unlock(devlink);
1565 }
1566
mlx5_load_one_devl_locked(struct mlx5_core_dev * dev,bool recovery)1567 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery)
1568 {
1569 int err = 0;
1570 u64 timeout;
1571
1572 devl_assert_locked(priv_to_devlink(dev));
1573 mutex_lock(&dev->intf_state_mutex);
1574 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1575 mlx5_core_warn(dev, "interface is up, NOP\n");
1576 goto out;
1577 }
1578 /* remove any previous indication of internal error */
1579 dev->state = MLX5_DEVICE_STATE_UP;
1580
1581 if (recovery)
1582 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT);
1583 else
1584 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT);
1585 err = mlx5_function_setup(dev, false, timeout);
1586 if (err)
1587 goto err_function;
1588
1589 err = mlx5_load(dev);
1590 if (err)
1591 goto err_load;
1592
1593 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1594
1595 err = mlx5_attach_device(dev);
1596 if (err)
1597 goto err_attach;
1598
1599 mutex_unlock(&dev->intf_state_mutex);
1600 return 0;
1601
1602 err_attach:
1603 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1604 mlx5_unload(dev);
1605 err_load:
1606 mlx5_function_teardown(dev, false);
1607 err_function:
1608 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1609 out:
1610 mutex_unlock(&dev->intf_state_mutex);
1611 return err;
1612 }
1613
mlx5_load_one(struct mlx5_core_dev * dev,bool recovery)1614 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery)
1615 {
1616 struct devlink *devlink = priv_to_devlink(dev);
1617 int ret;
1618
1619 devl_lock(devlink);
1620 ret = mlx5_load_one_devl_locked(dev, recovery);
1621 devl_unlock(devlink);
1622 return ret;
1623 }
1624
mlx5_unload_one_devl_locked(struct mlx5_core_dev * dev,bool suspend)1625 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend)
1626 {
1627 devl_assert_locked(priv_to_devlink(dev));
1628 mutex_lock(&dev->intf_state_mutex);
1629
1630 mlx5_detach_device(dev, suspend);
1631
1632 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1633 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1634 __func__);
1635 goto out;
1636 }
1637
1638 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1639 mlx5_unload(dev);
1640 mlx5_function_teardown(dev, false);
1641 out:
1642 mutex_unlock(&dev->intf_state_mutex);
1643 }
1644
mlx5_unload_one(struct mlx5_core_dev * dev,bool suspend)1645 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend)
1646 {
1647 struct devlink *devlink = priv_to_devlink(dev);
1648
1649 devl_lock(devlink);
1650 mlx5_unload_one_devl_locked(dev, suspend);
1651 devl_unlock(devlink);
1652 }
1653
1654 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps.
1655 * A full query of hca_caps will be done when the device will reload.
1656 */
mlx5_query_hca_caps_light(struct mlx5_core_dev * dev)1657 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev)
1658 {
1659 int err;
1660
1661 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
1662 if (err)
1663 return err;
1664
1665 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
1666 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
1667 HCA_CAP_OPMOD_GET_CUR);
1668 if (err)
1669 return err;
1670 }
1671
1672 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
1673 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
1674 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE,
1675 HCA_CAP_OPMOD_GET_CUR);
1676 if (err)
1677 return err;
1678 }
1679
1680 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
1681 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
1682 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION,
1683 HCA_CAP_OPMOD_GET_CUR);
1684 if (err)
1685 return err;
1686 }
1687
1688 return 0;
1689 }
1690
mlx5_init_one_light(struct mlx5_core_dev * dev)1691 int mlx5_init_one_light(struct mlx5_core_dev *dev)
1692 {
1693 struct devlink *devlink = priv_to_devlink(dev);
1694 int err;
1695
1696 devl_lock(devlink);
1697 devl_register(devlink);
1698 dev->state = MLX5_DEVICE_STATE_UP;
1699 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1700 if (err) {
1701 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err);
1702 goto out;
1703 }
1704
1705 err = mlx5_query_hca_caps_light(dev);
1706 if (err) {
1707 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err);
1708 goto query_hca_caps_err;
1709 }
1710
1711 err = mlx5_devlink_params_register(priv_to_devlink(dev));
1712 if (err) {
1713 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err);
1714 goto query_hca_caps_err;
1715 }
1716
1717 devl_unlock(devlink);
1718 return 0;
1719
1720 query_hca_caps_err:
1721 mlx5_function_disable(dev, true);
1722 out:
1723 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1724 devl_unregister(devlink);
1725 devl_unlock(devlink);
1726 return err;
1727 }
1728
mlx5_uninit_one_light(struct mlx5_core_dev * dev)1729 void mlx5_uninit_one_light(struct mlx5_core_dev *dev)
1730 {
1731 struct devlink *devlink = priv_to_devlink(dev);
1732
1733 devl_lock(devlink);
1734 mlx5_devlink_params_unregister(priv_to_devlink(dev));
1735 devl_unregister(devlink);
1736 devl_unlock(devlink);
1737 if (dev->state != MLX5_DEVICE_STATE_UP)
1738 return;
1739 mlx5_function_disable(dev, true);
1740 }
1741
1742 /* xxx_light() function are used in order to configure the device without full
1743 * init (light init). e.g.: There isn't a point in reload a device to light state.
1744 * Hence, mlx5_load_one_light() isn't needed.
1745 */
1746
mlx5_unload_one_light(struct mlx5_core_dev * dev)1747 void mlx5_unload_one_light(struct mlx5_core_dev *dev)
1748 {
1749 if (dev->state != MLX5_DEVICE_STATE_UP)
1750 return;
1751 mlx5_function_disable(dev, false);
1752 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1753 }
1754
1755 static const int types[] = {
1756 MLX5_CAP_GENERAL,
1757 MLX5_CAP_GENERAL_2,
1758 MLX5_CAP_ETHERNET_OFFLOADS,
1759 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1760 MLX5_CAP_ODP,
1761 MLX5_CAP_ATOMIC,
1762 MLX5_CAP_ROCE,
1763 MLX5_CAP_IPOIB_OFFLOADS,
1764 MLX5_CAP_FLOW_TABLE,
1765 MLX5_CAP_ESWITCH_FLOW_TABLE,
1766 MLX5_CAP_ESWITCH,
1767 MLX5_CAP_QOS,
1768 MLX5_CAP_DEBUG,
1769 MLX5_CAP_DEV_MEM,
1770 MLX5_CAP_DEV_EVENT,
1771 MLX5_CAP_TLS,
1772 MLX5_CAP_VDPA_EMULATION,
1773 MLX5_CAP_IPSEC,
1774 MLX5_CAP_PORT_SELECTION,
1775 MLX5_CAP_PSP,
1776 MLX5_CAP_MACSEC,
1777 MLX5_CAP_ADV_VIRTUALIZATION,
1778 MLX5_CAP_CRYPTO,
1779 MLX5_CAP_SHAMPO,
1780 MLX5_CAP_ADV_RDMA,
1781 };
1782
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1783 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1784 {
1785 int type;
1786 int i;
1787
1788 for (i = 0; i < ARRAY_SIZE(types); i++) {
1789 type = types[i];
1790 kfree(dev->caps.hca[type]);
1791 }
1792 }
1793
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1794 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1795 {
1796 struct mlx5_hca_cap *cap;
1797 int type;
1798 int i;
1799
1800 for (i = 0; i < ARRAY_SIZE(types); i++) {
1801 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1802 if (!cap)
1803 goto err;
1804 type = types[i];
1805 dev->caps.hca[type] = cap;
1806 }
1807
1808 return 0;
1809
1810 err:
1811 mlx5_hca_caps_free(dev);
1812 return -ENOMEM;
1813 }
1814
vhca_id_show(struct seq_file * file,void * priv)1815 static int vhca_id_show(struct seq_file *file, void *priv)
1816 {
1817 struct mlx5_core_dev *dev = file->private;
1818
1819 seq_printf(file, "0x%x\n", MLX5_CAP_GEN(dev, vhca_id));
1820 return 0;
1821 }
1822
1823 DEFINE_SHOW_ATTRIBUTE(vhca_id);
1824
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1825 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1826 {
1827 struct mlx5_priv *priv = &dev->priv;
1828 int err;
1829
1830 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1831 lockdep_register_key(&dev->lock_key);
1832 mutex_init(&dev->intf_state_mutex);
1833 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1834 mutex_init(&dev->mlx5e_res.uplink_netdev_lock);
1835 mutex_init(&dev->wc_state_lock);
1836
1837 mutex_init(&priv->bfregs.reg_head.lock);
1838 mutex_init(&priv->bfregs.wc_head.lock);
1839 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1840 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1841
1842 mutex_init(&priv->alloc_mutex);
1843 mutex_init(&priv->pgdir_mutex);
1844 INIT_LIST_HEAD(&priv->pgdir_list);
1845
1846 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1847 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1848 mlx5_debugfs_root);
1849 debugfs_create_file("vhca_id", 0400, priv->dbg.dbg_root, dev, &vhca_id_fops);
1850 INIT_LIST_HEAD(&priv->traps);
1851
1852 err = mlx5_cmd_init(dev);
1853 if (err) {
1854 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n");
1855 goto err_cmd_init;
1856 }
1857
1858 err = mlx5_tout_init(dev);
1859 if (err) {
1860 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1861 goto err_timeout_init;
1862 }
1863
1864 err = mlx5_health_init(dev);
1865 if (err)
1866 goto err_health_init;
1867
1868 err = mlx5_pagealloc_init(dev);
1869 if (err)
1870 goto err_pagealloc_init;
1871
1872 err = mlx5_adev_init(dev);
1873 if (err)
1874 goto err_adev_init;
1875
1876 err = mlx5_hca_caps_alloc(dev);
1877 if (err)
1878 goto err_hca_caps;
1879
1880 /* The conjunction of sw_vhca_id with sw_owner_id will be a global
1881 * unique id per function which uses mlx5_core.
1882 * Those values are supplied to FW as part of the init HCA command to
1883 * be used by both driver and FW when it's applicable.
1884 */
1885 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1,
1886 MAX_SW_VHCA_ID,
1887 GFP_KERNEL);
1888 if (dev->priv.sw_vhca_id < 0)
1889 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n",
1890 dev->priv.sw_vhca_id);
1891
1892 return 0;
1893
1894 err_hca_caps:
1895 mlx5_adev_cleanup(dev);
1896 err_adev_init:
1897 mlx5_pagealloc_cleanup(dev);
1898 err_pagealloc_init:
1899 mlx5_health_cleanup(dev);
1900 err_health_init:
1901 mlx5_tout_cleanup(dev);
1902 err_timeout_init:
1903 mlx5_cmd_cleanup(dev);
1904 err_cmd_init:
1905 debugfs_remove(dev->priv.dbg.dbg_root);
1906 mutex_destroy(&priv->pgdir_mutex);
1907 mutex_destroy(&priv->alloc_mutex);
1908 mutex_destroy(&priv->bfregs.wc_head.lock);
1909 mutex_destroy(&priv->bfregs.reg_head.lock);
1910 mutex_destroy(&dev->intf_state_mutex);
1911 lockdep_unregister_key(&dev->lock_key);
1912 return err;
1913 }
1914
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1915 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1916 {
1917 struct mlx5_priv *priv = &dev->priv;
1918
1919 if (priv->sw_vhca_id > 0)
1920 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id);
1921
1922 mlx5_hca_caps_free(dev);
1923 mlx5_adev_cleanup(dev);
1924 mlx5_pagealloc_cleanup(dev);
1925 mlx5_health_cleanup(dev);
1926 mlx5_tout_cleanup(dev);
1927 mlx5_cmd_cleanup(dev);
1928 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1929 mutex_destroy(&priv->pgdir_mutex);
1930 mutex_destroy(&priv->alloc_mutex);
1931 mutex_destroy(&priv->bfregs.wc_head.lock);
1932 mutex_destroy(&priv->bfregs.reg_head.lock);
1933 mutex_destroy(&dev->wc_state_lock);
1934 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock);
1935 mutex_destroy(&dev->intf_state_mutex);
1936 lockdep_unregister_key(&dev->lock_key);
1937 }
1938
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1939 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1940 {
1941 struct mlx5_core_dev *dev;
1942 struct devlink *devlink;
1943 int err;
1944
1945 devlink = mlx5_devlink_alloc(&pdev->dev);
1946 if (!devlink) {
1947 dev_err(&pdev->dev, "devlink alloc failed\n");
1948 return -ENOMEM;
1949 }
1950
1951 dev = devlink_priv(devlink);
1952 dev->device = &pdev->dev;
1953 dev->pdev = pdev;
1954
1955 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1956 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1957
1958 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1959 if (dev->priv.adev_idx < 0) {
1960 err = dev->priv.adev_idx;
1961 goto adev_init_err;
1962 }
1963
1964 err = mlx5_mdev_init(dev, prof_sel);
1965 if (err)
1966 goto mdev_init_err;
1967
1968 err = mlx5_pci_init(dev, pdev, id);
1969 if (err) {
1970 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1971 err);
1972 goto pci_init_err;
1973 }
1974
1975 err = mlx5_init_one(dev);
1976 if (err) {
1977 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1978 err);
1979 goto err_init_one;
1980 }
1981
1982 pci_save_state(pdev);
1983 return 0;
1984
1985 err_init_one:
1986 mlx5_pci_close(dev);
1987 pci_init_err:
1988 mlx5_mdev_uninit(dev);
1989 mdev_init_err:
1990 mlx5_adev_idx_free(dev->priv.adev_idx);
1991 adev_init_err:
1992 mlx5_devlink_free(devlink);
1993
1994 return err;
1995 }
1996
remove_one(struct pci_dev * pdev)1997 static void remove_one(struct pci_dev *pdev)
1998 {
1999 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2000 struct devlink *devlink = priv_to_devlink(dev);
2001
2002 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2003 mlx5_drain_fw_reset(dev);
2004 mlx5_drain_health_wq(dev);
2005 mlx5_sriov_disable(pdev, false);
2006 mlx5_uninit_one(dev);
2007 mlx5_pci_close(dev);
2008 mlx5_mdev_uninit(dev);
2009 mlx5_adev_idx_free(dev->priv.adev_idx);
2010 mlx5_devlink_free(devlink);
2011 }
2012
2013 #define mlx5_pci_trace(dev, fmt, ...) ({ \
2014 struct mlx5_core_dev *__dev = (dev); \
2015 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
2016 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
2017 __dev->pci_status, ##__VA_ARGS__); \
2018 })
2019
result2str(enum pci_ers_result result)2020 static const char *result2str(enum pci_ers_result result)
2021 {
2022 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
2023 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
2024 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
2025 "unknown";
2026 }
2027
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)2028 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
2029 pci_channel_state_t state)
2030 {
2031 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2032 enum pci_ers_result res;
2033
2034 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
2035
2036 mlx5_enter_error_state(dev, false);
2037 mlx5_error_sw_reset(dev);
2038 mlx5_unload_one(dev, false);
2039 mlx5_drain_health_wq(dev);
2040 mlx5_pci_disable_device(dev);
2041
2042 res = state == pci_channel_io_perm_failure ?
2043 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2044
2045 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
2046 __func__, dev->state, dev->pci_status, res, result2str(res));
2047 return res;
2048 }
2049
2050 /* wait for the device to show vital signs by waiting
2051 * for the health counter to start counting.
2052 */
wait_vital(struct pci_dev * pdev)2053 static int wait_vital(struct pci_dev *pdev)
2054 {
2055 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2056 struct mlx5_core_health *health = &dev->priv.health;
2057 const int niter = 100;
2058 u32 last_count = 0;
2059 u32 count;
2060 int i;
2061
2062 for (i = 0; i < niter; i++) {
2063 count = ioread32be(health->health_counter);
2064 if (count && count != 0xffffffff) {
2065 if (last_count && last_count != count) {
2066 mlx5_core_info(dev,
2067 "wait vital counter value 0x%x after %d iterations\n",
2068 count, i);
2069 return 0;
2070 }
2071 last_count = count;
2072 }
2073 msleep(50);
2074 }
2075
2076 return -ETIMEDOUT;
2077 }
2078
mlx5_pci_slot_reset(struct pci_dev * pdev)2079 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
2080 {
2081 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
2082 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2083 int err;
2084
2085 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
2086 __func__, dev->state, dev->pci_status);
2087
2088 err = mlx5_pci_enable_device(dev);
2089 if (err) {
2090 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
2091 __func__, err);
2092 goto out;
2093 }
2094
2095 pci_set_master(pdev);
2096 pci_restore_state(pdev);
2097 pci_save_state(pdev);
2098
2099 err = wait_vital(pdev);
2100 if (err) {
2101 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
2102 __func__, err);
2103 goto out;
2104 }
2105
2106 res = PCI_ERS_RESULT_RECOVERED;
2107 out:
2108 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
2109 __func__, dev->state, dev->pci_status, err, res, result2str(res));
2110 return res;
2111 }
2112
mlx5_pci_resume(struct pci_dev * pdev)2113 static void mlx5_pci_resume(struct pci_dev *pdev)
2114 {
2115 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2116 int err;
2117
2118 mlx5_pci_trace(dev, "Enter, loading driver..\n");
2119
2120 err = mlx5_load_one(dev, false);
2121
2122 if (!err)
2123 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
2124 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2125
2126 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
2127 !err ? "recovered" : "Failed");
2128 }
2129
2130 static const struct pci_error_handlers mlx5_err_handler = {
2131 .error_detected = mlx5_pci_err_detected,
2132 .slot_reset = mlx5_pci_slot_reset,
2133 .resume = mlx5_pci_resume
2134 };
2135
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2136 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2137 {
2138 bool fast_teardown = false, force_teardown = false;
2139 int ret = 1;
2140
2141 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2142 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2143
2144 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2145 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2146
2147 if (!fast_teardown && !force_teardown)
2148 return -EOPNOTSUPP;
2149
2150 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2151 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2152 return -EAGAIN;
2153 }
2154
2155 /* Panic tear down fw command will stop the PCI bus communication
2156 * with the HCA, so the health poll is no longer needed.
2157 */
2158 mlx5_stop_health_poll(dev, false);
2159
2160 ret = mlx5_cmd_fast_teardown_hca(dev);
2161 if (!ret)
2162 goto succeed;
2163
2164 ret = mlx5_cmd_force_teardown_hca(dev);
2165 if (!ret)
2166 goto succeed;
2167
2168 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
2169 mlx5_start_health_poll(dev);
2170 return ret;
2171
2172 succeed:
2173 mlx5_enter_error_state(dev, true);
2174
2175 /* Some platforms requiring freeing the IRQ's in the shutdown
2176 * flow. If they aren't freed they can't be allocated after
2177 * kexec. There is no need to cleanup the mlx5_core software
2178 * contexts.
2179 */
2180 mlx5_core_eq_free_irqs(dev);
2181
2182 return 0;
2183 }
2184
shutdown(struct pci_dev * pdev)2185 static void shutdown(struct pci_dev *pdev)
2186 {
2187 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2188 int err;
2189
2190 mlx5_core_info(dev, "Shutdown was called\n");
2191 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state);
2192 mlx5_drain_health_wq(dev);
2193 err = mlx5_try_fast_unload(dev);
2194 if (err)
2195 mlx5_unload_one(dev, false);
2196 mlx5_pci_disable_device(dev);
2197 }
2198
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)2199 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
2200 {
2201 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2202
2203 mlx5_unload_one(dev, true);
2204
2205 return 0;
2206 }
2207
mlx5_resume(struct pci_dev * pdev)2208 static int mlx5_resume(struct pci_dev *pdev)
2209 {
2210 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2211
2212 return mlx5_load_one(dev, false);
2213 }
2214
2215 static const struct pci_device_id mlx5_core_pci_table[] = {
2216 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
2217 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2218 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
2219 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2220 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
2221 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2222 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
2223 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2224 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
2225 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2226 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
2227 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2228 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
2229 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2230 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
2231 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
2232 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
2233 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */
2234 { PCI_VDEVICE(MELLANOX, 0x1027) }, /* ConnectX-10 */
2235 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2236 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
2237 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2238 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2239 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2240 { 0, }
2241 };
2242
2243 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2244
mlx5_disable_device(struct mlx5_core_dev * dev)2245 void mlx5_disable_device(struct mlx5_core_dev *dev)
2246 {
2247 mlx5_error_sw_reset(dev);
2248 mlx5_unload_one_devl_locked(dev, false);
2249 }
2250
mlx5_recover_device(struct mlx5_core_dev * dev)2251 int mlx5_recover_device(struct mlx5_core_dev *dev)
2252 {
2253 if (!mlx5_core_is_sf(dev)) {
2254 mlx5_pci_disable_device(dev);
2255 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
2256 return -EIO;
2257 }
2258
2259 return mlx5_load_one_devl_locked(dev, true);
2260 }
2261
2262 static struct pci_driver mlx5_core_driver = {
2263 .name = KBUILD_MODNAME,
2264 .id_table = mlx5_core_pci_table,
2265 .probe = probe_one,
2266 .remove = remove_one,
2267 .suspend = mlx5_suspend,
2268 .resume = mlx5_resume,
2269 .shutdown = shutdown,
2270 .err_handler = &mlx5_err_handler,
2271 .sriov_configure = mlx5_core_sriov_configure,
2272 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
2273 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
2274 };
2275
2276 /**
2277 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
2278 * mlx5_core is its driver.
2279 * @pdev: The associated PCI device.
2280 *
2281 * Upon return the interface state lock stay held to let caller uses it safely.
2282 * Caller must ensure to use the returned mlx5 device for a narrow window
2283 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
2284 *
2285 * Return: Pointer to the associated mlx5_core_dev or NULL.
2286 */
mlx5_vf_get_core_dev(struct pci_dev * pdev)2287 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
2288 {
2289 struct mlx5_core_dev *mdev;
2290
2291 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
2292 if (IS_ERR(mdev))
2293 return NULL;
2294
2295 mutex_lock(&mdev->intf_state_mutex);
2296 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
2297 mutex_unlock(&mdev->intf_state_mutex);
2298 return NULL;
2299 }
2300
2301 return mdev;
2302 }
2303 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
2304
2305 /**
2306 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
2307 * @mdev: The mlx5 core device.
2308 *
2309 * Upon return the interface state lock is unlocked and caller should not
2310 * access the mdev any more.
2311 */
mlx5_vf_put_core_dev(struct mlx5_core_dev * mdev)2312 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
2313 {
2314 mutex_unlock(&mdev->intf_state_mutex);
2315 }
2316 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
2317
mlx5_core_verify_params(void)2318 static void mlx5_core_verify_params(void)
2319 {
2320 if (prof_sel >= ARRAY_SIZE(profile)) {
2321 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
2322 prof_sel,
2323 ARRAY_SIZE(profile) - 1,
2324 MLX5_DEFAULT_PROF);
2325 prof_sel = MLX5_DEFAULT_PROF;
2326 }
2327 }
2328
mlx5_init(void)2329 static int __init mlx5_init(void)
2330 {
2331 int err;
2332
2333 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
2334 "mlx5_core name not in sync with kernel module name");
2335
2336 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
2337
2338 mlx5_core_verify_params();
2339 mlx5_register_debugfs();
2340
2341 err = mlx5e_init();
2342 if (err)
2343 goto err_debug;
2344
2345 err = mlx5_sf_driver_register();
2346 if (err)
2347 goto err_sf;
2348
2349 err = pci_register_driver(&mlx5_core_driver);
2350 if (err)
2351 goto err_pci;
2352
2353 return 0;
2354
2355 err_pci:
2356 mlx5_sf_driver_unregister();
2357 err_sf:
2358 mlx5e_cleanup();
2359 err_debug:
2360 mlx5_unregister_debugfs();
2361 return err;
2362 }
2363
mlx5_cleanup(void)2364 static void __exit mlx5_cleanup(void)
2365 {
2366 pci_unregister_driver(&mlx5_core_driver);
2367 mlx5_sf_driver_unregister();
2368 mlx5e_cleanup();
2369 mlx5_unregister_debugfs();
2370 }
2371
2372 module_init(mlx5_init);
2373 module_exit(mlx5_cleanup);
2374