1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/interrupt.h> 41 #include <linux/delay.h> 42 #include <linux/mlx5/driver.h> 43 #include <linux/mlx5/data_direct.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #include <linux/version.h> 51 #include <net/devlink.h> 52 #include "mlx5_core.h" 53 #include "lib/eq.h" 54 #include "fs_core.h" 55 #include "lib/mpfs.h" 56 #include "eswitch.h" 57 #include "devlink.h" 58 #include "fw_reset.h" 59 #include "lib/mlx5.h" 60 #include "lib/tout.h" 61 #include "fpga/core.h" 62 #include "en_accel/ipsec.h" 63 #include "lib/clock.h" 64 #include "lib/vxlan.h" 65 #include "lib/geneve.h" 66 #include "lib/devcom.h" 67 #include "lib/pci_vsc.h" 68 #include "diag/fw_tracer.h" 69 #include "ecpf.h" 70 #include "lib/hv_vhca.h" 71 #include "diag/rsc_dump.h" 72 #include "sf/vhca_event.h" 73 #include "sf/dev/dev.h" 74 #include "sf/sf.h" 75 #include "mlx5_irq.h" 76 #include "hwmon.h" 77 #include "lag/lag.h" 78 #include "sh_devlink.h" 79 80 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 81 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 82 MODULE_LICENSE("Dual BSD/GPL"); 83 84 unsigned int mlx5_core_debug_mask; 85 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 86 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 87 88 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 89 module_param_named(prof_sel, prof_sel, uint, 0444); 90 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 91 92 static u32 sw_owner_id[4]; 93 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) 94 static DEFINE_IDA(sw_vhca_ida); 95 96 enum { 97 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 99 }; 100 101 #define LOG_MAX_SUPPORTED_QPS 0xff 102 103 static struct mlx5_profile profile[] = { 104 [0] = { 105 .mask = 0, 106 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 107 }, 108 [1] = { 109 .mask = MLX5_PROF_MASK_QP_SIZE, 110 .log_max_qp = 12, 111 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 112 113 }, 114 [2] = { 115 .mask = MLX5_PROF_MASK_QP_SIZE, 116 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 117 .num_cmd_caches = MLX5_NUM_COMMAND_CACHES, 118 }, 119 [3] = { 120 .mask = MLX5_PROF_MASK_QP_SIZE, 121 .log_max_qp = LOG_MAX_SUPPORTED_QPS, 122 .num_cmd_caches = 0, 123 }, 124 }; 125 126 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 127 u32 warn_time_mili, const char *init_state) 128 { 129 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 130 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 131 u32 fw_initializing; 132 133 do { 134 fw_initializing = ioread32be(&dev->iseg->initializing); 135 if (!(fw_initializing >> 31)) 136 break; 137 if (time_after(jiffies, end)) { 138 mlx5_core_err(dev, "Firmware over %u MS in %s state, aborting\n", 139 max_wait_mili, init_state); 140 return -ETIMEDOUT; 141 } 142 if (test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { 143 mlx5_core_warn(dev, "device is being removed, stop waiting for FW %s\n", 144 init_state); 145 return -ENODEV; 146 } 147 if (warn_time_mili && time_after(jiffies, warn)) { 148 mlx5_core_warn(dev, "Waiting for FW %s, timeout abort in %ds (0x%x)\n", 149 init_state, jiffies_to_msecs(end - warn) / 1000, 150 fw_initializing); 151 warn = jiffies + msecs_to_jiffies(warn_time_mili); 152 } 153 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); 154 } while (true); 155 156 return 0; 157 } 158 159 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 160 { 161 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 162 driver_version); 163 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 164 char *string; 165 166 if (!MLX5_CAP_GEN(dev, driver_version)) 167 return; 168 169 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 170 171 snprintf(string, driver_ver_sz, "Linux,%s,%u.%u.%u", 172 KBUILD_MODNAME, LINUX_VERSION_MAJOR, 173 LINUX_VERSION_PATCHLEVEL, LINUX_VERSION_SUBLEVEL); 174 175 /*Send the command*/ 176 MLX5_SET(set_driver_version_in, in, opcode, 177 MLX5_CMD_OP_SET_DRIVER_VERSION); 178 179 mlx5_cmd_exec_in(dev, set_driver_version, in); 180 } 181 182 static int set_dma_caps(struct pci_dev *pdev) 183 { 184 int err; 185 186 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 187 if (err) { 188 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 189 return err; 190 } 191 192 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 193 return err; 194 } 195 196 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 197 { 198 struct pci_dev *pdev = dev->pdev; 199 int err = 0; 200 201 mutex_lock(&dev->pci_status_mutex); 202 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 203 err = pci_enable_device(pdev); 204 if (!err) 205 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 206 } 207 mutex_unlock(&dev->pci_status_mutex); 208 209 return err; 210 } 211 212 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 213 { 214 struct pci_dev *pdev = dev->pdev; 215 216 mutex_lock(&dev->pci_status_mutex); 217 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 218 pci_disable_device(pdev); 219 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 220 } 221 mutex_unlock(&dev->pci_status_mutex); 222 } 223 224 static int request_bar(struct pci_dev *pdev) 225 { 226 int err = 0; 227 228 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 229 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 230 return -ENODEV; 231 } 232 233 err = pci_request_regions(pdev, KBUILD_MODNAME); 234 if (err) 235 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 236 237 return err; 238 } 239 240 static void release_bar(struct pci_dev *pdev) 241 { 242 pci_release_regions(pdev); 243 } 244 245 struct mlx5_reg_host_endianness { 246 u8 he; 247 u8 rsvd[15]; 248 }; 249 250 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 251 { 252 switch (size) { 253 case 128: 254 return 0; 255 case 256: 256 return 1; 257 case 512: 258 return 2; 259 case 1024: 260 return 3; 261 case 2048: 262 return 4; 263 case 4096: 264 return 5; 265 default: 266 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 267 return 0; 268 } 269 } 270 271 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *dev, struct net_device *netdev) 272 { 273 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 274 dev->mlx5e_res.uplink_netdev = netdev; 275 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 276 netdev); 277 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 278 } 279 280 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *dev) 281 { 282 mutex_lock(&dev->mlx5e_res.uplink_netdev_lock); 283 mlx5_blocking_notifier_call_chain(dev, MLX5_DRIVER_EVENT_UPLINK_NETDEV, 284 dev->mlx5e_res.uplink_netdev); 285 mutex_unlock(&dev->mlx5e_res.uplink_netdev_lock); 286 } 287 EXPORT_SYMBOL(mlx5_core_uplink_netdev_event_replay); 288 289 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data) 290 { 291 mlx5_blocking_notifier_call_chain(dev, event, data); 292 } 293 EXPORT_SYMBOL(mlx5_core_mp_event_replay); 294 295 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 296 enum mlx5_cap_mode cap_mode) 297 { 298 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 299 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 300 void *out, *hca_caps; 301 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 302 int err; 303 304 if (WARN_ON(!dev->caps.hca[cap_type])) 305 /* this cap_type must be added to mlx5_hca_caps_alloc() */ 306 return -EINVAL; 307 308 memset(in, 0, sizeof(in)); 309 out = kzalloc(out_sz, GFP_KERNEL); 310 if (!out) 311 return -ENOMEM; 312 313 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 314 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 315 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 316 if (err) { 317 mlx5_core_warn(dev, 318 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 319 cap_type, cap_mode, err); 320 goto query_ex; 321 } 322 323 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 324 325 switch (cap_mode) { 326 case HCA_CAP_OPMOD_GET_MAX: 327 memcpy(dev->caps.hca[cap_type]->max, hca_caps, 328 MLX5_UN_SZ_BYTES(hca_cap_union)); 329 break; 330 case HCA_CAP_OPMOD_GET_CUR: 331 memcpy(dev->caps.hca[cap_type]->cur, hca_caps, 332 MLX5_UN_SZ_BYTES(hca_cap_union)); 333 break; 334 default: 335 mlx5_core_warn(dev, 336 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 337 cap_type, cap_mode); 338 err = -EINVAL; 339 break; 340 } 341 query_ex: 342 kfree(out); 343 return err; 344 } 345 346 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 347 { 348 int ret; 349 350 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 351 if (ret) 352 return ret; 353 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 354 } 355 356 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 357 { 358 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 359 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 360 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 361 } 362 363 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 364 { 365 void *set_hca_cap; 366 int req_endianness; 367 int err; 368 369 if (!MLX5_CAP_GEN(dev, atomic)) 370 return 0; 371 372 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 373 if (err) 374 return err; 375 376 req_endianness = 377 MLX5_CAP_ATOMIC(dev, 378 supported_atomic_req_8B_endianness_mode_1); 379 380 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 381 return 0; 382 383 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 384 385 /* Set requestor to host endianness */ 386 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 387 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 388 389 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 390 } 391 392 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 393 { 394 bool do_set = false, mem_page_fault = false; 395 void *set_hca_cap; 396 int err; 397 398 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 399 !MLX5_CAP_GEN(dev, pg)) 400 return 0; 401 402 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 403 if (err) 404 return err; 405 406 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 407 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, 408 MLX5_ST_SZ_BYTES(odp_cap)); 409 410 /* For best performance, enable memory scheme ODP only when 411 * it has page prefetch enabled. 412 */ 413 if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) && 414 MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) { 415 mem_page_fault = true; 416 do_set = true; 417 MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault); 418 goto set; 419 } 420 421 #define ODP_CAP_SET_MAX(dev, field) \ 422 do { \ 423 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 424 if (_res) { \ 425 do_set = true; \ 426 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 427 } \ 428 } while (0) 429 430 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.ud_odp_caps.srq_receive); 431 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.rc_odp_caps.srq_receive); 432 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.srq_receive); 433 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.send); 434 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.receive); 435 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.write); 436 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.read); 437 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.xrc_odp_caps.atomic); 438 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.srq_receive); 439 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.send); 440 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.receive); 441 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.write); 442 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read); 443 ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic); 444 445 set: 446 if (do_set) 447 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 448 449 mlx5_core_dbg(dev, "Using ODP %s scheme\n", 450 mem_page_fault ? "memory" : "transport"); 451 return err; 452 } 453 454 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) 455 { 456 struct devlink *devlink = priv_to_devlink(dev); 457 union devlink_param_value val; 458 int err; 459 460 err = devl_param_driverinit_value_get(devlink, 461 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 462 &val); 463 if (!err) 464 return val.vu32; 465 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 466 return err; 467 } 468 469 bool mlx5_is_roce_on(struct mlx5_core_dev *dev) 470 { 471 struct devlink *devlink = priv_to_devlink(dev); 472 union devlink_param_value val; 473 int err; 474 475 err = devl_param_driverinit_value_get(devlink, 476 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 477 &val); 478 479 if (!err) 480 return val.vbool; 481 482 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); 483 return MLX5_CAP_GEN(dev, roce); 484 } 485 EXPORT_SYMBOL(mlx5_is_roce_on); 486 487 static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) 488 { 489 bool do_set = false; 490 void *set_hca_cap; 491 int err; 492 493 if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) 494 return 0; 495 496 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 497 if (err) 498 return err; 499 500 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 501 capability); 502 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, 503 MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); 504 505 if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) && 506 dev->priv.sw_vhca_id > 0) { 507 MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); 508 do_set = true; 509 } 510 511 if (MLX5_CAP_GEN_2_MAX(dev, lag_per_mp_group)) { 512 MLX5_SET(cmd_hca_cap_2, set_hca_cap, lag_per_mp_group, 1); 513 do_set = true; 514 } 515 516 /* some FW versions that support querying MLX5_CAP_GENERAL_2 517 * capabilities but don't support setting them. 518 * Skip unnecessary update to hca_cap_2 when no changes were introduced 519 */ 520 return do_set ? set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2) : 0; 521 } 522 523 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 524 { 525 struct mlx5_profile *prof = &dev->profile; 526 void *set_hca_cap; 527 int err; 528 529 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 530 if (err) 531 return err; 532 533 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 534 capability); 535 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, 536 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 537 538 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 539 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 540 128); 541 /* we limit the size of the pkey table to 128 entries for now */ 542 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 543 to_fw_pkey_sz(dev, 128)); 544 545 /* Check log_max_qp from HCA caps to set in current profile */ 546 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { 547 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); 548 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { 549 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 550 prof->log_max_qp, 551 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 552 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 553 } 554 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 555 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 556 prof->log_max_qp); 557 558 /* disable cmdif checksum */ 559 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 560 561 /* Enable 4K UAR only when HCA supports it and page size is bigger 562 * than 4K. 563 */ 564 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 565 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 566 567 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 568 569 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 570 MLX5_SET(cmd_hca_cap, 571 set_hca_cap, 572 cache_line_128byte, 573 cache_line_size() >= 128 ? 1 : 0); 574 575 if (MLX5_CAP_GEN_MAX(dev, dct)) 576 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 577 578 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 579 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 580 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_with_driver_unload)) 581 MLX5_SET(cmd_hca_cap, set_hca_cap, 582 pci_sync_for_fw_update_with_driver_unload, 1); 583 if (MLX5_CAP_GEN_MAX(dev, pcie_reset_using_hotreset_method)) 584 MLX5_SET(cmd_hca_cap, set_hca_cap, 585 pcie_reset_using_hotreset_method, 1); 586 587 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 588 MLX5_SET(cmd_hca_cap, 589 set_hca_cap, 590 num_vhca_ports, 591 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 592 593 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 594 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 595 596 if (MLX5_CAP_GEN_MAX(dev, icm_mng_function_id_mode)) 597 MLX5_SET(cmd_hca_cap, set_hca_cap, icm_mng_function_id_mode, 1); 598 599 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 600 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 601 602 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 603 604 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) 605 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, 606 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); 607 608 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) 609 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, 610 mlx5_is_roce_on(dev)); 611 612 if (MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list)) { 613 int max_uc_list = max_uc_list_get_devlink_param(dev); 614 615 if (max_uc_list > 0) 616 MLX5_SET(cmd_hca_cap, set_hca_cap, 617 log_max_current_uc_list, ilog2(max_uc_list)); 618 } 619 620 /* enable absolute native port num */ 621 if (MLX5_CAP_GEN_MAX(dev, abs_native_port_num)) 622 MLX5_SET(cmd_hca_cap, set_hca_cap, abs_native_port_num, 1); 623 624 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 625 } 626 627 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the 628 * boot process. 629 * In case RoCE cap is writable in FW and user/devlink requested to change the 630 * cap, we are yet to query the final state of the above cap. 631 * Hence, the need for this function. 632 * 633 * Returns 634 * True: 635 * 1) RoCE cap is read only in FW and already disabled 636 * OR: 637 * 2) RoCE cap is writable in FW and user/devlink requested it off. 638 * 639 * In any other case, return False. 640 */ 641 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) 642 { 643 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || 644 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); 645 } 646 647 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 648 { 649 void *set_hca_cap; 650 int err; 651 652 if (is_roce_fw_disabled(dev)) 653 return 0; 654 655 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 656 if (err) 657 return err; 658 659 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 660 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 661 return 0; 662 663 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 664 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, 665 MLX5_ST_SZ_BYTES(roce_cap)); 666 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 667 668 if (MLX5_CAP_ROCE_MAX(dev, qp_ooo_transmit_default)) 669 MLX5_SET(roce_cap, set_hca_cap, qp_ooo_transmit_default, 1); 670 671 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 672 return err; 673 } 674 675 static int handle_hca_cap_port_selection(struct mlx5_core_dev *dev, 676 void *set_ctx) 677 { 678 void *set_hca_cap; 679 int err; 680 681 if (!MLX5_CAP_GEN(dev, port_selection_cap)) 682 return 0; 683 684 err = mlx5_core_get_caps(dev, MLX5_CAP_PORT_SELECTION); 685 if (err) 686 return err; 687 688 if (MLX5_CAP_PORT_SELECTION(dev, port_select_flow_table_bypass) || 689 !MLX5_CAP_PORT_SELECTION_MAX(dev, port_select_flow_table_bypass)) 690 return 0; 691 692 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 693 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, 694 MLX5_ST_SZ_BYTES(port_selection_cap)); 695 MLX5_SET(port_selection_cap, set_hca_cap, port_select_flow_table_bypass, 1); 696 697 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION); 698 699 return err; 700 } 701 702 static int set_hca_cap(struct mlx5_core_dev *dev) 703 { 704 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 705 void *set_ctx; 706 int err; 707 708 set_ctx = kzalloc(set_sz, GFP_KERNEL); 709 if (!set_ctx) 710 return -ENOMEM; 711 712 err = handle_hca_cap(dev, set_ctx); 713 if (err) { 714 mlx5_core_err(dev, "handle_hca_cap failed\n"); 715 goto out; 716 } 717 718 memset(set_ctx, 0, set_sz); 719 err = handle_hca_cap_atomic(dev, set_ctx); 720 if (err) { 721 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 722 goto out; 723 } 724 725 memset(set_ctx, 0, set_sz); 726 err = handle_hca_cap_odp(dev, set_ctx); 727 if (err) { 728 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 729 goto out; 730 } 731 732 memset(set_ctx, 0, set_sz); 733 err = handle_hca_cap_roce(dev, set_ctx); 734 if (err) { 735 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 736 goto out; 737 } 738 739 memset(set_ctx, 0, set_sz); 740 err = handle_hca_cap_2(dev, set_ctx); 741 if (err) { 742 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 743 goto out; 744 } 745 746 memset(set_ctx, 0, set_sz); 747 err = handle_hca_cap_port_selection(dev, set_ctx); 748 if (err) { 749 mlx5_core_err(dev, "handle_hca_cap_port_selection failed\n"); 750 goto out; 751 } 752 753 out: 754 kfree(set_ctx); 755 return err; 756 } 757 758 static int set_hca_ctrl(struct mlx5_core_dev *dev) 759 { 760 struct mlx5_reg_host_endianness he_in; 761 struct mlx5_reg_host_endianness he_out; 762 int err; 763 764 if (!mlx5_core_is_pf(dev)) 765 return 0; 766 767 memset(&he_in, 0, sizeof(he_in)); 768 he_in.he = MLX5_SET_HOST_ENDIANNESS; 769 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 770 &he_out, sizeof(he_out), 771 MLX5_REG_HOST_ENDIANNESS, 0, 1); 772 return err; 773 } 774 775 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 776 { 777 int ret = 0; 778 779 /* Disable local_lb by default */ 780 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 781 ret = mlx5_nic_vport_update_local_lb(dev, false); 782 783 return ret; 784 } 785 786 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 787 { 788 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 789 790 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 791 MLX5_SET(enable_hca_in, in, function_id, func_id); 792 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 793 dev->caps.embedded_cpu); 794 return mlx5_cmd_exec_in(dev, enable_hca, in); 795 } 796 797 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 798 { 799 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 800 801 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 802 MLX5_SET(disable_hca_in, in, function_id, func_id); 803 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 804 dev->caps.embedded_cpu); 805 return mlx5_cmd_exec_in(dev, disable_hca, in); 806 } 807 808 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 809 { 810 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 811 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 812 u32 sup_issi; 813 int err; 814 815 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 816 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 817 if (err) { 818 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); 819 u8 status = MLX5_GET(query_issi_out, query_out, status); 820 821 if (!status || syndrome == MLX5_DRIVER_SYND) { 822 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 823 err, status, syndrome); 824 return err; 825 } 826 827 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 828 dev->issi = 0; 829 return 0; 830 } 831 832 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 833 834 if (sup_issi & (1 << 1)) { 835 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 836 837 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 838 MLX5_SET(set_issi_in, set_in, current_issi, 1); 839 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 840 if (err) { 841 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 842 err); 843 return err; 844 } 845 846 dev->issi = 1; 847 848 return 0; 849 } else if (sup_issi & (1 << 0) || !sup_issi) { 850 return 0; 851 } 852 853 return -EOPNOTSUPP; 854 } 855 856 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 857 const struct pci_device_id *id) 858 { 859 int err = 0; 860 861 mutex_init(&dev->pci_status_mutex); 862 pci_set_drvdata(dev->pdev, dev); 863 864 dev->bar_addr = pci_resource_start(pdev, 0); 865 866 err = mlx5_pci_enable_device(dev); 867 if (err) { 868 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 869 return err; 870 } 871 872 err = request_bar(pdev); 873 if (err) { 874 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 875 goto err_disable; 876 } 877 878 pci_set_master(pdev); 879 880 err = set_dma_caps(pdev); 881 if (err) { 882 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 883 goto err_clr_master; 884 } 885 886 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 887 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 888 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 889 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 890 891 dev->iseg = ioremap(dev->bar_addr, sizeof(*dev->iseg)); 892 if (!dev->iseg) { 893 err = -ENOMEM; 894 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 895 goto err_clr_master; 896 } 897 898 mlx5_pci_vsc_init(dev); 899 900 pci_enable_ptm(pdev); 901 902 return 0; 903 904 err_clr_master: 905 release_bar(dev->pdev); 906 err_disable: 907 mlx5_pci_disable_device(dev); 908 return err; 909 } 910 911 static void mlx5_pci_close(struct mlx5_core_dev *dev) 912 { 913 /* health work might still be active, and it needs pci bar in 914 * order to know the NIC state. Therefore, drain the health WQ 915 * before removing the pci bars 916 */ 917 mlx5_drain_health_wq(dev); 918 pci_disable_ptm(dev->pdev); 919 iounmap(dev->iseg); 920 release_bar(dev->pdev); 921 mlx5_pci_disable_device(dev); 922 } 923 924 static int mlx5_init_once(struct mlx5_core_dev *dev) 925 { 926 int err; 927 928 dev->priv.devc = mlx5_devcom_register_device(dev); 929 if (!dev->priv.devc) 930 mlx5_core_warn(dev, "failed to register devcom device\n"); 931 932 err = mlx5_query_board_id(dev); 933 if (err) { 934 mlx5_core_err(dev, "query board id failed\n"); 935 goto err_devcom; 936 } 937 938 err = mlx5_irq_table_init(dev); 939 if (err) { 940 mlx5_core_err(dev, "failed to initialize irq table\n"); 941 goto err_devcom; 942 } 943 944 err = mlx5_eq_table_init(dev); 945 if (err) { 946 mlx5_core_err(dev, "failed to initialize eq\n"); 947 goto err_irq_cleanup; 948 } 949 950 err = mlx5_fw_reset_init(dev); 951 if (err) { 952 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 953 goto err_eq_cleanup; 954 } 955 956 mlx5_cq_debugfs_init(dev); 957 958 mlx5_init_reserved_gids(dev); 959 960 err = mlx5_init_clock(dev); 961 if (err) { 962 mlx5_core_err(dev, "failed to initialize hardware clock\n"); 963 goto err_tables_cleanup; 964 } 965 966 dev->vxlan = mlx5_vxlan_create(dev); 967 dev->geneve = mlx5_geneve_create(dev); 968 969 err = mlx5_init_rl_table(dev); 970 if (err) { 971 mlx5_core_err(dev, "Failed to init rate limiting\n"); 972 goto err_clock_cleanup; 973 } 974 975 err = mlx5_mpfs_init(dev); 976 if (err) { 977 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 978 goto err_rl_cleanup; 979 } 980 981 err = mlx5_sriov_init(dev); 982 if (err) { 983 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 984 goto err_mpfs_cleanup; 985 } 986 987 err = mlx5_eswitch_init(dev); 988 if (err) { 989 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 990 goto err_sriov_cleanup; 991 } 992 mlx5_pages_by_func_type_debugfs_init(dev); 993 994 err = mlx5_fpga_init(dev); 995 if (err) { 996 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 997 goto err_page_debugfs_cleanup; 998 } 999 1000 err = mlx5_vhca_event_init(dev); 1001 if (err) { 1002 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 1003 goto err_fpga_cleanup; 1004 } 1005 1006 err = mlx5_sf_hw_table_init(dev); 1007 if (err) { 1008 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 1009 goto err_sf_hw_table_cleanup; 1010 } 1011 1012 err = mlx5_sf_table_init(dev); 1013 if (err) { 1014 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 1015 goto err_sf_table_cleanup; 1016 } 1017 1018 err = mlx5_fs_core_alloc(dev); 1019 if (err) { 1020 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1021 goto err_fs; 1022 } 1023 1024 dev->dm = mlx5_dm_create(dev); 1025 dev->st = mlx5_st_create(dev); 1026 dev->tracer = mlx5_fw_tracer_create(dev); 1027 dev->hv_vhca = mlx5_hv_vhca_create(dev); 1028 dev->rsc_dump = mlx5_rsc_dump_create(dev); 1029 1030 return 0; 1031 1032 err_fs: 1033 mlx5_sf_table_cleanup(dev); 1034 err_sf_table_cleanup: 1035 mlx5_sf_hw_table_cleanup(dev); 1036 err_sf_hw_table_cleanup: 1037 mlx5_vhca_event_cleanup(dev); 1038 err_fpga_cleanup: 1039 mlx5_fpga_cleanup(dev); 1040 err_page_debugfs_cleanup: 1041 mlx5_pages_by_func_type_debugfs_cleanup(dev); 1042 mlx5_eswitch_cleanup(dev->priv.eswitch); 1043 err_sriov_cleanup: 1044 mlx5_sriov_cleanup(dev); 1045 err_mpfs_cleanup: 1046 mlx5_mpfs_cleanup(dev); 1047 err_rl_cleanup: 1048 mlx5_cleanup_rl_table(dev); 1049 err_clock_cleanup: 1050 mlx5_geneve_destroy(dev->geneve); 1051 mlx5_vxlan_destroy(dev->vxlan); 1052 mlx5_cleanup_clock(dev); 1053 err_tables_cleanup: 1054 mlx5_cleanup_reserved_gids(dev); 1055 mlx5_cq_debugfs_cleanup(dev); 1056 mlx5_fw_reset_cleanup(dev); 1057 err_eq_cleanup: 1058 mlx5_eq_table_cleanup(dev); 1059 err_irq_cleanup: 1060 mlx5_irq_table_cleanup(dev); 1061 err_devcom: 1062 mlx5_devcom_unregister_device(dev->priv.devc); 1063 1064 return err; 1065 } 1066 1067 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1068 { 1069 mlx5_rsc_dump_destroy(dev); 1070 mlx5_hv_vhca_destroy(dev->hv_vhca); 1071 mlx5_fw_tracer_destroy(dev->tracer); 1072 mlx5_st_destroy(dev); 1073 mlx5_dm_cleanup(dev); 1074 mlx5_fs_core_free(dev); 1075 mlx5_sf_table_cleanup(dev); 1076 mlx5_sf_hw_table_cleanup(dev); 1077 mlx5_vhca_event_cleanup(dev); 1078 mlx5_fpga_cleanup(dev); 1079 mlx5_pages_by_func_type_debugfs_cleanup(dev); 1080 mlx5_eswitch_cleanup(dev->priv.eswitch); 1081 mlx5_sriov_cleanup(dev); 1082 mlx5_mpfs_cleanup(dev); 1083 mlx5_cleanup_rl_table(dev); 1084 mlx5_geneve_destroy(dev->geneve); 1085 mlx5_vxlan_destroy(dev->vxlan); 1086 mlx5_cleanup_clock(dev); 1087 mlx5_cleanup_reserved_gids(dev); 1088 mlx5_cq_debugfs_cleanup(dev); 1089 mlx5_fw_reset_cleanup(dev); 1090 mlx5_eq_table_cleanup(dev); 1091 mlx5_irq_table_cleanup(dev); 1092 mlx5_devcom_unregister_device(dev->priv.devc); 1093 } 1094 1095 static int mlx5_function_enable(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1096 { 1097 int err; 1098 1099 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 1100 fw_rev_min(dev), fw_rev_sub(dev)); 1101 1102 /* Only PFs hold the relevant PCIe information for this query */ 1103 if (mlx5_core_is_pf(dev)) 1104 pcie_print_link_status(dev->pdev); 1105 1106 /* wait for firmware to accept initialization segments configurations 1107 */ 1108 err = wait_fw_init(dev, timeout, 1109 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL), 1110 "pre-initializing"); 1111 if (err) 1112 return err; 1113 1114 err = mlx5_cmd_enable(dev); 1115 if (err) { 1116 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 1117 return err; 1118 } 1119 1120 mlx5_tout_query_iseg(dev); 1121 1122 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0, "initializing"); 1123 if (err) 1124 goto err_cmd_cleanup; 1125 1126 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 1127 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1128 1129 err = mlx5_core_enable_hca(dev, 0); 1130 if (err) { 1131 mlx5_core_err(dev, "enable hca failed\n"); 1132 goto err_cmd_cleanup; 1133 } 1134 1135 mlx5_start_health_poll(dev); 1136 1137 err = mlx5_core_set_issi(dev); 1138 if (err) { 1139 mlx5_core_err(dev, "failed to set issi\n"); 1140 goto stop_health_poll; 1141 } 1142 1143 err = mlx5_satisfy_startup_pages(dev, 1); 1144 if (err) { 1145 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1146 goto stop_health_poll; 1147 } 1148 1149 err = mlx5_tout_query_dtor(dev); 1150 if (err) { 1151 mlx5_core_err(dev, "failed to read dtor\n"); 1152 goto reclaim_boot_pages; 1153 } 1154 1155 return 0; 1156 1157 reclaim_boot_pages: 1158 mlx5_reclaim_startup_pages(dev); 1159 stop_health_poll: 1160 mlx5_stop_health_poll(dev, boot); 1161 mlx5_core_disable_hca(dev, 0); 1162 err_cmd_cleanup: 1163 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1164 mlx5_cmd_disable(dev); 1165 1166 return err; 1167 } 1168 1169 static void mlx5_function_disable(struct mlx5_core_dev *dev, bool boot) 1170 { 1171 mlx5_reclaim_startup_pages(dev); 1172 mlx5_stop_health_poll(dev, boot); 1173 mlx5_core_disable_hca(dev, 0); 1174 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1175 mlx5_cmd_disable(dev); 1176 } 1177 1178 static int mlx5_function_open(struct mlx5_core_dev *dev) 1179 { 1180 int err; 1181 1182 err = set_hca_ctrl(dev); 1183 if (err) { 1184 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1185 return err; 1186 } 1187 1188 err = set_hca_cap(dev); 1189 if (err) { 1190 mlx5_core_err(dev, "set_hca_cap failed\n"); 1191 return err; 1192 } 1193 1194 err = mlx5_satisfy_startup_pages(dev, 0); 1195 if (err) { 1196 mlx5_core_err(dev, "failed to allocate init pages\n"); 1197 return err; 1198 } 1199 1200 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1201 if (err) { 1202 mlx5_core_err(dev, "init hca failed\n"); 1203 return err; 1204 } 1205 1206 mlx5_set_driver_version(dev); 1207 1208 err = mlx5_query_hca_caps(dev); 1209 if (err) { 1210 mlx5_core_err(dev, "query hca failed\n"); 1211 return err; 1212 } 1213 mlx5_start_health_fw_log_up(dev); 1214 return 0; 1215 } 1216 1217 static int mlx5_function_close(struct mlx5_core_dev *dev) 1218 { 1219 int err; 1220 1221 err = mlx5_cmd_teardown_hca(dev); 1222 if (err) { 1223 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1224 return err; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot, u64 timeout) 1231 { 1232 int err; 1233 1234 err = mlx5_function_enable(dev, boot, timeout); 1235 if (err) 1236 return err; 1237 1238 err = mlx5_function_open(dev); 1239 if (err) 1240 mlx5_function_disable(dev, boot); 1241 return err; 1242 } 1243 1244 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1245 { 1246 int err = mlx5_function_close(dev); 1247 1248 if (!err) 1249 mlx5_function_disable(dev, boot); 1250 else 1251 mlx5_stop_health_poll(dev, boot); 1252 1253 return err; 1254 } 1255 1256 static int mlx5_load(struct mlx5_core_dev *dev) 1257 { 1258 int err; 1259 1260 err = mlx5_alloc_bfreg(dev, &dev->priv.bfreg, false, false); 1261 if (err) { 1262 mlx5_core_err(dev, "Failed allocating bfreg, %d\n", err); 1263 return err; 1264 } 1265 1266 mlx5_events_start(dev); 1267 mlx5_pagealloc_start(dev); 1268 1269 err = mlx5_irq_table_create(dev); 1270 if (err) { 1271 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1272 goto err_irq_table; 1273 } 1274 1275 err = mlx5_eq_table_create(dev); 1276 if (err) { 1277 mlx5_core_err(dev, "Failed to create EQs\n"); 1278 goto err_eq_table; 1279 } 1280 1281 mlx5_clock_load(dev); 1282 1283 err = mlx5_fw_tracer_init(dev->tracer); 1284 if (err) { 1285 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); 1286 mlx5_fw_tracer_destroy(dev->tracer); 1287 dev->tracer = NULL; 1288 } 1289 1290 mlx5_fw_reset_events_start(dev); 1291 mlx5_hv_vhca_init(dev->hv_vhca); 1292 1293 err = mlx5_rsc_dump_init(dev); 1294 if (err) { 1295 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); 1296 mlx5_rsc_dump_destroy(dev); 1297 dev->rsc_dump = NULL; 1298 } 1299 1300 err = mlx5_fpga_device_start(dev); 1301 if (err) { 1302 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1303 goto err_fpga_start; 1304 } 1305 1306 err = mlx5_fs_core_init(dev); 1307 if (err) { 1308 mlx5_core_err(dev, "Failed to init flow steering\n"); 1309 goto err_fs; 1310 } 1311 1312 err = mlx5_core_set_hca_defaults(dev); 1313 if (err) { 1314 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1315 goto err_set_hca; 1316 } 1317 1318 mlx5_vhca_event_start(dev); 1319 1320 err = mlx5_ec_init(dev); 1321 if (err) { 1322 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1323 goto err_ec; 1324 } 1325 1326 mlx5_lag_add_mdev(dev); 1327 err = mlx5_sriov_attach(dev); 1328 if (err) { 1329 mlx5_core_err(dev, "sriov init failed %d\n", err); 1330 goto err_sriov; 1331 } 1332 1333 mlx5_sf_dev_table_create(dev); 1334 1335 err = mlx5_devlink_traps_register(priv_to_devlink(dev)); 1336 if (err) 1337 goto err_traps_reg; 1338 1339 err = mlx5_data_direct_init(dev); 1340 if (err) 1341 goto err_data_direct; 1342 1343 return 0; 1344 1345 err_data_direct: 1346 mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 1347 err_traps_reg: 1348 mlx5_sf_dev_table_destroy(dev); 1349 mlx5_sriov_detach(dev); 1350 err_sriov: 1351 mlx5_lag_remove_mdev(dev); 1352 mlx5_ec_cleanup(dev); 1353 err_ec: 1354 mlx5_vhca_event_stop(dev); 1355 err_set_hca: 1356 mlx5_fs_core_cleanup(dev); 1357 err_fs: 1358 mlx5_fpga_device_stop(dev); 1359 err_fpga_start: 1360 mlx5_rsc_dump_cleanup(dev); 1361 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1362 mlx5_fw_reset_events_stop(dev); 1363 mlx5_fw_tracer_cleanup(dev->tracer); 1364 mlx5_clock_unload(dev); 1365 mlx5_eq_table_destroy(dev); 1366 err_eq_table: 1367 mlx5_irq_table_destroy(dev); 1368 err_irq_table: 1369 mlx5_pagealloc_stop(dev); 1370 mlx5_events_stop(dev); 1371 mlx5_free_bfreg(dev, &dev->priv.bfreg); 1372 return err; 1373 } 1374 1375 static void mlx5_unload(struct mlx5_core_dev *dev) 1376 { 1377 mlx5_data_direct_cleanup(dev); 1378 mlx5_devlink_traps_unregister(priv_to_devlink(dev)); 1379 mlx5_vhca_event_stop(dev); 1380 mlx5_sf_dev_table_destroy(dev); 1381 mlx5_sriov_detach(dev); 1382 mlx5_lag_remove_mdev(dev); 1383 mlx5_ec_cleanup(dev); 1384 mlx5_sf_hw_table_destroy(dev); 1385 mlx5_fs_core_cleanup(dev); 1386 mlx5_fpga_device_stop(dev); 1387 mlx5_rsc_dump_cleanup(dev); 1388 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1389 mlx5_fw_reset_events_stop(dev); 1390 mlx5_fw_tracer_cleanup(dev->tracer); 1391 mlx5_clock_unload(dev); 1392 mlx5_eq_table_destroy(dev); 1393 mlx5_irq_table_destroy(dev); 1394 mlx5_pagealloc_stop(dev); 1395 mlx5_events_stop(dev); 1396 mlx5_free_bfreg(dev, &dev->priv.bfreg); 1397 } 1398 1399 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) 1400 { 1401 bool light_probe = mlx5_dev_is_lightweight(dev); 1402 int err = 0; 1403 1404 mutex_lock(&dev->intf_state_mutex); 1405 dev->state = MLX5_DEVICE_STATE_UP; 1406 1407 err = mlx5_function_setup(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1408 if (err) 1409 goto err_function; 1410 1411 err = mlx5_init_once(dev); 1412 if (err) { 1413 mlx5_core_err(dev, "sw objs init failed\n"); 1414 goto function_teardown; 1415 } 1416 1417 /* In case of light_probe, mlx5_devlink is already registered. 1418 * Hence, don't register devlink again. 1419 */ 1420 if (!light_probe) { 1421 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1422 if (err) 1423 goto err_devlink_params_reg; 1424 } 1425 1426 err = mlx5_load(dev); 1427 if (err) 1428 goto err_load; 1429 1430 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1431 1432 err = mlx5_register_device(dev); 1433 if (err) 1434 goto err_register; 1435 1436 err = mlx5_crdump_enable(dev); 1437 if (err) 1438 mlx5_core_err(dev, "mlx5_crdump_enable failed with error code %d\n", err); 1439 1440 err = mlx5_hwmon_dev_register(dev); 1441 if (err) 1442 mlx5_core_err(dev, "mlx5_hwmon_dev_register failed with error code %d\n", err); 1443 1444 mutex_unlock(&dev->intf_state_mutex); 1445 return 0; 1446 1447 err_register: 1448 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1449 mlx5_unload(dev); 1450 err_load: 1451 if (!light_probe) 1452 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1453 err_devlink_params_reg: 1454 mlx5_cleanup_once(dev); 1455 function_teardown: 1456 mlx5_function_teardown(dev, true); 1457 err_function: 1458 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1459 mutex_unlock(&dev->intf_state_mutex); 1460 return err; 1461 } 1462 1463 int mlx5_init_one(struct mlx5_core_dev *dev) 1464 { 1465 struct devlink *devlink = priv_to_devlink(dev); 1466 int err; 1467 1468 devl_lock(devlink); 1469 if (dev->shd) { 1470 err = devl_nested_devlink_set(dev->shd, devlink); 1471 if (err) 1472 goto unlock; 1473 } 1474 devl_register(devlink); 1475 err = mlx5_init_one_devl_locked(dev); 1476 if (err) 1477 devl_unregister(devlink); 1478 unlock: 1479 devl_unlock(devlink); 1480 return err; 1481 } 1482 1483 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1484 { 1485 struct devlink *devlink = priv_to_devlink(dev); 1486 1487 devl_lock(devlink); 1488 mutex_lock(&dev->intf_state_mutex); 1489 1490 mlx5_hwmon_dev_unregister(dev); 1491 mlx5_crdump_disable(dev); 1492 mlx5_eswitch_disable(dev->priv.eswitch); 1493 mlx5_unregister_device(dev); 1494 1495 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1496 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1497 __func__); 1498 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1499 mlx5_cleanup_once(dev); 1500 goto out; 1501 } 1502 1503 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1504 mlx5_unload(dev); 1505 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1506 mlx5_cleanup_once(dev); 1507 mlx5_function_teardown(dev, true); 1508 out: 1509 mutex_unlock(&dev->intf_state_mutex); 1510 devl_unregister(devlink); 1511 devl_unlock(devlink); 1512 } 1513 1514 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) 1515 { 1516 int err = 0; 1517 u64 timeout; 1518 1519 devl_assert_locked(priv_to_devlink(dev)); 1520 mutex_lock(&dev->intf_state_mutex); 1521 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1522 mlx5_core_warn(dev, "interface is up, NOP\n"); 1523 goto out; 1524 } 1525 /* remove any previous indication of internal error */ 1526 dev->state = MLX5_DEVICE_STATE_UP; 1527 1528 if (recovery) 1529 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); 1530 else 1531 timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); 1532 err = mlx5_function_setup(dev, false, timeout); 1533 if (err) 1534 goto err_function; 1535 1536 err = mlx5_load(dev); 1537 if (err) 1538 goto err_load; 1539 1540 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1541 1542 err = mlx5_attach_device(dev); 1543 if (err) 1544 goto err_attach; 1545 1546 mutex_unlock(&dev->intf_state_mutex); 1547 return 0; 1548 1549 err_attach: 1550 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1551 mlx5_unload(dev); 1552 err_load: 1553 mlx5_function_teardown(dev, false); 1554 err_function: 1555 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1556 out: 1557 mutex_unlock(&dev->intf_state_mutex); 1558 return err; 1559 } 1560 1561 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) 1562 { 1563 struct devlink *devlink = priv_to_devlink(dev); 1564 int ret; 1565 1566 devl_lock(devlink); 1567 ret = mlx5_load_one_devl_locked(dev, recovery); 1568 devl_unlock(devlink); 1569 return ret; 1570 } 1571 1572 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend) 1573 { 1574 devl_assert_locked(priv_to_devlink(dev)); 1575 mutex_lock(&dev->intf_state_mutex); 1576 1577 mlx5_eswitch_disable(dev->priv.eswitch); 1578 mlx5_detach_device(dev, suspend); 1579 1580 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1581 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1582 __func__); 1583 goto out; 1584 } 1585 1586 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1587 mlx5_unload(dev); 1588 mlx5_function_teardown(dev, false); 1589 out: 1590 mutex_unlock(&dev->intf_state_mutex); 1591 } 1592 1593 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend) 1594 { 1595 struct devlink *devlink = priv_to_devlink(dev); 1596 1597 devl_lock(devlink); 1598 mlx5_unload_one_devl_locked(dev, suspend); 1599 devl_unlock(devlink); 1600 } 1601 1602 /* In case of light probe, we don't need a full query of hca_caps, but only the bellow caps. 1603 * A full query of hca_caps will be done when the device will reload. 1604 */ 1605 static int mlx5_query_hca_caps_light(struct mlx5_core_dev *dev) 1606 { 1607 int err; 1608 1609 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 1610 if (err) 1611 return err; 1612 1613 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 1614 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS, 1615 HCA_CAP_OPMOD_GET_CUR); 1616 if (err) 1617 return err; 1618 } 1619 1620 if (MLX5_CAP_GEN(dev, nic_flow_table) || 1621 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 1622 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, 1623 HCA_CAP_OPMOD_GET_CUR); 1624 if (err) 1625 return err; 1626 } 1627 1628 if (MLX5_CAP_GEN_64(dev, general_obj_types) & 1629 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 1630 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, 1631 HCA_CAP_OPMOD_GET_CUR); 1632 if (err) 1633 return err; 1634 } 1635 1636 return 0; 1637 } 1638 1639 int mlx5_init_one_light(struct mlx5_core_dev *dev) 1640 { 1641 struct devlink *devlink = priv_to_devlink(dev); 1642 int err; 1643 1644 devl_lock(devlink); 1645 devl_register(devlink); 1646 dev->state = MLX5_DEVICE_STATE_UP; 1647 err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); 1648 if (err) { 1649 mlx5_core_warn(dev, "mlx5_function_enable err=%d\n", err); 1650 goto out; 1651 } 1652 1653 err = mlx5_query_hca_caps_light(dev); 1654 if (err) { 1655 mlx5_core_warn(dev, "mlx5_query_hca_caps_light err=%d\n", err); 1656 goto query_hca_caps_err; 1657 } 1658 1659 err = mlx5_devlink_params_register(priv_to_devlink(dev)); 1660 if (err) { 1661 mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err); 1662 goto query_hca_caps_err; 1663 } 1664 1665 devl_unlock(devlink); 1666 return 0; 1667 1668 query_hca_caps_err: 1669 mlx5_function_disable(dev, true); 1670 out: 1671 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1672 devl_unregister(devlink); 1673 devl_unlock(devlink); 1674 return err; 1675 } 1676 1677 void mlx5_uninit_one_light(struct mlx5_core_dev *dev) 1678 { 1679 struct devlink *devlink = priv_to_devlink(dev); 1680 1681 devl_lock(devlink); 1682 mlx5_devlink_params_unregister(priv_to_devlink(dev)); 1683 devl_unregister(devlink); 1684 devl_unlock(devlink); 1685 if (dev->state != MLX5_DEVICE_STATE_UP) 1686 return; 1687 mlx5_function_disable(dev, true); 1688 } 1689 1690 /* xxx_light() function are used in order to configure the device without full 1691 * init (light init). e.g.: There isn't a point in reload a device to light state. 1692 * Hence, mlx5_load_one_light() isn't needed. 1693 */ 1694 1695 void mlx5_unload_one_light(struct mlx5_core_dev *dev) 1696 { 1697 if (dev->state != MLX5_DEVICE_STATE_UP) 1698 return; 1699 mlx5_function_disable(dev, false); 1700 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1701 } 1702 1703 static const int types[] = { 1704 MLX5_CAP_GENERAL, 1705 MLX5_CAP_GENERAL_2, 1706 MLX5_CAP_ETHERNET_OFFLOADS, 1707 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1708 MLX5_CAP_ODP, 1709 MLX5_CAP_ATOMIC, 1710 MLX5_CAP_ROCE, 1711 MLX5_CAP_IPOIB_OFFLOADS, 1712 MLX5_CAP_FLOW_TABLE, 1713 MLX5_CAP_ESWITCH_FLOW_TABLE, 1714 MLX5_CAP_ESWITCH, 1715 MLX5_CAP_QOS, 1716 MLX5_CAP_DEBUG, 1717 MLX5_CAP_DEV_MEM, 1718 MLX5_CAP_DEV_EVENT, 1719 MLX5_CAP_TLS, 1720 MLX5_CAP_VDPA_EMULATION, 1721 MLX5_CAP_IPSEC, 1722 MLX5_CAP_PORT_SELECTION, 1723 MLX5_CAP_PSP, 1724 MLX5_CAP_MACSEC, 1725 MLX5_CAP_ADV_VIRTUALIZATION, 1726 MLX5_CAP_CRYPTO, 1727 MLX5_CAP_SHAMPO, 1728 MLX5_CAP_ADV_RDMA, 1729 MLX5_CAP_TLP_EMULATION, 1730 }; 1731 1732 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) 1733 { 1734 int type; 1735 int i; 1736 1737 for (i = 0; i < ARRAY_SIZE(types); i++) { 1738 type = types[i]; 1739 kfree(dev->caps.hca[type]); 1740 } 1741 } 1742 1743 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) 1744 { 1745 struct mlx5_hca_cap *cap; 1746 int type; 1747 int i; 1748 1749 for (i = 0; i < ARRAY_SIZE(types); i++) { 1750 cap = kzalloc_obj(*cap); 1751 if (!cap) 1752 goto err; 1753 type = types[i]; 1754 dev->caps.hca[type] = cap; 1755 } 1756 1757 return 0; 1758 1759 err: 1760 mlx5_hca_caps_free(dev); 1761 return -ENOMEM; 1762 } 1763 1764 static int mlx5_notifiers_init(struct mlx5_core_dev *dev) 1765 { 1766 int err; 1767 1768 err = mlx5_events_init(dev); 1769 if (err) { 1770 mlx5_core_err(dev, "failed to initialize events\n"); 1771 return err; 1772 } 1773 1774 BLOCKING_INIT_NOTIFIER_HEAD(&dev->priv.esw_n_head); 1775 mlx5_vhca_state_notifier_init(dev); 1776 1777 err = mlx5_sf_hw_notifier_init(dev); 1778 if (err) 1779 goto err_sf_hw_notifier; 1780 1781 err = mlx5_sf_notifiers_init(dev); 1782 if (err) 1783 goto err_sf_notifiers; 1784 1785 err = mlx5_sf_dev_notifier_init(dev); 1786 if (err) 1787 goto err_sf_dev_notifier; 1788 1789 return 0; 1790 1791 err_sf_dev_notifier: 1792 mlx5_sf_notifiers_cleanup(dev); 1793 err_sf_notifiers: 1794 mlx5_sf_hw_notifier_cleanup(dev); 1795 err_sf_hw_notifier: 1796 mlx5_events_cleanup(dev); 1797 return err; 1798 } 1799 1800 static void mlx5_notifiers_cleanup(struct mlx5_core_dev *dev) 1801 { 1802 mlx5_sf_dev_notifier_cleanup(dev); 1803 mlx5_sf_notifiers_cleanup(dev); 1804 mlx5_sf_hw_notifier_cleanup(dev); 1805 mlx5_events_cleanup(dev); 1806 } 1807 1808 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1809 { 1810 struct mlx5_priv *priv = &dev->priv; 1811 int err; 1812 1813 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); 1814 lockdep_register_key(&dev->lock_key); 1815 mutex_init(&dev->intf_state_mutex); 1816 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); 1817 mutex_init(&dev->mlx5e_res.uplink_netdev_lock); 1818 mutex_init(&dev->wc_state_lock); 1819 1820 mutex_init(&priv->bfregs.reg_head.lock); 1821 mutex_init(&priv->bfregs.wc_head.lock); 1822 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1823 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1824 1825 mutex_init(&priv->alloc_mutex); 1826 1827 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 1828 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), 1829 mlx5_debugfs_root); 1830 1831 err = mlx5_frag_buf_pools_init(dev); 1832 if (err) 1833 goto err_frag_buf_pools_init; 1834 1835 err = mlx5_db_pools_init(dev); 1836 if (err) 1837 goto err_db_pools_init; 1838 1839 INIT_LIST_HEAD(&priv->traps); 1840 1841 err = mlx5_cmd_init(dev); 1842 if (err) { 1843 mlx5_core_err(dev, "Failed initializing cmdif SW structs, aborting\n"); 1844 goto err_cmd_init; 1845 } 1846 1847 err = mlx5_tout_init(dev); 1848 if (err) { 1849 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); 1850 goto err_timeout_init; 1851 } 1852 1853 err = mlx5_health_init(dev); 1854 if (err) 1855 goto err_health_init; 1856 1857 err = mlx5_pagealloc_init(dev); 1858 if (err) 1859 goto err_pagealloc_init; 1860 1861 err = mlx5_adev_init(dev); 1862 if (err) 1863 goto err_adev_init; 1864 1865 err = mlx5_hca_caps_alloc(dev); 1866 if (err) 1867 goto err_hca_caps; 1868 1869 err = mlx5_notifiers_init(dev); 1870 if (err) 1871 goto err_notifiers_init; 1872 1873 /* The conjunction of sw_vhca_id with sw_owner_id will be a global 1874 * unique id per function which uses mlx5_core. 1875 * Those values are supplied to FW as part of the init HCA command to 1876 * be used by both driver and FW when it's applicable. 1877 */ 1878 dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, 1879 MAX_SW_VHCA_ID, 1880 GFP_KERNEL); 1881 if (dev->priv.sw_vhca_id < 0) 1882 mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", 1883 dev->priv.sw_vhca_id); 1884 1885 return 0; 1886 1887 err_notifiers_init: 1888 mlx5_hca_caps_free(dev); 1889 err_hca_caps: 1890 mlx5_adev_cleanup(dev); 1891 err_adev_init: 1892 mlx5_pagealloc_cleanup(dev); 1893 err_pagealloc_init: 1894 mlx5_health_cleanup(dev); 1895 err_health_init: 1896 mlx5_tout_cleanup(dev); 1897 err_timeout_init: 1898 mlx5_cmd_cleanup(dev); 1899 err_cmd_init: 1900 mlx5_db_pools_cleanup(dev); 1901 err_db_pools_init: 1902 mlx5_frag_buf_pools_cleanup(dev); 1903 err_frag_buf_pools_init: 1904 debugfs_remove(dev->priv.dbg.dbg_root); 1905 mutex_destroy(&priv->alloc_mutex); 1906 mutex_destroy(&priv->bfregs.wc_head.lock); 1907 mutex_destroy(&priv->bfregs.reg_head.lock); 1908 mutex_destroy(&dev->intf_state_mutex); 1909 lockdep_unregister_key(&dev->lock_key); 1910 return err; 1911 } 1912 1913 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1914 { 1915 struct mlx5_priv *priv = &dev->priv; 1916 1917 if (priv->sw_vhca_id > 0) 1918 ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); 1919 1920 mlx5_notifiers_cleanup(dev); 1921 mlx5_hca_caps_free(dev); 1922 mlx5_adev_cleanup(dev); 1923 mlx5_pagealloc_cleanup(dev); 1924 mlx5_health_cleanup(dev); 1925 mlx5_tout_cleanup(dev); 1926 mlx5_cmd_cleanup(dev); 1927 mlx5_db_pools_cleanup(dev); 1928 mlx5_frag_buf_pools_cleanup(dev); 1929 debugfs_remove_recursive(dev->priv.dbg.dbg_root); 1930 mutex_destroy(&priv->alloc_mutex); 1931 mutex_destroy(&priv->bfregs.wc_head.lock); 1932 mutex_destroy(&priv->bfregs.reg_head.lock); 1933 mutex_destroy(&dev->wc_state_lock); 1934 mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); 1935 mutex_destroy(&dev->intf_state_mutex); 1936 lockdep_unregister_key(&dev->lock_key); 1937 } 1938 1939 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1940 { 1941 struct mlx5_core_dev *dev; 1942 struct devlink *devlink; 1943 int err; 1944 1945 devlink = mlx5_devlink_alloc(&pdev->dev); 1946 if (!devlink) { 1947 dev_err(&pdev->dev, "devlink alloc failed\n"); 1948 return -ENOMEM; 1949 } 1950 1951 dev = devlink_priv(devlink); 1952 dev->device = &pdev->dev; 1953 dev->pdev = pdev; 1954 1955 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1956 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1957 1958 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1959 if (dev->priv.adev_idx < 0) { 1960 err = dev->priv.adev_idx; 1961 goto adev_init_err; 1962 } 1963 1964 err = mlx5_mdev_init(dev, prof_sel); 1965 if (err) 1966 goto mdev_init_err; 1967 1968 err = mlx5_pci_init(dev, pdev, id); 1969 if (err) { 1970 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1971 err); 1972 goto pci_init_err; 1973 } 1974 1975 err = mlx5_shd_init(dev); 1976 if (err) { 1977 mlx5_core_err(dev, "mlx5_shd_init failed with error code %d\n", 1978 err); 1979 goto shd_init_err; 1980 } 1981 1982 err = mlx5_init_one(dev); 1983 if (err) { 1984 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1985 err); 1986 goto err_init_one; 1987 } 1988 1989 mlx5_vhca_debugfs_init(dev); 1990 1991 pci_save_state(pdev); 1992 return 0; 1993 1994 err_init_one: 1995 mlx5_shd_uninit(dev); 1996 shd_init_err: 1997 mlx5_pci_close(dev); 1998 pci_init_err: 1999 mlx5_mdev_uninit(dev); 2000 mdev_init_err: 2001 mlx5_adev_idx_free(dev->priv.adev_idx); 2002 adev_init_err: 2003 mlx5_devlink_free(devlink); 2004 2005 return err; 2006 } 2007 2008 static void remove_one(struct pci_dev *pdev) 2009 { 2010 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2011 struct devlink *devlink = priv_to_devlink(dev); 2012 2013 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 2014 mlx5_drain_fw_reset(dev); 2015 mlx5_drain_health_wq(dev); 2016 mlx5_sriov_disable(pdev, false); 2017 mlx5_uninit_one(dev); 2018 mlx5_shd_uninit(dev); 2019 mlx5_pci_close(dev); 2020 mlx5_mdev_uninit(dev); 2021 mlx5_adev_idx_free(dev->priv.adev_idx); 2022 mlx5_devlink_free(devlink); 2023 } 2024 2025 #define mlx5_pci_trace(dev, fmt, ...) ({ \ 2026 struct mlx5_core_dev *__dev = (dev); \ 2027 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ 2028 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ 2029 __dev->pci_status, ##__VA_ARGS__); \ 2030 }) 2031 2032 static const char *result2str(enum pci_ers_result result) 2033 { 2034 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : 2035 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : 2036 result == PCI_ERS_RESULT_RECOVERED ? "recovered" : 2037 "unknown"; 2038 } 2039 2040 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 2041 pci_channel_state_t state) 2042 { 2043 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2044 enum pci_ers_result res; 2045 2046 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); 2047 2048 mlx5_enter_error_state(dev, false); 2049 mlx5_error_sw_reset(dev); 2050 mlx5_unload_one(dev, false); 2051 mlx5_drain_health_wq(dev); 2052 mlx5_pci_disable_device(dev); 2053 2054 res = state == pci_channel_io_perm_failure ? 2055 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 2056 2057 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n", 2058 __func__, dev->state, dev->pci_status, res, result2str(res)); 2059 return res; 2060 } 2061 2062 /* wait for the device to show vital signs by waiting 2063 * for the health counter to start counting. 2064 */ 2065 static int wait_vital(struct pci_dev *pdev) 2066 { 2067 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2068 struct mlx5_core_health *health = &dev->priv.health; 2069 const int niter = 100; 2070 u32 last_count = 0; 2071 u32 count; 2072 int i; 2073 2074 for (i = 0; i < niter; i++) { 2075 count = ioread32be(health->health_counter); 2076 if (count && count != 0xffffffff) { 2077 if (last_count && last_count != count) { 2078 mlx5_core_info(dev, 2079 "wait vital counter value 0x%x after %d iterations\n", 2080 count, i); 2081 return 0; 2082 } 2083 last_count = count; 2084 } 2085 msleep(50); 2086 } 2087 2088 return -ETIMEDOUT; 2089 } 2090 2091 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 2092 { 2093 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; 2094 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2095 int err; 2096 2097 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n", 2098 __func__, dev->state, dev->pci_status); 2099 2100 err = mlx5_pci_enable_device(dev); 2101 if (err) { 2102 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 2103 __func__, err); 2104 goto out; 2105 } 2106 2107 pci_set_master(pdev); 2108 pci_restore_state(pdev); 2109 2110 err = wait_vital(pdev); 2111 if (err) { 2112 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", 2113 __func__, err); 2114 goto out; 2115 } 2116 2117 res = PCI_ERS_RESULT_RECOVERED; 2118 out: 2119 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n", 2120 __func__, dev->state, dev->pci_status, err, res, result2str(res)); 2121 return res; 2122 } 2123 2124 static void mlx5_pci_resume(struct pci_dev *pdev) 2125 { 2126 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2127 int err; 2128 2129 mlx5_pci_trace(dev, "Enter, loading driver..\n"); 2130 2131 err = mlx5_load_one(dev, false); 2132 2133 if (!err) 2134 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter, 2135 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY); 2136 2137 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, 2138 !err ? "recovered" : "Failed"); 2139 } 2140 2141 static const struct pci_error_handlers mlx5_err_handler = { 2142 .error_detected = mlx5_pci_err_detected, 2143 .slot_reset = mlx5_pci_slot_reset, 2144 .resume = mlx5_pci_resume 2145 }; 2146 2147 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 2148 { 2149 bool fast_teardown = false, force_teardown = false; 2150 int ret = 1; 2151 2152 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 2153 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 2154 2155 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 2156 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 2157 2158 if (!fast_teardown && !force_teardown) 2159 return -EOPNOTSUPP; 2160 2161 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 2162 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 2163 return -EAGAIN; 2164 } 2165 2166 /* Panic tear down fw command will stop the PCI bus communication 2167 * with the HCA, so the health poll is no longer needed. 2168 */ 2169 mlx5_stop_health_poll(dev, false); 2170 2171 ret = mlx5_cmd_fast_teardown_hca(dev); 2172 if (!ret) 2173 goto succeed; 2174 2175 ret = mlx5_cmd_force_teardown_hca(dev); 2176 if (!ret) 2177 goto succeed; 2178 2179 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 2180 mlx5_start_health_poll(dev); 2181 return ret; 2182 2183 succeed: 2184 mlx5_enter_error_state(dev, true); 2185 2186 /* Some platforms requiring freeing the IRQ's in the shutdown 2187 * flow. If they aren't freed they can't be allocated after 2188 * kexec. There is no need to cleanup the mlx5_core software 2189 * contexts. 2190 */ 2191 mlx5_core_eq_free_irqs(dev); 2192 2193 return 0; 2194 } 2195 2196 static void shutdown(struct pci_dev *pdev) 2197 { 2198 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2199 int err; 2200 2201 mlx5_core_info(dev, "Shutdown was called\n"); 2202 set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); 2203 mlx5_drain_fw_reset(dev); 2204 mlx5_drain_health_wq(dev); 2205 err = mlx5_try_fast_unload(dev); 2206 if (err) 2207 mlx5_unload_one(dev, false); 2208 mlx5_pci_disable_device(dev); 2209 } 2210 2211 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 2212 { 2213 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2214 2215 mlx5_unload_one(dev, true); 2216 2217 return 0; 2218 } 2219 2220 static int mlx5_resume(struct pci_dev *pdev) 2221 { 2222 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2223 2224 return mlx5_load_one(dev, false); 2225 } 2226 2227 static const struct pci_device_id mlx5_core_pci_table[] = { 2228 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 2229 { PCI_VDEVICE(MELLANOX, 0x1012), 2230 .driver_data = MLX5_PCI_DEV_IS_VF }, /* Connect-IB VF */ 2231 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 2232 { PCI_VDEVICE(MELLANOX, 0x1014), 2233 .driver_data = MLX5_PCI_DEV_IS_VF }, /* ConnectX-4 VF */ 2234 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 2235 { PCI_VDEVICE(MELLANOX, 0x1016), 2236 .driver_data = MLX5_PCI_DEV_IS_VF }, /* ConnectX-4LX VF */ 2237 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 2238 { PCI_VDEVICE(MELLANOX, 0x1018), 2239 .driver_data = MLX5_PCI_DEV_IS_VF }, /* ConnectX-5 VF */ 2240 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 2241 { PCI_VDEVICE(MELLANOX, 0x101a), 2242 .driver_data = MLX5_PCI_DEV_IS_VF }, /* ConnectX-5 Ex VF */ 2243 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 2244 { PCI_VDEVICE(MELLANOX, 0x101c), 2245 .driver_data = MLX5_PCI_DEV_IS_VF }, /* ConnectX-6 VF */ 2246 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 2247 { PCI_VDEVICE(MELLANOX, 0x101e), 2248 .driver_data = MLX5_PCI_DEV_IS_VF }, /* ConnectX Family mlx5Gen Virtual Function */ 2249 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 2250 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 2251 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ 2252 { PCI_VDEVICE(MELLANOX, 0x1025) }, /* ConnectX-9 */ 2253 { PCI_VDEVICE(MELLANOX, 0x1027) }, /* ConnectX-10 */ 2254 { PCI_VDEVICE(MELLANOX, 0x2101) }, /* ConnectX-10 NVLink-C2C */ 2255 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2256 { PCI_VDEVICE(MELLANOX, 0xa2d3), 2257 .driver_data = MLX5_PCI_DEV_IS_VF }, /* BlueField integrated ConnectX-5 network controller VF */ 2258 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2259 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2260 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2261 { } 2262 }; 2263 2264 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2265 2266 void mlx5_disable_device(struct mlx5_core_dev *dev) 2267 { 2268 mlx5_error_sw_reset(dev); 2269 mlx5_unload_one_devl_locked(dev, false); 2270 } 2271 2272 int mlx5_recover_device(struct mlx5_core_dev *dev) 2273 { 2274 if (!mlx5_core_is_sf(dev)) { 2275 mlx5_pci_disable_device(dev); 2276 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) 2277 return -EIO; 2278 } 2279 2280 return mlx5_load_one_devl_locked(dev, true); 2281 } 2282 2283 static struct pci_driver mlx5_core_driver = { 2284 .name = KBUILD_MODNAME, 2285 .id_table = mlx5_core_pci_table, 2286 .probe = probe_one, 2287 .remove = remove_one, 2288 .suspend = mlx5_suspend, 2289 .resume = mlx5_resume, 2290 .shutdown = shutdown, 2291 .err_handler = &mlx5_err_handler, 2292 .sriov_configure = mlx5_core_sriov_configure, 2293 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, 2294 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, 2295 }; 2296 2297 /** 2298 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if 2299 * mlx5_core is its driver. 2300 * @pdev: The associated PCI device. 2301 * 2302 * Upon return the interface state lock stay held to let caller uses it safely. 2303 * Caller must ensure to use the returned mlx5 device for a narrow window 2304 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. 2305 * 2306 * Return: Pointer to the associated mlx5_core_dev or NULL. 2307 */ 2308 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) 2309 { 2310 struct mlx5_core_dev *mdev; 2311 2312 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); 2313 if (IS_ERR(mdev)) 2314 return NULL; 2315 2316 mutex_lock(&mdev->intf_state_mutex); 2317 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { 2318 mutex_unlock(&mdev->intf_state_mutex); 2319 return NULL; 2320 } 2321 2322 return mdev; 2323 } 2324 EXPORT_SYMBOL(mlx5_vf_get_core_dev); 2325 2326 /** 2327 * mlx5_vf_put_core_dev - Put the mlx5 core device back. 2328 * @mdev: The mlx5 core device. 2329 * 2330 * Upon return the interface state lock is unlocked and caller should not 2331 * access the mdev any more. 2332 */ 2333 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) 2334 { 2335 mutex_unlock(&mdev->intf_state_mutex); 2336 } 2337 EXPORT_SYMBOL(mlx5_vf_put_core_dev); 2338 2339 static void mlx5_core_verify_params(void) 2340 { 2341 if (prof_sel >= ARRAY_SIZE(profile)) { 2342 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 2343 prof_sel, 2344 ARRAY_SIZE(profile) - 1, 2345 MLX5_DEFAULT_PROF); 2346 prof_sel = MLX5_DEFAULT_PROF; 2347 } 2348 } 2349 2350 static int __init mlx5_init(void) 2351 { 2352 int err; 2353 2354 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 2355 "mlx5_core name not in sync with kernel module name"); 2356 2357 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 2358 2359 mlx5_core_verify_params(); 2360 mlx5_register_debugfs(); 2361 2362 err = mlx5e_init(); 2363 if (err) 2364 goto err_debug; 2365 2366 err = mlx5_sf_driver_register(); 2367 if (err) 2368 goto err_sf; 2369 2370 err = mlx5_data_direct_driver_register(); 2371 if (err) 2372 goto err_dd; 2373 2374 err = pci_register_driver(&mlx5_core_driver); 2375 if (err) 2376 goto err_pci; 2377 2378 return 0; 2379 2380 err_pci: 2381 mlx5_data_direct_driver_unregister(); 2382 err_dd: 2383 mlx5_sf_driver_unregister(); 2384 err_sf: 2385 mlx5e_cleanup(); 2386 err_debug: 2387 mlx5_unregister_debugfs(); 2388 return err; 2389 } 2390 2391 static void __exit mlx5_cleanup(void) 2392 { 2393 pci_unregister_driver(&mlx5_core_driver); 2394 mlx5_data_direct_driver_unregister(); 2395 mlx5_sf_driver_unregister(); 2396 mlx5e_cleanup(); 2397 mlx5_unregister_debugfs(); 2398 } 2399 2400 module_init(mlx5_init); 2401 module_exit(mlx5_cleanup); 2402