1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 #include <linux/mlx5/mlx5_ifc_macros.h> 40 #include <linux/bitfield.h> 41 42 #if defined(__LITTLE_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0 44 #elif defined(__BIG_ENDIAN) 45 #define MLX5_SET_HOST_ENDIANNESS 0x80 46 #else 47 #error Host endianness not defined 48 #endif 49 50 enum mlx5_inline_modes { 51 MLX5_INLINE_MODE_NONE, 52 MLX5_INLINE_MODE_L2, 53 MLX5_INLINE_MODE_IP, 54 MLX5_INLINE_MODE_TCP_UDP, 55 }; 56 57 enum { 58 MLX5_MAX_COMMANDS = 32, 59 MLX5_CMD_DATA_BLOCK_SIZE = 512, 60 MLX5_PCI_CMD_XPORT = MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT, 61 MLX5_MKEY_BSF_OCTO_SIZE = 4, 62 MLX5_MAX_PSVS = 4, 63 }; 64 65 enum { 66 MLX5_EXTENDED_UD_AV = 0x80000000, 67 }; 68 69 enum { 70 MLX5_CQ_STATE_ARMED = 9, 71 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 72 MLX5_CQ_STATE_FIRED = 0xa, 73 }; 74 75 enum { 76 MLX5_STAT_RATE_OFFSET = 5, 77 }; 78 79 enum { 80 MLX5_INLINE_SEG = 0x80000000, 81 }; 82 83 enum { 84 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 85 }; 86 87 enum { 88 MLX5_MIN_PKEY_TABLE_SIZE = 128, 89 MLX5_MAX_LOG_PKEY_TABLE = 5, 90 }; 91 92 enum { 93 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 94 }; 95 96 enum { 97 MLX5_PFAULT_SUBTYPE_WQE = 0, 98 MLX5_PFAULT_SUBTYPE_RDMA = 1, 99 MLX5_PFAULT_SUBTYPE_MEMORY = 2, 100 }; 101 102 enum wqe_page_fault_type { 103 MLX5_WQE_PF_TYPE_RMP = 0, 104 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, 105 MLX5_WQE_PF_TYPE_RESP = 2, 106 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, 107 }; 108 109 enum { 110 MLX5_PERM_LOCAL_READ = 1 << 2, 111 MLX5_PERM_LOCAL_WRITE = 1 << 3, 112 MLX5_PERM_REMOTE_READ = 1 << 4, 113 MLX5_PERM_REMOTE_WRITE = 1 << 5, 114 MLX5_PERM_ATOMIC = 1 << 6, 115 MLX5_PERM_UMR_EN = 1 << 7, 116 }; 117 118 enum { 119 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 120 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 121 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 122 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 123 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 124 }; 125 126 enum { 127 MLX5_EN_RD = (u64)1, 128 MLX5_EN_WR = (u64)2 129 }; 130 131 enum { 132 MLX5_ADAPTER_PAGE_SHIFT = 12, 133 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 134 }; 135 136 enum { 137 MLX5_BFREGS_PER_UAR = 4, 138 MLX5_MAX_UARS = 1 << 8, 139 MLX5_NON_FP_BFREGS_PER_UAR = 2, 140 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 141 MLX5_NON_FP_BFREGS_PER_UAR, 142 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 143 MLX5_NON_FP_BFREGS_PER_UAR, 144 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 145 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 146 MLX5_MIN_DYN_BFREGS = 512, 147 MLX5_MAX_DYN_BFREGS = 1024, 148 }; 149 150 enum { 151 MLX5_MKEY_MASK_LEN = 1ull << 0, 152 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 153 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 154 MLX5_MKEY_MASK_PD = 1ull << 7, 155 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 156 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 157 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 158 MLX5_MKEY_MASK_KEY = 1ull << 13, 159 MLX5_MKEY_MASK_QPN = 1ull << 14, 160 MLX5_MKEY_MASK_LR = 1ull << 17, 161 MLX5_MKEY_MASK_LW = 1ull << 18, 162 MLX5_MKEY_MASK_RR = 1ull << 19, 163 MLX5_MKEY_MASK_RW = 1ull << 20, 164 MLX5_MKEY_MASK_A = 1ull << 21, 165 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 166 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25, 167 MLX5_MKEY_MASK_FREE = 1ull << 29, 168 MLX5_MKEY_MASK_PAGE_SIZE_5 = 1ull << 42, 169 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47, 170 }; 171 172 enum { 173 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 174 175 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 176 MLX5_UMR_CHECK_FREE = (2 << 5), 177 178 MLX5_UMR_INLINE = (1 << 7), 179 }; 180 181 #define MLX5_UMR_ALIGN (2048) 182 #define MLX5_UMR_FLEX_ALIGNMENT 0x40 183 #define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt)) 184 #define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm)) 185 #define MLX5_UMR_KSM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_ksm)) 186 187 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 188 189 enum { 190 MLX5_EVENT_QUEUE_TYPE_QP = 0, 191 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 192 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 193 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 194 }; 195 196 enum mlx5_driver_event { 197 MLX5_DRIVER_EVENT_TYPE_TRAP = 0, 198 MLX5_DRIVER_EVENT_UPLINK_NETDEV, 199 MLX5_DRIVER_EVENT_MACSEC_SA_ADDED, 200 MLX5_DRIVER_EVENT_MACSEC_SA_DELETED, 201 MLX5_DRIVER_EVENT_SF_PEER_DEVLINK, 202 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 203 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 204 MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE, 205 }; 206 207 enum { 208 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, 209 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, 210 MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2, 211 }; 212 213 enum { 214 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 215 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 216 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7, 217 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8, 218 }; 219 220 enum { 221 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 222 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 223 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 224 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 225 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 226 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 227 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 228 }; 229 230 enum { 231 MLX5_ROCE_VERSION_1 = 0, 232 MLX5_ROCE_VERSION_2 = 2, 233 }; 234 235 enum { 236 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 237 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 238 }; 239 240 enum { 241 MLX5_ROCE_L3_TYPE_IPV4 = 0, 242 MLX5_ROCE_L3_TYPE_IPV6 = 1, 243 }; 244 245 enum { 246 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 247 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 248 }; 249 250 enum { 251 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 252 MLX5_RECV_OPCODE_SEND = 0x01, 253 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 254 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 255 256 MLX5_CQE_OPCODE_ERROR = 0x1e, 257 MLX5_CQE_OPCODE_RESIZE = 0x16, 258 }; 259 260 enum { 261 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, 262 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, 263 }; 264 265 enum { 266 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, 267 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, 268 }; 269 270 struct mlx5_wqe_tls_static_params_seg { 271 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; 272 }; 273 274 struct mlx5_wqe_tls_progress_params_seg { 275 __be32 tis_tir_num; 276 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; 277 }; 278 279 enum { 280 MLX5_SET_PORT_RESET_QKEY = 0, 281 MLX5_SET_PORT_GUID0 = 16, 282 MLX5_SET_PORT_NODE_GUID = 17, 283 MLX5_SET_PORT_SYS_GUID = 18, 284 MLX5_SET_PORT_GID_TABLE = 19, 285 MLX5_SET_PORT_PKEY_TABLE = 20, 286 }; 287 288 enum { 289 MLX5_BW_NO_LIMIT = 0, 290 MLX5_100_MBPS_UNIT = 3, 291 MLX5_GBPS_UNIT = 4, 292 }; 293 294 enum { 295 MLX5_MAX_PAGE_SHIFT = 31 296 }; 297 298 enum { 299 /* 300 * Max wqe size for rdma read is 512 bytes, so this 301 * limits our max_sge_rd as the wqe needs to fit: 302 * - ctrl segment (16 bytes) 303 * - rdma segment (16 bytes) 304 * - scatter elements (16 bytes each) 305 */ 306 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 307 }; 308 309 enum mlx5_odp_transport_cap_bits { 310 MLX5_ODP_SUPPORT_SEND = 1 << 31, 311 MLX5_ODP_SUPPORT_RECV = 1 << 30, 312 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 313 MLX5_ODP_SUPPORT_READ = 1 << 28, 314 }; 315 316 struct mlx5_odp_caps { 317 char reserved[0x10]; 318 struct { 319 __be32 rc_odp_caps; 320 __be32 uc_odp_caps; 321 __be32 ud_odp_caps; 322 } per_transport_caps; 323 char reserved2[0xe4]; 324 }; 325 326 struct mlx5_cmd_layout { 327 u8 type; 328 u8 rsvd0[3]; 329 __be32 inlen; 330 __be64 in_ptr; 331 __be32 in[4]; 332 __be32 out[4]; 333 __be64 out_ptr; 334 __be32 outlen; 335 u8 token; 336 u8 sig; 337 u8 rsvd1; 338 u8 status_own; 339 }; 340 341 enum mlx5_rfr_severity_bit_offsets { 342 MLX5_CRR_BIT_OFFSET = 0x6, 343 MLX5_RFR_BIT_OFFSET = 0x7, 344 }; 345 346 struct health_buffer { 347 __be32 assert_var[6]; 348 __be32 rsvd0[2]; 349 __be32 assert_exit_ptr; 350 __be32 assert_callra; 351 __be32 rsvd1[1]; 352 __be32 time; 353 __be32 fw_ver; 354 __be32 hw_id; 355 u8 rfr_severity; 356 u8 rsvd2[3]; 357 u8 irisc_index; 358 u8 synd; 359 __be16 ext_synd; 360 }; 361 362 enum mlx5_initializing_bit_offsets { 363 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 364 }; 365 366 enum mlx5_cmd_addr_l_sz_offset { 367 MLX5_NIC_IFC_OFFSET = 8, 368 }; 369 370 struct mlx5_init_seg { 371 __be32 fw_rev; 372 __be32 cmdif_rev_fw_sub; 373 __be32 rsvd0[2]; 374 __be32 cmdq_addr_h; 375 __be32 cmdq_addr_l_sz; 376 __be32 cmd_dbell; 377 __be32 rsvd1[120]; 378 __be32 initializing; 379 struct health_buffer health; 380 __be32 rsvd2[878]; 381 __be32 cmd_exec_to; 382 __be32 cmd_q_init_to; 383 __be32 internal_timer_h; 384 __be32 internal_timer_l; 385 __be32 rsvd3[2]; 386 __be32 health_counter; 387 __be32 rsvd4[11]; 388 __be32 real_time_h; 389 __be32 real_time_l; 390 __be32 rsvd5[1006]; 391 __be64 ieee1588_clk; 392 __be32 ieee1588_clk_type; 393 __be32 clr_intx; 394 }; 395 396 struct mlx5_eqe_comp { 397 __be32 reserved[6]; 398 __be32 cqn; 399 }; 400 401 struct mlx5_eqe_qp_srq { 402 __be32 reserved1[5]; 403 u8 type; 404 u8 reserved2[3]; 405 __be32 qp_srq_n; 406 }; 407 408 struct mlx5_eqe_cq_err { 409 __be32 cqn; 410 u8 reserved1[7]; 411 u8 syndrome; 412 }; 413 414 struct mlx5_eqe_xrq_err { 415 __be32 reserved1[5]; 416 __be32 type_xrqn; 417 __be32 reserved2; 418 }; 419 420 struct mlx5_eqe_port_state { 421 u8 reserved0[8]; 422 u8 port; 423 }; 424 425 struct mlx5_eqe_gpio { 426 __be32 reserved0[2]; 427 __be64 gpio_event; 428 }; 429 430 struct mlx5_eqe_congestion { 431 u8 type; 432 u8 rsvd0; 433 u8 congestion_level; 434 }; 435 436 struct mlx5_eqe_stall_vl { 437 u8 rsvd0[3]; 438 u8 port_vl; 439 }; 440 441 struct mlx5_eqe_cmd { 442 __be32 vector; 443 __be32 rsvd[6]; 444 }; 445 446 struct mlx5_eqe_page_req { 447 __be16 ec_function; 448 __be16 func_id; 449 __be32 num_pages; 450 __be32 rsvd1[5]; 451 }; 452 453 #define MEMORY_SCHEME_PAGE_FAULT_GRANULARITY 4096 454 struct mlx5_eqe_page_fault { 455 union { 456 struct { 457 __be32 bytes_committed; 458 u16 reserved1; 459 __be16 wqe_index; 460 u16 reserved2; 461 __be16 packet_length; 462 __be32 token; 463 u8 reserved4[8]; 464 __be32 pftype_wq; 465 } __packed wqe; 466 struct { 467 __be32 bytes_committed; 468 __be32 r_key; 469 u16 reserved1; 470 __be16 packet_length; 471 __be32 rdma_op_len; 472 __be64 rdma_va; 473 __be32 pftype_token; 474 } __packed rdma; 475 struct { 476 u8 flags; 477 u8 reserved1; 478 __be16 post_demand_fault_pages; 479 __be16 pre_demand_fault_pages; 480 __be16 token47_32; 481 __be32 token31_0; 482 /* 483 * FW changed from specifying the fault size in byte 484 * count to 4k pages granularity. The size specified 485 * in pages uses bits 31:12, to keep backward 486 * compatibility. 487 */ 488 __be32 demand_fault_pages; 489 __be32 mkey; 490 __be64 va; 491 } __packed memory; 492 } __packed; 493 } __packed; 494 495 struct mlx5_eqe_vport_change { 496 u8 rsvd0[2]; 497 __be16 vport_num; 498 __be32 rsvd1[6]; 499 } __packed; 500 501 struct mlx5_eqe_port_module { 502 u8 reserved_at_0[1]; 503 u8 module; 504 u8 reserved_at_2[1]; 505 u8 module_status; 506 u8 reserved_at_4[2]; 507 u8 error_type; 508 } __packed; 509 510 struct mlx5_eqe_pps { 511 u8 rsvd0[3]; 512 u8 pin; 513 u8 rsvd1[4]; 514 union { 515 struct { 516 __be32 time_sec; 517 __be32 time_nsec; 518 }; 519 struct { 520 __be64 time_stamp; 521 }; 522 }; 523 u8 rsvd2[12]; 524 } __packed; 525 526 struct mlx5_eqe_dct { 527 __be32 reserved[6]; 528 __be32 dctn; 529 }; 530 531 struct mlx5_eqe_temp_warning { 532 __be64 sensor_warning_msb; 533 __be64 sensor_warning_lsb; 534 } __packed; 535 536 struct mlx5_eqe_obj_change { 537 u8 rsvd0[2]; 538 __be16 obj_type; 539 __be32 obj_id; 540 } __packed; 541 542 #define SYNC_RST_STATE_MASK 0xf 543 544 enum sync_rst_state_type { 545 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0, 546 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1, 547 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2, 548 MLX5_SYNC_RST_STATE_RESET_UNLOAD = 0x3, 549 }; 550 551 struct mlx5_eqe_sync_fw_update { 552 u8 reserved_at_0[3]; 553 u8 sync_rst_state; 554 }; 555 556 struct mlx5_eqe_vhca_state { 557 __be16 ec_function; 558 __be16 function_id; 559 } __packed; 560 561 union ev_data { 562 __be32 raw[7]; 563 struct mlx5_eqe_cmd cmd; 564 struct mlx5_eqe_comp comp; 565 struct mlx5_eqe_qp_srq qp_srq; 566 struct mlx5_eqe_cq_err cq_err; 567 struct mlx5_eqe_port_state port; 568 struct mlx5_eqe_gpio gpio; 569 struct mlx5_eqe_congestion cong; 570 struct mlx5_eqe_stall_vl stall_vl; 571 struct mlx5_eqe_page_req req_pages; 572 struct mlx5_eqe_page_fault page_fault; 573 struct mlx5_eqe_vport_change vport_change; 574 struct mlx5_eqe_port_module port_module; 575 struct mlx5_eqe_pps pps; 576 struct mlx5_eqe_dct dct; 577 struct mlx5_eqe_temp_warning temp_warning; 578 struct mlx5_eqe_xrq_err xrq_err; 579 struct mlx5_eqe_sync_fw_update sync_fw_update; 580 struct mlx5_eqe_vhca_state vhca_state; 581 struct mlx5_eqe_obj_change obj_change; 582 } __packed; 583 584 struct mlx5_eqe { 585 u8 rsvd0; 586 u8 type; 587 u8 rsvd1; 588 u8 sub_type; 589 __be32 rsvd2[7]; 590 union ev_data data; 591 __be16 rsvd3; 592 u8 signature; 593 u8 owner; 594 } __packed; 595 596 struct mlx5_cmd_prot_block { 597 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 598 u8 rsvd0[48]; 599 __be64 next; 600 __be32 block_num; 601 u8 rsvd1; 602 u8 token; 603 u8 ctrl_sig; 604 u8 sig; 605 }; 606 607 enum { 608 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 609 }; 610 611 struct mlx5_err_cqe { 612 u8 rsvd0[32]; 613 __be32 srqn; 614 u8 rsvd1[18]; 615 u8 vendor_err_synd; 616 u8 syndrome; 617 __be32 s_wqe_opcode_qpn; 618 __be16 wqe_counter; 619 u8 signature; 620 u8 op_own; 621 }; 622 623 struct mlx5_cqe64 { 624 u8 tls_outer_l3_tunneled; 625 u8 rsvd0; 626 __be16 wqe_id; 627 union { 628 struct { 629 u8 tcppsh_abort_dupack; 630 u8 min_ttl; 631 __be16 tcp_win; 632 __be32 ack_seq_num; 633 } lro; 634 struct { 635 u8 reserved0:1; 636 u8 match:1; 637 u8 flush:1; 638 u8 reserved3:5; 639 u8 header_size; 640 __be16 header_entry_index; 641 __be32 data_offset; 642 } shampo; 643 }; 644 __be32 rss_hash_result; 645 u8 rss_hash_type; 646 u8 ml_path; 647 u8 rsvd20[2]; 648 __be16 check_sum; 649 __be16 slid; 650 __be32 flags_rqpn; 651 u8 hds_ip_ext; 652 u8 l4_l3_hdr_type; 653 __be16 vlan_info; 654 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 655 union { 656 __be32 immediate; 657 __be32 inval_rkey; 658 __be32 pkey; 659 __be32 ft_metadata; 660 }; 661 u8 rsvd40[4]; 662 __be32 byte_cnt; 663 __be32 timestamp_h; 664 __be32 timestamp_l; 665 __be32 sop_drop_qpn; 666 __be16 wqe_counter; 667 union { 668 u8 signature; 669 u8 validity_iteration_count; 670 }; 671 u8 op_own; 672 }; 673 674 struct mlx5_mini_cqe8 { 675 union { 676 __be32 rx_hash_result; 677 struct { 678 __be16 checksum; 679 __be16 stridx; 680 }; 681 struct { 682 __be16 wqe_counter; 683 u8 s_wqe_opcode; 684 u8 reserved; 685 } s_wqe_info; 686 }; 687 __be32 byte_cnt; 688 }; 689 690 enum { 691 MLX5_NO_INLINE_DATA, 692 MLX5_INLINE_DATA32_SEG, 693 MLX5_INLINE_DATA64_SEG, 694 MLX5_COMPRESSED, 695 }; 696 697 enum { 698 MLX5_CQE_FORMAT_CSUM = 0x1, 699 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3, 700 }; 701 702 enum { 703 MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0, 704 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1, 705 }; 706 707 #define MLX5_MINI_CQE_ARRAY_SIZE 8 708 709 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 710 { 711 return (cqe->op_own >> 2) & 0x3; 712 } 713 714 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 715 { 716 return cqe->op_own >> 4; 717 } 718 719 static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe) 720 { 721 /* num_of_mini_cqes is zero based */ 722 return get_cqe_opcode(cqe) + 1; 723 } 724 725 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 726 { 727 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1; 728 } 729 730 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 731 { 732 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 733 } 734 735 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 736 { 737 return cqe->tls_outer_l3_tunneled & 0x1; 738 } 739 740 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) 741 { 742 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; 743 } 744 745 static inline bool cqe_has_vlan(const struct mlx5_cqe64 *cqe) 746 { 747 return cqe->l4_l3_hdr_type & 0x1; 748 } 749 750 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 751 { 752 u32 hi, lo; 753 754 hi = be32_to_cpu(cqe->timestamp_h); 755 lo = be32_to_cpu(cqe->timestamp_l); 756 757 return (u64)lo | ((u64)hi << 32); 758 } 759 760 static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe) 761 { 762 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF; 763 } 764 765 static inline u8 get_cqe_lro_num_seg(struct mlx5_cqe64 *cqe) 766 { 767 return be32_to_cpu(cqe->srqn) >> 24; 768 } 769 770 #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3 771 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9 772 #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16 773 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6 774 #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13 775 776 struct mpwrq_cqe_bc { 777 __be16 filler_consumed_strides; 778 __be16 byte_cnt; 779 }; 780 781 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 782 { 783 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 784 785 return be16_to_cpu(bc->byte_cnt); 786 } 787 788 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 789 { 790 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 791 } 792 793 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 794 { 795 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 796 797 return mpwrq_get_cqe_bc_consumed_strides(bc); 798 } 799 800 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 801 { 802 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 803 804 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 805 } 806 807 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 808 { 809 return be16_to_cpu(cqe->wqe_counter); 810 } 811 812 enum { 813 CQE_L4_HDR_TYPE_NONE = 0x0, 814 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 815 CQE_L4_HDR_TYPE_UDP = 0x2, 816 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 817 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 818 }; 819 820 enum { 821 CQE_RSS_HTYPE_IP = GENMASK(3, 2), 822 /* cqe->rss_hash_type[3:2] - IP destination selected for hash 823 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) 824 */ 825 CQE_RSS_IP_NONE = 0x0, 826 CQE_RSS_IPV4 = 0x1, 827 CQE_RSS_IPV6 = 0x2, 828 CQE_RSS_RESERVED = 0x3, 829 830 CQE_RSS_HTYPE_L4 = GENMASK(7, 6), 831 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash 832 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI 833 */ 834 CQE_RSS_L4_NONE = 0x0, 835 CQE_RSS_L4_TCP = 0x1, 836 CQE_RSS_L4_UDP = 0x2, 837 CQE_RSS_L4_IPSEC = 0x3, 838 }; 839 840 enum { 841 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 842 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 843 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 844 }; 845 846 enum { 847 CQE_L2_OK = 1 << 0, 848 CQE_L3_OK = 1 << 1, 849 CQE_L4_OK = 1 << 2, 850 }; 851 852 enum { 853 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, 854 CQE_TLS_OFFLOAD_DECRYPTED = 0x1, 855 CQE_TLS_OFFLOAD_RESYNC = 0x2, 856 CQE_TLS_OFFLOAD_ERROR = 0x3, 857 }; 858 859 struct mlx5_sig_err_cqe { 860 u8 rsvd0[16]; 861 __be32 expected_trans_sig; 862 __be32 actual_trans_sig; 863 __be32 expected_reftag; 864 __be32 actual_reftag; 865 __be16 syndrome; 866 u8 rsvd22[2]; 867 __be32 mkey; 868 __be64 err_offset; 869 u8 rsvd30[8]; 870 __be32 qpn; 871 u8 rsvd38[2]; 872 u8 signature; 873 u8 op_own; 874 }; 875 876 struct mlx5_wqe_srq_next_seg { 877 u8 rsvd0[2]; 878 __be16 next_wqe_index; 879 u8 signature; 880 u8 rsvd1[11]; 881 }; 882 883 union mlx5_ext_cqe { 884 struct ib_grh grh; 885 u8 inl[64]; 886 }; 887 888 struct mlx5_cqe128 { 889 union mlx5_ext_cqe inl_grh; 890 struct mlx5_cqe64 cqe64; 891 }; 892 893 enum { 894 MLX5_MKEY_STATUS_FREE = 1 << 6, 895 }; 896 897 enum { 898 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 899 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 900 MLX5_MKEY_BSF_EN = 1 << 30, 901 }; 902 903 struct mlx5_mkey_seg { 904 /* This is a two bit field occupying bits 31-30. 905 * bit 31 is always 0, 906 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation 907 */ 908 u8 status; 909 u8 pcie_control; 910 u8 flags; 911 u8 version; 912 __be32 qpn_mkey7_0; 913 u8 rsvd1[4]; 914 __be32 flags_pd; 915 __be64 start_addr; 916 __be64 len; 917 __be32 bsfs_octo_size; 918 u8 rsvd2[16]; 919 __be32 xlt_oct_size; 920 u8 rsvd3[3]; 921 u8 log2_page_size; 922 u8 rsvd4[4]; 923 }; 924 925 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 926 927 enum { 928 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 929 }; 930 931 enum { 932 VPORT_STATE_DOWN = 0x0, 933 VPORT_STATE_UP = 0x1, 934 }; 935 936 enum { 937 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, 938 MLX5_VPORT_ADMIN_STATE_UP = 0x1, 939 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, 940 }; 941 942 enum { 943 MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1, 944 MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3, 945 }; 946 947 enum { 948 MLX5_L3_PROT_TYPE_IPV4 = 0, 949 MLX5_L3_PROT_TYPE_IPV6 = 1, 950 }; 951 952 enum { 953 MLX5_L4_PROT_TYPE_TCP = 0, 954 MLX5_L4_PROT_TYPE_UDP = 1, 955 }; 956 957 enum { 958 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 959 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 960 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 961 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 962 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 963 }; 964 965 enum { 966 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 967 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 968 MLX5_MATCH_INNER_HEADERS = 1 << 2, 969 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, 970 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, 971 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5, 972 MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6, 973 MLX5_MATCH_MISC_PARAMETERS_6 = 1 << 7, 974 }; 975 976 enum { 977 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 978 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 979 }; 980 981 enum { 982 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 983 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 984 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 985 }; 986 987 enum mlx5_list_type { 988 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 989 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 990 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 991 }; 992 993 enum { 994 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 995 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 996 }; 997 998 enum mlx5_wol_mode { 999 MLX5_WOL_DISABLE = 0, 1000 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1001 MLX5_WOL_MAGIC = 1 << 2, 1002 MLX5_WOL_ARP = 1 << 3, 1003 MLX5_WOL_BROADCAST = 1 << 4, 1004 MLX5_WOL_MULTICAST = 1 << 5, 1005 MLX5_WOL_UNICAST = 1 << 6, 1006 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1007 }; 1008 1009 enum mlx5_mpls_supported_fields { 1010 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, 1011 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, 1012 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, 1013 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 1014 }; 1015 1016 enum mlx5_flex_parser_protos { 1017 MLX5_FLEX_PROTO_GENEVE = 1 << 3, 1018 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, 1019 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, 1020 MLX5_FLEX_PROTO_ICMP = 1 << 8, 1021 MLX5_FLEX_PROTO_ICMPV6 = 1 << 9, 1022 }; 1023 1024 /* MLX5 DEV CAPs */ 1025 1026 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate 1027 * capability memory. 1028 */ 1029 enum mlx5_cap_type { 1030 MLX5_CAP_GENERAL = 0, 1031 MLX5_CAP_ETHERNET_OFFLOADS, 1032 MLX5_CAP_ODP, 1033 MLX5_CAP_ATOMIC, 1034 MLX5_CAP_ROCE, 1035 MLX5_CAP_IPOIB_OFFLOADS, 1036 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1037 MLX5_CAP_FLOW_TABLE, 1038 MLX5_CAP_ESWITCH_FLOW_TABLE, 1039 MLX5_CAP_ESWITCH, 1040 MLX5_CAP_QOS = 0xc, 1041 MLX5_CAP_DEBUG, 1042 MLX5_CAP_RESERVED_14, 1043 MLX5_CAP_DEV_MEM, 1044 MLX5_CAP_RESERVED_16, 1045 MLX5_CAP_TLS, 1046 MLX5_CAP_VDPA_EMULATION = 0x13, 1047 MLX5_CAP_DEV_EVENT = 0x14, 1048 MLX5_CAP_IPSEC, 1049 MLX5_CAP_CRYPTO = 0x1a, 1050 MLX5_CAP_SHAMPO = 0x1d, 1051 MLX5_CAP_PSP = 0x1e, 1052 MLX5_CAP_MACSEC = 0x1f, 1053 MLX5_CAP_GENERAL_2 = 0x20, 1054 MLX5_CAP_PORT_SELECTION = 0x25, 1055 MLX5_CAP_ADV_VIRTUALIZATION = 0x26, 1056 MLX5_CAP_ADV_RDMA = 0x28, 1057 MLX5_CAP_TLP_EMULATION = 0x2a, 1058 /* NUM OF CAP Types */ 1059 MLX5_CAP_NUM 1060 }; 1061 1062 enum mlx5_pcam_reg_groups { 1063 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 1064 }; 1065 1066 enum mlx5_pcam_feature_groups { 1067 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1068 }; 1069 1070 enum mlx5_mcam_reg_groups { 1071 MLX5_MCAM_REGS_FIRST_128 = 0x0, 1072 MLX5_MCAM_REGS_0x9100_0x917F = 0x2, 1073 MLX5_MCAM_REGS_0x9180_0x91FF = 0x3, 1074 MLX5_MCAM_REGS_NUM = 0x4, 1075 }; 1076 1077 enum mlx5_mcam_feature_groups { 1078 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1079 }; 1080 1081 enum mlx5_qcam_reg_groups { 1082 MLX5_QCAM_REGS_FIRST_128 = 0x0, 1083 }; 1084 1085 enum mlx5_qcam_feature_groups { 1086 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1087 }; 1088 1089 /* GET Dev Caps macros */ 1090 #define MLX5_CAP_GEN(mdev, cap) \ 1091 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) 1092 1093 #define MLX5_CAP_GEN_64(mdev, cap) \ 1094 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) 1095 1096 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1097 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap) 1098 1099 #define MLX5_CAP_GEN_2(mdev, cap) \ 1100 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) 1101 1102 #define MLX5_CAP_GEN_2_64(mdev, cap) \ 1103 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) 1104 1105 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \ 1106 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap) 1107 1108 #define MLX5_CAP_ETH(mdev, cap) \ 1109 MLX5_GET(per_protocol_networking_offload_caps,\ 1110 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap) 1111 1112 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ 1113 MLX5_GET(per_protocol_networking_offload_caps,\ 1114 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap) 1115 1116 #define MLX5_CAP_ROCE(mdev, cap) \ 1117 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap) 1118 1119 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1120 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap) 1121 1122 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1123 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap) 1124 1125 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1126 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap) 1127 1128 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1129 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) 1130 1131 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ 1132 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) 1133 1134 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1135 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1136 1137 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ 1138 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) 1139 1140 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1141 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1142 1143 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1144 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1145 1146 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ 1147 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) 1148 1149 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ 1150 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) 1151 1152 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \ 1153 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_rx_flow_table_properties.cap) 1154 1155 #define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \ 1156 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_tx_flow_table_properties.cap) 1157 1158 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1159 MLX5_GET(flow_table_eswitch_cap, \ 1160 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) 1161 1162 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1163 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1164 1165 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1166 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1167 1168 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1169 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1170 1171 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \ 1172 MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap) 1173 1174 #define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \ 1175 MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap) 1176 1177 #define MLX5_CAP_ESW(mdev, cap) \ 1178 MLX5_GET(e_switch_cap, \ 1179 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap) 1180 1181 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ 1182 MLX5_GET64(flow_table_eswitch_cap, \ 1183 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) 1184 1185 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \ 1186 MLX5_GET(port_selection_cap, \ 1187 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap) 1188 1189 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \ 1190 MLX5_GET(port_selection_cap, \ 1191 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap) 1192 1193 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \ 1194 MLX5_GET(adv_virtualization_cap, \ 1195 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap) 1196 1197 #define MLX5_CAP_ADV_RDMA(mdev, cap) \ 1198 MLX5_GET(adv_rdma_cap, \ 1199 mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap) 1200 1201 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ 1202 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap) 1203 1204 #define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \ 1205 MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap) 1206 1207 #define MLX5_CAP_ODP(mdev, cap)\ 1208 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap) 1209 1210 #define MLX5_CAP_ODP_SCHEME(mdev, cap) \ 1211 (MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \ 1212 mem_page_fault) ? \ 1213 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \ 1214 memory_page_fault_scheme_cap.cap) : \ 1215 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \ 1216 transport_page_fault_scheme_cap.cap)) 1217 1218 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1219 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap) 1220 1221 #define MLX5_CAP_QOS(mdev, cap)\ 1222 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap) 1223 1224 #define MLX5_CAP_DEBUG(mdev, cap)\ 1225 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap) 1226 1227 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1228 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1229 1230 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1231 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1232 1233 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1234 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ 1235 mng_access_reg_cap_mask.access_regs.reg) 1236 1237 #define MLX5_CAP_MCAM_REG2(mdev, reg) \ 1238 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ 1239 mng_access_reg_cap_mask.access_regs2.reg) 1240 1241 #define MLX5_CAP_MCAM_REG3(mdev, reg) \ 1242 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \ 1243 mng_access_reg_cap_mask.access_regs3.reg) 1244 1245 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1246 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1247 1248 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1249 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1250 1251 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1252 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1253 1254 #define MLX5_CAP_FPGA(mdev, cap) \ 1255 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1256 1257 #define MLX5_CAP64_FPGA(mdev, cap) \ 1258 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1259 1260 #define MLX5_CAP_DEV_MEM(mdev, cap)\ 1261 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) 1262 1263 #define MLX5_CAP64_DEV_MEM(mdev, cap)\ 1264 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) 1265 1266 #define MLX5_CAP_TLS(mdev, cap) \ 1267 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap) 1268 1269 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ 1270 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap) 1271 1272 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ 1273 MLX5_GET(virtio_emulation_cap, \ 1274 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) 1275 1276 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ 1277 MLX5_GET64(virtio_emulation_cap, \ 1278 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) 1279 1280 #define MLX5_CAP_DEV_TLP_EMULATION(mdev, cap)\ 1281 MLX5_GET(tlp_dev_emu_capabilities, \ 1282 (mdev)->caps.hca[MLX5_CAP_TLP_EMULATION]->cur, cap) 1283 1284 #define MLX5_CAP64_DEV_TLP_EMULATION(mdev, cap)\ 1285 MLX5_GET64(tlp_dev_emu_capabilities, \ 1286 (mdev)->caps.hca[MLX5_CAP_TLP_EMULATION]->cur, cap) 1287 1288 #define MLX5_CAP_IPSEC(mdev, cap)\ 1289 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap) 1290 1291 #define MLX5_CAP_CRYPTO(mdev, cap)\ 1292 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap) 1293 1294 #define MLX5_CAP_MACSEC(mdev, cap)\ 1295 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap) 1296 1297 #define MLX5_CAP_SHAMPO(mdev, cap) \ 1298 MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap) 1299 1300 #define MLX5_CAP_PSP(mdev, cap)\ 1301 MLX5_GET(psp_cap, (mdev)->caps.hca[MLX5_CAP_PSP]->cur, cap) 1302 1303 enum { 1304 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1305 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1306 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1307 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1308 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1309 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1310 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1311 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1312 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, 1313 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1314 MLX5_PHYSICAL_LAYER_RECOVERY_GROUP = 0x1a, 1315 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1316 MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP = 0x21, 1317 MLX5_RS_FEC_HISTOGRAM_GROUP = 0x23, 1318 }; 1319 1320 enum { 1321 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1322 }; 1323 1324 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1325 { 1326 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1327 return 0; 1328 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1329 } 1330 1331 #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 6 1332 #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 4 1333 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 1334 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 1335 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1336 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1337 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1338 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1339 1340 #endif /* MLX5_DEVICE_H */ 1341