xref: /linux/include/linux/mlx5/driver.h (revision 07fdad3a93756b872da7b53647715c48d0f4a2d0) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/pci-tph.h>
40 #include <linux/irq.h>
41 #include <linux/spinlock_types.h>
42 #include <linux/semaphore.h>
43 #include <linux/slab.h>
44 #include <linux/vmalloc.h>
45 #include <linux/xarray.h>
46 #include <linux/workqueue.h>
47 #include <linux/mempool.h>
48 #include <linux/interrupt.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53 
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <net/devlink.h>
59 
60 #define MLX5_ADEV_NAME "mlx5_core"
61 
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63 
64 enum {
65 	MLX5_BOARD_ID_LEN = 64,
66 };
67 
68 enum {
69 	MLX5_CMD_WQ_MAX_NAME	= 32,
70 };
71 
72 enum {
73 	CMD_OWNER_SW		= 0x0,
74 	CMD_OWNER_HW		= 0x1,
75 	CMD_STATUS_SUCCESS	= 0,
76 };
77 
78 enum mlx5_sqp_t {
79 	MLX5_SQP_SMI		= 0,
80 	MLX5_SQP_GSI		= 1,
81 	MLX5_SQP_IEEE_1588	= 2,
82 	MLX5_SQP_SNIFFER	= 3,
83 	MLX5_SQP_SYNC_UMR	= 4,
84 };
85 
86 enum {
87 	MLX5_MAX_PORTS	= 8,
88 };
89 
90 enum {
91 	MLX5_ATOMIC_MODE_OFFSET = 16,
92 	MLX5_ATOMIC_MODE_IB_COMP = 1,
93 	MLX5_ATOMIC_MODE_CX = 2,
94 	MLX5_ATOMIC_MODE_8B = 3,
95 	MLX5_ATOMIC_MODE_16B = 4,
96 	MLX5_ATOMIC_MODE_32B = 5,
97 	MLX5_ATOMIC_MODE_64B = 6,
98 	MLX5_ATOMIC_MODE_128B = 7,
99 	MLX5_ATOMIC_MODE_256B = 8,
100 };
101 
102 enum {
103 	MLX5_REG_SBPR            = 0xb001,
104 	MLX5_REG_SBCM            = 0xb002,
105 	MLX5_REG_QPTS            = 0x4002,
106 	MLX5_REG_QETCR		 = 0x4005,
107 	MLX5_REG_QTCT		 = 0x400a,
108 	MLX5_REG_QPDPM           = 0x4013,
109 	MLX5_REG_QCAM            = 0x4019,
110 	MLX5_REG_DCBX_PARAM      = 0x4020,
111 	MLX5_REG_DCBX_APP        = 0x4021,
112 	MLX5_REG_FPGA_CAP	 = 0x4022,
113 	MLX5_REG_FPGA_CTRL	 = 0x4023,
114 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 	MLX5_REG_CORE_DUMP	 = 0x402e,
116 	MLX5_REG_PCAP		 = 0x5001,
117 	MLX5_REG_PMTU		 = 0x5003,
118 	MLX5_REG_PTYS		 = 0x5004,
119 	MLX5_REG_PAOS		 = 0x5006,
120 	MLX5_REG_PFCC            = 0x5007,
121 	MLX5_REG_PPCNT		 = 0x5008,
122 	MLX5_REG_PPTB            = 0x500b,
123 	MLX5_REG_PBMC            = 0x500c,
124 	MLX5_REG_PMAOS		 = 0x5012,
125 	MLX5_REG_PUDE		 = 0x5009,
126 	MLX5_REG_PMPE		 = 0x5010,
127 	MLX5_REG_PELC		 = 0x500e,
128 	MLX5_REG_PVLC		 = 0x500f,
129 	MLX5_REG_PCMR		 = 0x5041,
130 	MLX5_REG_PDDR		 = 0x5031,
131 	MLX5_REG_PMLP		 = 0x5002,
132 	MLX5_REG_PPLM		 = 0x5023,
133 	MLX5_REG_PPHCR		 = 0x503E,
134 	MLX5_REG_PCAM		 = 0x507f,
135 	MLX5_REG_NODE_DESC	 = 0x6001,
136 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 	MLX5_REG_MTCAP		 = 0x9009,
138 	MLX5_REG_MTMP		 = 0x900A,
139 	MLX5_REG_MCIA		 = 0x9014,
140 	MLX5_REG_MNVDA		 = 0x9024,
141 	MLX5_REG_MFRL		 = 0x9028,
142 	MLX5_REG_MLCR		 = 0x902b,
143 	MLX5_REG_MRTC		 = 0x902d,
144 	MLX5_REG_MTRC_CAP	 = 0x9040,
145 	MLX5_REG_MTRC_CONF	 = 0x9041,
146 	MLX5_REG_MTRC_STDB	 = 0x9042,
147 	MLX5_REG_MTRC_CTRL	 = 0x9043,
148 	MLX5_REG_MPEIN		 = 0x9050,
149 	MLX5_REG_MPCNT		 = 0x9051,
150 	MLX5_REG_MTPPS		 = 0x9053,
151 	MLX5_REG_MTPPSE		 = 0x9054,
152 	MLX5_REG_MTUTC		 = 0x9055,
153 	MLX5_REG_MPEGC		 = 0x9056,
154 	MLX5_REG_MPIR		 = 0x9059,
155 	MLX5_REG_MCQS		 = 0x9060,
156 	MLX5_REG_MCQI		 = 0x9061,
157 	MLX5_REG_MCC		 = 0x9062,
158 	MLX5_REG_MCDA		 = 0x9063,
159 	MLX5_REG_MCAM		 = 0x907f,
160 	MLX5_REG_MSECQ		 = 0x9155,
161 	MLX5_REG_MSEES		 = 0x9156,
162 	MLX5_REG_MIRC		 = 0x9162,
163 	MLX5_REG_MTPTM		 = 0x9180,
164 	MLX5_REG_MTCTR		 = 0x9181,
165 	MLX5_REG_MRTCQ		 = 0x9182,
166 	MLX5_REG_SBCAM		 = 0xB01F,
167 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
168 	MLX5_REG_NIC_CAP	 = 0xC00D,
169 	MLX5_REG_DTOR            = 0xC00E,
170 	MLX5_REG_VHCA_ICM_CTRL	 = 0xC010,
171 };
172 
173 enum mlx5_qpts_trust_state {
174 	MLX5_QPTS_TRUST_PCP  = 1,
175 	MLX5_QPTS_TRUST_DSCP = 2,
176 };
177 
178 enum mlx5_dcbx_oper_mode {
179 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
180 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
181 };
182 
183 enum {
184 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
185 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
186 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
187 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
188 };
189 
190 enum mlx5_page_fault_resume_flags {
191 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
192 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
193 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
194 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
195 };
196 
197 enum dbg_rsc_type {
198 	MLX5_DBG_RSC_QP,
199 	MLX5_DBG_RSC_EQ,
200 	MLX5_DBG_RSC_CQ,
201 };
202 
203 enum port_state_policy {
204 	MLX5_POLICY_DOWN	= 0,
205 	MLX5_POLICY_UP		= 1,
206 	MLX5_POLICY_FOLLOW	= 2,
207 	MLX5_POLICY_INVALID	= 0xffffffff
208 };
209 
210 enum mlx5_coredev_type {
211 	MLX5_COREDEV_PF,
212 	MLX5_COREDEV_VF,
213 	MLX5_COREDEV_SF,
214 };
215 
216 struct mlx5_field_desc {
217 	int			i;
218 };
219 
220 struct mlx5_rsc_debug {
221 	struct mlx5_core_dev   *dev;
222 	void		       *object;
223 	enum dbg_rsc_type	type;
224 	struct dentry	       *root;
225 	struct mlx5_field_desc	fields[];
226 };
227 
228 enum mlx5_dev_event {
229 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
230 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
231 	MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
232 };
233 
234 enum mlx5_port_status {
235 	MLX5_PORT_UP        = 1,
236 	MLX5_PORT_DOWN      = 2,
237 };
238 
239 enum mlx5_cmdif_state {
240 	MLX5_CMDIF_STATE_UNINITIALIZED,
241 	MLX5_CMDIF_STATE_UP,
242 	MLX5_CMDIF_STATE_DOWN,
243 };
244 
245 struct mlx5_cmd_first {
246 	__be32		data[4];
247 };
248 
249 struct mlx5_cmd_msg {
250 	struct list_head		list;
251 	struct cmd_msg_cache	       *parent;
252 	u32				len;
253 	struct mlx5_cmd_first		first;
254 	struct mlx5_cmd_mailbox	       *next;
255 };
256 
257 struct mlx5_cmd_debug {
258 	struct dentry	       *dbg_root;
259 	void		       *in_msg;
260 	void		       *out_msg;
261 	u8			status;
262 	u16			inlen;
263 	u16			outlen;
264 };
265 
266 struct cmd_msg_cache {
267 	/* protect block chain allocations
268 	 */
269 	spinlock_t		lock;
270 	struct list_head	head;
271 	unsigned int		max_inbox_size;
272 	unsigned int		num_ent;
273 };
274 
275 enum {
276 	MLX5_NUM_COMMAND_CACHES = 5,
277 };
278 
279 struct mlx5_cmd_stats {
280 	u64		sum;
281 	u64		n;
282 	/* number of times command failed */
283 	u64		failed;
284 	/* number of times command failed on bad status returned by FW */
285 	u64		failed_mbox_status;
286 	/* last command failed returned errno */
287 	u32		last_failed_errno;
288 	/* last bad status returned by FW */
289 	u8		last_failed_mbox_status;
290 	/* last command failed syndrome returned by FW */
291 	u32		last_failed_syndrome;
292 	struct dentry  *root;
293 	/* protect command average calculations */
294 	spinlock_t	lock;
295 };
296 
297 struct mlx5_cmd {
298 	struct mlx5_nb    nb;
299 
300 	/* members which needs to be queried or reinitialized each reload */
301 	struct {
302 		u16		cmdif_rev;
303 		u8		log_sz;
304 		u8		log_stride;
305 		int		max_reg_cmds;
306 		unsigned long	bitmask;
307 		struct semaphore sem;
308 		struct semaphore pages_sem;
309 		struct semaphore throttle_sem;
310 		struct semaphore unprivileged_sem;
311 		struct xarray	privileged_uids;
312 	} vars;
313 	enum mlx5_cmdif_state	state;
314 	void	       *cmd_alloc_buf;
315 	dma_addr_t	alloc_dma;
316 	int		alloc_size;
317 	void	       *cmd_buf;
318 	dma_addr_t	dma;
319 
320 	/* protect command queue allocations
321 	 */
322 	spinlock_t	alloc_lock;
323 
324 	/* protect token allocations
325 	 */
326 	spinlock_t	token_lock;
327 	u8		token;
328 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
329 	struct workqueue_struct *wq;
330 	int	mode;
331 	u16     allowed_opcode;
332 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
333 	struct dma_pool *pool;
334 	struct mlx5_cmd_debug dbg;
335 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
336 	int checksum_disabled;
337 	struct xarray stats;
338 };
339 
340 struct mlx5_cmd_mailbox {
341 	void	       *buf;
342 	dma_addr_t	dma;
343 	struct mlx5_cmd_mailbox *next;
344 };
345 
346 struct mlx5_buf_list {
347 	void		       *buf;
348 	dma_addr_t		map;
349 };
350 
351 struct mlx5_frag_buf {
352 	struct mlx5_buf_list	*frags;
353 	int			npages;
354 	int			size;
355 	u8			page_shift;
356 };
357 
358 struct mlx5_frag_buf_ctrl {
359 	struct mlx5_buf_list   *frags;
360 	u32			sz_m1;
361 	u16			frag_sz_m1;
362 	u16			strides_offset;
363 	u8			log_sz;
364 	u8			log_stride;
365 	u8			log_frag_strides;
366 };
367 
368 struct mlx5_core_psv {
369 	u32	psv_idx;
370 	struct psv_layout {
371 		u32	pd;
372 		u16	syndrome;
373 		u16	reserved;
374 		u16	bg;
375 		u16	app_tag;
376 		u32	ref_tag;
377 	} psv;
378 };
379 
380 struct mlx5_core_sig_ctx {
381 	struct mlx5_core_psv	psv_memory;
382 	struct mlx5_core_psv	psv_wire;
383 	struct ib_sig_err       err_item;
384 	bool			sig_status_checked;
385 	bool			sig_err_exists;
386 	u32			sigerr_count;
387 };
388 
389 #define MLX5_24BIT_MASK		((1 << 24) - 1)
390 
391 enum mlx5_res_type {
392 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
393 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
394 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
395 	MLX5_RES_SRQ	= 3,
396 	MLX5_RES_XSRQ	= 4,
397 	MLX5_RES_XRQ	= 5,
398 };
399 
400 struct mlx5_core_rsc_common {
401 	enum mlx5_res_type	res;
402 	refcount_t		refcount;
403 	struct completion	free;
404 	bool			invalid;
405 };
406 
407 struct mlx5_uars_page {
408 	void __iomem	       *map;
409 	bool			wc;
410 	u32			index;
411 	struct list_head	list;
412 	unsigned int		bfregs;
413 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
414 	unsigned long	       *fp_bitmap;
415 	unsigned int		reg_avail;
416 	unsigned int		fp_avail;
417 	struct kref		ref_count;
418 	struct mlx5_core_dev   *mdev;
419 };
420 
421 struct mlx5_bfreg_head {
422 	/* protect blue flame registers allocations */
423 	struct mutex		lock;
424 	struct list_head	list;
425 };
426 
427 struct mlx5_bfreg_data {
428 	struct mlx5_bfreg_head	reg_head;
429 	struct mlx5_bfreg_head	wc_head;
430 };
431 
432 struct mlx5_sq_bfreg {
433 	void __iomem	       *map;
434 	struct mlx5_uars_page  *up;
435 	bool			wc;
436 	u32			index;
437 };
438 
439 struct mlx5_core_health {
440 	struct health_buffer __iomem   *health;
441 	__be32 __iomem		       *health_counter;
442 	struct timer_list		timer;
443 	u32				prev;
444 	int				miss_counter;
445 	u8				synd;
446 	u32				fatal_error;
447 	u32				crdump_size;
448 	struct workqueue_struct	       *wq;
449 	unsigned long			flags;
450 	struct work_struct		fatal_report_work;
451 	struct work_struct		report_work;
452 	struct devlink_health_reporter *fw_reporter;
453 	struct devlink_health_reporter *fw_fatal_reporter;
454 	struct devlink_health_reporter *vnic_reporter;
455 	struct delayed_work		update_fw_log_ts_work;
456 };
457 
458 enum {
459 	MLX5_PF_NOTIFY_DISABLE_VF,
460 	MLX5_PF_NOTIFY_ENABLE_VF,
461 };
462 
463 struct mlx5_vf_context {
464 	int	enabled;
465 	u64	port_guid;
466 	u64	node_guid;
467 	/* Valid bits are used to validate administrative guid only.
468 	 * Enabled after ndo_set_vf_guid
469 	 */
470 	u8	port_guid_valid:1;
471 	u8	node_guid_valid:1;
472 	enum port_state_policy	policy;
473 	struct blocking_notifier_head notifier;
474 };
475 
476 struct mlx5_core_sriov {
477 	struct mlx5_vf_context	*vfs_ctx;
478 	int			num_vfs;
479 	u16			max_vfs;
480 	u16			max_ec_vfs;
481 };
482 
483 struct mlx5_events;
484 struct mlx5_mpfs;
485 struct mlx5_eswitch;
486 struct mlx5_lag;
487 struct mlx5_devcom_dev;
488 struct mlx5_fw_reset;
489 struct mlx5_eq_table;
490 struct mlx5_irq_table;
491 struct mlx5_vhca_state_notifier;
492 struct mlx5_sf_dev_table;
493 struct mlx5_sf_hw_table;
494 struct mlx5_sf_table;
495 struct mlx5_crypto_dek_priv;
496 
497 struct mlx5_rate_limit {
498 	u32			rate;
499 	u32			max_burst_sz;
500 	u16			typical_pkt_sz;
501 };
502 
503 struct mlx5_rl_entry {
504 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
505 	u64 refcount;
506 	u16 index;
507 	u16 uid;
508 	u8 dedicated : 1;
509 };
510 
511 struct mlx5_rl_table {
512 	/* protect rate limit table */
513 	struct mutex            rl_lock;
514 	u16                     max_size;
515 	u32                     max_rate;
516 	u32                     min_rate;
517 	struct mlx5_rl_entry   *rl_entry;
518 	u64 refcount;
519 };
520 
521 struct mlx5_core_roce {
522 	struct mlx5_flow_table *ft;
523 	struct mlx5_flow_group *fg;
524 	struct mlx5_flow_handle *allow_rule;
525 };
526 
527 enum {
528 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
529 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
530 	/* Set during device detach to block any further devices
531 	 * creation/deletion on drivers rescan. Unset during device attach.
532 	 */
533 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
534 	MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
535 };
536 
537 struct mlx5_adev {
538 	struct auxiliary_device adev;
539 	struct mlx5_core_dev *mdev;
540 	int idx;
541 };
542 
543 struct mlx5_debugfs_entries {
544 	struct dentry *dbg_root;
545 	struct dentry *qp_debugfs;
546 	struct dentry *eq_debugfs;
547 	struct dentry *cq_debugfs;
548 	struct dentry *cmdif_debugfs;
549 	struct dentry *pages_debugfs;
550 	struct dentry *lag_debugfs;
551 };
552 
553 enum mlx5_func_type {
554 	MLX5_PF,
555 	MLX5_VF,
556 	MLX5_SF,
557 	MLX5_HOST_PF,
558 	MLX5_EC_VF,
559 	MLX5_FUNC_TYPE_NUM,
560 };
561 
562 struct mlx5_ft_pool;
563 struct mlx5_priv {
564 	/* IRQ table valid only for real pci devices PF or VF */
565 	struct mlx5_irq_table   *irq_table;
566 	struct mlx5_eq_table	*eq_table;
567 
568 	/* pages stuff */
569 	struct mlx5_nb          pg_nb;
570 	struct workqueue_struct *pg_wq;
571 	struct xarray           page_root_xa;
572 	atomic_t		reg_pages;
573 	struct list_head	free_list;
574 	u32			fw_pages;
575 	u32			page_counters[MLX5_FUNC_TYPE_NUM];
576 	u32			fw_pages_alloc_failed;
577 	u32			give_pages_dropped;
578 	u32			reclaim_pages_discard;
579 
580 	struct mlx5_core_health health;
581 	struct list_head	traps;
582 
583 	struct mlx5_debugfs_entries dbg;
584 
585 	/* start: alloc staff */
586 	/* protect buffer allocation according to numa node */
587 	struct mutex            alloc_mutex;
588 	int                     numa_node;
589 
590 	struct mutex            pgdir_mutex;
591 	struct list_head        pgdir_list;
592 	/* end: alloc staff */
593 
594 	struct mlx5_adev       **adev;
595 	int			adev_idx;
596 	int			sw_vhca_id;
597 	struct mlx5_events      *events;
598 	struct mlx5_vhca_events *vhca_events;
599 
600 	struct mlx5_flow_steering *steering;
601 	struct mlx5_mpfs        *mpfs;
602 	struct mlx5_eswitch     *eswitch;
603 	struct mlx5_core_sriov	sriov;
604 	struct mlx5_lag		*lag;
605 	u32			flags;
606 	struct mlx5_devcom_dev	*devc;
607 	struct mlx5_devcom_comp_dev *hca_devcom_comp;
608 	struct mlx5_fw_reset	*fw_reset;
609 	struct mlx5_core_roce	roce;
610 	struct mlx5_fc_stats		*fc_stats;
611 	struct mlx5_rl_table            rl_table;
612 	struct mlx5_ft_pool		*ft_pool;
613 
614 	struct mlx5_bfreg_data		bfregs;
615 	struct mlx5_sq_bfreg bfreg;
616 #ifdef CONFIG_MLX5_SF
617 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
618 	struct mlx5_sf_dev_table *sf_dev_table;
619 	struct mlx5_core_dev *parent_mdev;
620 #endif
621 #ifdef CONFIG_MLX5_SF_MANAGER
622 	struct mlx5_sf_hw_table *sf_hw_table;
623 	struct mlx5_sf_table *sf_table;
624 #endif
625 	struct blocking_notifier_head lag_nh;
626 };
627 
628 enum mlx5_device_state {
629 	MLX5_DEVICE_STATE_UP = 1,
630 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
631 };
632 
633 enum mlx5_interface_state {
634 	MLX5_INTERFACE_STATE_UP = BIT(0),
635 	MLX5_BREAK_FW_WAIT = BIT(1),
636 };
637 
638 enum mlx5_pci_status {
639 	MLX5_PCI_STATUS_DISABLED,
640 	MLX5_PCI_STATUS_ENABLED,
641 };
642 
643 enum mlx5_pagefault_type_flags {
644 	MLX5_PFAULT_REQUESTOR = 1 << 0,
645 	MLX5_PFAULT_WRITE     = 1 << 1,
646 	MLX5_PFAULT_RDMA      = 1 << 2,
647 };
648 
649 struct mlx5_td {
650 	/* protects tirs list changes while tirs refresh */
651 	struct mutex     list_lock;
652 	struct list_head tirs_list;
653 	u32              tdn;
654 };
655 
656 struct mlx5e_resources {
657 	struct mlx5e_hw_objs {
658 		u32                        pdn;
659 		struct mlx5_td             td;
660 		u32			   mkey;
661 		struct mlx5_sq_bfreg      *bfregs;
662 		unsigned int               num_bfregs;
663 #define MLX5_MAX_NUM_TC 8
664 		u32                        tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
665 		bool			   tisn_valid;
666 	} hw_objs;
667 	struct net_device *uplink_netdev;
668 	netdevice_tracker tracker;
669 	struct mutex uplink_netdev_lock;
670 	struct mlx5_crypto_dek_priv *dek_priv;
671 };
672 
673 enum mlx5_sw_icm_type {
674 	MLX5_SW_ICM_TYPE_STEERING,
675 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
676 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
677 	MLX5_SW_ICM_TYPE_SW_ENCAP,
678 };
679 
680 #define MLX5_MAX_RESERVED_GIDS 8
681 
682 struct mlx5_rsvd_gids {
683 	unsigned int start;
684 	unsigned int count;
685 	struct ida ida;
686 };
687 
688 struct mlx5_clock;
689 struct mlx5_clock_dev_state;
690 struct mlx5_dm;
691 struct mlx5_fw_tracer;
692 struct mlx5_vxlan;
693 struct mlx5_geneve;
694 struct mlx5_hv_vhca;
695 struct mlx5_st;
696 
697 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
698 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
699 
700 enum {
701 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
702 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
703 };
704 
705 enum {
706 	MKEY_CACHE_LAST_STD_ENTRY = 20,
707 	MLX5_IMR_KSM_CACHE_ENTRY,
708 	MAX_MKEY_CACHE_ENTRIES
709 };
710 
711 struct mlx5_profile {
712 	u64	mask;
713 	u8	log_max_qp;
714 	u8	num_cmd_caches;
715 	struct {
716 		int	size;
717 		int	limit;
718 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
719 };
720 
721 struct mlx5_hca_cap {
722 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
723 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
724 };
725 
726 enum mlx5_wc_state {
727 	MLX5_WC_STATE_UNINITIALIZED,
728 	MLX5_WC_STATE_UNSUPPORTED,
729 	MLX5_WC_STATE_SUPPORTED,
730 };
731 
732 struct mlx5_core_dev {
733 	struct device *device;
734 	enum mlx5_coredev_type coredev_type;
735 	struct pci_dev	       *pdev;
736 	/* sync pci state */
737 	struct mutex		pci_status_mutex;
738 	enum mlx5_pci_status	pci_status;
739 	u8			rev_id;
740 	char			board_id[MLX5_BOARD_ID_LEN];
741 	struct mlx5_cmd		cmd;
742 	struct {
743 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
744 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
745 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
746 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
747 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
748 		u8  embedded_cpu;
749 	} caps;
750 	struct mlx5_timeouts	*timeouts;
751 	u64			sys_image_guid;
752 	phys_addr_t		iseg_base;
753 	struct mlx5_init_seg __iomem *iseg;
754 	phys_addr_t             bar_addr;
755 	enum mlx5_device_state	state;
756 	/* sync interface state */
757 	struct mutex		intf_state_mutex;
758 	struct lock_class_key	lock_key;
759 	unsigned long		intf_state;
760 	struct mlx5_priv	priv;
761 	struct mlx5_profile	profile;
762 	u32			issi;
763 	struct mlx5e_resources  mlx5e_res;
764 	struct mlx5_dm          *dm;
765 	struct mlx5_st          *st;
766 	struct mlx5_vxlan       *vxlan;
767 	struct mlx5_geneve      *geneve;
768 	struct {
769 		struct mlx5_rsvd_gids	reserved_gids;
770 		u32			roce_en;
771 	} roce;
772 #ifdef CONFIG_MLX5_FPGA
773 	struct mlx5_fpga_device *fpga;
774 #endif
775 	struct mlx5_clock       *clock;
776 	struct mlx5_clock_dev_state *clock_state;
777 	struct mlx5_ib_clock_info  *clock_info;
778 	struct mlx5_fw_tracer   *tracer;
779 	struct mlx5_rsc_dump    *rsc_dump;
780 	u32                      vsc_addr;
781 	struct mlx5_hv_vhca	*hv_vhca;
782 	struct mlx5_hwmon	*hwmon;
783 	u64			num_block_tc;
784 	u64			num_block_ipsec;
785 #ifdef CONFIG_MLX5_MACSEC
786 	struct mlx5_macsec_fs *macsec_fs;
787 	/* MACsec notifier chain to sync MACsec core and IB database */
788 	struct blocking_notifier_head macsec_nh;
789 #endif
790 	u64 num_ipsec_offloads;
791 	struct mlx5_sd          *sd;
792 	enum mlx5_wc_state wc_state;
793 	/* sync write combining state */
794 	struct mutex wc_state_lock;
795 };
796 
797 struct mlx5_db {
798 	__be32			*db;
799 	union {
800 		struct mlx5_db_pgdir		*pgdir;
801 		struct mlx5_ib_user_db_page	*user_page;
802 	}			u;
803 	dma_addr_t		dma;
804 	int			index;
805 };
806 
807 #define MLX5_DEFAULT_NUM_DOORBELLS 8
808 
809 enum {
810 	MLX5_COMP_EQ_SIZE = 1024,
811 };
812 
813 enum {
814 	MLX5_PTYS_IB = 1 << 0,
815 	MLX5_PTYS_EN = 1 << 2,
816 };
817 
818 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
819 
820 enum {
821 	MLX5_CMD_ENT_STATE_PENDING_COMP,
822 };
823 
824 struct mlx5_cmd_work_ent {
825 	unsigned long		state;
826 	struct mlx5_cmd_msg    *in;
827 	struct mlx5_cmd_msg    *out;
828 	void		       *uout;
829 	int			uout_size;
830 	mlx5_cmd_cbk_t		callback;
831 	struct delayed_work	cb_timeout_work;
832 	void		       *context;
833 	int			idx;
834 	struct completion	handling;
835 	struct completion	slotted;
836 	struct completion	done;
837 	struct mlx5_cmd        *cmd;
838 	struct work_struct	work;
839 	struct mlx5_cmd_layout *lay;
840 	int			ret;
841 	int			page_queue;
842 	u8			status;
843 	u8			token;
844 	u64			ts1;
845 	u64			ts2;
846 	u16			op;
847 	bool			polling;
848 	/* Track the max comp handlers */
849 	refcount_t              refcnt;
850 };
851 
852 enum phy_port_state {
853 	MLX5_AAA_111
854 };
855 
856 struct mlx5_hca_vport_context {
857 	u32			field_select;
858 	bool			sm_virt_aware;
859 	bool			has_smi;
860 	bool			has_raw;
861 	enum port_state_policy	policy;
862 	enum phy_port_state	phys_state;
863 	enum ib_port_state	vport_state;
864 	u8			port_physical_state;
865 	u64			sys_image_guid;
866 	u64			port_guid;
867 	u64			node_guid;
868 	u32			cap_mask1;
869 	u32			cap_mask1_perm;
870 	u16			cap_mask2;
871 	u16			cap_mask2_perm;
872 	u16			lid;
873 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
874 	u8			lmc;
875 	u8			subnet_timeout;
876 	u16			sm_lid;
877 	u8			sm_sl;
878 	u16			qkey_violation_counter;
879 	u16			pkey_violation_counter;
880 	bool			grh_required;
881 	u8			num_plane;
882 };
883 
884 #define STRUCT_FIELD(header, field) \
885 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
886 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
887 
888 extern struct dentry *mlx5_debugfs_root;
889 
890 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
891 {
892 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
893 }
894 
895 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
896 {
897 	return ioread32be(&dev->iseg->fw_rev) >> 16;
898 }
899 
900 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
901 {
902 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
903 }
904 
905 static inline u32 mlx5_base_mkey(const u32 key)
906 {
907 	return key & 0xffffff00u;
908 }
909 
910 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
911 {
912 	return ((u32)1 << log_sz) << log_stride;
913 }
914 
915 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
916 					u8 log_stride, u8 log_sz,
917 					u16 strides_offset,
918 					struct mlx5_frag_buf_ctrl *fbc)
919 {
920 	fbc->frags      = frags;
921 	fbc->log_stride = log_stride;
922 	fbc->log_sz     = log_sz;
923 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
924 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
925 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
926 	fbc->strides_offset = strides_offset;
927 }
928 
929 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
930 				 u8 log_stride, u8 log_sz,
931 				 struct mlx5_frag_buf_ctrl *fbc)
932 {
933 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
934 }
935 
936 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
937 					  u32 ix)
938 {
939 	unsigned int frag;
940 
941 	ix  += fbc->strides_offset;
942 	frag = ix >> fbc->log_frag_strides;
943 
944 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
945 }
946 
947 static inline u32
948 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
949 {
950 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
951 
952 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
953 }
954 
955 enum {
956 	CMD_ALLOWED_OPCODE_ALL,
957 };
958 
959 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
960 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
961 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
962 
963 struct mlx5_async_ctx {
964 	struct mlx5_core_dev *dev;
965 	atomic_t num_inflight;
966 	struct completion inflight_done;
967 };
968 
969 struct mlx5_async_work;
970 
971 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
972 
973 struct mlx5_async_work {
974 	struct mlx5_async_ctx *ctx;
975 	mlx5_async_cbk_t user_callback;
976 	u16 opcode; /* cmd opcode */
977 	u16 op_mod; /* cmd op_mod */
978 	u8 throttle_locked:1;
979 	u8 unpriv_locked:1;
980 	void *out; /* pointer to the cmd output buffer */
981 };
982 
983 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
984 			     struct mlx5_async_ctx *ctx);
985 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
986 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
987 		     void *out, int out_size, mlx5_async_cbk_t callback,
988 		     struct mlx5_async_work *work);
989 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
990 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
991 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
992 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
993 		  int out_size);
994 
995 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
996 	({                                                                     \
997 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
998 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
999 	})
1000 
1001 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1002 	({                                                                     \
1003 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1004 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1005 	})
1006 
1007 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1008 			  void *out, int out_size);
1009 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1010 int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1011 void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1012 
1013 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1014 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1015 
1016 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1017 
1018 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1019 int mlx5_health_init(struct mlx5_core_dev *dev);
1020 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1021 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1022 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1023 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1024 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1025 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1026 			     struct mlx5_frag_buf *buf, int node);
1027 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1028 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1029 			  int inlen);
1030 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1031 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1032 			 int outlen);
1033 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1034 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1035 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1036 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1037 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1038 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1039 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1040 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1041 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1042 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1043 void mlx5_register_debugfs(void);
1044 void mlx5_unregister_debugfs(void);
1045 
1046 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1047 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1048 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1049 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1050 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1051 
1052 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1053 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1054 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1055 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1056 		    void *data_out, int size_out, u16 reg_id, int arg,
1057 		    int write, bool verbose);
1058 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1059 			 int size_in, void *data_out, int size_out,
1060 			 u16 reg_num, int arg, int write);
1061 
1062 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1063 		       int node);
1064 
1065 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1066 {
1067 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1068 }
1069 
1070 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1071 
1072 const char *mlx5_command_str(int command);
1073 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1074 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1075 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1076 			 int npsvs, u32 *sig_index);
1077 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1078 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1079 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1080 
1081 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1082 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1083 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1084 		     struct mlx5_rate_limit *rl);
1085 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1086 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1087 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1088 			 bool dedicated_entry, u16 *index);
1089 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1090 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1091 		       struct mlx5_rate_limit *rl_1);
1092 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1093 		     bool map_wc, bool fast_path);
1094 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1095 
1096 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1097 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1098 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1099 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1100 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1101 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1102 
1103 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1104 {
1105 	return mkey >> 8;
1106 }
1107 
1108 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1109 {
1110 	return mkey_idx << 8;
1111 }
1112 
1113 static inline u8 mlx5_mkey_variant(u32 mkey)
1114 {
1115 	return mkey & 0xff;
1116 }
1117 
1118 /* Async-atomic event notifier used by mlx5 core to forward FW
1119  * evetns received from event queue to mlx5 consumers.
1120  * Optimise event queue dipatching.
1121  */
1122 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1123 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1124 
1125 /* Async-atomic event notifier used for forwarding
1126  * evetns from the event queue into the to mlx5 events dispatcher,
1127  * eswitch, clock and others.
1128  */
1129 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1130 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1131 
1132 /* Blocking event notifier used to forward SW events, used for slow path */
1133 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1134 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1135 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1136 				      void *data);
1137 
1138 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1139 
1140 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1141 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1142 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1143 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1144 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1145 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1146 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1147 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1148 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1149 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1150 			   struct net_device *slave);
1151 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1152 				 u64 *values,
1153 				 int num_counters,
1154 				 size_t *offsets);
1155 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1156 
1157 #define mlx5_lag_for_each_peer_mdev(dev, peer, i)				\
1158 	for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i);		\
1159 	     peer;								\
1160 	     peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1161 
1162 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1163 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1164 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1165 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1166 			 u64 length, u32 log_alignment, u16 uid,
1167 			 phys_addr_t *addr, u32 *obj_id);
1168 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1169 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1170 
1171 #ifdef CONFIG_PCIE_TPH
1172 int mlx5_st_alloc_index(struct mlx5_core_dev *dev, enum tph_mem_type mem_type,
1173 			unsigned int cpu_uid, u16 *st_index);
1174 int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index);
1175 #else
1176 static inline int mlx5_st_alloc_index(struct mlx5_core_dev *dev,
1177 				      enum tph_mem_type mem_type,
1178 				      unsigned int cpu_uid, u16 *st_index)
1179 {
1180 	return -EOPNOTSUPP;
1181 }
1182 static inline int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index)
1183 {
1184 	return -EOPNOTSUPP;
1185 }
1186 #endif
1187 
1188 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1189 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1190 
1191 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1192 					  int vf_id,
1193 					  struct notifier_block *nb);
1194 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1195 					     int vf_id,
1196 					     struct notifier_block *nb);
1197 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1198 			    struct ib_device *device,
1199 			    struct rdma_netdev_alloc_params *params);
1200 
1201 enum {
1202 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1203 };
1204 
1205 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1206 {
1207 	return dev->coredev_type == MLX5_COREDEV_PF;
1208 }
1209 
1210 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1211 {
1212 	return dev->coredev_type == MLX5_COREDEV_VF;
1213 }
1214 
1215 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1216 					       const struct mlx5_core_dev *dev2)
1217 {
1218 	return dev1->coredev_type == dev2->coredev_type;
1219 }
1220 
1221 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1222 {
1223 	return dev->caps.embedded_cpu;
1224 }
1225 
1226 static inline bool
1227 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1228 {
1229 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1230 }
1231 
1232 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1233 {
1234 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1235 }
1236 
1237 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1238 {
1239 	return dev->priv.sriov.max_vfs;
1240 }
1241 
1242 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1243 {
1244 	/* LACP owner conditions:
1245 	 * 1) Function is physical.
1246 	 * 2) LAG is supported by FW.
1247 	 * 3) LAG is managed by driver (currently the only option).
1248 	 */
1249 	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
1250 		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1251 		    MLX5_CAP_GEN(dev, lag_master);
1252 }
1253 
1254 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1255 {
1256 	return dev->priv.sriov.max_ec_vfs;
1257 }
1258 
1259 static inline int mlx5_get_gid_table_len(u16 param)
1260 {
1261 	if (param > 4) {
1262 		pr_warn("gid table length is zero\n");
1263 		return 0;
1264 	}
1265 
1266 	return 8 * (1 << param);
1267 }
1268 
1269 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1270 {
1271 	return !!(dev->priv.rl_table.max_size);
1272 }
1273 
1274 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1275 {
1276 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1277 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1278 }
1279 
1280 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1281 {
1282 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1283 }
1284 
1285 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1286 {
1287 	return mlx5_core_is_mp_slave(dev) ||
1288 	       mlx5_core_is_mp_master(dev);
1289 }
1290 
1291 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1292 {
1293 	if (!mlx5_core_mp_enabled(dev))
1294 		return 1;
1295 
1296 	return MLX5_CAP_GEN(dev, native_port_num);
1297 }
1298 
1299 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1300 {
1301 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1302 
1303 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1304 		return idx - 1;
1305 	else
1306 		return PCI_FUNC(dev->pdev->devfn);
1307 }
1308 
1309 enum {
1310 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1311 };
1312 
1313 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1314 
1315 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1316 {
1317 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1318 		return MLX5_CAP_GEN(dev, roce);
1319 
1320 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1321 	 * in order to support RoCE enable/disable feature
1322 	 */
1323 	return mlx5_is_roce_on(dev);
1324 }
1325 
1326 #ifdef CONFIG_MLX5_MACSEC
1327 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1328 {
1329 	if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1330 	    MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1331 		return false;
1332 
1333 	if (!MLX5_CAP_GEN(mdev, log_max_dek))
1334 		return false;
1335 
1336 	if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1337 		return false;
1338 
1339 	if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1340 	    !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1341 		return false;
1342 
1343 	if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1344 	    !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1345 		return false;
1346 
1347 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1348 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1349 		return false;
1350 
1351 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1352 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1353 		return false;
1354 
1355 	return true;
1356 }
1357 
1358 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1359 
1360 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1361 {
1362 	if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1363 	     NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1364 	     !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1365 	     !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1366 		return false;
1367 
1368 	return true;
1369 }
1370 #endif
1371 
1372 enum {
1373 	MLX5_OCTWORD = 16,
1374 };
1375 
1376 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1377 
1378 static inline struct net *mlx5_core_net(struct mlx5_core_dev *dev)
1379 {
1380 	return devlink_net(priv_to_devlink(dev));
1381 }
1382 #endif /* MLX5_DRIVER_H */
1383