1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/etherdevice.h> 36 #include <net/ip.h> 37 #include <linux/slab.h> 38 #include <linux/netdevice.h> 39 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_pack.h> 42 #include <rdma/ib_addr.h> 43 #include <rdma/ib_mad.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include <linux/mlx4/driver.h> 47 #include <linux/mlx4/qp.h> 48 49 #include "mlx4_ib.h" 50 #include <rdma/mlx4-abi.h> 51 52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 53 struct mlx4_ib_cq *recv_cq); 54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 55 struct mlx4_ib_cq *recv_cq); 56 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 57 struct ib_udata *udata); 58 59 enum { 60 MLX4_IB_ACK_REQ_FREQ = 8, 61 }; 62 63 enum { 64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 66 MLX4_IB_LINK_TYPE_IB = 0, 67 MLX4_IB_LINK_TYPE_ETH = 1 68 }; 69 70 enum { 71 MLX4_IB_MIN_SQ_STRIDE = 6, 72 MLX4_IB_CACHE_LINE_SIZE = 64, 73 }; 74 75 enum { 76 MLX4_RAW_QP_MTU = 7, 77 MLX4_RAW_QP_MSGMAX = 31, 78 }; 79 80 #ifndef ETH_ALEN 81 #define ETH_ALEN 6 82 #endif 83 84 static const __be32 mlx4_ib_opcode[] = { 85 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 86 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 87 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 88 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 89 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 90 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 91 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 92 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 93 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 94 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 95 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 96 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 97 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 98 }; 99 100 enum mlx4_ib_source_type { 101 MLX4_IB_QP_SRC = 0, 102 MLX4_IB_RWQ_SRC = 1, 103 }; 104 105 struct mlx4_ib_qp_event_work { 106 struct work_struct work; 107 struct mlx4_qp *qp; 108 enum mlx4_event type; 109 }; 110 111 static struct workqueue_struct *mlx4_ib_qp_event_wq; 112 113 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 114 { 115 if (!mlx4_is_master(dev->dev)) 116 return 0; 117 118 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 119 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 120 8 * MLX4_MFUNC_MAX; 121 } 122 123 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 124 { 125 int proxy_sqp = 0; 126 int real_sqp = 0; 127 int i; 128 /* PPF or Native -- real SQP */ 129 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 130 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 131 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 132 if (real_sqp) 133 return 1; 134 /* VF or PF -- proxy SQP */ 135 if (mlx4_is_mfunc(dev->dev)) { 136 for (i = 0; i < dev->dev->caps.num_ports; i++) { 137 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy || 138 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) { 139 proxy_sqp = 1; 140 break; 141 } 142 } 143 } 144 if (proxy_sqp) 145 return 1; 146 147 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 148 } 149 150 /* used for INIT/CLOSE port logic */ 151 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 152 { 153 int proxy_qp0 = 0; 154 int real_qp0 = 0; 155 int i; 156 /* PPF or Native -- real QP0 */ 157 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 158 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 159 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 160 if (real_qp0) 161 return 1; 162 /* VF or PF -- proxy QP0 */ 163 if (mlx4_is_mfunc(dev->dev)) { 164 for (i = 0; i < dev->dev->caps.num_ports; i++) { 165 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) { 166 proxy_qp0 = 1; 167 break; 168 } 169 } 170 } 171 return proxy_qp0; 172 } 173 174 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 175 { 176 return mlx4_buf_offset(&qp->buf, offset); 177 } 178 179 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 180 { 181 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 182 } 183 184 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 185 { 186 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 187 } 188 189 /* 190 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 191 * first four bytes of every 64 byte chunk with 0xffffffff, except for 192 * the very first chunk of the WQE. 193 */ 194 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n) 195 { 196 __be32 *wqe; 197 int i; 198 int s; 199 void *buf; 200 struct mlx4_wqe_ctrl_seg *ctrl; 201 202 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 203 ctrl = (struct mlx4_wqe_ctrl_seg *)buf; 204 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4; 205 for (i = 64; i < s; i += 64) { 206 wqe = buf + i; 207 *wqe = cpu_to_be32(0xffffffff); 208 } 209 } 210 211 static void mlx4_ib_handle_qp_event(struct work_struct *_work) 212 { 213 struct mlx4_ib_qp_event_work *qpe_work = 214 container_of(_work, struct mlx4_ib_qp_event_work, work); 215 struct ib_qp *ibqp = &to_mibqp(qpe_work->qp)->ibqp; 216 struct ib_event event = {}; 217 218 event.device = ibqp->device; 219 event.element.qp = ibqp; 220 221 switch (qpe_work->type) { 222 case MLX4_EVENT_TYPE_PATH_MIG: 223 event.event = IB_EVENT_PATH_MIG; 224 break; 225 case MLX4_EVENT_TYPE_COMM_EST: 226 event.event = IB_EVENT_COMM_EST; 227 break; 228 case MLX4_EVENT_TYPE_SQ_DRAINED: 229 event.event = IB_EVENT_SQ_DRAINED; 230 break; 231 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 232 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 233 break; 234 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 235 event.event = IB_EVENT_QP_FATAL; 236 break; 237 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 238 event.event = IB_EVENT_PATH_MIG_ERR; 239 break; 240 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 241 event.event = IB_EVENT_QP_REQ_ERR; 242 break; 243 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 244 event.event = IB_EVENT_QP_ACCESS_ERR; 245 break; 246 default: 247 pr_warn("Unexpected event type %d on QP %06x\n", 248 qpe_work->type, qpe_work->qp->qpn); 249 goto out; 250 } 251 252 ibqp->event_handler(&event, ibqp->qp_context); 253 254 out: 255 mlx4_put_qp(qpe_work->qp); 256 kfree(qpe_work); 257 } 258 259 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 260 { 261 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 262 struct mlx4_ib_qp_event_work *qpe_work; 263 264 if (type == MLX4_EVENT_TYPE_PATH_MIG) 265 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 266 267 if (!ibqp->event_handler) 268 goto out_no_handler; 269 270 qpe_work = kzalloc_obj(*qpe_work, GFP_ATOMIC); 271 if (!qpe_work) 272 goto out_no_handler; 273 274 qpe_work->qp = qp; 275 qpe_work->type = type; 276 INIT_WORK(&qpe_work->work, mlx4_ib_handle_qp_event); 277 queue_work(mlx4_ib_qp_event_wq, &qpe_work->work); 278 return; 279 280 out_no_handler: 281 mlx4_put_qp(qp); 282 } 283 284 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type) 285 { 286 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n", 287 type, qp->qpn); 288 } 289 290 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 291 { 292 /* 293 * UD WQEs must have a datagram segment. 294 * RC and UC WQEs might have a remote address segment. 295 * MLX WQEs need two extra inline data segments (for the UD 296 * header and space for the ICRC). 297 */ 298 switch (type) { 299 case MLX4_IB_QPT_UD: 300 return sizeof (struct mlx4_wqe_ctrl_seg) + 301 sizeof (struct mlx4_wqe_datagram_seg) + 302 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 303 case MLX4_IB_QPT_PROXY_SMI_OWNER: 304 case MLX4_IB_QPT_PROXY_SMI: 305 case MLX4_IB_QPT_PROXY_GSI: 306 return sizeof (struct mlx4_wqe_ctrl_seg) + 307 sizeof (struct mlx4_wqe_datagram_seg) + 64; 308 case MLX4_IB_QPT_TUN_SMI_OWNER: 309 case MLX4_IB_QPT_TUN_GSI: 310 return sizeof (struct mlx4_wqe_ctrl_seg) + 311 sizeof (struct mlx4_wqe_datagram_seg); 312 313 case MLX4_IB_QPT_UC: 314 return sizeof (struct mlx4_wqe_ctrl_seg) + 315 sizeof (struct mlx4_wqe_raddr_seg); 316 case MLX4_IB_QPT_RC: 317 return sizeof (struct mlx4_wqe_ctrl_seg) + 318 sizeof (struct mlx4_wqe_masked_atomic_seg) + 319 sizeof (struct mlx4_wqe_raddr_seg); 320 case MLX4_IB_QPT_SMI: 321 case MLX4_IB_QPT_GSI: 322 return sizeof (struct mlx4_wqe_ctrl_seg) + 323 ALIGN(MLX4_IB_UD_HEADER_SIZE + 324 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 325 MLX4_INLINE_ALIGN) * 326 sizeof (struct mlx4_wqe_inline_seg), 327 sizeof (struct mlx4_wqe_data_seg)) + 328 ALIGN(4 + 329 sizeof (struct mlx4_wqe_inline_seg), 330 sizeof (struct mlx4_wqe_data_seg)); 331 default: 332 return sizeof (struct mlx4_wqe_ctrl_seg); 333 } 334 } 335 336 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 337 bool is_user, bool has_rq, struct mlx4_ib_qp *qp, 338 u32 inl_recv_sz) 339 { 340 /* Sanity check RQ size before proceeding */ 341 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 342 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 343 return -EINVAL; 344 345 if (!has_rq) { 346 if (cap->max_recv_wr || inl_recv_sz) 347 return -EINVAL; 348 349 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 350 } else { 351 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg * 352 sizeof(struct mlx4_wqe_data_seg); 353 u32 wqe_size; 354 355 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 356 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge || 357 inl_recv_sz > max_inl_recv_sz)) 358 return -EINVAL; 359 360 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 361 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 362 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg); 363 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz)); 364 } 365 366 /* leave userspace return values as they were, so as not to break ABI */ 367 if (is_user) { 368 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 369 cap->max_recv_sge = qp->rq.max_gs; 370 } else { 371 cap->max_recv_wr = qp->rq.max_post = 372 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 373 cap->max_recv_sge = min(qp->rq.max_gs, 374 min(dev->dev->caps.max_sq_sg, 375 dev->dev->caps.max_rq_sg)); 376 } 377 378 return 0; 379 } 380 381 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 382 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp) 383 { 384 int s; 385 386 /* Sanity check SQ size before proceeding */ 387 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 388 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 389 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 390 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 391 return -EINVAL; 392 393 /* 394 * For MLX transport we need 2 extra S/G entries: 395 * one for the header and one for the checksum at the end 396 */ 397 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 398 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 399 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 400 return -EINVAL; 401 402 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 403 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 404 send_wqe_overhead(type, qp->flags); 405 406 if (s > dev->dev->caps.max_sq_desc_sz) 407 return -EINVAL; 408 409 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); 410 411 /* 412 * We need to leave 2 KB + 1 WR of headroom in the SQ to 413 * allow HW to prefetch. 414 */ 415 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift); 416 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + 417 qp->sq_spare_wqes); 418 419 qp->sq.max_gs = 420 (min(dev->dev->caps.max_sq_desc_sz, 421 (1 << qp->sq.wqe_shift)) - 422 send_wqe_overhead(type, qp->flags)) / 423 sizeof (struct mlx4_wqe_data_seg); 424 425 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 426 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 427 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 428 qp->rq.offset = 0; 429 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 430 } else { 431 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 432 qp->sq.offset = 0; 433 } 434 435 cap->max_send_wr = qp->sq.max_post = 436 qp->sq.wqe_cnt - qp->sq_spare_wqes; 437 cap->max_send_sge = min(qp->sq.max_gs, 438 min(dev->dev->caps.max_sq_sg, 439 dev->dev->caps.max_rq_sg)); 440 /* We don't support inline sends for kernel QPs (yet) */ 441 cap->max_inline_data = 0; 442 443 return 0; 444 } 445 446 static int set_user_sq_size(struct mlx4_ib_dev *dev, 447 struct mlx4_ib_qp *qp, 448 struct mlx4_ib_create_qp *ucmd) 449 { 450 u32 cnt; 451 452 /* Sanity check SQ size before proceeding */ 453 if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) || 454 cnt > dev->dev->caps.max_wqes) 455 return -EINVAL; 456 if (ucmd->log_sq_stride > 457 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || 458 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 459 return -EINVAL; 460 461 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 462 qp->sq.wqe_shift = ucmd->log_sq_stride; 463 464 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 465 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 466 467 return 0; 468 } 469 470 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 471 { 472 int i; 473 474 qp->sqp_proxy_rcv = 475 kmalloc_objs(struct mlx4_ib_buf, qp->rq.wqe_cnt); 476 if (!qp->sqp_proxy_rcv) 477 return -ENOMEM; 478 for (i = 0; i < qp->rq.wqe_cnt; i++) { 479 qp->sqp_proxy_rcv[i].addr = 480 kmalloc_obj(struct mlx4_ib_proxy_sqp_hdr); 481 if (!qp->sqp_proxy_rcv[i].addr) 482 goto err; 483 qp->sqp_proxy_rcv[i].map = 484 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 485 sizeof (struct mlx4_ib_proxy_sqp_hdr), 486 DMA_FROM_DEVICE); 487 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 488 kfree(qp->sqp_proxy_rcv[i].addr); 489 goto err; 490 } 491 } 492 return 0; 493 494 err: 495 while (i > 0) { 496 --i; 497 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 498 sizeof (struct mlx4_ib_proxy_sqp_hdr), 499 DMA_FROM_DEVICE); 500 kfree(qp->sqp_proxy_rcv[i].addr); 501 } 502 kfree(qp->sqp_proxy_rcv); 503 qp->sqp_proxy_rcv = NULL; 504 return -ENOMEM; 505 } 506 507 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 508 { 509 int i; 510 511 for (i = 0; i < qp->rq.wqe_cnt; i++) { 512 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 513 sizeof (struct mlx4_ib_proxy_sqp_hdr), 514 DMA_FROM_DEVICE); 515 kfree(qp->sqp_proxy_rcv[i].addr); 516 } 517 kfree(qp->sqp_proxy_rcv); 518 } 519 520 static bool qp_has_rq(struct ib_qp_init_attr *attr) 521 { 522 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 523 return false; 524 525 return !attr->srq; 526 } 527 528 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 529 { 530 int i; 531 for (i = 0; i < dev->caps.num_ports; i++) { 532 if (qpn == dev->caps.spec_qps[i].qp0_proxy) 533 return !!dev->caps.spec_qps[i].qp0_qkey; 534 } 535 return 0; 536 } 537 538 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 539 struct mlx4_ib_qp *qp) 540 { 541 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 542 mlx4_counter_free(dev->dev, qp->counter_index->index); 543 list_del(&qp->counter_index->list); 544 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 545 546 kfree(qp->counter_index); 547 qp->counter_index = NULL; 548 } 549 550 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, 551 struct ib_qp_init_attr *init_attr, 552 struct mlx4_ib_create_qp_rss *ucmd) 553 { 554 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num | 555 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24); 556 557 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) && 558 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) { 559 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key, 560 MLX4_EN_RSS_KEY_SIZE); 561 } else { 562 pr_debug("RX Hash function is not supported\n"); 563 return (-EOPNOTSUPP); 564 } 565 566 if (ucmd->rx_hash_fields_mask & ~(u64)(MLX4_IB_RX_HASH_SRC_IPV4 | 567 MLX4_IB_RX_HASH_DST_IPV4 | 568 MLX4_IB_RX_HASH_SRC_IPV6 | 569 MLX4_IB_RX_HASH_DST_IPV6 | 570 MLX4_IB_RX_HASH_SRC_PORT_TCP | 571 MLX4_IB_RX_HASH_DST_PORT_TCP | 572 MLX4_IB_RX_HASH_SRC_PORT_UDP | 573 MLX4_IB_RX_HASH_DST_PORT_UDP | 574 MLX4_IB_RX_HASH_INNER)) { 575 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", 576 ucmd->rx_hash_fields_mask); 577 return (-EOPNOTSUPP); 578 } 579 580 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) && 581 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 582 rss_ctx->flags = MLX4_RSS_IPV4; 583 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) || 584 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) { 585 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n"); 586 return (-EOPNOTSUPP); 587 } 588 589 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) && 590 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 591 rss_ctx->flags |= MLX4_RSS_IPV6; 592 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) || 593 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) { 594 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n"); 595 return (-EOPNOTSUPP); 596 } 597 598 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) && 599 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 600 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) { 601 pr_debug("RX Hash fields_mask for UDP is not supported\n"); 602 return (-EOPNOTSUPP); 603 } 604 605 if (rss_ctx->flags & MLX4_RSS_IPV4) 606 rss_ctx->flags |= MLX4_RSS_UDP_IPV4; 607 if (rss_ctx->flags & MLX4_RSS_IPV6) 608 rss_ctx->flags |= MLX4_RSS_UDP_IPV6; 609 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 610 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n"); 611 return (-EOPNOTSUPP); 612 } 613 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) || 614 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) { 615 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n"); 616 return (-EOPNOTSUPP); 617 } 618 619 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) && 620 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 621 if (rss_ctx->flags & MLX4_RSS_IPV4) 622 rss_ctx->flags |= MLX4_RSS_TCP_IPV4; 623 if (rss_ctx->flags & MLX4_RSS_IPV6) 624 rss_ctx->flags |= MLX4_RSS_TCP_IPV6; 625 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) { 626 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n"); 627 return (-EOPNOTSUPP); 628 } 629 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) || 630 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) { 631 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n"); 632 return (-EOPNOTSUPP); 633 } 634 635 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) { 636 if (dev->dev->caps.tunnel_offload_mode == 637 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 638 /* 639 * Hash according to inner headers if exist, otherwise 640 * according to outer headers. 641 */ 642 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY; 643 } else { 644 pr_debug("RSS Hash for inner headers isn't supported\n"); 645 return (-EOPNOTSUPP); 646 } 647 } 648 649 return 0; 650 } 651 652 static int create_qp_rss(struct mlx4_ib_dev *dev, 653 struct ib_qp_init_attr *init_attr, 654 struct mlx4_ib_create_qp_rss *ucmd, 655 struct mlx4_ib_qp *qp) 656 { 657 int qpn; 658 int err; 659 660 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 661 662 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage); 663 if (err) 664 return err; 665 666 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 667 if (err) 668 goto err_qpn; 669 670 INIT_LIST_HEAD(&qp->gid_list); 671 INIT_LIST_HEAD(&qp->steering_rules); 672 673 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 674 qp->state = IB_QPS_RESET; 675 676 /* Set dummy send resources to be compatible with HV and PRM */ 677 qp->sq_no_prefetch = 1; 678 qp->sq.wqe_cnt = 1; 679 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 680 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE; 681 qp->mtt = (to_mqp( 682 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt; 683 684 qp->rss_ctx = kzalloc_obj(*qp->rss_ctx); 685 if (!qp->rss_ctx) { 686 err = -ENOMEM; 687 goto err_qp_alloc; 688 } 689 690 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd); 691 if (err) 692 goto err; 693 694 return 0; 695 696 err: 697 kfree(qp->rss_ctx); 698 699 err_qp_alloc: 700 mlx4_qp_remove(dev->dev, &qp->mqp); 701 mlx4_qp_free(dev->dev, &qp->mqp); 702 703 err_qpn: 704 mlx4_qp_release_range(dev->dev, qpn, 1); 705 return err; 706 } 707 708 static int _mlx4_ib_create_qp_rss(struct ib_pd *pd, struct mlx4_ib_qp *qp, 709 struct ib_qp_init_attr *init_attr, 710 struct ib_udata *udata) 711 { 712 struct mlx4_ib_create_qp_rss ucmd; 713 int err; 714 715 if (!udata) { 716 pr_debug("RSS QP with NULL udata\n"); 717 return -EINVAL; 718 } 719 720 if (udata->outlen) 721 return -EOPNOTSUPP; 722 723 err = ib_copy_validate_udata_in_cm(udata, ucmd, reserved1, 0); 724 if (err) { 725 pr_debug("copy failed\n"); 726 return err; 727 } 728 729 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved))) 730 return -EOPNOTSUPP; 731 732 if (ucmd.reserved1) 733 return -EOPNOTSUPP; 734 735 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 736 pr_debug("RSS QP with unsupported QP type %d\n", 737 init_attr->qp_type); 738 return -EOPNOTSUPP; 739 } 740 741 if (init_attr->create_flags) { 742 pr_debug("RSS QP doesn't support create flags\n"); 743 return -EOPNOTSUPP; 744 } 745 746 if (init_attr->send_cq || init_attr->cap.max_send_wr) { 747 pr_debug("RSS QP with unsupported send attributes\n"); 748 return -EOPNOTSUPP; 749 } 750 751 qp->pri.vid = 0xFFFF; 752 qp->alt.vid = 0xFFFF; 753 754 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp); 755 if (err) 756 return err; 757 758 qp->ibqp.qp_num = qp->mqp.qpn; 759 return 0; 760 } 761 762 /* 763 * This function allocates a WQN from a range which is consecutive and aligned 764 * to its size. In case the range is full, then it creates a new range and 765 * allocates WQN from it. The new range will be used for following allocations. 766 */ 767 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context, 768 struct mlx4_ib_qp *qp, int range_size, int *wqn) 769 { 770 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 771 struct mlx4_wqn_range *range; 772 int err = 0; 773 774 mutex_lock(&context->wqn_ranges_mutex); 775 776 range = list_first_entry_or_null(&context->wqn_ranges_list, 777 struct mlx4_wqn_range, list); 778 779 if (!range || (range->refcount == range->size) || range->dirty) { 780 range = kzalloc_obj(*range); 781 if (!range) { 782 err = -ENOMEM; 783 goto out; 784 } 785 786 err = mlx4_qp_reserve_range(dev->dev, range_size, 787 range_size, &range->base_wqn, 0, 788 qp->mqp.usage); 789 if (err) { 790 kfree(range); 791 goto out; 792 } 793 794 range->size = range_size; 795 list_add(&range->list, &context->wqn_ranges_list); 796 } else if (range_size != 1) { 797 /* 798 * Requesting a new range (>1) when last range is still open, is 799 * not valid. 800 */ 801 err = -EINVAL; 802 goto out; 803 } 804 805 qp->wqn_range = range; 806 807 *wqn = range->base_wqn + range->refcount; 808 809 range->refcount++; 810 811 out: 812 mutex_unlock(&context->wqn_ranges_mutex); 813 814 return err; 815 } 816 817 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context, 818 struct mlx4_ib_qp *qp, bool dirty_release) 819 { 820 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device); 821 struct mlx4_wqn_range *range; 822 823 mutex_lock(&context->wqn_ranges_mutex); 824 825 range = qp->wqn_range; 826 827 range->refcount--; 828 if (!range->refcount) { 829 mlx4_qp_release_range(dev->dev, range->base_wqn, 830 range->size); 831 list_del(&range->list); 832 kfree(range); 833 } else if (dirty_release) { 834 /* 835 * A range which one of its WQNs is destroyed, won't be able to be 836 * reused for further WQN allocations. 837 * The next created WQ will allocate a new range. 838 */ 839 range->dirty = true; 840 } 841 842 mutex_unlock(&context->wqn_ranges_mutex); 843 } 844 845 static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, 846 struct ib_udata *udata, struct mlx4_ib_qp *qp) 847 { 848 struct mlx4_ib_dev *dev = to_mdev(pd->device); 849 int qpn; 850 int err; 851 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 852 udata, struct mlx4_ib_ucontext, ibucontext); 853 struct mlx4_ib_cq *mcq; 854 unsigned long flags; 855 int range_size; 856 struct mlx4_ib_create_wq wq; 857 int shift; 858 int n; 859 860 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET; 861 862 spin_lock_init(&qp->sq.lock); 863 spin_lock_init(&qp->rq.lock); 864 INIT_LIST_HEAD(&qp->gid_list); 865 INIT_LIST_HEAD(&qp->steering_rules); 866 867 qp->state = IB_QPS_RESET; 868 869 err = ib_copy_validate_udata_in_cm(udata, wq, comp_mask, 0); 870 if (err) 871 goto err; 872 873 if (wq.reserved[0] || wq.reserved[1] || wq.reserved[2]) { 874 pr_debug("user command isn't supported\n"); 875 err = -EOPNOTSUPP; 876 goto err; 877 } 878 879 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) { 880 pr_debug("WQN range size must be equal or smaller than %d\n", 881 dev->dev->caps.max_rss_tbl_sz); 882 err = -EOPNOTSUPP; 883 goto err; 884 } 885 range_size = 1 << wq.log_range_size; 886 887 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) 888 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 889 890 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz); 891 if (err) 892 goto err; 893 894 qp->sq_no_prefetch = 1; 895 qp->sq.wqe_cnt = 1; 896 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE; 897 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 898 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 899 900 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0); 901 if (IS_ERR(qp->umem)) { 902 err = PTR_ERR(qp->umem); 903 goto err; 904 } 905 906 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 907 if (shift < 0) { 908 err = shift; 909 goto err_buf; 910 } 911 912 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 913 if (err) 914 goto err_buf; 915 916 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 917 if (err) 918 goto err_mtt; 919 920 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db); 921 if (err) 922 goto err_mtt; 923 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 924 925 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn); 926 if (err) 927 goto err_wrid; 928 929 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 930 if (err) 931 goto err_qpn; 932 933 /* 934 * Hardware wants QPN written in big-endian order (after 935 * shifting) for send doorbell. Precompute this value to save 936 * a little bit when posting sends. 937 */ 938 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 939 940 qp->mqp.event = mlx4_ib_wq_event; 941 942 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 943 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 944 to_mcq(init_attr->recv_cq)); 945 /* Maintain device to QPs access, needed for further handling 946 * via reset flow 947 */ 948 list_add_tail(&qp->qps_list, &dev->qp_list); 949 /* Maintain CQ to QPs access, needed for further handling 950 * via reset flow 951 */ 952 mcq = to_mcq(init_attr->send_cq); 953 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 954 mcq = to_mcq(init_attr->recv_cq); 955 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 956 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 957 to_mcq(init_attr->recv_cq)); 958 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 959 return 0; 960 961 err_qpn: 962 mlx4_ib_release_wqn(context, qp, 0); 963 err_wrid: 964 mlx4_ib_db_unmap_user(context, &qp->db); 965 966 err_mtt: 967 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 968 err_buf: 969 ib_umem_release(qp->umem); 970 err: 971 return err; 972 } 973 974 static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr, 975 struct ib_udata *udata, int sqpn, 976 struct mlx4_ib_qp *qp) 977 { 978 struct mlx4_ib_dev *dev = to_mdev(pd->device); 979 int qpn; 980 int err; 981 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 982 udata, struct mlx4_ib_ucontext, ibucontext); 983 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 984 struct mlx4_ib_cq *mcq; 985 unsigned long flags; 986 987 /* When tunneling special qps, we use a plain UD qp */ 988 if (sqpn) { 989 if (mlx4_is_mfunc(dev->dev) && 990 (!mlx4_is_master(dev->dev) || 991 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 992 if (init_attr->qp_type == IB_QPT_GSI) 993 qp_type = MLX4_IB_QPT_PROXY_GSI; 994 else { 995 if (mlx4_is_master(dev->dev) || 996 qp0_enabled_vf(dev->dev, sqpn)) 997 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 998 else 999 qp_type = MLX4_IB_QPT_PROXY_SMI; 1000 } 1001 } 1002 qpn = sqpn; 1003 /* add extra sg entry for tunneling */ 1004 init_attr->cap.max_recv_sge++; 1005 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 1006 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 1007 container_of(init_attr, 1008 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 1009 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 1010 tnl_init->proxy_qp_type != IB_QPT_GSI) || 1011 !mlx4_is_master(dev->dev)) 1012 return -EINVAL; 1013 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 1014 qp_type = MLX4_IB_QPT_TUN_GSI; 1015 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 1016 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 1017 tnl_init->port)) 1018 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 1019 else 1020 qp_type = MLX4_IB_QPT_TUN_SMI; 1021 /* we are definitely in the PPF here, since we are creating 1022 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 1023 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 1024 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 1025 sqpn = qpn; 1026 } 1027 1028 if (init_attr->qp_type == IB_QPT_SMI || 1029 init_attr->qp_type == IB_QPT_GSI || qp_type == MLX4_IB_QPT_SMI || 1030 qp_type == MLX4_IB_QPT_GSI || 1031 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 1032 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 1033 qp->sqp = kzalloc_obj(struct mlx4_ib_sqp); 1034 if (!qp->sqp) 1035 return -ENOMEM; 1036 } 1037 1038 qp->mlx4_ib_qp_type = qp_type; 1039 1040 spin_lock_init(&qp->sq.lock); 1041 spin_lock_init(&qp->rq.lock); 1042 INIT_LIST_HEAD(&qp->gid_list); 1043 INIT_LIST_HEAD(&qp->steering_rules); 1044 1045 qp->state = IB_QPS_RESET; 1046 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1047 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 1048 1049 if (udata) { 1050 struct mlx4_ib_create_qp ucmd; 1051 int shift; 1052 int n; 1053 1054 err = ib_copy_validate_udata_in(udata, ucmd, sq_no_prefetch); 1055 if (err) 1056 goto err; 1057 1058 qp->inl_recv_sz = ucmd.inl_recv_sz; 1059 1060 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1061 if (!(dev->dev->caps.flags & 1062 MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 1063 pr_debug("scatter FCS is unsupported\n"); 1064 err = -EOPNOTSUPP; 1065 goto err; 1066 } 1067 1068 qp->flags |= MLX4_IB_QP_SCATTER_FCS; 1069 } 1070 1071 err = set_rq_size(dev, &init_attr->cap, udata, 1072 qp_has_rq(init_attr), qp, qp->inl_recv_sz); 1073 if (err) 1074 goto err; 1075 1076 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 1077 1078 err = set_user_sq_size(dev, qp, &ucmd); 1079 if (err) 1080 goto err; 1081 1082 qp->umem = 1083 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0); 1084 if (IS_ERR(qp->umem)) { 1085 err = PTR_ERR(qp->umem); 1086 goto err; 1087 } 1088 1089 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1090 if (shift < 0) { 1091 err = shift; 1092 goto err_buf; 1093 } 1094 1095 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1096 if (err) 1097 goto err_buf; 1098 1099 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 1100 if (err) 1101 goto err_mtt; 1102 1103 if (qp_has_rq(init_attr)) { 1104 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db); 1105 if (err) 1106 goto err_mtt; 1107 } 1108 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS; 1109 } else { 1110 err = set_rq_size(dev, &init_attr->cap, udata, 1111 qp_has_rq(init_attr), qp, 0); 1112 if (err) 1113 goto err; 1114 1115 qp->sq_no_prefetch = 0; 1116 1117 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 1118 qp->flags |= MLX4_IB_QP_LSO; 1119 1120 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1121 if (dev->steering_support == 1122 MLX4_STEERING_MODE_DEVICE_MANAGED) 1123 qp->flags |= MLX4_IB_QP_NETIF; 1124 else { 1125 err = -EINVAL; 1126 goto err; 1127 } 1128 } 1129 1130 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp); 1131 if (err) 1132 goto err; 1133 1134 if (qp_has_rq(init_attr)) { 1135 err = mlx4_db_alloc(dev->dev, &qp->db, 0); 1136 if (err) 1137 goto err; 1138 1139 *qp->db.db = 0; 1140 } 1141 1142 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, 1143 &qp->buf)) { 1144 err = -ENOMEM; 1145 goto err_db; 1146 } 1147 1148 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 1149 &qp->mtt); 1150 if (err) 1151 goto err_buf; 1152 1153 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); 1154 if (err) 1155 goto err_mtt; 1156 1157 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, 1158 sizeof(u64), GFP_KERNEL); 1159 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, 1160 sizeof(u64), GFP_KERNEL); 1161 if (!qp->sq.wrid || !qp->rq.wrid) { 1162 err = -ENOMEM; 1163 goto err_wrid; 1164 } 1165 qp->mqp.usage = MLX4_RES_USAGE_DRIVER; 1166 } 1167 1168 if (sqpn) { 1169 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1170 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 1171 if (alloc_proxy_bufs(pd->device, qp)) { 1172 err = -ENOMEM; 1173 goto err_wrid; 1174 } 1175 } 1176 } else { 1177 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 1178 * otherwise, the WQE BlueFlame setup flow wrongly causes 1179 * VLAN insertion. */ 1180 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 1181 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 1182 (init_attr->cap.max_send_wr ? 1183 MLX4_RESERVE_ETH_BF_QP : 0) | 1184 (init_attr->cap.max_recv_wr ? 1185 MLX4_RESERVE_A0_QP : 0), 1186 qp->mqp.usage); 1187 else 1188 if (qp->flags & MLX4_IB_QP_NETIF) 1189 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 1190 else 1191 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 1192 &qpn, 0, qp->mqp.usage); 1193 if (err) 1194 goto err_proxy; 1195 } 1196 1197 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 1198 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1199 1200 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp); 1201 if (err) 1202 goto err_qpn; 1203 1204 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1205 qp->mqp.qpn |= (1 << 23); 1206 1207 /* 1208 * Hardware wants QPN written in big-endian order (after 1209 * shifting) for send doorbell. Precompute this value to save 1210 * a little bit when posting sends. 1211 */ 1212 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 1213 1214 qp->mqp.event = mlx4_ib_qp_event; 1215 1216 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1217 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 1218 to_mcq(init_attr->recv_cq)); 1219 /* Maintain device to QPs access, needed for further handling 1220 * via reset flow 1221 */ 1222 list_add_tail(&qp->qps_list, &dev->qp_list); 1223 /* Maintain CQ to QPs access, needed for further handling 1224 * via reset flow 1225 */ 1226 mcq = to_mcq(init_attr->send_cq); 1227 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 1228 mcq = to_mcq(init_attr->recv_cq); 1229 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 1230 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 1231 to_mcq(init_attr->recv_cq)); 1232 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1233 return 0; 1234 1235 err_qpn: 1236 if (!sqpn) { 1237 if (qp->flags & MLX4_IB_QP_NETIF) 1238 mlx4_ib_steer_qp_free(dev, qpn, 1); 1239 else 1240 mlx4_qp_release_range(dev->dev, qpn, 1); 1241 } 1242 err_proxy: 1243 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1244 free_proxy_bufs(pd->device, qp); 1245 err_wrid: 1246 if (udata) { 1247 if (qp_has_rq(init_attr)) 1248 mlx4_ib_db_unmap_user(context, &qp->db); 1249 } else { 1250 kvfree(qp->sq.wrid); 1251 kvfree(qp->rq.wrid); 1252 } 1253 1254 err_mtt: 1255 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1256 1257 err_buf: 1258 if (!qp->umem) 1259 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1260 ib_umem_release(qp->umem); 1261 1262 err_db: 1263 if (!udata && qp_has_rq(init_attr)) 1264 mlx4_db_free(dev->dev, &qp->db); 1265 1266 err: 1267 kfree(qp->sqp); 1268 return err; 1269 } 1270 1271 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 1272 { 1273 switch (state) { 1274 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 1275 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 1276 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 1277 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 1278 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 1279 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 1280 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 1281 default: return -1; 1282 } 1283 } 1284 1285 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1286 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1287 { 1288 if (send_cq == recv_cq) { 1289 spin_lock(&send_cq->lock); 1290 __acquire(&recv_cq->lock); 1291 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1292 spin_lock(&send_cq->lock); 1293 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1294 } else { 1295 spin_lock(&recv_cq->lock); 1296 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1297 } 1298 } 1299 1300 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 1301 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1302 { 1303 if (send_cq == recv_cq) { 1304 __release(&recv_cq->lock); 1305 spin_unlock(&send_cq->lock); 1306 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1307 spin_unlock(&recv_cq->lock); 1308 spin_unlock(&send_cq->lock); 1309 } else { 1310 spin_unlock(&send_cq->lock); 1311 spin_unlock(&recv_cq->lock); 1312 } 1313 } 1314 1315 static void del_gid_entries(struct mlx4_ib_qp *qp) 1316 { 1317 struct mlx4_ib_gid_entry *ge, *tmp; 1318 1319 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1320 list_del(&ge->list); 1321 kfree(ge); 1322 } 1323 } 1324 1325 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 1326 { 1327 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1328 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1329 else 1330 return to_mpd(qp->ibqp.pd); 1331 } 1332 1333 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src, 1334 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1335 { 1336 switch (qp->ibqp.qp_type) { 1337 case IB_QPT_XRC_TGT: 1338 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1339 *recv_cq = *send_cq; 1340 break; 1341 case IB_QPT_XRC_INI: 1342 *send_cq = to_mcq(qp->ibqp.send_cq); 1343 *recv_cq = *send_cq; 1344 break; 1345 default: 1346 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) : 1347 to_mcq(qp->ibwq.cq); 1348 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) : 1349 *recv_cq; 1350 break; 1351 } 1352 } 1353 1354 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1355 { 1356 if (qp->state != IB_QPS_RESET) { 1357 int i; 1358 1359 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size); 1360 i++) { 1361 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i]; 1362 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1363 1364 mutex_lock(&wq->mutex); 1365 1366 wq->rss_usecnt--; 1367 1368 mutex_unlock(&wq->mutex); 1369 } 1370 1371 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1372 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1373 pr_warn("modify QP %06x to RESET failed.\n", 1374 qp->mqp.qpn); 1375 } 1376 1377 mlx4_qp_remove(dev->dev, &qp->mqp); 1378 mlx4_qp_free(dev->dev, &qp->mqp); 1379 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1380 del_gid_entries(qp); 1381 } 1382 1383 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1384 enum mlx4_ib_source_type src, 1385 struct ib_udata *udata) 1386 { 1387 struct mlx4_ib_cq *send_cq, *recv_cq; 1388 unsigned long flags; 1389 1390 if (qp->state != IB_QPS_RESET) { 1391 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1392 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1393 pr_warn("modify QP %06x to RESET failed.\n", 1394 qp->mqp.qpn); 1395 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1396 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1397 qp->pri.smac = 0; 1398 qp->pri.smac_port = 0; 1399 } 1400 if (qp->alt.smac) { 1401 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1402 qp->alt.smac = 0; 1403 } 1404 if (qp->pri.vid < 0x1000) { 1405 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1406 qp->pri.vid = 0xFFFF; 1407 qp->pri.candidate_vid = 0xFFFF; 1408 qp->pri.update_vid = 0; 1409 } 1410 if (qp->alt.vid < 0x1000) { 1411 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1412 qp->alt.vid = 0xFFFF; 1413 qp->alt.candidate_vid = 0xFFFF; 1414 qp->alt.update_vid = 0; 1415 } 1416 } 1417 1418 get_cqs(qp, src, &send_cq, &recv_cq); 1419 1420 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1421 mlx4_ib_lock_cqs(send_cq, recv_cq); 1422 1423 /* del from lists under both locks above to protect reset flow paths */ 1424 list_del(&qp->qps_list); 1425 list_del(&qp->cq_send_list); 1426 list_del(&qp->cq_recv_list); 1427 if (!udata) { 1428 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1429 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1430 if (send_cq != recv_cq) 1431 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1432 } 1433 1434 mlx4_qp_remove(dev->dev, &qp->mqp); 1435 1436 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1437 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1438 1439 mlx4_qp_free(dev->dev, &qp->mqp); 1440 1441 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1442 if (qp->flags & MLX4_IB_QP_NETIF) 1443 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1444 else if (src == MLX4_IB_RWQ_SRC) 1445 mlx4_ib_release_wqn( 1446 rdma_udata_to_drv_context( 1447 udata, 1448 struct mlx4_ib_ucontext, 1449 ibucontext), 1450 qp, 1); 1451 else 1452 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1453 } 1454 1455 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1456 1457 if (udata) { 1458 if (qp->rq.wqe_cnt) { 1459 struct mlx4_ib_ucontext *mcontext = 1460 rdma_udata_to_drv_context( 1461 udata, 1462 struct mlx4_ib_ucontext, 1463 ibucontext); 1464 1465 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1466 } 1467 } else { 1468 kvfree(qp->sq.wrid); 1469 kvfree(qp->rq.wrid); 1470 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1471 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1472 free_proxy_bufs(&dev->ib_dev, qp); 1473 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1474 if (qp->rq.wqe_cnt) 1475 mlx4_db_free(dev->dev, &qp->db); 1476 } 1477 ib_umem_release(qp->umem); 1478 1479 del_gid_entries(qp); 1480 } 1481 1482 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1483 { 1484 /* Native or PPF */ 1485 if (!mlx4_is_mfunc(dev->dev) || 1486 (mlx4_is_master(dev->dev) && 1487 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1488 return dev->dev->phys_caps.base_sqpn + 1489 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1490 attr->port_num - 1; 1491 } 1492 /* PF or VF -- creating proxies */ 1493 if (attr->qp_type == IB_QPT_SMI) 1494 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy; 1495 else 1496 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy; 1497 } 1498 1499 static int _mlx4_ib_create_qp(struct ib_pd *pd, struct mlx4_ib_qp *qp, 1500 struct ib_qp_init_attr *init_attr, 1501 struct ib_udata *udata) 1502 { 1503 int err; 1504 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1505 u16 xrcdn = 0; 1506 1507 if (init_attr->rwq_ind_tbl) 1508 return _mlx4_ib_create_qp_rss(pd, qp, init_attr, udata); 1509 1510 /* 1511 * We only support LSO, vendor flag1, and multicast loopback blocking, 1512 * and only for kernel UD QPs. 1513 */ 1514 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1515 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1516 MLX4_IB_SRIOV_TUNNEL_QP | 1517 MLX4_IB_SRIOV_SQP | 1518 MLX4_IB_QP_NETIF | 1519 MLX4_IB_QP_CREATE_ROCE_V2_GSI)) 1520 return -EOPNOTSUPP; 1521 1522 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1523 if (init_attr->qp_type != IB_QPT_UD) 1524 return -EINVAL; 1525 } 1526 1527 if (init_attr->create_flags) { 1528 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1529 return -EINVAL; 1530 1531 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1532 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1533 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1534 init_attr->qp_type != IB_QPT_UD) || 1535 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1536 init_attr->qp_type > IB_QPT_GSI) || 1537 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1538 init_attr->qp_type != IB_QPT_GSI)) 1539 return -EINVAL; 1540 } 1541 1542 switch (init_attr->qp_type) { 1543 case IB_QPT_XRC_TGT: 1544 pd = to_mxrcd(init_attr->xrcd)->pd; 1545 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1546 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1547 fallthrough; 1548 case IB_QPT_XRC_INI: 1549 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1550 return -ENOSYS; 1551 init_attr->recv_cq = init_attr->send_cq; 1552 fallthrough; 1553 case IB_QPT_RC: 1554 case IB_QPT_UC: 1555 case IB_QPT_RAW_PACKET: 1556 case IB_QPT_UD: 1557 qp->pri.vid = 0xFFFF; 1558 qp->alt.vid = 0xFFFF; 1559 err = create_qp_common(pd, init_attr, udata, 0, qp); 1560 if (err) 1561 return err; 1562 1563 qp->ibqp.qp_num = qp->mqp.qpn; 1564 qp->xrcdn = xrcdn; 1565 break; 1566 case IB_QPT_SMI: 1567 case IB_QPT_GSI: 1568 { 1569 int sqpn; 1570 1571 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1572 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1573 1, 1, &sqpn, 0, 1574 MLX4_RES_USAGE_DRIVER); 1575 1576 if (res) 1577 return res; 1578 } else { 1579 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1580 } 1581 1582 qp->pri.vid = 0xFFFF; 1583 qp->alt.vid = 0xFFFF; 1584 err = create_qp_common(pd, init_attr, udata, sqpn, qp); 1585 if (err) 1586 return err; 1587 1588 if (init_attr->create_flags & 1589 (MLX4_IB_SRIOV_SQP | MLX4_IB_SRIOV_TUNNEL_QP)) 1590 /* Internal QP created with ib_create_qp */ 1591 rdma_restrack_no_track(&qp->ibqp.res); 1592 1593 qp->port = init_attr->port_num; 1594 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1595 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1596 break; 1597 } 1598 default: 1599 /* Don't support raw QPs */ 1600 return -EOPNOTSUPP; 1601 } 1602 return 0; 1603 } 1604 1605 int mlx4_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *init_attr, 1606 struct ib_udata *udata) 1607 { 1608 struct ib_device *device = ibqp->device; 1609 struct mlx4_ib_dev *dev = to_mdev(device); 1610 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1611 struct ib_pd *pd = ibqp->pd; 1612 int ret; 1613 1614 mutex_init(&qp->mutex); 1615 ret = _mlx4_ib_create_qp(pd, qp, init_attr, udata); 1616 if (ret) 1617 return ret; 1618 1619 if (init_attr->qp_type == IB_QPT_GSI && 1620 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1621 struct mlx4_ib_sqp *sqp = qp->sqp; 1622 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1623 1624 if (is_eth && 1625 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1626 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1627 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1628 1629 if (IS_ERR(sqp->roce_v2_gsi)) { 1630 pr_err("Failed to create GSI QP for RoCEv2 (%pe)\n", 1631 sqp->roce_v2_gsi); 1632 sqp->roce_v2_gsi = NULL; 1633 } else { 1634 to_mqp(sqp->roce_v2_gsi)->flags |= 1635 MLX4_IB_ROCE_V2_GSI_QP; 1636 } 1637 1638 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1639 } 1640 } 1641 return 0; 1642 } 1643 1644 static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1645 { 1646 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1647 struct mlx4_ib_qp *mqp = to_mqp(qp); 1648 1649 if (is_qp0(dev, mqp)) 1650 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1651 1652 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI && 1653 dev->qp1_proxy[mqp->port - 1] == mqp) { 1654 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1655 dev->qp1_proxy[mqp->port - 1] = NULL; 1656 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1657 } 1658 1659 if (mqp->counter_index) 1660 mlx4_ib_free_qp_counter(dev, mqp); 1661 1662 if (qp->rwq_ind_tbl) { 1663 destroy_qp_rss(dev, mqp); 1664 } else { 1665 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata); 1666 } 1667 1668 kfree(mqp->sqp); 1669 return 0; 1670 } 1671 1672 int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1673 { 1674 struct mlx4_ib_qp *mqp = to_mqp(qp); 1675 1676 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1677 struct mlx4_ib_sqp *sqp = mqp->sqp; 1678 1679 if (sqp->roce_v2_gsi) 1680 ib_destroy_qp(sqp->roce_v2_gsi); 1681 } 1682 1683 return _mlx4_ib_destroy_qp(qp, udata); 1684 } 1685 1686 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1687 { 1688 switch (type) { 1689 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1690 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1691 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1692 case MLX4_IB_QPT_XRC_INI: 1693 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1694 case MLX4_IB_QPT_SMI: 1695 case MLX4_IB_QPT_GSI: 1696 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1697 1698 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1699 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1700 MLX4_QP_ST_MLX : -1); 1701 case MLX4_IB_QPT_PROXY_SMI: 1702 case MLX4_IB_QPT_TUN_SMI: 1703 case MLX4_IB_QPT_PROXY_GSI: 1704 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1705 MLX4_QP_ST_UD : -1); 1706 default: return -1; 1707 } 1708 } 1709 1710 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1711 int attr_mask) 1712 { 1713 u8 dest_rd_atomic; 1714 u32 access_flags; 1715 u32 hw_access_flags = 0; 1716 1717 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1718 dest_rd_atomic = attr->max_dest_rd_atomic; 1719 else 1720 dest_rd_atomic = qp->resp_depth; 1721 1722 if (attr_mask & IB_QP_ACCESS_FLAGS) 1723 access_flags = attr->qp_access_flags; 1724 else 1725 access_flags = qp->atomic_rd_en; 1726 1727 if (!dest_rd_atomic) 1728 access_flags &= IB_ACCESS_REMOTE_WRITE; 1729 1730 if (access_flags & IB_ACCESS_REMOTE_READ) 1731 hw_access_flags |= MLX4_QP_BIT_RRE; 1732 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1733 hw_access_flags |= MLX4_QP_BIT_RAE; 1734 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1735 hw_access_flags |= MLX4_QP_BIT_RWE; 1736 1737 return cpu_to_be32(hw_access_flags); 1738 } 1739 1740 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1741 int attr_mask) 1742 { 1743 if (attr_mask & IB_QP_PKEY_INDEX) 1744 sqp->pkey_index = attr->pkey_index; 1745 if (attr_mask & IB_QP_QKEY) 1746 sqp->qkey = attr->qkey; 1747 if (attr_mask & IB_QP_SQ_PSN) 1748 sqp->send_psn = attr->sq_psn; 1749 } 1750 1751 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1752 { 1753 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1754 } 1755 1756 static int _mlx4_set_path(struct mlx4_ib_dev *dev, 1757 const struct rdma_ah_attr *ah, 1758 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1759 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1760 { 1761 int vidx; 1762 int smac_index; 1763 int err; 1764 1765 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1766 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1767 if (rdma_ah_get_static_rate(ah)) { 1768 path->static_rate = rdma_ah_get_static_rate(ah) + 1769 MLX4_STAT_RATE_OFFSET; 1770 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1771 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1772 --path->static_rate; 1773 } else 1774 path->static_rate = 0; 1775 1776 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1777 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1778 int real_sgid_index = 1779 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr); 1780 1781 if (real_sgid_index < 0) 1782 return real_sgid_index; 1783 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1784 pr_err("sgid_index (%u) too large. max is %d\n", 1785 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1786 return -1; 1787 } 1788 1789 path->grh_mylmc |= 1 << 7; 1790 path->mgid_index = real_sgid_index; 1791 path->hop_limit = grh->hop_limit; 1792 path->tclass_flowlabel = 1793 cpu_to_be32((grh->traffic_class << 20) | 1794 (grh->flow_label)); 1795 memcpy(path->rgid, grh->dgid.raw, 16); 1796 } 1797 1798 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1799 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1800 return -1; 1801 1802 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1803 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1804 1805 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1806 if (vlan_tag < 0x1000) { 1807 if (smac_info->vid < 0x1000) { 1808 /* both valid vlan ids */ 1809 if (smac_info->vid != vlan_tag) { 1810 /* different VIDs. unreg old and reg new */ 1811 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1812 if (err) 1813 return err; 1814 smac_info->candidate_vid = vlan_tag; 1815 smac_info->candidate_vlan_index = vidx; 1816 smac_info->candidate_vlan_port = port; 1817 smac_info->update_vid = 1; 1818 path->vlan_index = vidx; 1819 } else { 1820 path->vlan_index = smac_info->vlan_index; 1821 } 1822 } else { 1823 /* no current vlan tag in qp */ 1824 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1825 if (err) 1826 return err; 1827 smac_info->candidate_vid = vlan_tag; 1828 smac_info->candidate_vlan_index = vidx; 1829 smac_info->candidate_vlan_port = port; 1830 smac_info->update_vid = 1; 1831 path->vlan_index = vidx; 1832 } 1833 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1834 path->fl = 1 << 6; 1835 } else { 1836 /* have current vlan tag. unregister it at modify-qp success */ 1837 if (smac_info->vid < 0x1000) { 1838 smac_info->candidate_vid = 0xFFFF; 1839 smac_info->update_vid = 1; 1840 } 1841 } 1842 1843 /* get smac_index for RoCE use. 1844 * If no smac was yet assigned, register one. 1845 * If one was already assigned, but the new mac differs, 1846 * unregister the old one and register the new one. 1847 */ 1848 if ((!smac_info->smac && !smac_info->smac_port) || 1849 smac_info->smac != smac) { 1850 /* register candidate now, unreg if needed, after success */ 1851 smac_index = mlx4_register_mac(dev->dev, port, smac); 1852 if (smac_index >= 0) { 1853 smac_info->candidate_smac_index = smac_index; 1854 smac_info->candidate_smac = smac; 1855 smac_info->candidate_smac_port = port; 1856 } else { 1857 return -EINVAL; 1858 } 1859 } else { 1860 smac_index = smac_info->smac_index; 1861 } 1862 memcpy(path->dmac, ah->roce.dmac, 6); 1863 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1864 /* put MAC table smac index for IBoE */ 1865 path->grh_mylmc = (u8) (smac_index) | 0x80; 1866 } else { 1867 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1868 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1869 } 1870 1871 return 0; 1872 } 1873 1874 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1875 enum ib_qp_attr_mask qp_attr_mask, 1876 struct mlx4_ib_qp *mqp, 1877 struct mlx4_qp_path *path, u8 port, 1878 u16 vlan_id, u8 *smac) 1879 { 1880 return _mlx4_set_path(dev, &qp->ah_attr, 1881 ether_addr_to_u64(smac), 1882 vlan_id, 1883 path, &mqp->pri, port); 1884 } 1885 1886 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1887 const struct ib_qp_attr *qp, 1888 enum ib_qp_attr_mask qp_attr_mask, 1889 struct mlx4_ib_qp *mqp, 1890 struct mlx4_qp_path *path, u8 port) 1891 { 1892 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1893 0, 1894 0xffff, 1895 path, &mqp->alt, port); 1896 } 1897 1898 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1899 { 1900 struct mlx4_ib_gid_entry *ge, *tmp; 1901 1902 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1903 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1904 ge->added = 1; 1905 ge->port = qp->port; 1906 } 1907 } 1908 } 1909 1910 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1911 struct mlx4_ib_qp *qp, 1912 struct mlx4_qp_context *context) 1913 { 1914 u64 u64_mac; 1915 int smac_index; 1916 1917 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1918 1919 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1920 if (!qp->pri.smac && !qp->pri.smac_port) { 1921 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1922 if (smac_index >= 0) { 1923 qp->pri.candidate_smac_index = smac_index; 1924 qp->pri.candidate_smac = u64_mac; 1925 qp->pri.candidate_smac_port = qp->port; 1926 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1927 } else { 1928 return -ENOENT; 1929 } 1930 } 1931 return 0; 1932 } 1933 1934 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1935 { 1936 struct counter_index *new_counter_index; 1937 int err; 1938 u32 tmp_idx; 1939 1940 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1941 IB_LINK_LAYER_ETHERNET || 1942 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1943 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1944 return 0; 1945 1946 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER); 1947 if (err) 1948 return err; 1949 1950 new_counter_index = kmalloc_obj(*new_counter_index); 1951 if (!new_counter_index) { 1952 mlx4_counter_free(dev->dev, tmp_idx); 1953 return -ENOMEM; 1954 } 1955 1956 new_counter_index->index = tmp_idx; 1957 new_counter_index->allocated = 1; 1958 qp->counter_index = new_counter_index; 1959 1960 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1961 list_add_tail(&new_counter_index->list, 1962 &dev->counters_table[qp->port - 1].counters_list); 1963 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1964 1965 return 0; 1966 } 1967 1968 enum { 1969 MLX4_QPC_ROCE_MODE_1 = 0, 1970 MLX4_QPC_ROCE_MODE_2 = 2, 1971 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1972 }; 1973 1974 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1975 { 1976 switch (gid_type) { 1977 case IB_GID_TYPE_ROCE: 1978 return MLX4_QPC_ROCE_MODE_1; 1979 case IB_GID_TYPE_ROCE_UDP_ENCAP: 1980 return MLX4_QPC_ROCE_MODE_2; 1981 default: 1982 return MLX4_QPC_ROCE_MODE_UNDEFINED; 1983 } 1984 } 1985 1986 /* 1987 * Go over all RSS QP's childes (WQs) and apply their HW state according to 1988 * their logic state if the RSS QP is the first RSS QP associated for the WQ. 1989 */ 1990 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num, 1991 struct ib_udata *udata) 1992 { 1993 int err = 0; 1994 int i; 1995 1996 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 1997 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 1998 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 1999 2000 mutex_lock(&wq->mutex); 2001 2002 /* Mlx4_ib restrictions: 2003 * WQ's is associated to a port according to the RSS QP it is 2004 * associates to. 2005 * In case the WQ is associated to a different port by another 2006 * RSS QP, return a failure. 2007 */ 2008 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) { 2009 err = -EINVAL; 2010 mutex_unlock(&wq->mutex); 2011 break; 2012 } 2013 wq->port = port_num; 2014 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) { 2015 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata); 2016 if (err) { 2017 mutex_unlock(&wq->mutex); 2018 break; 2019 } 2020 } 2021 wq->rss_usecnt++; 2022 2023 mutex_unlock(&wq->mutex); 2024 } 2025 2026 if (i && err) { 2027 int j; 2028 2029 for (j = (i - 1); j >= 0; j--) { 2030 struct ib_wq *ibwq = ind_tbl->ind_tbl[j]; 2031 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2032 2033 mutex_lock(&wq->mutex); 2034 2035 if ((wq->rss_usecnt == 1) && 2036 (ibwq->state == IB_WQS_RDY)) 2037 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, 2038 udata)) 2039 pr_warn("failed to reverse WQN=0x%06x\n", 2040 ibwq->wq_num); 2041 wq->rss_usecnt--; 2042 2043 mutex_unlock(&wq->mutex); 2044 } 2045 } 2046 2047 return err; 2048 } 2049 2050 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, 2051 struct ib_udata *udata) 2052 { 2053 int i; 2054 2055 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) { 2056 struct ib_wq *ibwq = ind_tbl->ind_tbl[i]; 2057 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq); 2058 2059 mutex_lock(&wq->mutex); 2060 2061 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY)) 2062 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata)) 2063 pr_warn("failed to reverse WQN=%x\n", 2064 ibwq->wq_num); 2065 wq->rss_usecnt--; 2066 2067 mutex_unlock(&wq->mutex); 2068 } 2069 } 2070 2071 static void fill_qp_rss_context(struct mlx4_qp_context *context, 2072 struct mlx4_ib_qp *qp) 2073 { 2074 struct mlx4_rss_context *rss_context; 2075 2076 rss_context = (void *)context + offsetof(struct mlx4_qp_context, 2077 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; 2078 2079 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz); 2080 rss_context->default_qpn = 2081 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff); 2082 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6)) 2083 rss_context->base_qpn_udp = rss_context->default_qpn; 2084 rss_context->flags = qp->rss_ctx->flags; 2085 /* Currently support just toeplitz */ 2086 rss_context->hash_fn = MLX4_RSS_HASH_TOP; 2087 2088 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key, 2089 MLX4_EN_RSS_KEY_SIZE); 2090 } 2091 2092 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type, 2093 const struct ib_qp_attr *attr, int attr_mask, 2094 enum ib_qp_state cur_state, 2095 enum ib_qp_state new_state, 2096 struct ib_udata *udata) 2097 { 2098 struct ib_srq *ibsrq; 2099 const struct ib_gid_attr *gid_attr = NULL; 2100 struct ib_rwq_ind_table *rwq_ind_tbl; 2101 enum ib_qp_type qp_type; 2102 struct mlx4_ib_dev *dev; 2103 struct mlx4_ib_qp *qp; 2104 struct mlx4_ib_pd *pd; 2105 struct mlx4_ib_cq *send_cq, *recv_cq; 2106 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context( 2107 udata, struct mlx4_ib_ucontext, ibucontext); 2108 struct mlx4_qp_context *context; 2109 enum mlx4_qp_optpar optpar = 0; 2110 int sqd_event; 2111 int steer_qp = 0; 2112 int err = -EINVAL; 2113 int counter_index; 2114 2115 if (src_type == MLX4_IB_RWQ_SRC) { 2116 struct ib_wq *ibwq; 2117 2118 ibwq = (struct ib_wq *)src; 2119 ibsrq = NULL; 2120 rwq_ind_tbl = NULL; 2121 qp_type = IB_QPT_RAW_PACKET; 2122 qp = to_mqp((struct ib_qp *)ibwq); 2123 dev = to_mdev(ibwq->device); 2124 pd = to_mpd(ibwq->pd); 2125 } else { 2126 struct ib_qp *ibqp; 2127 2128 ibqp = (struct ib_qp *)src; 2129 ibsrq = ibqp->srq; 2130 rwq_ind_tbl = ibqp->rwq_ind_tbl; 2131 qp_type = ibqp->qp_type; 2132 qp = to_mqp(ibqp); 2133 dev = to_mdev(ibqp->device); 2134 pd = get_pd(qp); 2135 } 2136 2137 /* APM is not supported under RoCE */ 2138 if (attr_mask & IB_QP_ALT_PATH && 2139 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2140 IB_LINK_LAYER_ETHERNET) 2141 return -ENOTSUPP; 2142 2143 context = kzalloc_obj(*context); 2144 if (!context) 2145 return -ENOMEM; 2146 2147 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 2148 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 2149 2150 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 2151 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2152 else { 2153 optpar |= MLX4_QP_OPTPAR_PM_STATE; 2154 switch (attr->path_mig_state) { 2155 case IB_MIG_MIGRATED: 2156 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 2157 break; 2158 case IB_MIG_REARM: 2159 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 2160 break; 2161 case IB_MIG_ARMED: 2162 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 2163 break; 2164 } 2165 } 2166 2167 if (qp->inl_recv_sz) 2168 context->param3 |= cpu_to_be32(1 << 25); 2169 2170 if (qp->flags & MLX4_IB_QP_SCATTER_FCS) 2171 context->param3 |= cpu_to_be32(1 << 29); 2172 2173 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI) 2174 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 2175 else if (qp_type == IB_QPT_RAW_PACKET) 2176 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 2177 else if (qp_type == IB_QPT_UD) { 2178 if (qp->flags & MLX4_IB_QP_LSO) 2179 context->mtu_msgmax = (IB_MTU_4096 << 5) | 2180 ilog2(dev->dev->caps.max_gso_sz); 2181 else 2182 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13; 2183 } else if (attr_mask & IB_QP_PATH_MTU) { 2184 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 2185 pr_err("path MTU (%u) is invalid\n", 2186 attr->path_mtu); 2187 goto out; 2188 } 2189 context->mtu_msgmax = (attr->path_mtu << 5) | 2190 ilog2(dev->dev->caps.max_msg_sz); 2191 } 2192 2193 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */ 2194 if (qp->rq.wqe_cnt) 2195 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 2196 context->rq_size_stride |= qp->rq.wqe_shift - 4; 2197 } 2198 2199 if (qp->sq.wqe_cnt) 2200 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 2201 context->sq_size_stride |= qp->sq.wqe_shift - 4; 2202 2203 if (new_state == IB_QPS_RESET && qp->counter_index) 2204 mlx4_ib_free_qp_counter(dev, qp); 2205 2206 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2207 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 2208 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 2209 if (qp_type == IB_QPT_RAW_PACKET) 2210 context->param3 |= cpu_to_be32(1 << 30); 2211 } 2212 2213 if (ucontext) 2214 context->usr_page = cpu_to_be32( 2215 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index)); 2216 else 2217 context->usr_page = cpu_to_be32( 2218 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 2219 2220 if (attr_mask & IB_QP_DEST_QPN) 2221 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 2222 2223 if (attr_mask & IB_QP_PORT) { 2224 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 2225 !(attr_mask & IB_QP_AV)) { 2226 mlx4_set_sched(&context->pri_path, attr->port_num); 2227 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 2228 } 2229 } 2230 2231 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 2232 err = create_qp_lb_counter(dev, qp); 2233 if (err) 2234 goto out; 2235 2236 counter_index = 2237 dev->counters_table[qp->port - 1].default_counter; 2238 if (qp->counter_index) 2239 counter_index = qp->counter_index->index; 2240 2241 if (counter_index != -1) { 2242 context->pri_path.counter_index = counter_index; 2243 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 2244 if (qp->counter_index) { 2245 context->pri_path.fl |= 2246 MLX4_FL_ETH_SRC_CHECK_MC_LB; 2247 context->pri_path.vlan_control |= 2248 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 2249 } 2250 } else 2251 context->pri_path.counter_index = 2252 MLX4_SINK_COUNTER_INDEX(dev->dev); 2253 2254 if (qp->flags & MLX4_IB_QP_NETIF) { 2255 mlx4_ib_steer_qp_reg(dev, qp, 1); 2256 steer_qp = 1; 2257 } 2258 2259 if (qp_type == IB_QPT_GSI) { 2260 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 2261 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 2262 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 2263 2264 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2265 } 2266 } 2267 2268 if (attr_mask & IB_QP_PKEY_INDEX) { 2269 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2270 context->pri_path.disable_pkey_check = 0x40; 2271 context->pri_path.pkey_index = attr->pkey_index; 2272 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 2273 } 2274 2275 if (attr_mask & IB_QP_AV) { 2276 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 : 2277 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2278 u16 vlan = 0xffff; 2279 u8 smac[ETH_ALEN]; 2280 int is_eth = 2281 rdma_cap_eth_ah(&dev->ib_dev, port_num) && 2282 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 2283 2284 if (is_eth) { 2285 gid_attr = attr->ah_attr.grh.sgid_attr; 2286 err = rdma_read_gid_l2_fields(gid_attr, &vlan, 2287 &smac[0]); 2288 if (err) 2289 goto out; 2290 } 2291 2292 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 2293 port_num, vlan, smac)) 2294 goto out; 2295 2296 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 2297 MLX4_QP_OPTPAR_SCHED_QUEUE); 2298 2299 if (is_eth && 2300 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 2301 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type); 2302 2303 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 2304 err = -EINVAL; 2305 goto out; 2306 } 2307 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 2308 } 2309 2310 } 2311 2312 if (attr_mask & IB_QP_TIMEOUT) { 2313 context->pri_path.ackto |= attr->timeout << 3; 2314 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 2315 } 2316 2317 if (attr_mask & IB_QP_ALT_PATH) { 2318 if (attr->alt_port_num == 0 || 2319 attr->alt_port_num > dev->dev->caps.num_ports) 2320 goto out; 2321 2322 if (attr->alt_pkey_index >= 2323 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 2324 goto out; 2325 2326 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 2327 &context->alt_path, 2328 attr->alt_port_num)) 2329 goto out; 2330 2331 context->alt_path.pkey_index = attr->alt_pkey_index; 2332 context->alt_path.ackto = attr->alt_timeout << 3; 2333 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 2334 } 2335 2336 context->pd = cpu_to_be32(pd->pdn); 2337 2338 if (!rwq_ind_tbl) { 2339 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 2340 get_cqs(qp, src_type, &send_cq, &recv_cq); 2341 } else { /* Set dummy CQs to be compatible with HV and PRM */ 2342 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq); 2343 recv_cq = send_cq; 2344 } 2345 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 2346 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 2347 2348 /* Set "fast registration enabled" for all kernel QPs */ 2349 if (!ucontext) 2350 context->params1 |= cpu_to_be32(1 << 11); 2351 2352 if (attr_mask & IB_QP_RNR_RETRY) { 2353 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2354 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 2355 } 2356 2357 if (attr_mask & IB_QP_RETRY_CNT) { 2358 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2359 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 2360 } 2361 2362 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2363 if (attr->max_rd_atomic) 2364 context->params1 |= 2365 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2366 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 2367 } 2368 2369 if (attr_mask & IB_QP_SQ_PSN) 2370 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2371 2372 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2373 if (attr->max_dest_rd_atomic) 2374 context->params2 |= 2375 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2376 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 2377 } 2378 2379 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2380 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 2381 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 2382 } 2383 2384 if (ibsrq) 2385 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 2386 2387 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 2388 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2389 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 2390 } 2391 if (attr_mask & IB_QP_RQ_PSN) 2392 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2393 2394 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 2395 if (attr_mask & IB_QP_QKEY) { 2396 if (qp->mlx4_ib_qp_type & 2397 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 2398 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2399 else { 2400 if (mlx4_is_mfunc(dev->dev) && 2401 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 2402 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 2403 MLX4_RESERVED_QKEY_BASE) { 2404 pr_err("Cannot use reserved QKEY" 2405 " 0x%x (range 0xffff0000..0xffffffff" 2406 " is reserved)\n", attr->qkey); 2407 err = -EINVAL; 2408 goto out; 2409 } 2410 context->qkey = cpu_to_be32(attr->qkey); 2411 } 2412 optpar |= MLX4_QP_OPTPAR_Q_KEY; 2413 } 2414 2415 if (ibsrq) 2416 context->srqn = cpu_to_be32(1 << 24 | 2417 to_msrq(ibsrq)->msrq.srqn); 2418 2419 if (qp->rq.wqe_cnt && 2420 cur_state == IB_QPS_RESET && 2421 new_state == IB_QPS_INIT) 2422 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2423 2424 if (cur_state == IB_QPS_INIT && 2425 new_state == IB_QPS_RTR && 2426 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI || 2427 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) { 2428 context->pri_path.sched_queue = (qp->port - 1) << 6; 2429 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 2430 qp->mlx4_ib_qp_type & 2431 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 2432 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 2433 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 2434 context->pri_path.fl = 0x80; 2435 } else { 2436 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 2437 context->pri_path.fl = 0x80; 2438 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 2439 } 2440 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 2441 IB_LINK_LAYER_ETHERNET) { 2442 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 2443 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 2444 context->pri_path.feup = 1 << 7; /* don't fsm */ 2445 /* handle smac_index */ 2446 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 2447 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 2448 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 2449 err = handle_eth_ud_smac_index(dev, qp, context); 2450 if (err) { 2451 err = -EINVAL; 2452 goto out; 2453 } 2454 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 2455 dev->qp1_proxy[qp->port - 1] = qp; 2456 } 2457 } 2458 } 2459 2460 if (qp_type == IB_QPT_RAW_PACKET) { 2461 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 2462 MLX4_IB_LINK_TYPE_ETH; 2463 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 2464 /* set QP to receive both tunneled & non-tunneled packets */ 2465 if (!rwq_ind_tbl) 2466 context->srqn = cpu_to_be32(7 << 28); 2467 } 2468 } 2469 2470 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 2471 int is_eth = rdma_port_get_link_layer( 2472 &dev->ib_dev, qp->port) == 2473 IB_LINK_LAYER_ETHERNET; 2474 if (is_eth) { 2475 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 2476 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 2477 } 2478 } 2479 2480 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 2481 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 2482 sqd_event = 1; 2483 else 2484 sqd_event = 0; 2485 2486 if (!ucontext && 2487 cur_state == IB_QPS_RESET && 2488 new_state == IB_QPS_INIT) 2489 context->rlkey_roce_mode |= (1 << 4); 2490 2491 /* 2492 * Before passing a kernel QP to the HW, make sure that the 2493 * ownership bits of the send queue are set and the SQ 2494 * headroom is stamped so that the hardware doesn't start 2495 * processing stale work requests. 2496 */ 2497 if (!ucontext && 2498 cur_state == IB_QPS_RESET && 2499 new_state == IB_QPS_INIT) { 2500 struct mlx4_wqe_ctrl_seg *ctrl; 2501 int i; 2502 2503 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 2504 ctrl = get_send_wqe(qp, i); 2505 ctrl->owner_opcode = cpu_to_be32(1 << 31); 2506 ctrl->qpn_vlan.fence_size = 2507 1 << (qp->sq.wqe_shift - 4); 2508 stamp_send_wqe(qp, i); 2509 } 2510 } 2511 2512 if (rwq_ind_tbl && 2513 cur_state == IB_QPS_RESET && 2514 new_state == IB_QPS_INIT) { 2515 fill_qp_rss_context(context, qp); 2516 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET); 2517 } 2518 2519 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2520 to_mlx4_state(new_state), context, optpar, 2521 sqd_event, &qp->mqp); 2522 if (err) 2523 goto out; 2524 2525 qp->state = new_state; 2526 2527 if (attr_mask & IB_QP_ACCESS_FLAGS) 2528 qp->atomic_rd_en = attr->qp_access_flags; 2529 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2530 qp->resp_depth = attr->max_dest_rd_atomic; 2531 if (attr_mask & IB_QP_PORT) { 2532 qp->port = attr->port_num; 2533 update_mcg_macs(dev, qp); 2534 } 2535 if (attr_mask & IB_QP_ALT_PATH) 2536 qp->alt_port = attr->alt_port_num; 2537 2538 if (is_sqp(dev, qp)) 2539 store_sqp_attrs(qp->sqp, attr, attr_mask); 2540 2541 /* 2542 * If we moved QP0 to RTR, bring the IB link up; if we moved 2543 * QP0 to RESET or ERROR, bring the link back down. 2544 */ 2545 if (is_qp0(dev, qp)) { 2546 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2547 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2548 pr_warn("INIT_PORT failed for port %d\n", 2549 qp->port); 2550 2551 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2552 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2553 mlx4_CLOSE_PORT(dev->dev, qp->port); 2554 } 2555 2556 /* 2557 * If we moved a kernel QP to RESET, clean up all old CQ 2558 * entries and reinitialize the QP. 2559 */ 2560 if (new_state == IB_QPS_RESET) { 2561 if (!ucontext) { 2562 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2563 ibsrq ? to_msrq(ibsrq) : NULL); 2564 if (send_cq != recv_cq) 2565 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2566 2567 qp->rq.head = 0; 2568 qp->rq.tail = 0; 2569 qp->sq.head = 0; 2570 qp->sq.tail = 0; 2571 qp->sq_next_wqe = 0; 2572 if (qp->rq.wqe_cnt) 2573 *qp->db.db = 0; 2574 2575 if (qp->flags & MLX4_IB_QP_NETIF) 2576 mlx4_ib_steer_qp_reg(dev, qp, 0); 2577 } 2578 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2579 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2580 qp->pri.smac = 0; 2581 qp->pri.smac_port = 0; 2582 } 2583 if (qp->alt.smac) { 2584 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2585 qp->alt.smac = 0; 2586 } 2587 if (qp->pri.vid < 0x1000) { 2588 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2589 qp->pri.vid = 0xFFFF; 2590 qp->pri.candidate_vid = 0xFFFF; 2591 qp->pri.update_vid = 0; 2592 } 2593 2594 if (qp->alt.vid < 0x1000) { 2595 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2596 qp->alt.vid = 0xFFFF; 2597 qp->alt.candidate_vid = 0xFFFF; 2598 qp->alt.update_vid = 0; 2599 } 2600 } 2601 out: 2602 if (err && qp->counter_index) 2603 mlx4_ib_free_qp_counter(dev, qp); 2604 if (err && steer_qp) 2605 mlx4_ib_steer_qp_reg(dev, qp, 0); 2606 kfree(context); 2607 if (qp->pri.candidate_smac || 2608 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2609 if (err) { 2610 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2611 } else { 2612 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2613 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2614 qp->pri.smac = qp->pri.candidate_smac; 2615 qp->pri.smac_index = qp->pri.candidate_smac_index; 2616 qp->pri.smac_port = qp->pri.candidate_smac_port; 2617 } 2618 qp->pri.candidate_smac = 0; 2619 qp->pri.candidate_smac_index = 0; 2620 qp->pri.candidate_smac_port = 0; 2621 } 2622 if (qp->alt.candidate_smac) { 2623 if (err) { 2624 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2625 } else { 2626 if (qp->alt.smac) 2627 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2628 qp->alt.smac = qp->alt.candidate_smac; 2629 qp->alt.smac_index = qp->alt.candidate_smac_index; 2630 qp->alt.smac_port = qp->alt.candidate_smac_port; 2631 } 2632 qp->alt.candidate_smac = 0; 2633 qp->alt.candidate_smac_index = 0; 2634 qp->alt.candidate_smac_port = 0; 2635 } 2636 2637 if (qp->pri.update_vid) { 2638 if (err) { 2639 if (qp->pri.candidate_vid < 0x1000) 2640 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2641 qp->pri.candidate_vid); 2642 } else { 2643 if (qp->pri.vid < 0x1000) 2644 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2645 qp->pri.vid); 2646 qp->pri.vid = qp->pri.candidate_vid; 2647 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2648 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2649 } 2650 qp->pri.candidate_vid = 0xFFFF; 2651 qp->pri.update_vid = 0; 2652 } 2653 2654 if (qp->alt.update_vid) { 2655 if (err) { 2656 if (qp->alt.candidate_vid < 0x1000) 2657 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2658 qp->alt.candidate_vid); 2659 } else { 2660 if (qp->alt.vid < 0x1000) 2661 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2662 qp->alt.vid); 2663 qp->alt.vid = qp->alt.candidate_vid; 2664 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2665 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2666 } 2667 qp->alt.candidate_vid = 0xFFFF; 2668 qp->alt.update_vid = 0; 2669 } 2670 2671 return err; 2672 } 2673 2674 enum { 2675 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE | 2676 IB_QP_PORT), 2677 }; 2678 2679 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2680 int attr_mask, struct ib_udata *udata) 2681 { 2682 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2683 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2684 enum ib_qp_state cur_state, new_state; 2685 int err = -EINVAL; 2686 mutex_lock(&qp->mutex); 2687 2688 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2689 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2690 2691 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2692 attr_mask)) { 2693 pr_debug("qpn 0x%x: invalid attribute mask specified " 2694 "for transition %d to %d. qp_type %d," 2695 " attr_mask 0x%x\n", 2696 ibqp->qp_num, cur_state, new_state, 2697 ibqp->qp_type, attr_mask); 2698 goto out; 2699 } 2700 2701 if (ibqp->rwq_ind_tbl) { 2702 if (!(((cur_state == IB_QPS_RESET) && 2703 (new_state == IB_QPS_INIT)) || 2704 ((cur_state == IB_QPS_INIT) && 2705 (new_state == IB_QPS_RTR)))) { 2706 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n", 2707 ibqp->qp_num, cur_state, new_state); 2708 2709 err = -EOPNOTSUPP; 2710 goto out; 2711 } 2712 2713 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) { 2714 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n", 2715 ibqp->qp_num, attr_mask, cur_state, new_state); 2716 2717 err = -EOPNOTSUPP; 2718 goto out; 2719 } 2720 } 2721 2722 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2723 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2724 if ((ibqp->qp_type == IB_QPT_RC) || 2725 (ibqp->qp_type == IB_QPT_UD) || 2726 (ibqp->qp_type == IB_QPT_UC) || 2727 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2728 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2729 attr->port_num = mlx4_ib_bond_next_port(dev); 2730 } 2731 } else { 2732 /* no sense in changing port_num 2733 * when ports are bonded */ 2734 attr_mask &= ~IB_QP_PORT; 2735 } 2736 } 2737 2738 if ((attr_mask & IB_QP_PORT) && 2739 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2740 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2741 "for transition %d to %d. qp_type %d\n", 2742 ibqp->qp_num, attr->port_num, cur_state, 2743 new_state, ibqp->qp_type); 2744 goto out; 2745 } 2746 2747 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2748 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2749 IB_LINK_LAYER_ETHERNET)) 2750 goto out; 2751 2752 if (attr_mask & IB_QP_PKEY_INDEX) { 2753 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2754 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2755 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2756 "for transition %d to %d. qp_type %d\n", 2757 ibqp->qp_num, attr->pkey_index, cur_state, 2758 new_state, ibqp->qp_type); 2759 goto out; 2760 } 2761 } 2762 2763 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2764 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2765 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2766 "Transition %d to %d. qp_type %d\n", 2767 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2768 new_state, ibqp->qp_type); 2769 goto out; 2770 } 2771 2772 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2773 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2774 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2775 "Transition %d to %d. qp_type %d\n", 2776 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2777 new_state, ibqp->qp_type); 2778 goto out; 2779 } 2780 2781 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2782 err = 0; 2783 goto out; 2784 } 2785 2786 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) { 2787 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num, 2788 udata); 2789 if (err) 2790 goto out; 2791 } 2792 2793 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask, 2794 cur_state, new_state, udata); 2795 2796 if (ibqp->rwq_ind_tbl && err) 2797 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata); 2798 2799 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2800 attr->port_num = 1; 2801 2802 out: 2803 mutex_unlock(&qp->mutex); 2804 return err; 2805 } 2806 2807 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2808 int attr_mask, struct ib_udata *udata) 2809 { 2810 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2811 int ret; 2812 2813 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 2814 return -EOPNOTSUPP; 2815 2816 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2817 2818 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2819 struct mlx4_ib_sqp *sqp = mqp->sqp; 2820 int err = 0; 2821 2822 if (sqp->roce_v2_gsi) 2823 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2824 if (err) 2825 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2826 err); 2827 } 2828 return ret; 2829 } 2830 2831 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2832 { 2833 int i; 2834 for (i = 0; i < dev->caps.num_ports; i++) { 2835 if (qpn == dev->caps.spec_qps[i].qp0_proxy || 2836 qpn == dev->caps.spec_qps[i].qp0_tunnel) { 2837 *qkey = dev->caps.spec_qps[i].qp0_qkey; 2838 return 0; 2839 } 2840 } 2841 return -EINVAL; 2842 } 2843 2844 static int build_sriov_qp0_header(struct mlx4_ib_qp *qp, 2845 const struct ib_ud_wr *wr, 2846 void *wqe, unsigned *mlx_seg_len) 2847 { 2848 struct mlx4_ib_dev *mdev = to_mdev(qp->ibqp.device); 2849 struct mlx4_ib_sqp *sqp = qp->sqp; 2850 struct ib_device *ib_dev = qp->ibqp.device; 2851 struct mlx4_wqe_mlx_seg *mlx = wqe; 2852 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2853 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2854 u16 pkey; 2855 u32 qkey; 2856 int send_size; 2857 int header_size; 2858 int spc; 2859 int err; 2860 int i; 2861 2862 if (wr->wr.opcode != IB_WR_SEND) 2863 return -EINVAL; 2864 2865 send_size = 0; 2866 2867 for (i = 0; i < wr->wr.num_sge; ++i) 2868 send_size += wr->wr.sg_list[i].length; 2869 2870 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2871 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2872 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2873 send_size += sizeof (struct mlx4_ib_tunnel_header); 2874 2875 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2876 2877 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2878 sqp->ud_header.lrh.service_level = 2879 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2880 sqp->ud_header.lrh.destination_lid = 2881 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2882 sqp->ud_header.lrh.source_lid = 2883 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2884 } 2885 2886 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2887 2888 /* force loopback */ 2889 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2890 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2891 2892 sqp->ud_header.lrh.virtual_lane = 0; 2893 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2894 err = ib_get_cached_pkey(ib_dev, qp->port, 0, &pkey); 2895 if (err) 2896 return err; 2897 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2898 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2899 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2900 else 2901 sqp->ud_header.bth.destination_qpn = 2902 cpu_to_be32(mdev->dev->caps.spec_qps[qp->port - 1].qp0_tunnel); 2903 2904 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2905 if (mlx4_is_master(mdev->dev)) { 2906 if (mlx4_get_parav_qkey(mdev->dev, qp->mqp.qpn, &qkey)) 2907 return -EINVAL; 2908 } else { 2909 if (vf_get_qp0_qkey(mdev->dev, qp->mqp.qpn, &qkey)) 2910 return -EINVAL; 2911 } 2912 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2913 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->mqp.qpn); 2914 2915 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2916 sqp->ud_header.immediate_present = 0; 2917 2918 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2919 2920 /* 2921 * Inline data segments may not cross a 64 byte boundary. If 2922 * our UD header is bigger than the space available up to the 2923 * next 64 byte boundary in the WQE, use two inline data 2924 * segments to hold the UD header. 2925 */ 2926 spc = MLX4_INLINE_ALIGN - 2927 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2928 if (header_size <= spc) { 2929 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 2930 memcpy(inl + 1, sqp->header_buf, header_size); 2931 i = 1; 2932 } else { 2933 inl->byte_count = cpu_to_be32(1 << 31 | spc); 2934 memcpy(inl + 1, sqp->header_buf, spc); 2935 2936 inl = (void *) (inl + 1) + spc; 2937 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2938 /* 2939 * Need a barrier here to make sure all the data is 2940 * visible before the byte_count field is set. 2941 * Otherwise the HCA prefetcher could grab the 64-byte 2942 * chunk with this inline segment and get a valid (!= 2943 * 0xffffffff) byte count but stale data, and end up 2944 * generating a packet with bad headers. 2945 * 2946 * The first inline segment's byte_count field doesn't 2947 * need a barrier, because it comes after a 2948 * control/MLX segment and therefore is at an offset 2949 * of 16 mod 64. 2950 */ 2951 wmb(); 2952 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 2953 i = 2; 2954 } 2955 2956 *mlx_seg_len = 2957 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2958 return 0; 2959 } 2960 2961 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 2962 { 2963 union sl2vl_tbl_to_u64 tmp_vltab; 2964 u8 vl; 2965 2966 if (sl > 15) 2967 return 0xf; 2968 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 2969 vl = tmp_vltab.sl8[sl >> 1]; 2970 if (sl & 1) 2971 vl &= 0x0f; 2972 else 2973 vl >>= 4; 2974 return vl; 2975 } 2976 2977 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 2978 int index, union ib_gid *gid, 2979 enum ib_gid_type *gid_type) 2980 { 2981 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 2982 struct mlx4_port_gid_table *port_gid_table; 2983 unsigned long flags; 2984 2985 port_gid_table = &iboe->gids[port_num - 1]; 2986 spin_lock_irqsave(&iboe->lock, flags); 2987 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 2988 *gid_type = port_gid_table->gids[index].gid_type; 2989 spin_unlock_irqrestore(&iboe->lock, flags); 2990 if (rdma_is_zero_gid(gid)) 2991 return -ENOENT; 2992 2993 return 0; 2994 } 2995 2996 #define MLX4_ROCEV2_QP1_SPORT 0xC000 2997 static int build_mlx_header(struct mlx4_ib_qp *qp, const struct ib_ud_wr *wr, 2998 void *wqe, unsigned *mlx_seg_len) 2999 { 3000 struct mlx4_ib_sqp *sqp = qp->sqp; 3001 struct ib_device *ib_dev = qp->ibqp.device; 3002 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 3003 struct mlx4_wqe_mlx_seg *mlx = wqe; 3004 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 3005 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 3006 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3007 union ib_gid sgid; 3008 u16 pkey; 3009 int send_size; 3010 int header_size; 3011 int spc; 3012 int i; 3013 int err = 0; 3014 u16 vlan = 0xffff; 3015 bool is_eth; 3016 bool is_vlan = false; 3017 bool is_grh; 3018 bool is_udp = false; 3019 int ip_version = 0; 3020 3021 send_size = 0; 3022 for (i = 0; i < wr->wr.num_sge; ++i) 3023 send_size += wr->wr.sg_list[i].length; 3024 3025 is_eth = rdma_port_get_link_layer(qp->ibqp.device, qp->port) == IB_LINK_LAYER_ETHERNET; 3026 is_grh = mlx4_ib_ah_grh_present(ah); 3027 if (is_eth) { 3028 enum ib_gid_type gid_type; 3029 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3030 /* When multi-function is enabled, the ib_core gid 3031 * indexes don't necessarily match the hw ones, so 3032 * we must use our own cache */ 3033 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 3034 be32_to_cpu(ah->av.ib.port_pd) >> 24, 3035 ah->av.ib.gid_index, &sgid.raw[0]); 3036 if (err) 3037 return err; 3038 } else { 3039 err = fill_gid_by_hw_index(ibdev, qp->port, 3040 ah->av.ib.gid_index, &sgid, 3041 &gid_type); 3042 if (!err) { 3043 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 3044 if (is_udp) { 3045 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 3046 ip_version = 4; 3047 else 3048 ip_version = 6; 3049 is_grh = false; 3050 } 3051 } else { 3052 return err; 3053 } 3054 } 3055 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 3056 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 3057 is_vlan = true; 3058 } 3059 } 3060 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 3061 ip_version, is_udp, 0, &sqp->ud_header); 3062 if (err) 3063 return err; 3064 3065 if (!is_eth) { 3066 sqp->ud_header.lrh.service_level = 3067 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 3068 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 3069 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 3070 } 3071 3072 if (is_grh || (ip_version == 6)) { 3073 sqp->ud_header.grh.traffic_class = 3074 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3075 sqp->ud_header.grh.flow_label = 3076 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 3077 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 3078 if (is_eth) { 3079 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 3080 } else { 3081 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 3082 /* When multi-function is enabled, the ib_core gid 3083 * indexes don't necessarily match the hw ones, so 3084 * we must use our own cache 3085 */ 3086 sqp->ud_header.grh.source_gid.global 3087 .subnet_prefix = 3088 cpu_to_be64(atomic64_read( 3089 &(to_mdev(ib_dev) 3090 ->sriov 3091 .demux[qp->port - 1] 3092 .subnet_prefix))); 3093 sqp->ud_header.grh.source_gid.global 3094 .interface_id = 3095 to_mdev(ib_dev) 3096 ->sriov.demux[qp->port - 1] 3097 .guid_cache[ah->av.ib.gid_index]; 3098 } else { 3099 sqp->ud_header.grh.source_gid = 3100 ah->ibah.sgid_attr->gid; 3101 } 3102 } 3103 memcpy(sqp->ud_header.grh.destination_gid.raw, 3104 ah->av.ib.dgid, 16); 3105 } 3106 3107 if (ip_version == 4) { 3108 sqp->ud_header.ip4.tos = 3109 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 3110 sqp->ud_header.ip4.id = 0; 3111 sqp->ud_header.ip4.frag_off = htons(IP_DF); 3112 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 3113 3114 memcpy(&sqp->ud_header.ip4.saddr, 3115 sgid.raw + 12, 4); 3116 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 3117 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 3118 } 3119 3120 if (is_udp) { 3121 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 3122 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 3123 sqp->ud_header.udp.csum = 0; 3124 } 3125 3126 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 3127 3128 if (!is_eth) { 3129 mlx->flags |= 3130 cpu_to_be32((!qp->ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 3131 (sqp->ud_header.lrh.destination_lid == 3132 IB_LID_PERMISSIVE ? 3133 MLX4_WQE_MLX_SLR : 3134 0) | 3135 (sqp->ud_header.lrh.service_level << 8)); 3136 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 3137 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 3138 mlx->rlid = sqp->ud_header.lrh.destination_lid; 3139 } 3140 3141 switch (wr->wr.opcode) { 3142 case IB_WR_SEND: 3143 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 3144 sqp->ud_header.immediate_present = 0; 3145 break; 3146 case IB_WR_SEND_WITH_IMM: 3147 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 3148 sqp->ud_header.immediate_present = 1; 3149 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 3150 break; 3151 default: 3152 return -EINVAL; 3153 } 3154 3155 if (is_eth) { 3156 u16 ether_type; 3157 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 3158 3159 ether_type = (!is_udp) ? ETH_P_IBOE: 3160 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6); 3161 3162 mlx->sched_prio = cpu_to_be16(pcp); 3163 3164 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 3165 ether_addr_copy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac); 3166 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 3167 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 3168 3169 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 3170 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 3171 if (!is_vlan) { 3172 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 3173 } else { 3174 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 3175 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 3176 } 3177 } else { 3178 sqp->ud_header.lrh.virtual_lane = 3179 !qp->ibqp.qp_num ? 3180 15 : 3181 sl_to_vl(to_mdev(ib_dev), 3182 sqp->ud_header.lrh.service_level, 3183 qp->port); 3184 if (qp->ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 3185 return -EINVAL; 3186 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 3187 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 3188 } 3189 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 3190 if (!qp->ibqp.qp_num) 3191 err = ib_get_cached_pkey(ib_dev, qp->port, sqp->pkey_index, 3192 &pkey); 3193 else 3194 err = ib_get_cached_pkey(ib_dev, qp->port, wr->pkey_index, 3195 &pkey); 3196 if (err) 3197 return err; 3198 3199 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 3200 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 3201 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 3202 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 3203 sqp->qkey : wr->remote_qkey); 3204 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->ibqp.qp_num); 3205 3206 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 3207 3208 if (0) { 3209 pr_err("built UD header of size %d:\n", header_size); 3210 for (i = 0; i < header_size / 4; ++i) { 3211 if (i % 8 == 0) 3212 pr_err(" [%02x] ", i * 4); 3213 pr_cont(" %08x", 3214 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 3215 if ((i + 1) % 8 == 0) 3216 pr_cont("\n"); 3217 } 3218 pr_err("\n"); 3219 } 3220 3221 /* 3222 * Inline data segments may not cross a 64 byte boundary. If 3223 * our UD header is bigger than the space available up to the 3224 * next 64 byte boundary in the WQE, use two inline data 3225 * segments to hold the UD header. 3226 */ 3227 spc = MLX4_INLINE_ALIGN - 3228 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3229 if (header_size <= spc) { 3230 inl->byte_count = cpu_to_be32(1 << 31 | header_size); 3231 memcpy(inl + 1, sqp->header_buf, header_size); 3232 i = 1; 3233 } else { 3234 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3235 memcpy(inl + 1, sqp->header_buf, spc); 3236 3237 inl = (void *) (inl + 1) + spc; 3238 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 3239 /* 3240 * Need a barrier here to make sure all the data is 3241 * visible before the byte_count field is set. 3242 * Otherwise the HCA prefetcher could grab the 64-byte 3243 * chunk with this inline segment and get a valid (!= 3244 * 0xffffffff) byte count but stale data, and end up 3245 * generating a packet with bad headers. 3246 * 3247 * The first inline segment's byte_count field doesn't 3248 * need a barrier, because it comes after a 3249 * control/MLX segment and therefore is at an offset 3250 * of 16 mod 64. 3251 */ 3252 wmb(); 3253 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); 3254 i = 2; 3255 } 3256 3257 *mlx_seg_len = 3258 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 3259 return 0; 3260 } 3261 3262 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3263 { 3264 unsigned cur; 3265 struct mlx4_ib_cq *cq; 3266 3267 cur = wq->head - wq->tail; 3268 if (likely(cur + nreq < wq->max_post)) 3269 return 0; 3270 3271 cq = to_mcq(ib_cq); 3272 spin_lock(&cq->lock); 3273 cur = wq->head - wq->tail; 3274 spin_unlock(&cq->lock); 3275 3276 return cur + nreq >= wq->max_post; 3277 } 3278 3279 static __be32 convert_access(int acc) 3280 { 3281 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 3282 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 3283 (acc & IB_ACCESS_REMOTE_WRITE ? 3284 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 3285 (acc & IB_ACCESS_REMOTE_READ ? 3286 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 3287 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 3288 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 3289 } 3290 3291 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 3292 const struct ib_reg_wr *wr) 3293 { 3294 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 3295 3296 fseg->flags = convert_access(wr->access); 3297 fseg->mem_key = cpu_to_be32(wr->key); 3298 fseg->buf_list = cpu_to_be64(mr->page_map); 3299 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 3300 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 3301 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 3302 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 3303 fseg->reserved[0] = 0; 3304 fseg->reserved[1] = 0; 3305 } 3306 3307 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 3308 { 3309 memset(iseg, 0, sizeof(*iseg)); 3310 iseg->mem_key = cpu_to_be32(rkey); 3311 } 3312 3313 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 3314 u64 remote_addr, u32 rkey) 3315 { 3316 rseg->raddr = cpu_to_be64(remote_addr); 3317 rseg->rkey = cpu_to_be32(rkey); 3318 rseg->reserved = 0; 3319 } 3320 3321 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 3322 const struct ib_atomic_wr *wr) 3323 { 3324 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 3325 aseg->swap_add = cpu_to_be64(wr->swap); 3326 aseg->compare = cpu_to_be64(wr->compare_add); 3327 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 3328 aseg->swap_add = cpu_to_be64(wr->compare_add); 3329 aseg->compare = cpu_to_be64(wr->compare_add_mask); 3330 } else { 3331 aseg->swap_add = cpu_to_be64(wr->compare_add); 3332 aseg->compare = 0; 3333 } 3334 3335 } 3336 3337 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 3338 const struct ib_atomic_wr *wr) 3339 { 3340 aseg->swap_add = cpu_to_be64(wr->swap); 3341 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 3342 aseg->compare = cpu_to_be64(wr->compare_add); 3343 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 3344 } 3345 3346 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 3347 const struct ib_ud_wr *wr) 3348 { 3349 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 3350 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 3351 dseg->qkey = cpu_to_be32(wr->remote_qkey); 3352 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 3353 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 3354 } 3355 3356 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 3357 struct mlx4_wqe_datagram_seg *dseg, 3358 const struct ib_ud_wr *wr, 3359 enum mlx4_ib_qp_type qpt) 3360 { 3361 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 3362 struct mlx4_av sqp_av = {0}; 3363 int port = *((u8 *) &av->ib.port_pd) & 0x3; 3364 3365 /* force loopback */ 3366 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 3367 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 3368 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 3369 cpu_to_be32(0xf0000000); 3370 3371 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 3372 if (qpt == MLX4_IB_QPT_PROXY_GSI) 3373 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel); 3374 else 3375 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel); 3376 /* Use QKEY from the QP context, which is set by master */ 3377 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 3378 } 3379 3380 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe, 3381 unsigned *mlx_seg_len) 3382 { 3383 struct mlx4_wqe_inline_seg *inl = wqe; 3384 struct mlx4_ib_tunnel_header hdr; 3385 struct mlx4_ib_ah *ah = to_mah(wr->ah); 3386 int spc; 3387 int i; 3388 3389 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 3390 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 3391 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 3392 hdr.qkey = cpu_to_be32(wr->remote_qkey); 3393 memcpy(hdr.mac, ah->av.eth.mac, 6); 3394 hdr.vlan = ah->av.eth.vlan; 3395 3396 spc = MLX4_INLINE_ALIGN - 3397 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 3398 if (sizeof (hdr) <= spc) { 3399 memcpy(inl + 1, &hdr, sizeof (hdr)); 3400 wmb(); 3401 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr)); 3402 i = 1; 3403 } else { 3404 memcpy(inl + 1, &hdr, spc); 3405 wmb(); 3406 inl->byte_count = cpu_to_be32(1 << 31 | spc); 3407 3408 inl = (void *) (inl + 1) + spc; 3409 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 3410 wmb(); 3411 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc)); 3412 i = 2; 3413 } 3414 3415 *mlx_seg_len = 3416 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 3417 } 3418 3419 static void set_mlx_icrc_seg(void *dseg) 3420 { 3421 u32 *t = dseg; 3422 struct mlx4_wqe_inline_seg *iseg = dseg; 3423 3424 t[1] = 0; 3425 3426 /* 3427 * Need a barrier here before writing the byte_count field to 3428 * make sure that all the data is visible before the 3429 * byte_count field is set. Otherwise, if the segment begins 3430 * a new cacheline, the HCA prefetcher could grab the 64-byte 3431 * chunk and get a valid (!= * 0xffffffff) byte count but 3432 * stale data, and end up sending the wrong data. 3433 */ 3434 wmb(); 3435 3436 iseg->byte_count = cpu_to_be32((1 << 31) | 4); 3437 } 3438 3439 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3440 { 3441 dseg->lkey = cpu_to_be32(sg->lkey); 3442 dseg->addr = cpu_to_be64(sg->addr); 3443 3444 /* 3445 * Need a barrier here before writing the byte_count field to 3446 * make sure that all the data is visible before the 3447 * byte_count field is set. Otherwise, if the segment begins 3448 * a new cacheline, the HCA prefetcher could grab the 64-byte 3449 * chunk and get a valid (!= * 0xffffffff) byte count but 3450 * stale data, and end up sending the wrong data. 3451 */ 3452 wmb(); 3453 3454 dseg->byte_count = cpu_to_be32(sg->length); 3455 } 3456 3457 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 3458 { 3459 dseg->byte_count = cpu_to_be32(sg->length); 3460 dseg->lkey = cpu_to_be32(sg->lkey); 3461 dseg->addr = cpu_to_be64(sg->addr); 3462 } 3463 3464 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, 3465 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp, 3466 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh) 3467 { 3468 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 3469 3470 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 3471 *blh = cpu_to_be32(1 << 6); 3472 3473 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 3474 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 3475 return -EINVAL; 3476 3477 memcpy(wqe->header, wr->header, wr->hlen); 3478 3479 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 3480 *lso_seg_len = halign; 3481 return 0; 3482 } 3483 3484 static __be32 send_ieth(const struct ib_send_wr *wr) 3485 { 3486 switch (wr->opcode) { 3487 case IB_WR_SEND_WITH_IMM: 3488 case IB_WR_RDMA_WRITE_WITH_IMM: 3489 return wr->ex.imm_data; 3490 3491 case IB_WR_SEND_WITH_INV: 3492 return cpu_to_be32(wr->ex.invalidate_rkey); 3493 3494 default: 3495 return 0; 3496 } 3497 } 3498 3499 static void add_zero_len_inline(void *wqe) 3500 { 3501 struct mlx4_wqe_inline_seg *inl = wqe; 3502 memset(wqe, 0, 16); 3503 inl->byte_count = cpu_to_be32(1 << 31); 3504 } 3505 3506 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3507 const struct ib_send_wr **bad_wr, bool drain) 3508 { 3509 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3510 void *wqe; 3511 struct mlx4_wqe_ctrl_seg *ctrl; 3512 struct mlx4_wqe_data_seg *dseg; 3513 unsigned long flags; 3514 int nreq; 3515 int err = 0; 3516 unsigned ind; 3517 int size; 3518 unsigned seglen; 3519 __be32 dummy; 3520 __be32 *lso_wqe; 3521 __be32 lso_hdr_sz; 3522 __be32 blh; 3523 int i; 3524 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3525 3526 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 3527 struct mlx4_ib_sqp *sqp = qp->sqp; 3528 3529 if (sqp->roce_v2_gsi) { 3530 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 3531 enum ib_gid_type gid_type; 3532 union ib_gid gid; 3533 3534 if (!fill_gid_by_hw_index(mdev, qp->port, 3535 ah->av.ib.gid_index, 3536 &gid, &gid_type)) 3537 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 3538 to_mqp(sqp->roce_v2_gsi) : qp; 3539 else 3540 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 3541 ah->av.ib.gid_index); 3542 } 3543 } 3544 3545 spin_lock_irqsave(&qp->sq.lock, flags); 3546 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3547 !drain) { 3548 err = -EIO; 3549 *bad_wr = wr; 3550 nreq = 0; 3551 goto out; 3552 } 3553 3554 ind = qp->sq_next_wqe; 3555 3556 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3557 lso_wqe = &dummy; 3558 blh = 0; 3559 3560 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 3561 err = -ENOMEM; 3562 *bad_wr = wr; 3563 goto out; 3564 } 3565 3566 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 3567 err = -EINVAL; 3568 *bad_wr = wr; 3569 goto out; 3570 } 3571 3572 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 3573 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 3574 3575 ctrl->srcrb_flags = 3576 (wr->send_flags & IB_SEND_SIGNALED ? 3577 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3578 (wr->send_flags & IB_SEND_SOLICITED ? 3579 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3580 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3581 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3582 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3583 qp->sq_signal_bits; 3584 3585 ctrl->imm = send_ieth(wr); 3586 3587 wqe += sizeof *ctrl; 3588 size = sizeof *ctrl / 16; 3589 3590 switch (qp->mlx4_ib_qp_type) { 3591 case MLX4_IB_QPT_RC: 3592 case MLX4_IB_QPT_UC: 3593 switch (wr->opcode) { 3594 case IB_WR_ATOMIC_CMP_AND_SWP: 3595 case IB_WR_ATOMIC_FETCH_AND_ADD: 3596 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3597 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3598 atomic_wr(wr)->rkey); 3599 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3600 3601 set_atomic_seg(wqe, atomic_wr(wr)); 3602 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3603 3604 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3605 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3606 3607 break; 3608 3609 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3610 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3611 atomic_wr(wr)->rkey); 3612 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3613 3614 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3615 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3616 3617 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3618 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3619 3620 break; 3621 3622 case IB_WR_RDMA_READ: 3623 case IB_WR_RDMA_WRITE: 3624 case IB_WR_RDMA_WRITE_WITH_IMM: 3625 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3626 rdma_wr(wr)->rkey); 3627 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3628 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3629 break; 3630 3631 case IB_WR_LOCAL_INV: 3632 ctrl->srcrb_flags |= 3633 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3634 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3635 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3636 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3637 break; 3638 3639 case IB_WR_REG_MR: 3640 ctrl->srcrb_flags |= 3641 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3642 set_reg_seg(wqe, reg_wr(wr)); 3643 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3644 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3645 break; 3646 3647 default: 3648 /* No extra segments required for sends */ 3649 break; 3650 } 3651 break; 3652 3653 case MLX4_IB_QPT_TUN_SMI_OWNER: 3654 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl, 3655 &seglen); 3656 if (unlikely(err)) { 3657 *bad_wr = wr; 3658 goto out; 3659 } 3660 wqe += seglen; 3661 size += seglen / 16; 3662 break; 3663 case MLX4_IB_QPT_TUN_SMI: 3664 case MLX4_IB_QPT_TUN_GSI: 3665 /* this is a UD qp used in MAD responses to slaves. */ 3666 set_datagram_seg(wqe, ud_wr(wr)); 3667 /* set the forced-loopback bit in the data seg av */ 3668 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3669 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3670 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3671 break; 3672 case MLX4_IB_QPT_UD: 3673 set_datagram_seg(wqe, ud_wr(wr)); 3674 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3675 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3676 3677 if (wr->opcode == IB_WR_LSO) { 3678 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3679 &lso_hdr_sz, &blh); 3680 if (unlikely(err)) { 3681 *bad_wr = wr; 3682 goto out; 3683 } 3684 lso_wqe = (__be32 *) wqe; 3685 wqe += seglen; 3686 size += seglen / 16; 3687 } 3688 break; 3689 3690 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3691 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl, 3692 &seglen); 3693 if (unlikely(err)) { 3694 *bad_wr = wr; 3695 goto out; 3696 } 3697 wqe += seglen; 3698 size += seglen / 16; 3699 /* to start tunnel header on a cache-line boundary */ 3700 add_zero_len_inline(wqe); 3701 wqe += 16; 3702 size++; 3703 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3704 wqe += seglen; 3705 size += seglen / 16; 3706 break; 3707 case MLX4_IB_QPT_PROXY_SMI: 3708 case MLX4_IB_QPT_PROXY_GSI: 3709 /* If we are tunneling special qps, this is a UD qp. 3710 * In this case we first add a UD segment targeting 3711 * the tunnel qp, and then add a header with address 3712 * information */ 3713 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3714 ud_wr(wr), 3715 qp->mlx4_ib_qp_type); 3716 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3717 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3718 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3719 wqe += seglen; 3720 size += seglen / 16; 3721 break; 3722 3723 case MLX4_IB_QPT_SMI: 3724 case MLX4_IB_QPT_GSI: 3725 err = build_mlx_header(qp, ud_wr(wr), ctrl, &seglen); 3726 if (unlikely(err)) { 3727 *bad_wr = wr; 3728 goto out; 3729 } 3730 wqe += seglen; 3731 size += seglen / 16; 3732 break; 3733 3734 default: 3735 break; 3736 } 3737 3738 /* 3739 * Write data segments in reverse order, so as to 3740 * overwrite cacheline stamp last within each 3741 * cacheline. This avoids issues with WQE 3742 * prefetching. 3743 */ 3744 3745 dseg = wqe; 3746 dseg += wr->num_sge - 1; 3747 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3748 3749 /* Add one more inline data segment for ICRC for MLX sends */ 3750 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3751 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3752 qp->mlx4_ib_qp_type & 3753 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3754 set_mlx_icrc_seg(dseg + 1); 3755 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3756 } 3757 3758 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3759 set_data_seg(dseg, wr->sg_list + i); 3760 3761 /* 3762 * Possibly overwrite stamping in cacheline with LSO 3763 * segment only after making sure all data segments 3764 * are written. 3765 */ 3766 wmb(); 3767 *lso_wqe = lso_hdr_sz; 3768 3769 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ? 3770 MLX4_WQE_CTRL_FENCE : 0) | size; 3771 3772 /* 3773 * Make sure descriptor is fully written before 3774 * setting ownership bit (because HW can start 3775 * executing as soon as we do). 3776 */ 3777 wmb(); 3778 3779 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3780 *bad_wr = wr; 3781 err = -EINVAL; 3782 goto out; 3783 } 3784 3785 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3786 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh; 3787 3788 /* 3789 * We can improve latency by not stamping the last 3790 * send queue WQE until after ringing the doorbell, so 3791 * only stamp here if there are still more WQEs to post. 3792 */ 3793 if (wr->next) 3794 stamp_send_wqe(qp, ind + qp->sq_spare_wqes); 3795 ind++; 3796 } 3797 3798 out: 3799 if (likely(nreq)) { 3800 qp->sq.head += nreq; 3801 3802 /* 3803 * Make sure that descriptors are written before 3804 * doorbell record. 3805 */ 3806 wmb(); 3807 3808 writel_relaxed(qp->doorbell_qpn, 3809 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3810 3811 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1); 3812 3813 qp->sq_next_wqe = ind; 3814 } 3815 3816 spin_unlock_irqrestore(&qp->sq.lock, flags); 3817 3818 return err; 3819 } 3820 3821 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3822 const struct ib_send_wr **bad_wr) 3823 { 3824 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false); 3825 } 3826 3827 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3828 const struct ib_recv_wr **bad_wr, bool drain) 3829 { 3830 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3831 struct mlx4_wqe_data_seg *scat; 3832 unsigned long flags; 3833 int err = 0; 3834 int nreq; 3835 int ind; 3836 int max_gs; 3837 int i; 3838 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3839 3840 max_gs = qp->rq.max_gs; 3841 spin_lock_irqsave(&qp->rq.lock, flags); 3842 3843 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR && 3844 !drain) { 3845 err = -EIO; 3846 *bad_wr = wr; 3847 nreq = 0; 3848 goto out; 3849 } 3850 3851 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3852 3853 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3854 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3855 err = -ENOMEM; 3856 *bad_wr = wr; 3857 goto out; 3858 } 3859 3860 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3861 err = -EINVAL; 3862 *bad_wr = wr; 3863 goto out; 3864 } 3865 3866 scat = get_recv_wqe(qp, ind); 3867 3868 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3869 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3870 ib_dma_sync_single_for_device(ibqp->device, 3871 qp->sqp_proxy_rcv[ind].map, 3872 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3873 DMA_FROM_DEVICE); 3874 scat->byte_count = 3875 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3876 /* use dma lkey from upper layer entry */ 3877 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3878 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3879 scat++; 3880 max_gs--; 3881 } 3882 3883 for (i = 0; i < wr->num_sge; ++i) 3884 __set_data_seg(scat + i, wr->sg_list + i); 3885 3886 if (i < max_gs) { 3887 scat[i].byte_count = 0; 3888 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3889 scat[i].addr = 0; 3890 } 3891 3892 qp->rq.wrid[ind] = wr->wr_id; 3893 3894 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3895 } 3896 3897 out: 3898 if (likely(nreq)) { 3899 qp->rq.head += nreq; 3900 3901 /* 3902 * Make sure that descriptors are written before 3903 * doorbell record. 3904 */ 3905 wmb(); 3906 3907 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3908 } 3909 3910 spin_unlock_irqrestore(&qp->rq.lock, flags); 3911 3912 return err; 3913 } 3914 3915 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3916 const struct ib_recv_wr **bad_wr) 3917 { 3918 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false); 3919 } 3920 3921 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3922 { 3923 switch (mlx4_state) { 3924 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3925 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3926 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3927 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3928 case MLX4_QP_STATE_SQ_DRAINING: 3929 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3930 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3931 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3932 default: return -1; 3933 } 3934 } 3935 3936 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3937 { 3938 switch (mlx4_mig_state) { 3939 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3940 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3941 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3942 default: return -1; 3943 } 3944 } 3945 3946 static int to_ib_qp_access_flags(int mlx4_flags) 3947 { 3948 int ib_flags = 0; 3949 3950 if (mlx4_flags & MLX4_QP_BIT_RRE) 3951 ib_flags |= IB_ACCESS_REMOTE_READ; 3952 if (mlx4_flags & MLX4_QP_BIT_RWE) 3953 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3954 if (mlx4_flags & MLX4_QP_BIT_RAE) 3955 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3956 3957 return ib_flags; 3958 } 3959 3960 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3961 struct rdma_ah_attr *ah_attr, 3962 struct mlx4_qp_path *path) 3963 { 3964 struct mlx4_dev *dev = ibdev->dev; 3965 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 3966 3967 memset(ah_attr, 0, sizeof(*ah_attr)); 3968 if (port_num == 0 || port_num > dev->caps.num_ports) 3969 return; 3970 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 3971 3972 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 3973 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 3974 ((path->sched_queue & 4) << 1)); 3975 else 3976 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 3977 rdma_ah_set_port_num(ah_attr, port_num); 3978 3979 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 3980 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 3981 rdma_ah_set_static_rate(ah_attr, 3982 path->static_rate ? path->static_rate - 5 : 0); 3983 if (path->grh_mylmc & (1 << 7)) { 3984 rdma_ah_set_grh(ah_attr, NULL, 3985 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 3986 path->mgid_index, 3987 path->hop_limit, 3988 (be32_to_cpu(path->tclass_flowlabel) 3989 >> 20) & 0xff); 3990 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 3991 } 3992 } 3993 3994 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3995 struct ib_qp_init_attr *qp_init_attr) 3996 { 3997 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3998 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3999 struct mlx4_qp_context context; 4000 int mlx4_state; 4001 int err = 0; 4002 4003 if (ibqp->rwq_ind_tbl) 4004 return -EOPNOTSUPP; 4005 4006 mutex_lock(&qp->mutex); 4007 4008 if (qp->state == IB_QPS_RESET) { 4009 qp_attr->qp_state = IB_QPS_RESET; 4010 goto done; 4011 } 4012 4013 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 4014 if (err) { 4015 err = -EINVAL; 4016 goto out; 4017 } 4018 4019 mlx4_state = be32_to_cpu(context.flags) >> 28; 4020 4021 qp->state = to_ib_qp_state(mlx4_state); 4022 qp_attr->qp_state = qp->state; 4023 qp_attr->path_mtu = context.mtu_msgmax >> 5; 4024 qp_attr->path_mig_state = 4025 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 4026 qp_attr->qkey = be32_to_cpu(context.qkey); 4027 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 4028 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 4029 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 4030 qp_attr->qp_access_flags = 4031 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 4032 4033 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC || 4034 qp->ibqp.qp_type == IB_QPT_XRC_INI || 4035 qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 4036 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 4037 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 4038 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 4039 qp_attr->alt_port_num = 4040 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 4041 } 4042 4043 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 4044 if (qp_attr->qp_state == IB_QPS_INIT) 4045 qp_attr->port_num = qp->port; 4046 else 4047 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 4048 4049 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4050 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 4051 4052 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 4053 4054 qp_attr->max_dest_rd_atomic = 4055 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 4056 qp_attr->min_rnr_timer = 4057 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 4058 qp_attr->timeout = context.pri_path.ackto >> 3; 4059 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 4060 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 4061 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 4062 4063 done: 4064 qp_attr->cur_qp_state = qp_attr->qp_state; 4065 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4066 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4067 4068 if (!ibqp->uobject) { 4069 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 4070 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4071 } else { 4072 qp_attr->cap.max_send_wr = 0; 4073 qp_attr->cap.max_send_sge = 0; 4074 } 4075 4076 /* 4077 * We don't support inline sends for kernel QPs (yet), and we 4078 * don't know what userspace's value should be. 4079 */ 4080 qp_attr->cap.max_inline_data = 0; 4081 4082 qp_init_attr->cap = qp_attr->cap; 4083 4084 qp_init_attr->create_flags = 0; 4085 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4086 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4087 4088 if (qp->flags & MLX4_IB_QP_LSO) 4089 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 4090 4091 if (qp->flags & MLX4_IB_QP_NETIF) 4092 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 4093 4094 qp_init_attr->sq_sig_type = 4095 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 4096 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4097 4098 out: 4099 mutex_unlock(&qp->mutex); 4100 return err; 4101 } 4102 4103 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, 4104 struct ib_wq_init_attr *init_attr, 4105 struct ib_udata *udata) 4106 { 4107 struct mlx4_dev *dev = to_mdev(pd->device)->dev; 4108 struct ib_qp_init_attr ib_qp_init_attr = {}; 4109 struct mlx4_ib_qp *qp; 4110 int err; 4111 4112 if (!udata) 4113 return ERR_PTR(-EINVAL); 4114 4115 if (udata->outlen) 4116 return ERR_PTR(-EOPNOTSUPP); 4117 4118 if (init_attr->wq_type != IB_WQT_RQ) { 4119 pr_debug("unsupported wq type %d\n", init_attr->wq_type); 4120 return ERR_PTR(-EOPNOTSUPP); 4121 } 4122 4123 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS || 4124 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 4125 pr_debug("unsupported create_flags %u\n", 4126 init_attr->create_flags); 4127 return ERR_PTR(-EOPNOTSUPP); 4128 } 4129 4130 qp = kzalloc_obj(*qp); 4131 if (!qp) 4132 return ERR_PTR(-ENOMEM); 4133 4134 mutex_init(&qp->mutex); 4135 qp->pri.vid = 0xFFFF; 4136 qp->alt.vid = 0xFFFF; 4137 4138 ib_qp_init_attr.qp_context = init_attr->wq_context; 4139 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET; 4140 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr; 4141 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge; 4142 ib_qp_init_attr.recv_cq = init_attr->cq; 4143 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */ 4144 4145 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) 4146 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS; 4147 4148 err = create_rq(pd, &ib_qp_init_attr, udata, qp); 4149 if (err) { 4150 kfree(qp); 4151 return ERR_PTR(err); 4152 } 4153 4154 qp->ibwq.event_handler = init_attr->event_handler; 4155 qp->ibwq.wq_num = qp->mqp.qpn; 4156 qp->ibwq.state = IB_WQS_RESET; 4157 4158 return &qp->ibwq; 4159 } 4160 4161 static int ib_wq2qp_state(enum ib_wq_state state) 4162 { 4163 switch (state) { 4164 case IB_WQS_RESET: 4165 return IB_QPS_RESET; 4166 case IB_WQS_RDY: 4167 return IB_QPS_RTR; 4168 default: 4169 return IB_QPS_ERR; 4170 } 4171 } 4172 4173 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state, 4174 struct ib_udata *udata) 4175 { 4176 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4177 enum ib_qp_state qp_cur_state; 4178 enum ib_qp_state qp_new_state; 4179 int attr_mask; 4180 int err; 4181 4182 /* ib_qp.state represents the WQ HW state while ib_wq.state represents 4183 * the WQ logic state. 4184 */ 4185 qp_cur_state = qp->state; 4186 qp_new_state = ib_wq2qp_state(new_state); 4187 4188 if (ib_wq2qp_state(new_state) == qp_cur_state) 4189 return 0; 4190 4191 if (new_state == IB_WQS_RDY) { 4192 struct ib_qp_attr attr = {}; 4193 4194 attr.port_num = qp->port; 4195 attr_mask = IB_QP_PORT; 4196 4197 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr, 4198 attr_mask, IB_QPS_RESET, IB_QPS_INIT, 4199 udata); 4200 if (err) { 4201 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n", 4202 ibwq->wq_num); 4203 return err; 4204 } 4205 4206 qp_cur_state = IB_QPS_INIT; 4207 } 4208 4209 attr_mask = 0; 4210 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask, 4211 qp_cur_state, qp_new_state, udata); 4212 4213 if (err && (qp_cur_state == IB_QPS_INIT)) { 4214 qp_new_state = IB_QPS_RESET; 4215 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, 4216 attr_mask, IB_QPS_INIT, IB_QPS_RESET, 4217 udata)) { 4218 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n", 4219 ibwq->wq_num); 4220 qp_new_state = IB_QPS_INIT; 4221 } 4222 } 4223 4224 qp->state = qp_new_state; 4225 4226 return err; 4227 } 4228 4229 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr, 4230 u32 wq_attr_mask, struct ib_udata *udata) 4231 { 4232 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4233 struct mlx4_ib_modify_wq ucmd; 4234 enum ib_wq_state cur_state, new_state; 4235 int err; 4236 4237 err = ib_copy_validate_udata_in_cm(udata, ucmd, reserved, 0); 4238 if (err) 4239 return err; 4240 4241 if (ucmd.reserved) 4242 return -EOPNOTSUPP; 4243 4244 if (wq_attr_mask & IB_WQ_FLAGS) 4245 return -EOPNOTSUPP; 4246 4247 cur_state = wq_attr->curr_wq_state; 4248 new_state = wq_attr->wq_state; 4249 4250 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR)) 4251 return -EINVAL; 4252 4253 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET)) 4254 return -EINVAL; 4255 4256 /* Need to protect against the parent RSS which also may modify WQ 4257 * state. 4258 */ 4259 mutex_lock(&qp->mutex); 4260 4261 /* Can update HW state only if a RSS QP has already associated to this 4262 * WQ, so we can apply its port on the WQ. 4263 */ 4264 if (qp->rss_usecnt) 4265 err = _mlx4_ib_modify_wq(ibwq, new_state, udata); 4266 4267 if (!err) 4268 ibwq->state = new_state; 4269 4270 mutex_unlock(&qp->mutex); 4271 4272 return err; 4273 } 4274 4275 int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata) 4276 { 4277 struct mlx4_ib_dev *dev = to_mdev(ibwq->device); 4278 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq); 4279 4280 if (qp->counter_index) 4281 mlx4_ib_free_qp_counter(dev, qp); 4282 4283 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata); 4284 4285 kfree(qp); 4286 return 0; 4287 } 4288 4289 int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table, 4290 struct ib_rwq_ind_table_init_attr *init_attr, 4291 struct ib_udata *udata) 4292 { 4293 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {}; 4294 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size; 4295 struct ib_device *device = rwq_ind_table->device; 4296 unsigned int base_wqn; 4297 size_t min_resp_len; 4298 int i, err = 0; 4299 4300 if (udata->inlen > 0 && 4301 !ib_is_udata_cleared(udata, 0, 4302 udata->inlen)) 4303 return -EOPNOTSUPP; 4304 4305 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4306 if (udata->outlen && udata->outlen < min_resp_len) 4307 return -EINVAL; 4308 4309 if (ind_tbl_size > 4310 device->attrs.rss_caps.max_rwq_indirection_table_size) { 4311 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n", 4312 ind_tbl_size, 4313 device->attrs.rss_caps.max_rwq_indirection_table_size); 4314 return -EINVAL; 4315 } 4316 4317 base_wqn = init_attr->ind_tbl[0]->wq_num; 4318 4319 if (base_wqn % ind_tbl_size) { 4320 pr_debug("WQN=0x%x isn't aligned with indirection table size\n", 4321 base_wqn); 4322 return -EINVAL; 4323 } 4324 4325 for (i = 1; i < ind_tbl_size; i++) { 4326 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) { 4327 pr_debug("indirection table's WQNs aren't consecutive\n"); 4328 return -EINVAL; 4329 } 4330 } 4331 4332 if (udata->outlen) { 4333 resp.response_length = offsetof(typeof(resp), response_length) + 4334 sizeof(resp.response_length); 4335 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4336 } 4337 4338 return err; 4339 } 4340 4341 struct mlx4_ib_drain_cqe { 4342 struct ib_cqe cqe; 4343 struct completion done; 4344 }; 4345 4346 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 4347 { 4348 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe, 4349 struct mlx4_ib_drain_cqe, 4350 cqe); 4351 4352 complete(&cqe->done); 4353 } 4354 4355 /* This function returns only once the drained WR was completed */ 4356 static void handle_drain_completion(struct ib_cq *cq, 4357 struct mlx4_ib_drain_cqe *sdrain, 4358 struct mlx4_ib_dev *dev) 4359 { 4360 struct mlx4_dev *mdev = dev->dev; 4361 4362 if (cq->poll_ctx == IB_POLL_DIRECT) { 4363 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) 4364 ib_process_cq_direct(cq, -1); 4365 return; 4366 } 4367 4368 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4369 struct mlx4_ib_cq *mcq = to_mcq(cq); 4370 bool triggered = false; 4371 unsigned long flags; 4372 4373 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 4374 /* Make sure that the CQ handler won't run if wasn't run yet */ 4375 if (!mcq->mcq.reset_notify_added) 4376 mcq->mcq.reset_notify_added = 1; 4377 else 4378 triggered = true; 4379 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 4380 4381 if (triggered) { 4382 /* Wait for any scheduled/running task to be ended */ 4383 switch (cq->poll_ctx) { 4384 case IB_POLL_SOFTIRQ: 4385 irq_poll_disable(&cq->iop); 4386 irq_poll_enable(&cq->iop); 4387 break; 4388 case IB_POLL_WORKQUEUE: 4389 cancel_work_sync(&cq->work); 4390 break; 4391 default: 4392 WARN_ON_ONCE(1); 4393 } 4394 } 4395 4396 /* Run the CQ handler - this makes sure that the drain WR will 4397 * be processed if wasn't processed yet. 4398 */ 4399 mcq->mcq.comp(&mcq->mcq); 4400 } 4401 4402 wait_for_completion(&sdrain->done); 4403 } 4404 4405 void mlx4_ib_drain_sq(struct ib_qp *qp) 4406 { 4407 struct ib_cq *cq = qp->send_cq; 4408 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4409 struct mlx4_ib_drain_cqe sdrain; 4410 const struct ib_send_wr *bad_swr; 4411 struct ib_rdma_wr swr = { 4412 .wr = { 4413 .next = NULL, 4414 { .wr_cqe = &sdrain.cqe, }, 4415 .opcode = IB_WR_RDMA_WRITE, 4416 }, 4417 }; 4418 int ret; 4419 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4420 struct mlx4_dev *mdev = dev->dev; 4421 4422 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4423 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4424 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4425 return; 4426 } 4427 4428 sdrain.cqe.done = mlx4_ib_drain_qp_done; 4429 init_completion(&sdrain.done); 4430 4431 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true); 4432 if (ret) { 4433 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); 4434 return; 4435 } 4436 4437 handle_drain_completion(cq, &sdrain, dev); 4438 } 4439 4440 void mlx4_ib_drain_rq(struct ib_qp *qp) 4441 { 4442 struct ib_cq *cq = qp->recv_cq; 4443 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 4444 struct mlx4_ib_drain_cqe rdrain; 4445 struct ib_recv_wr rwr = {}; 4446 const struct ib_recv_wr *bad_rwr; 4447 int ret; 4448 struct mlx4_ib_dev *dev = to_mdev(qp->device); 4449 struct mlx4_dev *mdev = dev->dev; 4450 4451 ret = ib_modify_qp(qp, &attr, IB_QP_STATE); 4452 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) { 4453 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4454 return; 4455 } 4456 4457 rwr.wr_cqe = &rdrain.cqe; 4458 rdrain.cqe.done = mlx4_ib_drain_qp_done; 4459 init_completion(&rdrain.done); 4460 4461 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true); 4462 if (ret) { 4463 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); 4464 return; 4465 } 4466 4467 handle_drain_completion(cq, &rdrain, dev); 4468 } 4469 4470 int mlx4_ib_qp_event_init(void) 4471 { 4472 mlx4_ib_qp_event_wq = alloc_ordered_workqueue("mlx4_ib_qp_event_wq", 0); 4473 if (!mlx4_ib_qp_event_wq) 4474 return -ENOMEM; 4475 4476 return 0; 4477 } 4478 4479 void mlx4_ib_qp_event_cleanup(void) 4480 { 4481 destroy_workqueue(mlx4_ib_qp_event_wq); 4482 } 4483