1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 4 * 5 * Multi-channel Audio Serial Port Driver 6 * 7 * Author: Nirmal Pandey <n-pandey@ti.com>, 8 * Suresh Rajashekara <suresh.r@ti.com> 9 * Steve Chen <schen@.mvista.com> 10 * 11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright: (C) 2009 Texas Instruments, India 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/of_graph.h> 25 #include <linux/platform_data/davinci_asp.h> 26 #include <linux/math64.h> 27 #include <linux/bitmap.h> 28 #include <linux/gpio/driver.h> 29 #include <linux/property.h> 30 31 #include <sound/asoundef.h> 32 #include <sound/core.h> 33 #include <sound/pcm.h> 34 #include <sound/pcm_params.h> 35 #include <sound/initval.h> 36 #include <sound/soc.h> 37 #include <sound/dmaengine_pcm.h> 38 39 #include "edma-pcm.h" 40 #include "sdma-pcm.h" 41 #include "udma-pcm.h" 42 #include "davinci-mcasp.h" 43 44 #define MCASP_MAX_AFIFO_DEPTH 64 45 46 #ifdef CONFIG_PM 47 static u32 context_regs[] = { 48 DAVINCI_MCASP_TXFMCTL_REG, 49 DAVINCI_MCASP_RXFMCTL_REG, 50 DAVINCI_MCASP_TXFMT_REG, 51 DAVINCI_MCASP_RXFMT_REG, 52 DAVINCI_MCASP_ACLKXCTL_REG, 53 DAVINCI_MCASP_ACLKRCTL_REG, 54 DAVINCI_MCASP_AHCLKXCTL_REG, 55 DAVINCI_MCASP_AHCLKRCTL_REG, 56 DAVINCI_MCASP_PDIR_REG, 57 DAVINCI_MCASP_PFUNC_REG, 58 DAVINCI_MCASP_RXMASK_REG, 59 DAVINCI_MCASP_TXMASK_REG, 60 DAVINCI_MCASP_RXTDM_REG, 61 DAVINCI_MCASP_TXTDM_REG, 62 }; 63 64 struct davinci_mcasp_context { 65 u32 config_regs[ARRAY_SIZE(context_regs)]; 66 u32 afifo_regs[2]; /* for read/write fifo control registers */ 67 u32 *xrsr_regs; /* for serializer configuration */ 68 bool pm_state; 69 }; 70 #endif 71 72 struct davinci_mcasp_ruledata { 73 struct davinci_mcasp *mcasp; 74 int serializers; 75 int stream; 76 }; 77 78 enum mcasp_graph_mode { 79 MCASP_GRAPH_NONE, /* 1:1, simple-audio-card, no of-graph endpoints */ 80 MCASP_GRAPH_PORT, /* 1:1, audio-graph-card: port { endpoint } */ 81 MCASP_GRAPH_PORTS, /* 1:N, audio-graph-card2 non-DPCM: ports { port@0; ... } */ 82 MCASP_GRAPH_DPCM, /* N:M, audio-graph-card2 DPCM: N FE DAIs, detected via */ 83 /* remote "dpcm" node in the sound card DT */ 84 }; 85 86 struct davinci_mcasp { 87 struct snd_dmaengine_dai_dma_data dma_data[2]; 88 struct davinci_mcasp_pdata *pdata; 89 void __iomem *base; 90 u32 fifo_base; 91 struct device *dev; 92 struct snd_pcm_substream *substreams[2]; 93 unsigned int dai_fmt; 94 95 u32 iec958_status; 96 97 /* Audio can not be enabled due to missing parameter(s) */ 98 bool missing_audio_param; 99 100 /* McASP specific data */ 101 int tdm_slots_tx; 102 int tdm_slots_rx; 103 u32 tdm_mask[2]; 104 int slot_width_tx; 105 int slot_width_rx; 106 u8 op_mode; 107 u8 dismod; 108 u8 num_serializer; 109 u8 *serial_dir; 110 u8 version; 111 u8 bclk_div_tx; 112 u8 bclk_div_rx; 113 int streams; 114 u32 irq_request[2]; 115 116 unsigned int sysclk_freq_tx; 117 unsigned int sysclk_freq_rx; 118 bool bclk_master; 119 bool async_mode; 120 u32 auxclk_fs_ratio_tx; 121 u32 auxclk_fs_ratio_rx; 122 123 unsigned long pdir; /* Pin direction bitfield */ 124 125 /* McASP FIFO related */ 126 u8 txnumevt; 127 u8 rxnumevt; 128 129 bool dat_port; 130 131 /* Used for comstraint setting on the second stream */ 132 u32 channels; 133 int max_format_width; 134 u8 active_serializers[2]; 135 136 /* Audio graph support */ 137 enum mcasp_graph_mode graph_mode; 138 int num_dais; 139 140 #ifdef CONFIG_GPIOLIB 141 struct gpio_chip gpio_chip; 142 #endif 143 144 #ifdef CONFIG_PM 145 struct davinci_mcasp_context context; 146 #endif 147 148 struct davinci_mcasp_ruledata ruledata[2]; 149 struct snd_pcm_hw_constraint_list chconstr[2]; 150 }; 151 152 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 153 u32 val) 154 { 155 void __iomem *reg = mcasp->base + offset; 156 __raw_writel(__raw_readl(reg) | val, reg); 157 } 158 159 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 160 u32 val) 161 { 162 void __iomem *reg = mcasp->base + offset; 163 __raw_writel((__raw_readl(reg) & ~(val)), reg); 164 } 165 166 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 167 u32 val, u32 mask) 168 { 169 void __iomem *reg = mcasp->base + offset; 170 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 171 } 172 173 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 174 u32 val) 175 { 176 __raw_writel(val, mcasp->base + offset); 177 } 178 179 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 180 { 181 return (u32)__raw_readl(mcasp->base + offset); 182 } 183 184 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 185 { 186 int i = 0; 187 188 mcasp_set_bits(mcasp, ctl_reg, val); 189 190 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 191 /* loop count is to avoid the lock-up */ 192 for (i = 0; i < 1000; i++) { 193 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 194 break; 195 } 196 197 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 198 printk(KERN_ERR "GBLCTL write error\n"); 199 } 200 201 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 202 { 203 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 204 205 return !(aclkxctl & TX_ASYNC); 206 } 207 208 static bool mcasp_is_frame_producer(struct davinci_mcasp *mcasp) 209 { 210 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 211 212 return rxfmctl & AFSRE; 213 } 214 215 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 216 { 217 u32 bit = PIN_BIT_AMUTE; 218 219 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 220 if (enable) 221 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 222 else 223 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 224 } 225 } 226 227 static inline void mcasp_set_clk_pdir_stream(struct davinci_mcasp *mcasp, 228 int stream, bool enable) 229 { 230 u32 bit, bit_end; 231 232 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 233 bit = PIN_BIT_ACLKX; 234 bit_end = PIN_BIT_AFSX + 1; 235 } else { 236 bit = PIN_BIT_ACLKR; 237 bit_end = PIN_BIT_AFSR + 1; 238 } 239 240 for_each_set_bit_from(bit, &mcasp->pdir, bit_end) { 241 if (enable) 242 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 243 else 244 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 245 } 246 } 247 248 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 249 { 250 u32 bit; 251 252 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { 253 if (enable) 254 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 255 else 256 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 257 } 258 } 259 260 static inline int mcasp_get_tdm_slots(struct davinci_mcasp *mcasp, int stream) 261 { 262 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 263 mcasp->tdm_slots_tx : mcasp->tdm_slots_rx; 264 } 265 266 static inline int mcasp_get_slot_width(struct davinci_mcasp *mcasp, int stream) 267 { 268 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 269 mcasp->slot_width_tx : mcasp->slot_width_rx; 270 } 271 272 static inline unsigned int mcasp_get_sysclk_freq(struct davinci_mcasp *mcasp, int stream) 273 { 274 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 275 mcasp->sysclk_freq_tx : mcasp->sysclk_freq_rx; 276 } 277 278 static inline unsigned int mcasp_get_bclk_div(struct davinci_mcasp *mcasp, int stream) 279 { 280 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 281 mcasp->bclk_div_tx : mcasp->bclk_div_rx; 282 } 283 284 static inline unsigned int mcasp_get_auxclk_fs_ratio(struct davinci_mcasp *mcasp, int stream) 285 { 286 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 287 mcasp->auxclk_fs_ratio_tx : mcasp->auxclk_fs_ratio_rx; 288 } 289 290 static inline bool mcasp_is_auxclk_enabled(struct davinci_mcasp *mcasp, int stream) 291 { 292 if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_CAPTURE) 293 return mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG) & AHCLKRE; 294 295 return mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG) & AHCLKXE; 296 } 297 298 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 299 { 300 if (mcasp->rxnumevt) { /* enable FIFO */ 301 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 302 303 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 304 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 305 } 306 307 /* Start clocks */ 308 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 309 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 310 /* 311 * When ASYNC == 0 the transmit and receive sections operate 312 * synchronously from the transmit clock and frame sync. We need to make 313 * sure that the TX signals are enabled when starting reception, 314 * when the McASP is the producer. 315 */ 316 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) { 317 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 318 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 319 } 320 if (mcasp_is_synchronous(mcasp)) 321 mcasp_set_clk_pdir(mcasp, true); 322 else 323 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, true); 324 325 /* Activate serializer(s) */ 326 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 327 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 328 /* Release RX state machine */ 329 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 330 /* Release Frame Sync generator */ 331 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 332 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) 333 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 334 335 /* enable receive IRQs */ 336 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 337 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 338 } 339 340 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 341 { 342 u32 cnt; 343 344 if (mcasp->txnumevt) { /* enable FIFO */ 345 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 346 347 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 348 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 349 } 350 351 /* Start clocks */ 352 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 353 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 354 if (mcasp_is_synchronous(mcasp)) 355 mcasp_set_clk_pdir(mcasp, true); 356 else 357 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, true); 358 359 /* Activate serializer(s) */ 360 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 361 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 362 363 /* wait for XDATA to be cleared */ 364 cnt = 0; 365 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 366 (cnt < 100000)) 367 cnt++; 368 369 mcasp_set_axr_pdir(mcasp, true); 370 371 /* Release TX state machine */ 372 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 373 /* Release Frame Sync generator */ 374 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 375 376 /* enable transmit IRQs */ 377 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 378 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 379 } 380 381 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 382 { 383 mcasp->streams++; 384 385 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 386 mcasp_start_tx(mcasp); 387 else 388 mcasp_start_rx(mcasp); 389 } 390 391 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 392 { 393 /* disable IRQ sources */ 394 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 395 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 396 397 /* 398 * In synchronous mode stop the TX clocks if no other stream is 399 * running 400 * Otherwise in async mode only stop RX clocks 401 */ 402 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) 403 mcasp_set_clk_pdir(mcasp, false); 404 else if (!mcasp_is_synchronous(mcasp)) 405 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, false); 406 /* 407 * When McASP is the producer and operating in synchronous mode, 408 * stop the transmit clocks if no other stream is running. As 409 * tx & rx operate synchronously from the transmit clock. 410 */ 411 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && !mcasp->streams) 412 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 413 414 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 415 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 416 417 if (mcasp->rxnumevt) { /* disable FIFO */ 418 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 419 420 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 421 } 422 } 423 424 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 425 { 426 u32 val = 0; 427 428 /* disable IRQ sources */ 429 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 430 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 431 432 /* 433 * In synchronous mode keep TX clocks running if the capture stream is 434 * still running. 435 * Otherwise in async mode only stop TX clocks 436 */ 437 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && mcasp->streams) 438 val = TXHCLKRST | TXCLKRST | TXFSRST; 439 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) 440 mcasp_set_clk_pdir(mcasp, false); 441 else if (!mcasp_is_synchronous(mcasp)) 442 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, false); 443 444 445 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 446 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 447 448 if (mcasp->txnumevt) { /* disable FIFO */ 449 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 450 451 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 452 } 453 454 mcasp_set_axr_pdir(mcasp, false); 455 } 456 457 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 458 { 459 mcasp->streams--; 460 461 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 462 mcasp_stop_tx(mcasp); 463 else 464 mcasp_stop_rx(mcasp); 465 } 466 467 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 468 { 469 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 470 struct snd_pcm_substream *substream; 471 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 472 u32 handled_mask = 0; 473 u32 stat; 474 475 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 476 if (stat & XUNDRN & irq_mask) { 477 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 478 handled_mask |= XUNDRN; 479 480 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 481 if (substream) 482 snd_pcm_stop_xrun(substream); 483 } 484 485 if (!handled_mask) 486 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 487 stat); 488 489 if (stat & XRERR) 490 handled_mask |= XRERR; 491 492 /* Ack the handled event only */ 493 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 494 495 return IRQ_RETVAL(handled_mask); 496 } 497 498 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 499 { 500 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 501 struct snd_pcm_substream *substream; 502 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 503 u32 handled_mask = 0; 504 u32 stat; 505 506 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 507 if (stat & ROVRN & irq_mask) { 508 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 509 handled_mask |= ROVRN; 510 511 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 512 if (substream) 513 snd_pcm_stop_xrun(substream); 514 } 515 516 if (!handled_mask) 517 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 518 stat); 519 520 if (stat & XRERR) 521 handled_mask |= XRERR; 522 523 /* Ack the handled event only */ 524 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 525 526 return IRQ_RETVAL(handled_mask); 527 } 528 529 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 530 { 531 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 532 irqreturn_t ret = IRQ_NONE; 533 534 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 535 ret = davinci_mcasp_tx_irq_handler(irq, data); 536 537 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 538 ret |= davinci_mcasp_rx_irq_handler(irq, data); 539 540 return ret; 541 } 542 543 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 544 unsigned int fmt) 545 { 546 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 547 int ret = 0; 548 u32 data_delay; 549 bool fs_pol_rising; 550 bool inv_fs = false; 551 552 if (!fmt) 553 return 0; 554 555 pm_runtime_get_sync(mcasp->dev); 556 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 557 case SND_SOC_DAIFMT_DSP_A: 558 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 559 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 560 /* 1st data bit occur one ACLK cycle after the frame sync */ 561 data_delay = 1; 562 break; 563 case SND_SOC_DAIFMT_DSP_B: 564 case SND_SOC_DAIFMT_AC97: 565 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 567 /* No delay after FS */ 568 data_delay = 0; 569 break; 570 case SND_SOC_DAIFMT_I2S: 571 /* configure a full-word SYNC pulse (LRCLK) */ 572 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 573 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 574 /* 1st data bit occur one ACLK cycle after the frame sync */ 575 data_delay = 1; 576 /* FS need to be inverted */ 577 inv_fs = true; 578 break; 579 case SND_SOC_DAIFMT_RIGHT_J: 580 case SND_SOC_DAIFMT_LEFT_J: 581 /* configure a full-word SYNC pulse (LRCLK) */ 582 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 583 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 584 /* No delay after FS */ 585 data_delay = 0; 586 break; 587 default: 588 ret = -EINVAL; 589 goto out; 590 } 591 592 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 593 FSXDLY(3)); 594 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 595 FSRDLY(3)); 596 597 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 598 case SND_SOC_DAIFMT_BP_FP: 599 /* codec is clock and frame slave */ 600 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 601 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 602 603 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 604 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 605 606 /* BCLK */ 607 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 608 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 609 /* Frame Sync */ 610 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 611 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 612 613 mcasp->bclk_master = 1; 614 break; 615 case SND_SOC_DAIFMT_BP_FC: 616 /* codec is clock slave and frame master */ 617 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 618 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 619 620 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 621 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 622 623 /* BCLK */ 624 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 625 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 626 /* Frame Sync */ 627 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 628 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 629 630 mcasp->bclk_master = 1; 631 break; 632 case SND_SOC_DAIFMT_BC_FP: 633 /* codec is clock master and frame slave */ 634 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 635 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 636 637 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 638 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 639 640 /* BCLK */ 641 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 642 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 643 /* Frame Sync */ 644 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 645 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 646 647 mcasp->bclk_master = 0; 648 break; 649 case SND_SOC_DAIFMT_BC_FC: 650 /* codec is clock and frame master */ 651 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 652 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 653 654 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 655 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 656 657 /* BCLK */ 658 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 659 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 660 /* Frame Sync */ 661 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 662 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 663 664 mcasp->bclk_master = 0; 665 break; 666 default: 667 ret = -EINVAL; 668 goto out; 669 } 670 671 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 672 case SND_SOC_DAIFMT_IB_NF: 673 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 674 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 675 fs_pol_rising = true; 676 break; 677 case SND_SOC_DAIFMT_NB_IF: 678 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 679 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 680 fs_pol_rising = false; 681 break; 682 case SND_SOC_DAIFMT_IB_IF: 683 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 684 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 685 fs_pol_rising = false; 686 break; 687 case SND_SOC_DAIFMT_NB_NF: 688 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 689 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 690 fs_pol_rising = true; 691 break; 692 default: 693 ret = -EINVAL; 694 goto out; 695 } 696 697 if (inv_fs) 698 fs_pol_rising = !fs_pol_rising; 699 700 if (fs_pol_rising) { 701 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 702 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 703 } else { 704 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 705 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 706 } 707 708 mcasp->dai_fmt = fmt; 709 out: 710 pm_runtime_put(mcasp->dev); 711 return ret; 712 } 713 714 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 715 int div, bool explicit) 716 { 717 pm_runtime_get_sync(mcasp->dev); 718 switch (div_id) { 719 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 720 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 721 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 722 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 723 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 724 break; 725 726 case MCASP_CLKDIV_AUXCLK_TXONLY: /* MCLK divider for TX only */ 727 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 728 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 729 break; 730 731 case MCASP_CLKDIV_AUXCLK_RXONLY: /* MCLK divider for RX only */ 732 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 733 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 734 break; 735 736 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 737 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 738 ACLKXDIV(div - 1), ACLKXDIV_MASK); 739 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 740 ACLKRDIV(div - 1), ACLKRDIV_MASK); 741 if (explicit) { 742 mcasp->bclk_div_tx = div; 743 mcasp->bclk_div_rx = div; 744 } 745 break; 746 747 case MCASP_CLKDIV_BCLK_TXONLY: /* BCLK divider for TX only */ 748 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 749 ACLKXDIV(div - 1), ACLKXDIV_MASK); 750 if (explicit) 751 mcasp->bclk_div_tx = div; 752 break; 753 754 case MCASP_CLKDIV_BCLK_RXONLY: /* BCLK divider for RX only */ 755 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 756 ACLKRDIV(div - 1), ACLKRDIV_MASK); 757 if (explicit) 758 mcasp->bclk_div_rx = div; 759 break; 760 761 case MCASP_CLKDIV_BCLK_FS_RATIO: 762 /* 763 * BCLK/LRCLK ratio descries how many bit-clock cycles 764 * fit into one frame. The clock ratio is given for a 765 * full period of data (for I2S format both left and 766 * right channels), so it has to be divided by number 767 * of tdm-slots (for I2S - divided by 2). 768 * Instead of storing this ratio, we calculate a new 769 * tdm_slot width by dividing the ratio by the 770 * number of configured tdm slots. 771 */ 772 mcasp->slot_width_tx = div / mcasp->tdm_slots_tx; 773 if (div % mcasp->tdm_slots_tx) 774 dev_warn(mcasp->dev, 775 "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots", 776 __func__, div, mcasp->tdm_slots_tx); 777 778 mcasp->slot_width_rx = div / mcasp->tdm_slots_rx; 779 if (div % mcasp->tdm_slots_rx) 780 dev_warn(mcasp->dev, 781 "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots", 782 __func__, div, mcasp->tdm_slots_rx); 783 break; 784 785 case MCASP_CLKDIV_BCLK_FS_RATIO_TXONLY: 786 mcasp->slot_width_tx = div / mcasp->tdm_slots_tx; 787 if (div % mcasp->tdm_slots_tx) 788 dev_warn(mcasp->dev, 789 "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots", 790 __func__, div, mcasp->tdm_slots_tx); 791 break; 792 793 case MCASP_CLKDIV_BCLK_FS_RATIO_RXONLY: 794 mcasp->slot_width_rx = div / mcasp->tdm_slots_rx; 795 if (div % mcasp->tdm_slots_rx) 796 dev_warn(mcasp->dev, 797 "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots", 798 __func__, div, mcasp->tdm_slots_rx); 799 break; 800 801 default: 802 return -EINVAL; 803 } 804 805 pm_runtime_put(mcasp->dev); 806 return 0; 807 } 808 809 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 810 int div) 811 { 812 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 813 814 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 815 } 816 817 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 818 unsigned int freq, int dir) 819 { 820 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 821 822 pm_runtime_get_sync(mcasp->dev); 823 824 if (dir == SND_SOC_CLOCK_IN) { 825 switch (clk_id) { 826 case MCASP_CLK_HCLK_AHCLK: 827 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 828 AHCLKXE); 829 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 830 AHCLKRE); 831 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 832 mcasp->sysclk_freq_tx = freq; 833 mcasp->sysclk_freq_rx = freq; 834 break; 835 case MCASP_CLK_HCLK_AHCLK_TXONLY: 836 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 837 AHCLKXE); 838 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 839 mcasp->sysclk_freq_tx = freq; 840 break; 841 case MCASP_CLK_HCLK_AHCLK_RXONLY: 842 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 843 AHCLKRE); 844 clear_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 845 mcasp->sysclk_freq_rx = freq; 846 break; 847 case MCASP_CLK_HCLK_AUXCLK: 848 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 849 AHCLKXE); 850 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 851 AHCLKRE); 852 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 853 mcasp->sysclk_freq_tx = freq; 854 mcasp->sysclk_freq_rx = freq; 855 break; 856 case MCASP_CLK_HCLK_AUXCLK_TXONLY: 857 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 858 AHCLKXE); 859 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 860 mcasp->sysclk_freq_tx = freq; 861 break; 862 case MCASP_CLK_HCLK_AUXCLK_RXONLY: 863 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 864 AHCLKRE); 865 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 866 mcasp->sysclk_freq_rx = freq; 867 break; 868 default: 869 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); 870 goto out; 871 } 872 } else { 873 /* McASP is clock master, select AUXCLK as HCLK */ 874 switch (clk_id) { 875 case MCASP_CLK_HCLK_AUXCLK_TXONLY: 876 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 877 AHCLKXE); 878 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 879 mcasp->sysclk_freq_tx = freq; 880 break; 881 case MCASP_CLK_HCLK_AUXCLK_RXONLY: 882 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 883 AHCLKRE); 884 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 885 mcasp->sysclk_freq_rx = freq; 886 break; 887 default: 888 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 889 AHCLKXE); 890 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 891 AHCLKRE); 892 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 893 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 894 mcasp->sysclk_freq_tx = freq; 895 mcasp->sysclk_freq_rx = freq; 896 break; 897 } 898 } 899 /* 900 * When AHCLK X/R is selected to be output it means that the HCLK is 901 * the same clock - coming via AUXCLK. 902 */ 903 out: 904 pm_runtime_put(mcasp->dev); 905 return 0; 906 } 907 908 /* All serializers must have equal number of channels */ 909 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 910 int serializers) 911 { 912 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 913 unsigned int *list = (unsigned int *) cl->list; 914 int slots; 915 int i, count = 0; 916 917 slots = mcasp_get_tdm_slots(mcasp, stream); 918 919 if (mcasp->tdm_mask[stream]) 920 slots = hweight32(mcasp->tdm_mask[stream]); 921 922 for (i = 1; i <= slots; i++) 923 list[count++] = i; 924 925 for (i = 2; i <= serializers; i++) 926 list[count++] = i*slots; 927 928 cl->count = count; 929 930 return 0; 931 } 932 933 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 934 { 935 int rx_serializers = 0, tx_serializers = 0, ret, i; 936 937 for (i = 0; i < mcasp->num_serializer; i++) 938 if (mcasp->serial_dir[i] == TX_MODE) 939 tx_serializers++; 940 else if (mcasp->serial_dir[i] == RX_MODE) 941 rx_serializers++; 942 943 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 944 tx_serializers); 945 if (ret) 946 return ret; 947 948 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 949 rx_serializers); 950 951 return ret; 952 } 953 954 955 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 956 unsigned int tx_mask, 957 unsigned int rx_mask, 958 int slots, int slot_width) 959 { 960 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 961 962 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 963 return 0; 964 965 dev_dbg(mcasp->dev, 966 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 967 __func__, tx_mask, rx_mask, slots, slot_width); 968 969 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 970 dev_err(mcasp->dev, 971 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 972 tx_mask, rx_mask, slots); 973 return -EINVAL; 974 } 975 976 if (slot_width && 977 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 978 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 979 __func__, slot_width); 980 return -EINVAL; 981 } 982 983 if (mcasp->async_mode) { 984 if (tx_mask) { 985 mcasp->tdm_slots_tx = slots; 986 mcasp->slot_width_tx = slot_width; 987 } 988 if (rx_mask) { 989 mcasp->tdm_slots_rx = slots; 990 mcasp->slot_width_rx = slot_width; 991 } 992 } else { 993 mcasp->tdm_slots_tx = slots; 994 mcasp->tdm_slots_rx = slots; 995 mcasp->slot_width_tx = slot_width; 996 mcasp->slot_width_rx = slot_width; 997 } 998 999 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 1000 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 1001 1002 return davinci_mcasp_set_ch_constraints(mcasp); 1003 } 1004 1005 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 1006 int sample_width, int stream) 1007 { 1008 u32 fmt; 1009 u32 tx_rotate, rx_rotate, slot_width; 1010 u32 mask = (1ULL << sample_width) - 1; 1011 1012 slot_width = mcasp_get_slot_width(mcasp, stream); 1013 if (!slot_width) { 1014 if (mcasp->max_format_width) 1015 slot_width = mcasp->max_format_width; 1016 else 1017 slot_width = sample_width; 1018 } 1019 /* 1020 * TX rotation: 1021 * right aligned formats: rotate w/ slot_width 1022 * left aligned formats: rotate w/ sample_width 1023 * 1024 * RX rotation: 1025 * right aligned formats: no rotation needed 1026 * left aligned formats: rotate w/ (slot_width - sample_width) 1027 */ 1028 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 1029 SND_SOC_DAIFMT_RIGHT_J) { 1030 tx_rotate = (slot_width / 4) & 0x7; 1031 rx_rotate = 0; 1032 } else { 1033 tx_rotate = (sample_width / 4) & 0x7; 1034 rx_rotate = (slot_width - sample_width) / 4; 1035 } 1036 1037 /* mapping of the XSSZ bit-field as described in the datasheet */ 1038 fmt = (slot_width >> 1) - 1; 1039 1040 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 1041 if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_PLAYBACK) { 1042 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 1043 TXSSZ(0x0F)); 1044 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 1045 TXROT(7)); 1046 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 1047 } 1048 if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_CAPTURE) { 1049 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 1050 RXSSZ(0x0F)); 1051 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 1052 RXROT(7)); 1053 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 1054 } 1055 } else { 1056 /* 1057 * DIT mode only use TX serializers 1058 * according to the TRM it should be TXROT=0, this one works: 1059 * 16 bit to 23-8 (TXROT=6, rotate 24 bits) 1060 * 24 bit to 23-0 (TXROT=0, rotate 0 bits) 1061 * 1062 * TXROT = 0 only works with 24bit samples 1063 */ 1064 tx_rotate = (sample_width / 4 + 2) & 0x7; 1065 1066 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 1067 TXROT(7)); 1068 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15), 1069 TXSSZ(0x0F)); 1070 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 1077 int period_words, int channels) 1078 { 1079 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 1080 int i; 1081 u8 tx_ser = 0; 1082 u8 rx_ser = 0; 1083 int slots; 1084 u8 max_active_serializers, max_rx_serializers, max_tx_serializers; 1085 int active_serializers, numevt; 1086 u32 reg; 1087 1088 slots = mcasp_get_tdm_slots(mcasp, stream); 1089 1090 /* In DIT mode we only allow maximum of one serializers for now */ 1091 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1092 max_active_serializers = 1; 1093 else 1094 max_active_serializers = DIV_ROUND_UP(channels, slots); 1095 1096 /* Default configuration */ 1097 if (mcasp->version < MCASP_VERSION_3) 1098 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 1099 1100 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1101 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 1102 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1103 max_tx_serializers = max_active_serializers; 1104 max_rx_serializers = 1105 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; 1106 } else { 1107 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 1108 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 1109 max_tx_serializers = 1110 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; 1111 max_rx_serializers = max_active_serializers; 1112 } 1113 1114 for (i = 0; i < mcasp->num_serializer; i++) { 1115 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1116 mcasp->serial_dir[i]); 1117 if (mcasp->serial_dir[i] == TX_MODE && 1118 tx_ser < max_tx_serializers) { 1119 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1120 mcasp->dismod, DISMOD_MASK); 1121 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1122 tx_ser++; 1123 } else if (mcasp->serial_dir[i] == RX_MODE && 1124 rx_ser < max_rx_serializers) { 1125 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1126 rx_ser++; 1127 } else { 1128 /* Inactive or unused pin, set it to inactive */ 1129 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1130 SRMOD_INACTIVE, SRMOD_MASK); 1131 /* If unused, set DISMOD for the pin */ 1132 if (mcasp->serial_dir[i] != INACTIVE_MODE) 1133 mcasp_mod_bits(mcasp, 1134 DAVINCI_MCASP_XRSRCTL_REG(i), 1135 mcasp->dismod, DISMOD_MASK); 1136 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1137 } 1138 } 1139 1140 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1141 active_serializers = tx_ser; 1142 numevt = mcasp->txnumevt; 1143 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 1144 } else { 1145 active_serializers = rx_ser; 1146 numevt = mcasp->rxnumevt; 1147 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 1148 } 1149 1150 if (active_serializers < max_active_serializers) { 1151 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 1152 "enabled in mcasp (%d)\n", channels, 1153 active_serializers * slots); 1154 return -EINVAL; 1155 } 1156 1157 /* AFIFO is not in use */ 1158 if (!numevt) { 1159 /* Configure the burst size for platform drivers */ 1160 if (active_serializers > 1) { 1161 /* 1162 * If more than one serializers are in use we have one 1163 * DMA request to provide data for all serializers. 1164 * For example if three serializers are enabled the DMA 1165 * need to transfer three words per DMA request. 1166 */ 1167 dma_data->maxburst = active_serializers; 1168 } else { 1169 dma_data->maxburst = 0; 1170 } 1171 1172 goto out; 1173 } 1174 1175 if (period_words % active_serializers) { 1176 dev_err(mcasp->dev, "Invalid combination of period words and " 1177 "active serializers: %d, %d\n", period_words, 1178 active_serializers); 1179 return -EINVAL; 1180 } 1181 1182 /* 1183 * Calculate the optimal AFIFO depth for platform side: 1184 * The number of words for numevt need to be in steps of active 1185 * serializers. 1186 */ 1187 numevt = (numevt / active_serializers) * active_serializers; 1188 1189 while (period_words % numevt && numevt > 0) 1190 numevt -= active_serializers; 1191 if (numevt <= 0) 1192 numevt = active_serializers; 1193 1194 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 1195 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 1196 1197 /* Configure the burst size for platform drivers */ 1198 if (numevt == 1) 1199 numevt = 0; 1200 dma_data->maxburst = numevt; 1201 1202 out: 1203 mcasp->active_serializers[stream] = active_serializers; 1204 1205 return 0; 1206 } 1207 1208 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 1209 int channels) 1210 { 1211 int i, active_slots; 1212 int total_slots; 1213 int active_serializers; 1214 u32 mask = 0; 1215 u32 busel = 0; 1216 1217 total_slots = mcasp_get_tdm_slots(mcasp, stream); 1218 1219 /* 1220 * If more than one serializer is needed, then use them with 1221 * all the specified tdm_slots. Otherwise, one serializer can 1222 * cope with the transaction using just as many slots as there 1223 * are channels in the stream. 1224 */ 1225 if (mcasp->tdm_mask[stream]) { 1226 active_slots = hweight32(mcasp->tdm_mask[stream]); 1227 active_serializers = DIV_ROUND_UP(channels, active_slots); 1228 if (active_serializers == 1) 1229 active_slots = channels; 1230 for (i = 0; i < total_slots; i++) { 1231 if ((1 << i) & mcasp->tdm_mask[stream]) { 1232 mask |= (1 << i); 1233 if (--active_slots <= 0) 1234 break; 1235 } 1236 } 1237 } else { 1238 active_serializers = DIV_ROUND_UP(channels, total_slots); 1239 if (active_serializers == 1) 1240 active_slots = channels; 1241 else 1242 active_slots = total_slots; 1243 1244 for (i = 0; i < active_slots; i++) 1245 mask |= (1 << i); 1246 } 1247 1248 if (mcasp->async_mode) 1249 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1250 else 1251 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1252 1253 if (!mcasp->dat_port) 1254 busel = TXSEL; 1255 1256 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1257 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 1258 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 1259 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1260 FSXMOD(total_slots), FSXMOD(0x1FF)); 1261 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 1262 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 1263 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 1264 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 1265 FSRMOD(total_slots), FSRMOD(0x1FF)); 1266 /* 1267 * If McASP is set to be TX/RX synchronous and the playback is 1268 * not running already we need to configure the TX slots in 1269 * order to have correct FSX on the bus 1270 */ 1271 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && 1272 !mcasp->channels) 1273 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1274 FSXMOD(total_slots), FSXMOD(0x1FF)); 1275 } 1276 1277 return 0; 1278 } 1279 1280 /* S/PDIF */ 1281 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 1282 unsigned int rate) 1283 { 1284 u8 *cs_bytes = (u8 *)&mcasp->iec958_status; 1285 1286 if (!mcasp->dat_port) 1287 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1288 else 1289 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1290 1291 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1292 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1293 1294 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF); 1295 1296 /* Set the TX tdm : for all the slots */ 1297 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1298 1299 /* Set the TX clock controls : div = 1 and internal */ 1300 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1301 1302 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1303 1304 /* Set S/PDIF channel status bits */ 1305 cs_bytes[3] &= ~IEC958_AES3_CON_FS; 1306 switch (rate) { 1307 case 22050: 1308 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1309 break; 1310 case 24000: 1311 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1312 break; 1313 case 32000: 1314 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1315 break; 1316 case 44100: 1317 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1318 break; 1319 case 48000: 1320 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1321 break; 1322 case 88200: 1323 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1324 break; 1325 case 96000: 1326 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1327 break; 1328 case 176400: 1329 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1330 break; 1331 case 192000: 1332 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1333 break; 1334 default: 1335 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate); 1336 return -EINVAL; 1337 } 1338 1339 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status); 1340 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status); 1341 1342 /* Enable the DIT */ 1343 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1344 1345 return 0; 1346 } 1347 1348 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1349 unsigned int sysclk_freq, 1350 unsigned int bclk_freq, 1351 int stream, 1352 bool set) 1353 { 1354 int div = sysclk_freq / bclk_freq; 1355 int rem = sysclk_freq % bclk_freq; 1356 int error_ppm; 1357 int aux_div = 1; 1358 int bclk_div_id, auxclk_div_id; 1359 bool auxclk_enabled; 1360 1361 auxclk_enabled = mcasp_is_auxclk_enabled(mcasp, stream); 1362 1363 if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_CAPTURE) { 1364 bclk_div_id = MCASP_CLKDIV_BCLK_RXONLY; 1365 auxclk_div_id = MCASP_CLKDIV_AUXCLK_RXONLY; 1366 } else if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_PLAYBACK) { 1367 bclk_div_id = MCASP_CLKDIV_BCLK_TXONLY; 1368 auxclk_div_id = MCASP_CLKDIV_AUXCLK_TXONLY; 1369 } else { 1370 bclk_div_id = MCASP_CLKDIV_BCLK; 1371 auxclk_div_id = MCASP_CLKDIV_AUXCLK; 1372 } 1373 1374 if (div > (ACLKXDIV_MASK + 1) && auxclk_enabled) { 1375 if (div <= (AHCLKXDIV_MASK + 1)) { 1376 /* aux_div absorbs entire division; bclk_div = 1 */ 1377 aux_div = div; 1378 if ((div + 1) <= (AHCLKXDIV_MASK + 1)) { 1379 unsigned int err_lo = sysclk_freq / div - 1380 bclk_freq; 1381 unsigned int err_hi = bclk_freq - 1382 sysclk_freq / (div + 1); 1383 1384 if (err_hi < err_lo) 1385 aux_div = div + 1; 1386 } 1387 } else { 1388 aux_div = DIV_ROUND_UP(div, ACLKXDIV_MASK + 1); 1389 } 1390 1391 sysclk_freq /= aux_div; 1392 div = sysclk_freq / bclk_freq; 1393 rem = sysclk_freq % bclk_freq; 1394 } else if (div > (ACLKXDIV_MASK + 1) && set) { 1395 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1396 sysclk_freq); 1397 } 1398 1399 if (rem != 0) { 1400 if (div == 0 || 1401 ((sysclk_freq / div) - bclk_freq) > 1402 (bclk_freq - (sysclk_freq / (div+1)))) { 1403 div++; 1404 rem = rem - bclk_freq; 1405 } 1406 } 1407 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1408 (int)bclk_freq)) / div - 1000000; 1409 1410 if (set) { 1411 if (error_ppm) 1412 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1413 error_ppm); 1414 1415 __davinci_mcasp_set_clkdiv(mcasp, bclk_div_id, div, false); 1416 if (auxclk_enabled) 1417 __davinci_mcasp_set_clkdiv(mcasp, auxclk_div_id, 1418 aux_div, false); 1419 } 1420 1421 return error_ppm; 1422 } 1423 1424 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1425 { 1426 if (!mcasp->txnumevt) 1427 return 0; 1428 1429 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1430 } 1431 1432 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1433 { 1434 if (!mcasp->rxnumevt) 1435 return 0; 1436 1437 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1438 } 1439 1440 static snd_pcm_sframes_t davinci_mcasp_delay( 1441 struct snd_pcm_substream *substream, 1442 struct snd_soc_dai *cpu_dai) 1443 { 1444 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1445 u32 fifo_use; 1446 1447 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1448 fifo_use = davinci_mcasp_tx_delay(mcasp); 1449 else 1450 fifo_use = davinci_mcasp_rx_delay(mcasp); 1451 1452 /* 1453 * Divide the used locations with the channel count to get the 1454 * FIFO usage in samples (don't care about partial samples in the 1455 * buffer). 1456 */ 1457 return fifo_use / substream->runtime->channels; 1458 } 1459 1460 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1461 struct snd_pcm_hw_params *params, 1462 struct snd_soc_dai *cpu_dai) 1463 { 1464 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1465 int word_length; 1466 int channels = params_channels(params); 1467 int period_size = params_period_size(params); 1468 int ret; 1469 unsigned int sysclk_freq = mcasp_get_sysclk_freq(mcasp, substream->stream); 1470 1471 switch (params_format(params)) { 1472 case SNDRV_PCM_FORMAT_U8: 1473 case SNDRV_PCM_FORMAT_S8: 1474 word_length = 8; 1475 break; 1476 1477 case SNDRV_PCM_FORMAT_U16_LE: 1478 case SNDRV_PCM_FORMAT_S16_LE: 1479 word_length = 16; 1480 break; 1481 1482 case SNDRV_PCM_FORMAT_U24_3LE: 1483 case SNDRV_PCM_FORMAT_S24_3LE: 1484 word_length = 24; 1485 break; 1486 1487 case SNDRV_PCM_FORMAT_U24_LE: 1488 case SNDRV_PCM_FORMAT_S24_LE: 1489 word_length = 24; 1490 break; 1491 1492 case SNDRV_PCM_FORMAT_U32_LE: 1493 case SNDRV_PCM_FORMAT_S32_LE: 1494 word_length = 32; 1495 break; 1496 1497 default: 1498 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1499 return -EINVAL; 1500 } 1501 1502 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1503 unsigned int cpu_fmt; 1504 1505 if (mcasp->graph_mode != MCASP_GRAPH_NONE && rtd->dai_link->dai_fmt) 1506 /* clock provider bits stored separately in ext_fmt */ 1507 cpu_fmt = snd_soc_daifmt_clock_provider_flipped( 1508 rtd->dai_link->dai_fmt) | 1509 rtd->dai_link->cpus[0].ext_fmt; 1510 else 1511 cpu_fmt = mcasp->dai_fmt; 1512 1513 ret = davinci_mcasp_set_dai_fmt(cpu_dai, cpu_fmt); 1514 if (ret) 1515 return ret; 1516 1517 /* 1518 * If mcasp is BCLK master, and a BCLK divider was not provided by 1519 * the machine driver, we need to calculate the ratio. 1520 */ 1521 if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 && 1522 sysclk_freq) { 1523 int slots, slot_width; 1524 int rate = params_rate(params); 1525 int sbits = params_width(params); 1526 unsigned int bclk_target; 1527 1528 slots = mcasp_get_tdm_slots(mcasp, substream->stream); 1529 1530 slot_width = mcasp_get_slot_width(mcasp, substream->stream); 1531 if (slot_width) 1532 sbits = slot_width; 1533 1534 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1535 bclk_target = rate * sbits * slots; 1536 else 1537 bclk_target = rate * 128; 1538 1539 davinci_mcasp_calc_clk_div(mcasp, sysclk_freq, 1540 bclk_target, substream->stream, true); 1541 } 1542 1543 ret = mcasp_common_hw_param(mcasp, substream->stream, 1544 period_size * channels, channels); 1545 if (ret) 1546 return ret; 1547 1548 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1549 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1550 else 1551 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1552 channels); 1553 1554 if (ret) 1555 return ret; 1556 1557 davinci_config_channel_size(mcasp, word_length, substream->stream); 1558 1559 /* Channel constraints are disabled for async mode */ 1560 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE && !mcasp->async_mode) { 1561 mcasp->channels = channels; 1562 if (!mcasp->max_format_width) 1563 mcasp->max_format_width = word_length; 1564 } 1565 1566 return 0; 1567 } 1568 1569 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1570 int cmd, struct snd_soc_dai *cpu_dai) 1571 { 1572 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1573 int ret = 0; 1574 1575 switch (cmd) { 1576 case SNDRV_PCM_TRIGGER_RESUME: 1577 case SNDRV_PCM_TRIGGER_START: 1578 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1579 davinci_mcasp_start(mcasp, substream->stream); 1580 break; 1581 case SNDRV_PCM_TRIGGER_SUSPEND: 1582 case SNDRV_PCM_TRIGGER_STOP: 1583 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1584 davinci_mcasp_stop(mcasp, substream->stream); 1585 break; 1586 1587 default: 1588 ret = -EINVAL; 1589 } 1590 1591 return ret; 1592 } 1593 1594 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params, 1595 struct snd_pcm_hw_rule *rule) 1596 { 1597 struct davinci_mcasp_ruledata *rd = rule->private; 1598 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1599 struct snd_mask nfmt; 1600 int slot_width; 1601 snd_pcm_format_t i; 1602 1603 snd_mask_none(&nfmt); 1604 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1605 1606 pcm_for_each_format(i) { 1607 if (snd_mask_test_format(fmt, i)) { 1608 if (snd_pcm_format_width(i) <= slot_width) { 1609 snd_mask_set_format(&nfmt, i); 1610 } 1611 } 1612 } 1613 1614 return snd_mask_refine(fmt, &nfmt); 1615 } 1616 1617 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params, 1618 struct snd_pcm_hw_rule *rule) 1619 { 1620 struct davinci_mcasp_ruledata *rd = rule->private; 1621 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1622 struct snd_mask nfmt; 1623 int format_width; 1624 snd_pcm_format_t i; 1625 1626 snd_mask_none(&nfmt); 1627 format_width = rd->mcasp->max_format_width; 1628 1629 pcm_for_each_format(i) { 1630 if (snd_mask_test_format(fmt, i)) { 1631 if (snd_pcm_format_width(i) == format_width) { 1632 snd_mask_set_format(&nfmt, i); 1633 } 1634 } 1635 } 1636 1637 return snd_mask_refine(fmt, &nfmt); 1638 } 1639 1640 static const unsigned int davinci_mcasp_dai_rates[] = { 1641 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1642 88200, 96000, 176400, 192000, 1643 }; 1644 1645 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1646 1647 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1648 struct snd_pcm_hw_rule *rule) 1649 { 1650 struct davinci_mcasp_ruledata *rd = rule->private; 1651 struct snd_interval *ri = 1652 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1653 int sbits = params_width(params); 1654 int slots, slot_width; 1655 struct snd_interval range; 1656 int i; 1657 1658 slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream); 1659 1660 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1661 if (slot_width) 1662 sbits = slot_width; 1663 1664 snd_interval_any(&range); 1665 range.empty = 1; 1666 1667 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1668 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1669 uint bclk_freq = sbits * slots * 1670 davinci_mcasp_dai_rates[i]; 1671 unsigned int sysclk_freq; 1672 unsigned int ratio; 1673 int ppm; 1674 1675 ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream); 1676 if (ratio) 1677 sysclk_freq = davinci_mcasp_dai_rates[i] * ratio; 1678 else 1679 sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream); 1680 1681 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1682 bclk_freq, rd->stream, false); 1683 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1684 if (range.empty) { 1685 range.min = davinci_mcasp_dai_rates[i]; 1686 range.empty = 0; 1687 } 1688 range.max = davinci_mcasp_dai_rates[i]; 1689 } 1690 } 1691 } 1692 1693 dev_dbg(rd->mcasp->dev, 1694 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1695 ri->min, ri->max, range.min, range.max, sbits, slots); 1696 1697 return snd_interval_refine(hw_param_interval(params, rule->var), 1698 &range); 1699 } 1700 1701 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1702 struct snd_pcm_hw_rule *rule) 1703 { 1704 struct davinci_mcasp_ruledata *rd = rule->private; 1705 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1706 struct snd_mask nfmt; 1707 int rate = params_rate(params); 1708 int slots; 1709 int count = 0; 1710 snd_pcm_format_t i; 1711 1712 slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream); 1713 1714 snd_mask_none(&nfmt); 1715 1716 pcm_for_each_format(i) { 1717 if (snd_mask_test_format(fmt, i)) { 1718 uint sbits = snd_pcm_format_width(i); 1719 unsigned int sysclk_freq; 1720 unsigned int ratio; 1721 int ppm, slot_width; 1722 1723 ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream); 1724 if (ratio) 1725 sysclk_freq = rate * ratio; 1726 else 1727 sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream); 1728 1729 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1730 if (slot_width) 1731 sbits = slot_width; 1732 1733 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1734 sbits * slots * rate, 1735 rd->stream, false); 1736 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1737 snd_mask_set_format(&nfmt, i); 1738 count++; 1739 } 1740 } 1741 } 1742 dev_dbg(rd->mcasp->dev, 1743 "%d possible sample format for %d Hz and %d tdm slots\n", 1744 count, rate, slots); 1745 1746 return snd_mask_refine(fmt, &nfmt); 1747 } 1748 1749 static int davinci_mcasp_hw_rule_min_periodsize( 1750 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1751 { 1752 struct snd_interval *period_size = hw_param_interval(params, 1753 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1754 u8 numevt = *((u8 *)rule->private); 1755 struct snd_interval frames; 1756 1757 snd_interval_any(&frames); 1758 frames.min = numevt; 1759 frames.integer = 1; 1760 1761 return snd_interval_refine(period_size, &frames); 1762 } 1763 1764 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1765 struct snd_soc_dai *cpu_dai) 1766 { 1767 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1768 struct davinci_mcasp_ruledata *ruledata = 1769 &mcasp->ruledata[substream->stream]; 1770 u32 max_channels = 0; 1771 int i, dir, ret; 1772 int tdm_slots; 1773 u8 *numevt; 1774 1775 /* Do not allow more then one stream per direction */ 1776 if (mcasp->substreams[substream->stream]) 1777 return -EBUSY; 1778 1779 mcasp->substreams[substream->stream] = substream; 1780 1781 tdm_slots = mcasp_get_tdm_slots(mcasp, substream->stream); 1782 1783 if (mcasp->tdm_mask[substream->stream]) 1784 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1785 1786 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1787 return 0; 1788 1789 /* 1790 * Limit the maximum allowed channels for the first stream: 1791 * number of serializers for the direction * tdm slots per serializer 1792 */ 1793 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1794 dir = TX_MODE; 1795 else 1796 dir = RX_MODE; 1797 1798 for (i = 0; i < mcasp->num_serializer; i++) { 1799 if (mcasp->serial_dir[i] == dir) 1800 max_channels++; 1801 } 1802 ruledata->serializers = max_channels; 1803 ruledata->mcasp = mcasp; 1804 ruledata->stream = substream->stream; 1805 max_channels *= tdm_slots; 1806 /* 1807 * If the already active stream has less channels than the calculated 1808 * limit based on the seirializers * tdm_slots, and only one serializer 1809 * is in use we need to use that as a constraint for the second stream. 1810 * Otherwise (first stream or less allowed channels or more than one 1811 * serializer in use) we use the calculated constraint. 1812 * 1813 * However, in async mode, TX and RX have independent clocks and can 1814 * use different configurations, so don't apply the constraint. 1815 */ 1816 if (mcasp->channels && mcasp->channels < max_channels && 1817 ruledata->serializers == 1 && 1818 !mcasp->async_mode) 1819 max_channels = mcasp->channels; 1820 /* 1821 * But we can always allow channels upto the amount of 1822 * the available tdm_slots. 1823 */ 1824 if (max_channels < tdm_slots) 1825 max_channels = tdm_slots; 1826 1827 snd_pcm_hw_constraint_minmax(substream->runtime, 1828 SNDRV_PCM_HW_PARAM_CHANNELS, 1829 0, max_channels); 1830 1831 snd_pcm_hw_constraint_list(substream->runtime, 1832 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1833 &mcasp->chconstr[substream->stream]); 1834 1835 if (mcasp->max_format_width && !mcasp->async_mode) { 1836 /* 1837 * Only allow formats which require same amount of bits on the 1838 * bus as the currently running stream to ensure sync mode 1839 */ 1840 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1841 SNDRV_PCM_HW_PARAM_FORMAT, 1842 davinci_mcasp_hw_rule_format_width, 1843 ruledata, 1844 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1845 if (ret) 1846 return ret; 1847 } else if (mcasp_get_slot_width(mcasp, substream->stream)) { 1848 /* Only allow formats require <= slot_width bits on the bus */ 1849 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1850 SNDRV_PCM_HW_PARAM_FORMAT, 1851 davinci_mcasp_hw_rule_slot_width, 1852 ruledata, 1853 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1854 if (ret) 1855 return ret; 1856 } 1857 1858 /* 1859 * If we rely on implicit BCLK divider setting we should 1860 * set constraints based on what we can provide. 1861 */ 1862 if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 && 1863 mcasp_get_sysclk_freq(mcasp, substream->stream)) { 1864 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1865 SNDRV_PCM_HW_PARAM_RATE, 1866 davinci_mcasp_hw_rule_rate, 1867 ruledata, 1868 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1869 if (ret) 1870 return ret; 1871 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1872 SNDRV_PCM_HW_PARAM_FORMAT, 1873 davinci_mcasp_hw_rule_format, 1874 ruledata, 1875 SNDRV_PCM_HW_PARAM_RATE, -1); 1876 if (ret) 1877 return ret; 1878 } 1879 1880 numevt = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1881 &mcasp->txnumevt : 1882 &mcasp->rxnumevt; 1883 snd_pcm_hw_rule_add(substream->runtime, 0, 1884 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1885 davinci_mcasp_hw_rule_min_periodsize, numevt, 1886 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1887 1888 return 0; 1889 } 1890 1891 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1892 struct snd_soc_dai *cpu_dai) 1893 { 1894 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1895 1896 mcasp->substreams[substream->stream] = NULL; 1897 mcasp->active_serializers[substream->stream] = 0; 1898 1899 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1900 return; 1901 1902 if (!snd_soc_dai_active(cpu_dai)) { 1903 mcasp->channels = 0; 1904 mcasp->max_format_width = 0; 1905 } 1906 } 1907 1908 static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol, 1909 struct snd_ctl_elem_info *uinfo) 1910 { 1911 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1912 uinfo->count = 1; 1913 1914 return 0; 1915 } 1916 1917 static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol, 1918 struct snd_ctl_elem_value *uctl) 1919 { 1920 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1921 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1922 1923 memcpy(uctl->value.iec958.status, &mcasp->iec958_status, 1924 sizeof(mcasp->iec958_status)); 1925 1926 return 0; 1927 } 1928 1929 static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol, 1930 struct snd_ctl_elem_value *uctl) 1931 { 1932 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1933 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1934 1935 memcpy(&mcasp->iec958_status, uctl->value.iec958.status, 1936 sizeof(mcasp->iec958_status)); 1937 1938 return 0; 1939 } 1940 1941 static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol, 1942 struct snd_ctl_elem_value *ucontrol) 1943 { 1944 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1945 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1946 1947 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status)); 1948 return 0; 1949 } 1950 1951 static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = { 1952 { 1953 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 1954 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1955 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1956 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1957 .info = davinci_mcasp_iec958_info, 1958 .get = davinci_mcasp_iec958_get, 1959 .put = davinci_mcasp_iec958_put, 1960 }, { 1961 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1962 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1963 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1964 .info = davinci_mcasp_iec958_info, 1965 .get = davinci_mcasp_iec958_con_mask_get, 1966 }, 1967 }; 1968 1969 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp) 1970 { 1971 unsigned char *cs = (u8 *)&mcasp->iec958_status; 1972 1973 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 1974 cs[1] = IEC958_AES1_CON_PCM_CODER; 1975 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 1976 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM; 1977 } 1978 1979 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1980 { 1981 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1982 int stream; 1983 1984 for_each_pcm_streams(stream) 1985 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]); 1986 1987 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) { 1988 davinci_mcasp_init_iec958_status(mcasp); 1989 snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls, 1990 ARRAY_SIZE(davinci_mcasp_iec958_ctls)); 1991 } 1992 1993 return 0; 1994 } 1995 1996 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1997 .probe = davinci_mcasp_dai_probe, 1998 .startup = davinci_mcasp_startup, 1999 .shutdown = davinci_mcasp_shutdown, 2000 .trigger = davinci_mcasp_trigger, 2001 .delay = davinci_mcasp_delay, 2002 .hw_params = davinci_mcasp_hw_params, 2003 .set_fmt = davinci_mcasp_set_dai_fmt, 2004 .set_clkdiv = davinci_mcasp_set_clkdiv, 2005 .set_sysclk = davinci_mcasp_set_sysclk, 2006 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 2007 }; 2008 2009 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 2010 2011 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 2012 SNDRV_PCM_FMTBIT_U8 | \ 2013 SNDRV_PCM_FMTBIT_S16_LE | \ 2014 SNDRV_PCM_FMTBIT_U16_LE | \ 2015 SNDRV_PCM_FMTBIT_S24_LE | \ 2016 SNDRV_PCM_FMTBIT_U24_LE | \ 2017 SNDRV_PCM_FMTBIT_S24_3LE | \ 2018 SNDRV_PCM_FMTBIT_U24_3LE | \ 2019 SNDRV_PCM_FMTBIT_S32_LE | \ 2020 SNDRV_PCM_FMTBIT_U32_LE) 2021 2022 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 2023 { 2024 .name = "davinci-mcasp.0", 2025 .playback = { 2026 .stream_name = "IIS Playback", 2027 .channels_min = 1, 2028 .channels_max = 32 * 16, 2029 .rates = DAVINCI_MCASP_RATES, 2030 .formats = DAVINCI_MCASP_PCM_FMTS, 2031 }, 2032 .capture = { 2033 .stream_name = "IIS Capture", 2034 .channels_min = 1, 2035 .channels_max = 32 * 16, 2036 .rates = DAVINCI_MCASP_RATES, 2037 .formats = DAVINCI_MCASP_PCM_FMTS, 2038 }, 2039 .ops = &davinci_mcasp_dai_ops, 2040 }, 2041 { 2042 .name = "davinci-mcasp.1", 2043 .playback = { 2044 .stream_name = "DIT Playback", 2045 .channels_min = 1, 2046 .channels_max = 384, 2047 .rates = DAVINCI_MCASP_RATES, 2048 .formats = SNDRV_PCM_FMTBIT_S16_LE | 2049 SNDRV_PCM_FMTBIT_S24_LE, 2050 }, 2051 .ops = &davinci_mcasp_dai_ops, 2052 }, 2053 2054 }; 2055 2056 /* Translate of-graph endpoint to DAI ID (DPCM: port reg; else 0). */ 2057 static int davinci_mcasp_of_xlate_dai_id(struct snd_soc_component *component, 2058 struct device_node *endpoint) 2059 { 2060 struct davinci_mcasp *mcasp = snd_soc_component_get_drvdata(component); 2061 struct device_node *port; 2062 u32 port_reg = 0; 2063 2064 if (mcasp->graph_mode != MCASP_GRAPH_DPCM) 2065 return 0; 2066 2067 /* endpoint is inside mcasp/ports/port@N — read port's reg */ 2068 port = of_get_parent(endpoint); 2069 if (!port) 2070 return -EINVAL; 2071 2072 of_property_read_u32(port, "reg", &port_reg); 2073 of_node_put(port); 2074 2075 return port_reg; 2076 } 2077 2078 static const struct snd_soc_component_driver davinci_mcasp_component = { 2079 .name = "davinci-mcasp", 2080 .of_xlate_dai_id = davinci_mcasp_of_xlate_dai_id, 2081 .legacy_dai_naming = 1, 2082 }; 2083 2084 /* Some HW specific values and defaults. The rest is filled in from DT. */ 2085 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 2086 .tx_dma_offset = 0x400, 2087 .rx_dma_offset = 0x400, 2088 .version = MCASP_VERSION_1, 2089 }; 2090 2091 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 2092 .tx_dma_offset = 0x2000, 2093 .rx_dma_offset = 0x2000, 2094 .version = MCASP_VERSION_2, 2095 }; 2096 2097 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 2098 .tx_dma_offset = 0, 2099 .rx_dma_offset = 0, 2100 .version = MCASP_VERSION_3, 2101 }; 2102 2103 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 2104 /* The CFG port offset will be calculated if it is needed */ 2105 .tx_dma_offset = 0, 2106 .rx_dma_offset = 0, 2107 .version = MCASP_VERSION_4, 2108 }; 2109 2110 static struct davinci_mcasp_pdata omap_mcasp_pdata = { 2111 .tx_dma_offset = 0x200, 2112 .rx_dma_offset = 0, 2113 .version = MCASP_VERSION_OMAP, 2114 }; 2115 2116 static const struct of_device_id mcasp_dt_ids[] = { 2117 { 2118 .compatible = "ti,dm646x-mcasp-audio", 2119 .data = &dm646x_mcasp_pdata, 2120 }, 2121 { 2122 .compatible = "ti,da830-mcasp-audio", 2123 .data = &da830_mcasp_pdata, 2124 }, 2125 { 2126 .compatible = "ti,am33xx-mcasp-audio", 2127 .data = &am33xx_mcasp_pdata, 2128 }, 2129 { 2130 .compatible = "ti,dra7-mcasp-audio", 2131 .data = &dra7_mcasp_pdata, 2132 }, 2133 { 2134 .compatible = "ti,omap4-mcasp-audio", 2135 .data = &omap_mcasp_pdata, 2136 }, 2137 { /* sentinel */ } 2138 }; 2139 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 2140 2141 static int mcasp_reparent_fck(struct platform_device *pdev) 2142 { 2143 struct device_node *node = pdev->dev.of_node; 2144 struct clk *gfclk, *parent_clk; 2145 const char *parent_name; 2146 int ret; 2147 2148 if (!node) 2149 return 0; 2150 2151 parent_name = of_get_property(node, "fck_parent", NULL); 2152 if (!parent_name) 2153 return 0; 2154 2155 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 2156 2157 gfclk = clk_get(&pdev->dev, "fck"); 2158 if (IS_ERR(gfclk)) { 2159 dev_err(&pdev->dev, "failed to get fck\n"); 2160 return PTR_ERR(gfclk); 2161 } 2162 2163 parent_clk = clk_get(NULL, parent_name); 2164 if (IS_ERR(parent_clk)) { 2165 dev_err(&pdev->dev, "failed to get parent clock\n"); 2166 ret = PTR_ERR(parent_clk); 2167 goto err1; 2168 } 2169 2170 ret = clk_set_parent(gfclk, parent_clk); 2171 if (ret) { 2172 dev_err(&pdev->dev, "failed to reparent fck\n"); 2173 goto err2; 2174 } 2175 2176 err2: 2177 clk_put(parent_clk); 2178 err1: 2179 clk_put(gfclk); 2180 return ret; 2181 } 2182 2183 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp) 2184 { 2185 return device_property_present(mcasp->dev, "gpio-controller"); 2186 } 2187 2188 /* Return true if the remote sound card uses a "dpcm" container. */ 2189 static bool mcasp_detect_dpcm(struct device_node *np) 2190 { 2191 struct device_node *ep, *remote_ep; 2192 struct device_node *port, *container, *parent; 2193 bool is_dpcm = false; 2194 2195 /* Grab the first endpoint under this McASP node */ 2196 ep = of_graph_get_next_endpoint(np, NULL); 2197 if (!ep) 2198 return false; 2199 2200 /* Follow remote-endpoint phandle into the card node */ 2201 remote_ep = of_graph_get_remote_endpoint(ep); 2202 of_node_put(ep); 2203 if (!remote_ep) 2204 return false; 2205 2206 /* Traverse the remote: remote_ep -> port -> ports@N -> dpcm */ 2207 port = of_get_parent(remote_ep); 2208 of_node_put(remote_ep); 2209 if (!port) 2210 return false; 2211 2212 container = of_get_parent(port); 2213 of_node_put(port); 2214 if (!container) 2215 return false; 2216 2217 if (of_node_name_eq(container, "ports")) { 2218 parent = of_get_parent(container); 2219 of_node_put(container); 2220 if (parent) { 2221 is_dpcm = of_node_name_eq(parent, "dpcm"); 2222 of_node_put(parent); 2223 } 2224 } else { 2225 of_node_put(container); 2226 } 2227 2228 return is_dpcm; 2229 } 2230 2231 /* Detect audio-graph topology and return the number of DAIs to register. */ 2232 static int davinci_mcasp_parse_of_graph(struct davinci_mcasp *mcasp, 2233 struct device_node *np) 2234 { 2235 struct device_node *port, *ports; 2236 int num_dais = 0; 2237 2238 mcasp->graph_mode = MCASP_GRAPH_NONE; 2239 2240 /* audio-graph-card2: ports { port@0 ... }; DPCM -> N DAIs, else 1 */ 2241 ports = of_get_child_by_name(np, "ports"); 2242 if (ports) { 2243 int port_count = of_get_child_count(ports); 2244 2245 of_node_put(ports); 2246 2247 if (mcasp_detect_dpcm(np)) { 2248 num_dais = port_count; 2249 mcasp->graph_mode = MCASP_GRAPH_DPCM; 2250 } else { 2251 num_dais = 1; 2252 mcasp->graph_mode = MCASP_GRAPH_PORTS; 2253 } 2254 2255 return num_dais; 2256 } 2257 2258 /* audio-graph-card: single port { endpoint } */ 2259 port = of_get_child_by_name(np, "port"); 2260 if (port) { 2261 num_dais = of_graph_get_endpoint_count(port); 2262 if (num_dais > 0) 2263 mcasp->graph_mode = MCASP_GRAPH_PORT; 2264 of_node_put(port); 2265 } 2266 2267 return num_dais ? num_dais : 1; 2268 } 2269 2270 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp, 2271 struct platform_device *pdev) 2272 { 2273 struct device_node *np = pdev->dev.of_node; 2274 struct davinci_mcasp_pdata *pdata = NULL; 2275 const struct davinci_mcasp_pdata *match_pdata = 2276 device_get_match_data(&pdev->dev); 2277 const u32 *of_serial_dir32; 2278 u32 val; 2279 int i; 2280 2281 if (pdev->dev.platform_data) { 2282 pdata = pdev->dev.platform_data; 2283 pdata->dismod = DISMOD_LOW; 2284 goto out; 2285 } else if (match_pdata) { 2286 pdata = devm_kmemdup(&pdev->dev, match_pdata, sizeof(*pdata), 2287 GFP_KERNEL); 2288 if (!pdata) 2289 return -ENOMEM; 2290 } else { 2291 dev_err(&pdev->dev, "No compatible match found\n"); 2292 return -EINVAL; 2293 } 2294 2295 if (of_property_read_u32(np, "op-mode", &val) == 0) { 2296 pdata->op_mode = val; 2297 } else { 2298 mcasp->missing_audio_param = true; 2299 goto out; 2300 } 2301 2302 /* Parse TX-specific TDM slot and use it as default for RX */ 2303 if (of_property_read_u32(np, "tdm-slots", &val) == 0) { 2304 if (val < 2 || val > 32) { 2305 dev_err(&pdev->dev, "tdm-slots must be in range [2-32]\n"); 2306 return -EINVAL; 2307 } 2308 2309 pdata->tdm_slots_tx = val; 2310 pdata->tdm_slots_rx = val; 2311 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) { 2312 mcasp->missing_audio_param = true; 2313 goto out; 2314 } 2315 2316 /* Parse RX-specific TDM slot count if provided */ 2317 if (of_property_read_u32(np, "tdm-slots-rx", &val) == 0) { 2318 if (val < 2 || val > 32) { 2319 dev_err(&pdev->dev, "tdm-slots-rx must be in range [2-32]\n"); 2320 return -EINVAL; 2321 } 2322 2323 pdata->tdm_slots_rx = val; 2324 } 2325 2326 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) 2327 mcasp->async_mode = of_property_read_bool(np, "ti,async-mode"); 2328 2329 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 2330 val /= sizeof(u32); 2331 if (of_serial_dir32) { 2332 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 2333 (sizeof(*of_serial_dir) * val), 2334 GFP_KERNEL); 2335 if (!of_serial_dir) 2336 return -ENOMEM; 2337 2338 for (i = 0; i < val; i++) 2339 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 2340 2341 pdata->num_serializer = val; 2342 pdata->serial_dir = of_serial_dir; 2343 } else { 2344 mcasp->missing_audio_param = true; 2345 goto out; 2346 } 2347 2348 if (of_property_read_u32(np, "tx-num-evt", &val) == 0) 2349 pdata->txnumevt = val; 2350 2351 if (of_property_read_u32(np, "rx-num-evt", &val) == 0) 2352 pdata->rxnumevt = val; 2353 2354 /* Parse TX-specific auxclk/fs ratio and use it as default for RX */ 2355 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) { 2356 mcasp->auxclk_fs_ratio_tx = val; 2357 mcasp->auxclk_fs_ratio_rx = val; 2358 } 2359 2360 /* Parse RX-specific auxclk/fs ratio if provided */ 2361 if (of_property_read_u32(np, "auxclk-fs-ratio-rx", &val) == 0) 2362 mcasp->auxclk_fs_ratio_rx = val; 2363 2364 if (of_property_read_u32(np, "dismod", &val) == 0) { 2365 if (val == 0 || val == 2 || val == 3) { 2366 pdata->dismod = DISMOD_VAL(val); 2367 } else { 2368 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 2369 pdata->dismod = DISMOD_LOW; 2370 } 2371 } else { 2372 pdata->dismod = DISMOD_LOW; 2373 } 2374 2375 out: 2376 mcasp->pdata = pdata; 2377 2378 if (mcasp->missing_audio_param) { 2379 if (davinci_mcasp_have_gpiochip(mcasp)) { 2380 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n"); 2381 return 0; 2382 } 2383 2384 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n"); 2385 return -ENODEV; 2386 } 2387 2388 mcasp->op_mode = pdata->op_mode; 2389 /* sanity check for tdm slots parameter */ 2390 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 2391 if (pdata->tdm_slots_tx < 2) { 2392 dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n", 2393 pdata->tdm_slots_tx); 2394 mcasp->tdm_slots_tx = 2; 2395 } else if (pdata->tdm_slots_tx > 32) { 2396 dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n", 2397 pdata->tdm_slots_tx); 2398 mcasp->tdm_slots_tx = 32; 2399 } else { 2400 mcasp->tdm_slots_tx = pdata->tdm_slots_tx; 2401 } 2402 2403 if (pdata->tdm_slots_rx < 2) { 2404 dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n", 2405 pdata->tdm_slots_rx); 2406 mcasp->tdm_slots_rx = 2; 2407 } else if (pdata->tdm_slots_rx > 32) { 2408 dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n", 2409 pdata->tdm_slots_rx); 2410 mcasp->tdm_slots_rx = 32; 2411 } else { 2412 mcasp->tdm_slots_rx = pdata->tdm_slots_rx; 2413 } 2414 } else { 2415 mcasp->tdm_slots_tx = 32; 2416 mcasp->tdm_slots_rx = 32; 2417 } 2418 2419 /* Different TX/RX slot counts require async mode */ 2420 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE && 2421 mcasp->tdm_slots_tx != mcasp->tdm_slots_rx && !mcasp->async_mode) { 2422 dev_err(&pdev->dev, 2423 "Different TX (%d) and RX (%d) TDM slots require ti,async-mode\n", 2424 mcasp->tdm_slots_tx, mcasp->tdm_slots_rx); 2425 return -EINVAL; 2426 } 2427 2428 /* Different TX/RX auxclk-fs-ratio require async mode */ 2429 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE && 2430 mcasp->auxclk_fs_ratio_tx && mcasp->auxclk_fs_ratio_rx && 2431 mcasp->auxclk_fs_ratio_tx != mcasp->auxclk_fs_ratio_rx && !mcasp->async_mode) { 2432 dev_err(&pdev->dev, 2433 "Different TX (%d) and RX (%d) auxclk-fs-ratio require ti,async-mode\n", 2434 mcasp->auxclk_fs_ratio_tx, mcasp->auxclk_fs_ratio_rx); 2435 return -EINVAL; 2436 } 2437 2438 mcasp->num_serializer = pdata->num_serializer; 2439 #ifdef CONFIG_PM 2440 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 2441 mcasp->num_serializer, sizeof(u32), 2442 GFP_KERNEL); 2443 if (!mcasp->context.xrsr_regs) 2444 return -ENOMEM; 2445 #endif 2446 mcasp->serial_dir = pdata->serial_dir; 2447 mcasp->version = pdata->version; 2448 mcasp->txnumevt = pdata->txnumevt; 2449 mcasp->rxnumevt = pdata->rxnumevt; 2450 mcasp->dismod = pdata->dismod; 2451 2452 return 0; 2453 } 2454 2455 enum { 2456 PCM_EDMA, 2457 PCM_SDMA, 2458 PCM_UDMA, 2459 }; 2460 static const char *sdma_prefix = "ti,omap"; 2461 2462 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 2463 { 2464 struct dma_chan *chan; 2465 const char *tmp; 2466 int ret = PCM_EDMA; 2467 2468 if (!mcasp->dev->of_node) 2469 return PCM_EDMA; 2470 2471 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 2472 chan = dma_request_chan(mcasp->dev, tmp); 2473 if (IS_ERR(chan)) 2474 return dev_err_probe(mcasp->dev, PTR_ERR(chan), 2475 "Can't verify DMA configuration\n"); 2476 if (WARN_ON(!chan->device || !chan->device->dev)) { 2477 dma_release_channel(chan); 2478 return -EINVAL; 2479 } 2480 2481 if (chan->device->dev->of_node) 2482 ret = of_property_read_string(chan->device->dev->of_node, 2483 "compatible", &tmp); 2484 else 2485 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 2486 2487 dma_release_channel(chan); 2488 if (ret) 2489 return ret; 2490 2491 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 2492 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 2493 return PCM_SDMA; 2494 else if (strstr(tmp, "udmap")) 2495 return PCM_UDMA; 2496 else if (strstr(tmp, "bcdma")) 2497 return PCM_UDMA; 2498 2499 return PCM_EDMA; 2500 } 2501 2502 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 2503 { 2504 int i; 2505 u32 offset = 0; 2506 2507 if (pdata->version != MCASP_VERSION_4) 2508 return pdata->tx_dma_offset; 2509 2510 for (i = 0; i < pdata->num_serializer; i++) { 2511 if (pdata->serial_dir[i] == TX_MODE) { 2512 if (!offset) { 2513 offset = DAVINCI_MCASP_TXBUF_REG(i); 2514 } else { 2515 pr_err("%s: Only one serializer allowed!\n", 2516 __func__); 2517 break; 2518 } 2519 } 2520 } 2521 2522 return offset; 2523 } 2524 2525 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 2526 { 2527 int i; 2528 u32 offset = 0; 2529 2530 if (pdata->version != MCASP_VERSION_4) 2531 return pdata->rx_dma_offset; 2532 2533 for (i = 0; i < pdata->num_serializer; i++) { 2534 if (pdata->serial_dir[i] == RX_MODE) { 2535 if (!offset) { 2536 offset = DAVINCI_MCASP_RXBUF_REG(i); 2537 } else { 2538 pr_err("%s: Only one serializer allowed!\n", 2539 __func__); 2540 break; 2541 } 2542 } 2543 } 2544 2545 return offset; 2546 } 2547 2548 #ifdef CONFIG_GPIOLIB 2549 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 2550 { 2551 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2552 2553 if (mcasp->num_serializer && offset < mcasp->num_serializer && 2554 mcasp->serial_dir[offset] != INACTIVE_MODE) { 2555 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 2556 return -EBUSY; 2557 } 2558 2559 /* Do not change the PIN yet */ 2560 return pm_runtime_resume_and_get(mcasp->dev); 2561 } 2562 2563 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 2564 { 2565 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2566 2567 /* Set the direction to input */ 2568 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2569 2570 /* Set the pin as McASP pin */ 2571 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2572 2573 pm_runtime_put_sync(mcasp->dev); 2574 } 2575 2576 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 2577 unsigned offset, int value) 2578 { 2579 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2580 u32 val; 2581 2582 if (value) 2583 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2584 else 2585 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2586 2587 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2588 if (!(val & BIT(offset))) { 2589 /* Set the pin as GPIO pin */ 2590 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2591 2592 /* Set the direction to output */ 2593 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2594 } 2595 2596 return 0; 2597 } 2598 2599 static int davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned int offset, 2600 int value) 2601 { 2602 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2603 2604 if (value) 2605 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2606 else 2607 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2608 2609 return 0; 2610 } 2611 2612 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 2613 unsigned offset) 2614 { 2615 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2616 u32 val; 2617 2618 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2619 if (!(val & BIT(offset))) { 2620 /* Set the direction to input */ 2621 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2622 2623 /* Set the pin as GPIO pin */ 2624 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2625 } 2626 2627 return 0; 2628 } 2629 2630 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 2631 { 2632 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2633 u32 val; 2634 2635 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 2636 if (val & BIT(offset)) 2637 return 1; 2638 2639 return 0; 2640 } 2641 2642 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 2643 unsigned offset) 2644 { 2645 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2646 u32 val; 2647 2648 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 2649 if (val & BIT(offset)) 2650 return 0; 2651 2652 return 1; 2653 } 2654 2655 static const struct gpio_chip davinci_mcasp_template_chip = { 2656 .owner = THIS_MODULE, 2657 .request = davinci_mcasp_gpio_request, 2658 .free = davinci_mcasp_gpio_free, 2659 .direction_output = davinci_mcasp_gpio_direction_out, 2660 .set = davinci_mcasp_gpio_set, 2661 .direction_input = davinci_mcasp_gpio_direction_in, 2662 .get = davinci_mcasp_gpio_get, 2663 .get_direction = davinci_mcasp_gpio_get_direction, 2664 .base = -1, 2665 .ngpio = 32, 2666 }; 2667 2668 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2669 { 2670 if (!davinci_mcasp_have_gpiochip(mcasp)) 2671 return 0; 2672 2673 mcasp->gpio_chip = davinci_mcasp_template_chip; 2674 mcasp->gpio_chip.label = dev_name(mcasp->dev); 2675 mcasp->gpio_chip.parent = mcasp->dev; 2676 2677 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 2678 } 2679 2680 #else /* CONFIG_GPIOLIB */ 2681 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2682 { 2683 return 0; 2684 } 2685 #endif /* CONFIG_GPIOLIB */ 2686 2687 static int davinci_mcasp_register_component(struct davinci_mcasp *mcasp, 2688 struct platform_device *pdev) 2689 { 2690 struct snd_soc_dai_driver *dais; 2691 int i; 2692 2693 if (mcasp->graph_mode == MCASP_GRAPH_NONE || mcasp->num_dais <= 1) 2694 return devm_snd_soc_register_component(&pdev->dev, 2695 &davinci_mcasp_component, 2696 &davinci_mcasp_dai[mcasp->op_mode], 1); 2697 2698 dais = devm_kcalloc(&pdev->dev, mcasp->num_dais, sizeof(*dais), 2699 GFP_KERNEL); 2700 if (!dais) 2701 return -ENOMEM; 2702 2703 for (i = 0; i < mcasp->num_dais; i++) { 2704 memcpy(&dais[i], &davinci_mcasp_dai[mcasp->op_mode], 2705 sizeof(*dais)); 2706 dais[i].id = i; 2707 dais[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, 2708 "davinci-mcasp.%d", i); 2709 if (!dais[i].name) 2710 return -ENOMEM; 2711 2712 /* Unique stream names per DAI */ 2713 if (dais[i].playback.channels_min) { 2714 dais[i].playback.stream_name = 2715 devm_kasprintf(&pdev->dev, GFP_KERNEL, 2716 "Playback Port %d", i); 2717 if (!dais[i].playback.stream_name) 2718 return -ENOMEM; 2719 } 2720 if (dais[i].capture.channels_min) { 2721 dais[i].capture.stream_name = 2722 devm_kasprintf(&pdev->dev, GFP_KERNEL, 2723 "Capture Port %d", i); 2724 if (!dais[i].capture.stream_name) 2725 return -ENOMEM; 2726 } 2727 } 2728 2729 return devm_snd_soc_register_component(&pdev->dev, 2730 &davinci_mcasp_component, 2731 dais, mcasp->num_dais); 2732 } 2733 2734 static int davinci_mcasp_probe(struct platform_device *pdev) 2735 { 2736 struct snd_dmaengine_dai_dma_data *dma_data; 2737 struct resource *mem, *dat; 2738 struct davinci_mcasp *mcasp; 2739 char *irq_name; 2740 int irq; 2741 int ret; 2742 2743 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2744 dev_err(&pdev->dev, "No platform data supplied\n"); 2745 return -EINVAL; 2746 } 2747 2748 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2749 GFP_KERNEL); 2750 if (!mcasp) 2751 return -ENOMEM; 2752 2753 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2754 if (!mem) { 2755 dev_warn(&pdev->dev, 2756 "\"mpu\" mem resource not found, using index 0\n"); 2757 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2758 if (!mem) { 2759 dev_err(&pdev->dev, "no mem resource?\n"); 2760 return -ENODEV; 2761 } 2762 } 2763 2764 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2765 if (IS_ERR(mcasp->base)) 2766 return PTR_ERR(mcasp->base); 2767 2768 dev_set_drvdata(&pdev->dev, mcasp); 2769 pm_runtime_enable(&pdev->dev); 2770 2771 mcasp->dev = &pdev->dev; 2772 ret = davinci_mcasp_get_config(mcasp, pdev); 2773 if (ret) 2774 goto err; 2775 2776 /* All PINS as McASP */ 2777 pm_runtime_get_sync(mcasp->dev); 2778 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2779 pm_runtime_put(mcasp->dev); 2780 2781 /* Skip audio related setup code if the configuration is not adequat */ 2782 if (mcasp->missing_audio_param) 2783 goto no_audio; 2784 2785 irq = platform_get_irq_byname_optional(pdev, "common"); 2786 if (irq > 0) { 2787 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2788 dev_name(&pdev->dev)); 2789 if (!irq_name) { 2790 ret = -ENOMEM; 2791 goto err; 2792 } 2793 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2794 davinci_mcasp_common_irq_handler, 2795 IRQF_ONESHOT | IRQF_SHARED, 2796 irq_name, mcasp); 2797 if (ret) { 2798 dev_err(&pdev->dev, "common IRQ request failed\n"); 2799 goto err; 2800 } 2801 2802 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2803 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2804 } 2805 2806 irq = platform_get_irq_byname_optional(pdev, "rx"); 2807 if (irq > 0) { 2808 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2809 dev_name(&pdev->dev)); 2810 if (!irq_name) { 2811 ret = -ENOMEM; 2812 goto err; 2813 } 2814 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2815 davinci_mcasp_rx_irq_handler, 2816 IRQF_ONESHOT, irq_name, mcasp); 2817 if (ret) { 2818 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2819 goto err; 2820 } 2821 2822 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2823 } 2824 2825 irq = platform_get_irq_byname_optional(pdev, "tx"); 2826 if (irq > 0) { 2827 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2828 dev_name(&pdev->dev)); 2829 if (!irq_name) { 2830 ret = -ENOMEM; 2831 goto err; 2832 } 2833 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2834 davinci_mcasp_tx_irq_handler, 2835 IRQF_ONESHOT, irq_name, mcasp); 2836 if (ret) { 2837 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2838 goto err; 2839 } 2840 2841 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2842 } 2843 2844 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2845 if (dat) 2846 mcasp->dat_port = true; 2847 2848 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2849 dma_data->filter_data = "tx"; 2850 if (dat) { 2851 dma_data->addr = dat->start; 2852 /* 2853 * According to the TRM there should be 0x200 offset added to 2854 * the DAT port address 2855 */ 2856 if (mcasp->version == MCASP_VERSION_OMAP) 2857 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata); 2858 } else { 2859 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata); 2860 } 2861 2862 2863 /* RX is not valid in DIT mode */ 2864 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2865 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2866 dma_data->filter_data = "rx"; 2867 if (dat) 2868 dma_data->addr = dat->start; 2869 else 2870 dma_data->addr = 2871 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata); 2872 } 2873 2874 if (mcasp->version < MCASP_VERSION_3) { 2875 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2876 /* dma_params->dma_addr is pointing to the data port address */ 2877 mcasp->dat_port = true; 2878 } else { 2879 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2880 } 2881 2882 /* Allocate memory for long enough list for all possible 2883 * scenarios. Maximum number tdm slots is 32 and there cannot 2884 * be more serializers than given in the configuration. The 2885 * serializer directions could be taken into account, but it 2886 * would make code much more complex and save only couple of 2887 * bytes. 2888 */ 2889 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2890 devm_kcalloc(mcasp->dev, 2891 32 + mcasp->num_serializer - 1, 2892 sizeof(unsigned int), 2893 GFP_KERNEL); 2894 2895 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2896 devm_kcalloc(mcasp->dev, 2897 32 + mcasp->num_serializer - 1, 2898 sizeof(unsigned int), 2899 GFP_KERNEL); 2900 2901 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2902 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2903 ret = -ENOMEM; 2904 goto err; 2905 } 2906 2907 ret = davinci_mcasp_set_ch_constraints(mcasp); 2908 if (ret) 2909 goto err; 2910 2911 mcasp_reparent_fck(pdev); 2912 2913 ret = davinci_mcasp_get_dma_type(mcasp); 2914 switch (ret) { 2915 case PCM_EDMA: 2916 ret = edma_pcm_platform_register(&pdev->dev); 2917 break; 2918 case PCM_SDMA: 2919 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 2920 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 2921 else 2922 ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL); 2923 break; 2924 case PCM_UDMA: 2925 ret = udma_pcm_platform_register(&pdev->dev); 2926 break; 2927 default: 2928 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2929 fallthrough; 2930 case -EPROBE_DEFER: 2931 goto err; 2932 } 2933 2934 if (ret) { 2935 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2936 goto err; 2937 } 2938 2939 /* Parse audio-graph structure and register DAIs */ 2940 mcasp->num_dais = davinci_mcasp_parse_of_graph(mcasp, pdev->dev.of_node); 2941 2942 ret = davinci_mcasp_register_component(mcasp, pdev); 2943 if (ret != 0) 2944 goto err; 2945 2946 no_audio: 2947 ret = davinci_mcasp_init_gpiochip(mcasp); 2948 if (ret) { 2949 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret); 2950 goto err; 2951 } 2952 2953 return 0; 2954 err: 2955 pm_runtime_disable(&pdev->dev); 2956 return ret; 2957 } 2958 2959 static void davinci_mcasp_remove(struct platform_device *pdev) 2960 { 2961 pm_runtime_disable(&pdev->dev); 2962 } 2963 2964 #ifdef CONFIG_PM 2965 static int davinci_mcasp_runtime_suspend(struct device *dev) 2966 { 2967 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2968 struct davinci_mcasp_context *context = &mcasp->context; 2969 u32 reg; 2970 int i; 2971 2972 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2973 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2974 2975 if (mcasp->txnumevt) { 2976 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2977 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2978 } 2979 if (mcasp->rxnumevt) { 2980 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2981 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2982 } 2983 2984 for (i = 0; i < mcasp->num_serializer; i++) 2985 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2986 DAVINCI_MCASP_XRSRCTL_REG(i)); 2987 2988 return 0; 2989 } 2990 2991 static int davinci_mcasp_runtime_resume(struct device *dev) 2992 { 2993 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2994 struct davinci_mcasp_context *context = &mcasp->context; 2995 u32 reg; 2996 int i; 2997 2998 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2999 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 3000 3001 if (mcasp->txnumevt) { 3002 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 3003 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 3004 } 3005 if (mcasp->rxnumevt) { 3006 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 3007 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 3008 } 3009 3010 for (i = 0; i < mcasp->num_serializer; i++) 3011 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 3012 context->xrsr_regs[i]); 3013 3014 return 0; 3015 } 3016 3017 #endif 3018 3019 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 3020 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 3021 pm_runtime_force_resume) 3022 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 3023 davinci_mcasp_runtime_resume, 3024 NULL) 3025 }; 3026 3027 static struct platform_driver davinci_mcasp_driver = { 3028 .probe = davinci_mcasp_probe, 3029 .remove = davinci_mcasp_remove, 3030 .driver = { 3031 .name = "davinci-mcasp", 3032 .pm = &davinci_mcasp_pm_ops, 3033 .of_match_table = mcasp_dt_ids, 3034 }, 3035 }; 3036 3037 module_platform_driver(davinci_mcasp_driver); 3038 3039 MODULE_AUTHOR("Steve Chen"); 3040 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 3041 MODULE_LICENSE("GPL"); 3042