1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * tdfxfb.c 5 * 6 * Author: Hannu Mallat <hmallat@cc.hut.fi> 7 * 8 * Copyright © 1999 Hannu Mallat 9 * All rights reserved 10 * 11 * Created : Thu Sep 23 18:17:43 1999, hmallat 12 * Last modified: Tue Nov 2 21:19:47 1999, hmallat 13 * 14 * I2C part copied from the i2c-voodoo3.c driver by: 15 * Frodo Looijaard <frodol@dds.nl>, 16 * Philip Edelbrock <phil@netroedge.com>, 17 * Ralph Metzler <rjkm@thp.uni-koeln.de>, and 18 * Mark D. Studebaker <mdsxyz123@yahoo.com> 19 * 20 * Lots of the information here comes from the Daryll Strauss' Banshee 21 * patches to the XF86 server, and the rest comes from the 3dfx 22 * Banshee specification. I'm very much indebted to Daryll for his 23 * work on the X server. 24 * 25 * Voodoo3 support was contributed Harold Oga. Lots of additions 26 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila 27 * Kesmarki. Thanks guys! 28 * 29 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they 30 * behave very differently from the Voodoo3/4/5. For anyone wanting to 31 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is 32 * located at http://www.sourceforge.net/projects/sstfb). 33 * 34 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee, 35 * I do wish the next version is a bit more complete. Without the XF86 36 * patches I couldn't have gotten even this far... for instance, the 37 * extensions to the VGA register set go completely unmentioned in the 38 * spec! Also, lots of references are made to the 'SST core', but no 39 * spec is publicly available, AFAIK. 40 * 41 * The structure of this driver comes pretty much from the Permedia 42 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb. 43 * 44 * TODO: 45 * - multihead support (basically need to support an array of fb_infos) 46 * - support other architectures (PPC, Alpha); does the fact that the VGA 47 * core can be accessed only thru I/O (not memory mapped) complicate 48 * things? 49 * 50 * Version history: 51 * 52 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons 53 * 54 * 0.1.3 (released 1999-11-02) added Attila's panning support, code 55 * reorg, hwcursor address page size alignment 56 * (for mmapping both frame buffer and regs), 57 * and my changes to get rid of hardcoded 58 * VGA i/o register locations (uses PCI 59 * configuration info now) 60 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and 61 * improvements 62 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga. 63 * 0.1.0 (released 1999-10-06) initial version 64 * 65 */ 66 67 #include <linux/aperture.h> 68 #include <linux/module.h> 69 #include <linux/kernel.h> 70 #include <linux/errno.h> 71 #include <linux/string.h> 72 #include <linux/mm.h> 73 #include <linux/slab.h> 74 #include <linux/fb.h> 75 #include <linux/init.h> 76 #include <linux/pci.h> 77 #include <asm/io.h> 78 79 #include <video/tdfx.h> 80 #include <video/vga.h> 81 82 #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b) 83 84 #define BANSHEE_MAX_PIXCLOCK 270000 85 #define VOODOO3_MAX_PIXCLOCK 300000 86 #define VOODOO5_MAX_PIXCLOCK 350000 87 88 static const struct fb_fix_screeninfo tdfx_fix = { 89 .type = FB_TYPE_PACKED_PIXELS, 90 .visual = FB_VISUAL_PSEUDOCOLOR, 91 .ypanstep = 1, 92 .ywrapstep = 1, 93 .accel = FB_ACCEL_3DFX_BANSHEE 94 }; 95 96 static const struct fb_var_screeninfo tdfx_var = { 97 /* "640x480, 8 bpp @ 60 Hz */ 98 .xres = 640, 99 .yres = 480, 100 .xres_virtual = 640, 101 .yres_virtual = 1024, 102 .bits_per_pixel = 8, 103 .red = {0, 8, 0}, 104 .blue = {0, 8, 0}, 105 .green = {0, 8, 0}, 106 .activate = FB_ACTIVATE_NOW, 107 .height = -1, 108 .width = -1, 109 .accel_flags = FB_ACCELF_TEXT, 110 .pixclock = 39722, 111 .left_margin = 40, 112 .right_margin = 24, 113 .upper_margin = 32, 114 .lower_margin = 11, 115 .hsync_len = 96, 116 .vsync_len = 2, 117 .vmode = FB_VMODE_NONINTERLACED 118 }; 119 120 /* 121 * PCI driver prototypes 122 */ 123 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id); 124 static void tdfxfb_remove(struct pci_dev *pdev); 125 126 static const struct pci_device_id tdfxfb_id_table[] = { 127 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE, 128 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 129 0xff0000, 0 }, 130 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3, 131 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 132 0xff0000, 0 }, 133 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5, 134 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 135 0xff0000, 0 }, 136 { 0, } 137 }; 138 139 static struct pci_driver tdfxfb_driver = { 140 .name = "tdfxfb", 141 .id_table = tdfxfb_id_table, 142 .probe = tdfxfb_probe, 143 .remove = tdfxfb_remove, 144 }; 145 146 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table); 147 148 /* 149 * Driver data 150 */ 151 static int nopan; 152 static int nowrap = 1; /* not implemented (yet) */ 153 static int hwcursor = 1; 154 static char *mode_option; 155 static bool nomtrr; 156 157 /* ------------------------------------------------------------------------- 158 * Hardware-specific funcions 159 * ------------------------------------------------------------------------- */ 160 161 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) 162 { 163 return inb(par->iobase + reg - 0x300); 164 } 165 166 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) 167 { 168 outb(val, par->iobase + reg - 0x300); 169 } 170 171 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) 172 { 173 vga_outb(par, GRA_I, idx); 174 wmb(); 175 vga_outb(par, GRA_D, val); 176 wmb(); 177 } 178 179 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) 180 { 181 vga_outb(par, SEQ_I, idx); 182 wmb(); 183 vga_outb(par, SEQ_D, val); 184 wmb(); 185 } 186 187 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) 188 { 189 vga_outb(par, SEQ_I, idx); 190 mb(); 191 return vga_inb(par, SEQ_D); 192 } 193 194 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) 195 { 196 vga_outb(par, CRT_I, idx); 197 wmb(); 198 vga_outb(par, CRT_D, val); 199 wmb(); 200 } 201 202 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) 203 { 204 vga_outb(par, CRT_I, idx); 205 mb(); 206 return vga_inb(par, CRT_D); 207 } 208 209 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val) 210 { 211 vga_inb(par, IS1_R); 212 vga_outb(par, ATT_IW, idx); 213 vga_outb(par, ATT_IW, val); 214 } 215 216 static inline void vga_disable_video(struct tdfx_par *par) 217 { 218 unsigned char s; 219 220 s = seq_inb(par, 0x01) | 0x20; 221 seq_outb(par, 0x00, 0x01); 222 seq_outb(par, 0x01, s); 223 seq_outb(par, 0x00, 0x03); 224 } 225 226 static inline void vga_enable_video(struct tdfx_par *par) 227 { 228 unsigned char s; 229 230 s = seq_inb(par, 0x01) & 0xdf; 231 seq_outb(par, 0x00, 0x01); 232 seq_outb(par, 0x01, s); 233 seq_outb(par, 0x00, 0x03); 234 } 235 236 static inline void vga_enable_palette(struct tdfx_par *par) 237 { 238 vga_inb(par, IS1_R); 239 mb(); 240 vga_outb(par, ATT_IW, 0x20); 241 } 242 243 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg) 244 { 245 return readl(par->regbase_virt + reg); 246 } 247 248 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val) 249 { 250 writel(val, par->regbase_virt + reg); 251 } 252 253 static inline void banshee_make_room(struct tdfx_par *par, int size) 254 { 255 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop 256 * won't quit if you ask for more. */ 257 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1) 258 cpu_relax(); 259 } 260 261 static int banshee_wait_idle(struct fb_info *info) 262 { 263 struct tdfx_par *par = info->par; 264 int i = 0; 265 266 banshee_make_room(par, 1); 267 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP); 268 269 do { 270 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0) 271 i++; 272 } while (i < 3); 273 274 return 0; 275 } 276 277 /* 278 * Set the color of a palette entry in 8bpp mode 279 */ 280 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c) 281 { 282 banshee_make_room(par, 2); 283 tdfx_outl(par, DACADDR, regno); 284 /* read after write makes it working */ 285 tdfx_inl(par, DACADDR); 286 tdfx_outl(par, DACDATA, c); 287 } 288 289 static u32 do_calc_pll(int freq, int *freq_out) 290 { 291 int m, n, k, best_m, best_n, best_k, best_error; 292 int fref = 14318; 293 294 best_error = freq; 295 best_n = best_m = best_k = 0; 296 297 for (k = 3; k >= 0; k--) { 298 for (m = 63; m >= 0; m--) { 299 /* 300 * Estimate value of n that produces target frequency 301 * with current m and k 302 */ 303 int n_estimated = ((freq * (m + 2) << k) / fref) - 2; 304 305 /* Search neighborhood of estimated n */ 306 for (n = max(0, n_estimated); 307 n <= min(255, n_estimated + 1); 308 n++) { 309 /* 310 * Calculate PLL freqency with current m, k and 311 * estimated n 312 */ 313 int f = (fref * (n + 2) / (m + 2)) >> k; 314 int error = abs(f - freq); 315 316 /* 317 * If this is the closest we've come to the 318 * target frequency then remember n, m and k 319 */ 320 if (error < best_error) { 321 best_error = error; 322 best_n = n; 323 best_m = m; 324 best_k = k; 325 } 326 } 327 } 328 } 329 330 n = best_n; 331 m = best_m; 332 k = best_k; 333 *freq_out = (fref * (n + 2) / (m + 2)) >> k; 334 335 return (n << 8) | (m << 2) | k; 336 } 337 338 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg) 339 { 340 struct tdfx_par *par = info->par; 341 int i; 342 343 banshee_wait_idle(info); 344 345 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01); 346 347 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */ 348 349 banshee_make_room(par, 3); 350 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF); 351 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001); 352 #if 0 353 tdfx_outl(par, PLLCTRL1, reg->mempll); 354 tdfx_outl(par, PLLCTRL2, reg->gfxpll); 355 #endif 356 tdfx_outl(par, PLLCTRL0, reg->vidpll); 357 358 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01); 359 360 for (i = 0; i < 5; i++) 361 seq_outb(par, i, reg->seq[i]); 362 363 for (i = 0; i < 25; i++) 364 crt_outb(par, i, reg->crt[i]); 365 366 for (i = 0; i < 9; i++) 367 gra_outb(par, i, reg->gra[i]); 368 369 for (i = 0; i < 21; i++) 370 att_outb(par, i, reg->att[i]); 371 372 crt_outb(par, 0x1a, reg->ext[0]); 373 crt_outb(par, 0x1b, reg->ext[1]); 374 375 vga_enable_palette(par); 376 vga_enable_video(par); 377 378 banshee_make_room(par, 9); 379 tdfx_outl(par, VGAINIT0, reg->vgainit0); 380 tdfx_outl(par, DACMODE, reg->dacmode); 381 tdfx_outl(par, VIDDESKSTRIDE, reg->stride); 382 tdfx_outl(par, HWCURPATADDR, reg->curspataddr); 383 384 tdfx_outl(par, VIDSCREENSIZE, reg->screensize); 385 tdfx_outl(par, VIDDESKSTART, reg->startaddr); 386 tdfx_outl(par, VIDPROCCFG, reg->vidcfg); 387 tdfx_outl(par, VGAINIT1, reg->vgainit1); 388 tdfx_outl(par, MISCINIT0, reg->miscinit0); 389 390 banshee_make_room(par, 8); 391 tdfx_outl(par, SRCBASE, reg->startaddr); 392 tdfx_outl(par, DSTBASE, reg->startaddr); 393 tdfx_outl(par, COMMANDEXTRA_2D, 0); 394 tdfx_outl(par, CLIP0MIN, 0); 395 tdfx_outl(par, CLIP0MAX, 0x0fff0fff); 396 tdfx_outl(par, CLIP1MIN, 0); 397 tdfx_outl(par, CLIP1MAX, 0x0fff0fff); 398 tdfx_outl(par, SRCXY, 0); 399 400 banshee_wait_idle(info); 401 } 402 403 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id) 404 { 405 u32 draminit0 = tdfx_inl(par, DRAMINIT0); 406 u32 draminit1 = tdfx_inl(par, DRAMINIT1); 407 u32 miscinit1; 408 int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4; 409 int chip_size; /* in MB */ 410 int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM; 411 412 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) { 413 /* Banshee/Voodoo3 */ 414 chip_size = 2; 415 if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE)) 416 chip_size = 1; 417 } else { 418 /* Voodoo4/5 */ 419 has_sgram = 0; 420 chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK; 421 chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT); 422 } 423 424 /* disable block writes for SDRAM */ 425 miscinit1 = tdfx_inl(par, MISCINIT1); 426 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS; 427 miscinit1 |= MISCINIT1_CLUT_INV; 428 429 banshee_make_room(par, 1); 430 tdfx_outl(par, MISCINIT1, miscinit1); 431 return num_chips * chip_size * 1024l * 1024; 432 } 433 434 /* ------------------------------------------------------------------------- */ 435 436 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 437 { 438 struct tdfx_par *par = info->par; 439 u32 lpitch; 440 441 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && 442 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { 443 DPRINTK("depth not supported: %u\n", var->bits_per_pixel); 444 return -EINVAL; 445 } 446 447 if (var->xres != var->xres_virtual) 448 var->xres_virtual = var->xres; 449 450 if (var->yres > var->yres_virtual) 451 var->yres_virtual = var->yres; 452 453 if (var->xoffset) { 454 DPRINTK("xoffset not supported\n"); 455 return -EINVAL; 456 } 457 var->yoffset = 0; 458 459 /* 460 * Banshee doesn't support interlace, but Voodoo4/5 and probably 461 * Voodoo3 do. 462 * no direct information about device id now? 463 * use max_pixclock for this... 464 */ 465 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) && 466 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) { 467 DPRINTK("interlace not supported\n"); 468 return -EINVAL; 469 } 470 471 if (info->monspecs.hfmax && info->monspecs.vfmax && 472 info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) { 473 DPRINTK("mode outside monitor's specs\n"); 474 return -EINVAL; 475 } 476 477 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */ 478 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); 479 480 if (var->xres < 320 || var->xres > 2048) { 481 DPRINTK("width not supported: %u\n", var->xres); 482 return -EINVAL; 483 } 484 485 if (var->yres < 200 || var->yres > 2048) { 486 DPRINTK("height not supported: %u\n", var->yres); 487 return -EINVAL; 488 } 489 490 if (lpitch * var->yres_virtual > info->fix.smem_len) { 491 var->yres_virtual = info->fix.smem_len / lpitch; 492 if (var->yres_virtual < var->yres) { 493 DPRINTK("no memory for screen (%ux%ux%u)\n", 494 var->xres, var->yres_virtual, 495 var->bits_per_pixel); 496 return -EINVAL; 497 } 498 } 499 500 if (!var->pixclock) 501 return -EINVAL; 502 503 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) { 504 DPRINTK("pixclock too high (%ldKHz)\n", 505 PICOS2KHZ(var->pixclock)); 506 return -EINVAL; 507 } 508 509 var->transp.offset = 0; 510 var->transp.length = 0; 511 switch (var->bits_per_pixel) { 512 case 8: 513 var->red.length = 8; 514 var->red.offset = 0; 515 var->green = var->red; 516 var->blue = var->red; 517 break; 518 case 16: 519 var->red.offset = 11; 520 var->red.length = 5; 521 var->green.offset = 5; 522 var->green.length = 6; 523 var->blue.offset = 0; 524 var->blue.length = 5; 525 break; 526 case 32: 527 var->transp.offset = 24; 528 var->transp.length = 8; 529 fallthrough; 530 case 24: 531 var->red.offset = 16; 532 var->green.offset = 8; 533 var->blue.offset = 0; 534 var->red.length = var->green.length = var->blue.length = 8; 535 break; 536 } 537 var->width = -1; 538 var->height = -1; 539 540 var->accel_flags = FB_ACCELF_TEXT; 541 542 DPRINTK("Checking graphics mode at %dx%d depth %d\n", 543 var->xres, var->yres, var->bits_per_pixel); 544 return 0; 545 } 546 547 static int tdfxfb_set_par(struct fb_info *info) 548 { 549 struct tdfx_par *par = info->par; 550 u32 hdispend = info->var.xres; 551 u32 hsyncsta = hdispend + info->var.right_margin; 552 u32 hsyncend = hsyncsta + info->var.hsync_len; 553 u32 htotal = hsyncend + info->var.left_margin; 554 u32 hd, hs, he, ht, hbs, hbe; 555 u32 vd, vs, ve, vt, vbs, vbe; 556 struct banshee_reg reg; 557 int fout, freq; 558 u32 wd; 559 u32 cpp = (info->var.bits_per_pixel + 7) >> 3; 560 561 memset(®, 0, sizeof(reg)); 562 563 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | 564 VIDCFG_CURS_X11 | 565 ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | 566 (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0); 567 568 /* PLL settings */ 569 freq = PICOS2KHZ(info->var.pixclock); 570 571 reg.vidcfg &= ~VIDCFG_2X; 572 573 if (freq > par->max_pixclock / 2) { 574 freq = freq > par->max_pixclock ? par->max_pixclock : freq; 575 reg.dacmode |= DACMODE_2X; 576 reg.vidcfg |= VIDCFG_2X; 577 hdispend >>= 1; 578 hsyncsta >>= 1; 579 hsyncend >>= 1; 580 htotal >>= 1; 581 } 582 583 wd = (hdispend >> 3) - 1; 584 hd = wd; 585 hs = (hsyncsta >> 3) - 1; 586 he = (hsyncend >> 3) - 1; 587 ht = (htotal >> 3) - 1; 588 hbs = hd; 589 hbe = ht; 590 591 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) { 592 vd = (info->var.yres << 1) - 1; 593 vs = vd + (info->var.lower_margin << 1); 594 ve = vs + (info->var.vsync_len << 1); 595 vt = ve + (info->var.upper_margin << 1) - 1; 596 reg.screensize = info->var.xres | (info->var.yres << 13); 597 reg.vidcfg |= VIDCFG_HALF_MODE; 598 reg.crt[VGA_CRTC_MAX_SCAN] = 0x80; 599 } else { 600 vd = info->var.yres - 1; 601 vs = vd + info->var.lower_margin; 602 ve = vs + info->var.vsync_len; 603 vt = ve + info->var.upper_margin - 1; 604 reg.screensize = info->var.xres | (info->var.yres << 12); 605 reg.vidcfg &= ~VIDCFG_HALF_MODE; 606 } 607 vbs = vd; 608 vbe = vt; 609 610 /* this is all pretty standard VGA register stuffing */ 611 reg.misc[0x00] = 0x0f | 612 (info->var.xres < 400 ? 0xa0 : 613 info->var.xres < 480 ? 0x60 : 614 info->var.xres < 768 ? 0xe0 : 0x20); 615 616 reg.gra[VGA_GFX_MODE] = 0x40; 617 reg.gra[VGA_GFX_MISC] = 0x05; 618 reg.gra[VGA_GFX_COMPARE_MASK] = 0x0f; 619 reg.gra[VGA_GFX_BIT_MASK] = 0xff; 620 621 reg.att[VGA_ATC_PALETTE0] = 0x00; 622 reg.att[VGA_ATC_PALETTE1] = 0x01; 623 reg.att[VGA_ATC_PALETTE2] = 0x02; 624 reg.att[VGA_ATC_PALETTE3] = 0x03; 625 reg.att[VGA_ATC_PALETTE4] = 0x04; 626 reg.att[VGA_ATC_PALETTE5] = 0x05; 627 reg.att[VGA_ATC_PALETTE6] = 0x06; 628 reg.att[VGA_ATC_PALETTE7] = 0x07; 629 reg.att[VGA_ATC_PALETTE8] = 0x08; 630 reg.att[VGA_ATC_PALETTE9] = 0x09; 631 reg.att[VGA_ATC_PALETTEA] = 0x0a; 632 reg.att[VGA_ATC_PALETTEB] = 0x0b; 633 reg.att[VGA_ATC_PALETTEC] = 0x0c; 634 reg.att[VGA_ATC_PALETTED] = 0x0d; 635 reg.att[VGA_ATC_PALETTEE] = 0x0e; 636 reg.att[VGA_ATC_PALETTEF] = 0x0f; 637 reg.att[VGA_ATC_MODE] = 0x41; 638 reg.att[VGA_ATC_PLANE_ENABLE] = 0x0f; 639 640 reg.seq[VGA_SEQ_RESET] = 0x03; 641 reg.seq[VGA_SEQ_CLOCK_MODE] = 0x01; /* fixme: clkdiv2? */ 642 reg.seq[VGA_SEQ_PLANE_WRITE] = 0x0f; 643 reg.seq[VGA_SEQ_CHARACTER_MAP] = 0x00; 644 reg.seq[VGA_SEQ_MEMORY_MODE] = 0x0e; 645 646 reg.crt[VGA_CRTC_H_TOTAL] = ht - 4; 647 reg.crt[VGA_CRTC_H_DISP] = hd; 648 reg.crt[VGA_CRTC_H_BLANK_START] = hbs; 649 reg.crt[VGA_CRTC_H_BLANK_END] = 0x80 | (hbe & 0x1f); 650 reg.crt[VGA_CRTC_H_SYNC_START] = hs; 651 reg.crt[VGA_CRTC_H_SYNC_END] = ((hbe & 0x20) << 2) | (he & 0x1f); 652 reg.crt[VGA_CRTC_V_TOTAL] = vt; 653 reg.crt[VGA_CRTC_OVERFLOW] = ((vs & 0x200) >> 2) | 654 ((vd & 0x200) >> 3) | 655 ((vt & 0x200) >> 4) | 0x10 | 656 ((vbs & 0x100) >> 5) | 657 ((vs & 0x100) >> 6) | 658 ((vd & 0x100) >> 7) | 659 ((vt & 0x100) >> 8); 660 reg.crt[VGA_CRTC_MAX_SCAN] |= 0x40 | ((vbs & 0x200) >> 4); 661 reg.crt[VGA_CRTC_V_SYNC_START] = vs; 662 reg.crt[VGA_CRTC_V_SYNC_END] = (ve & 0x0f) | 0x20; 663 reg.crt[VGA_CRTC_V_DISP_END] = vd; 664 reg.crt[VGA_CRTC_OFFSET] = wd; 665 reg.crt[VGA_CRTC_V_BLANK_START] = vbs; 666 reg.crt[VGA_CRTC_V_BLANK_END] = vbe + 1; 667 reg.crt[VGA_CRTC_MODE] = 0xc3; 668 reg.crt[VGA_CRTC_LINE_COMPARE] = 0xff; 669 670 /* Banshee's nonvga stuff */ 671 reg.ext[0x00] = (((ht & 0x100) >> 8) | 672 ((hd & 0x100) >> 6) | 673 ((hbs & 0x100) >> 4) | 674 ((hbe & 0x40) >> 1) | 675 ((hs & 0x100) >> 2) | 676 ((he & 0x20) << 2)); 677 reg.ext[0x01] = (((vt & 0x400) >> 10) | 678 ((vd & 0x400) >> 8) | 679 ((vbs & 0x400) >> 6) | 680 ((vbe & 0x400) >> 4)); 681 682 reg.vgainit0 = VGAINIT0_8BIT_DAC | 683 VGAINIT0_EXT_ENABLE | 684 VGAINIT0_WAKEUP_3C3 | 685 VGAINIT0_ALT_READBACK | 686 VGAINIT0_EXTSHIFTOUT; 687 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff; 688 689 if (hwcursor) 690 reg.curspataddr = info->fix.smem_len; 691 692 reg.cursloc = 0; 693 694 reg.cursc0 = 0; 695 reg.cursc1 = 0xffffff; 696 697 reg.stride = info->var.xres * cpp; 698 reg.startaddr = info->var.yoffset * reg.stride 699 + info->var.xoffset * cpp; 700 701 reg.vidpll = do_calc_pll(freq, &fout); 702 #if 0 703 reg.mempll = do_calc_pll(..., &fout); 704 reg.gfxpll = do_calc_pll(..., &fout); 705 #endif 706 707 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 708 reg.vidcfg |= VIDCFG_INTERLACE; 709 reg.miscinit0 = tdfx_inl(par, MISCINIT0); 710 711 #if defined(__BIG_ENDIAN) 712 switch (info->var.bits_per_pixel) { 713 case 8: 714 case 24: 715 reg.miscinit0 &= ~(1 << 30); 716 reg.miscinit0 &= ~(1 << 31); 717 break; 718 case 16: 719 reg.miscinit0 |= (1 << 30); 720 reg.miscinit0 |= (1 << 31); 721 break; 722 case 32: 723 reg.miscinit0 |= (1 << 30); 724 reg.miscinit0 &= ~(1 << 31); 725 break; 726 } 727 #endif 728 do_write_regs(info, ®); 729 730 /* Now change fb_fix_screeninfo according to changes in par */ 731 info->fix.line_length = reg.stride; 732 info->fix.visual = (info->var.bits_per_pixel == 8) 733 ? FB_VISUAL_PSEUDOCOLOR 734 : FB_VISUAL_TRUECOLOR; 735 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", 736 info->var.xres, info->var.yres, info->var.bits_per_pixel); 737 return 0; 738 } 739 740 /* A handy macro shamelessly pinched from matroxfb */ 741 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) 742 743 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green, 744 unsigned blue, unsigned transp, 745 struct fb_info *info) 746 { 747 struct tdfx_par *par = info->par; 748 u32 rgbcol; 749 750 if (regno >= info->cmap.len || regno > 255) 751 return 1; 752 753 /* grayscale works only partially under directcolor */ 754 if (info->var.grayscale) { 755 /* grayscale = 0.30*R + 0.59*G + 0.11*B */ 756 blue = (red * 77 + green * 151 + blue * 28) >> 8; 757 green = blue; 758 red = blue; 759 } 760 761 switch (info->fix.visual) { 762 case FB_VISUAL_PSEUDOCOLOR: 763 rgbcol = (((u32)red & 0xff00) << 8) | 764 (((u32)green & 0xff00) << 0) | 765 (((u32)blue & 0xff00) >> 8); 766 do_setpalentry(par, regno, rgbcol); 767 break; 768 /* Truecolor has no hardware color palettes. */ 769 case FB_VISUAL_TRUECOLOR: 770 if (regno < 16) { 771 rgbcol = (CNVT_TOHW(red, info->var.red.length) << 772 info->var.red.offset) | 773 (CNVT_TOHW(green, info->var.green.length) << 774 info->var.green.offset) | 775 (CNVT_TOHW(blue, info->var.blue.length) << 776 info->var.blue.offset) | 777 (CNVT_TOHW(transp, info->var.transp.length) << 778 info->var.transp.offset); 779 par->palette[regno] = rgbcol; 780 } 781 782 break; 783 default: 784 DPRINTK("bad depth %u\n", info->var.bits_per_pixel); 785 break; 786 } 787 788 return 0; 789 } 790 791 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */ 792 static int tdfxfb_blank(int blank, struct fb_info *info) 793 { 794 struct tdfx_par *par = info->par; 795 int vgablank = 1; 796 u32 dacmode = tdfx_inl(par, DACMODE); 797 798 dacmode &= ~(BIT(1) | BIT(3)); 799 800 switch (blank) { 801 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */ 802 vgablank = 0; 803 break; 804 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */ 805 break; 806 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */ 807 dacmode |= BIT(3); 808 break; 809 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */ 810 dacmode |= BIT(1); 811 break; 812 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */ 813 dacmode |= BIT(1) | BIT(3); 814 break; 815 } 816 817 banshee_make_room(par, 1); 818 tdfx_outl(par, DACMODE, dacmode); 819 if (vgablank) 820 vga_disable_video(par); 821 else 822 vga_enable_video(par); 823 return 0; 824 } 825 826 /* 827 * Set the starting position of the visible screen to var->yoffset 828 */ 829 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, 830 struct fb_info *info) 831 { 832 struct tdfx_par *par = info->par; 833 u32 addr = var->yoffset * info->fix.line_length; 834 835 if (nopan || var->xoffset) 836 return -EINVAL; 837 838 banshee_make_room(par, 1); 839 tdfx_outl(par, VIDDESKSTART, addr); 840 841 return 0; 842 } 843 844 #ifdef CONFIG_FB_3DFX_ACCEL 845 /* 846 * FillRect 2D command (solidfill or invert (via ROP_XOR)) 847 */ 848 static void tdfxfb_fillrect(struct fb_info *info, 849 const struct fb_fillrect *rect) 850 { 851 struct tdfx_par *par = info->par; 852 u32 bpp = info->var.bits_per_pixel; 853 u32 stride = info->fix.line_length; 854 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 855 int tdfx_rop; 856 u32 dx = rect->dx; 857 u32 dy = rect->dy; 858 u32 dstbase = 0; 859 860 if (rect->rop == ROP_COPY) 861 tdfx_rop = TDFX_ROP_COPY; 862 else 863 tdfx_rop = TDFX_ROP_XOR; 864 865 /* assume always rect->height < 4096 */ 866 if (dy + rect->height > 4095) { 867 dstbase = stride * dy; 868 dy = 0; 869 } 870 /* assume always rect->width < 4096 */ 871 if (dx + rect->width > 4095) { 872 dstbase += dx * bpp >> 3; 873 dx = 0; 874 } 875 banshee_make_room(par, 6); 876 tdfx_outl(par, DSTFORMAT, fmt); 877 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) { 878 tdfx_outl(par, COLORFORE, rect->color); 879 } else { /* FB_VISUAL_TRUECOLOR */ 880 tdfx_outl(par, COLORFORE, par->palette[rect->color]); 881 } 882 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24)); 883 tdfx_outl(par, DSTBASE, dstbase); 884 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16)); 885 tdfx_outl(par, LAUNCH_2D, dx | (dy << 16)); 886 } 887 888 /* 889 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) 890 */ 891 static void tdfxfb_copyarea(struct fb_info *info, 892 const struct fb_copyarea *area) 893 { 894 struct tdfx_par *par = info->par; 895 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy; 896 u32 bpp = info->var.bits_per_pixel; 897 u32 stride = info->fix.line_length; 898 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24); 899 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 900 u32 dstbase = 0; 901 u32 srcbase = 0; 902 903 /* assume always area->height < 4096 */ 904 if (sy + area->height > 4095) { 905 srcbase = stride * sy; 906 sy = 0; 907 } 908 /* assume always area->width < 4096 */ 909 if (sx + area->width > 4095) { 910 srcbase += sx * bpp >> 3; 911 sx = 0; 912 } 913 /* assume always area->height < 4096 */ 914 if (dy + area->height > 4095) { 915 dstbase = stride * dy; 916 dy = 0; 917 } 918 /* assume always area->width < 4096 */ 919 if (dx + area->width > 4095) { 920 dstbase += dx * bpp >> 3; 921 dx = 0; 922 } 923 924 if (area->sx <= area->dx) { 925 /* -X */ 926 blitcmd |= BIT(14); 927 sx += area->width - 1; 928 dx += area->width - 1; 929 } 930 if (area->sy <= area->dy) { 931 /* -Y */ 932 blitcmd |= BIT(15); 933 sy += area->height - 1; 934 dy += area->height - 1; 935 } 936 937 banshee_make_room(par, 8); 938 939 tdfx_outl(par, SRCFORMAT, fmt); 940 tdfx_outl(par, DSTFORMAT, fmt); 941 tdfx_outl(par, COMMAND_2D, blitcmd); 942 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16)); 943 tdfx_outl(par, DSTXY, dx | (dy << 16)); 944 tdfx_outl(par, SRCBASE, srcbase); 945 tdfx_outl(par, DSTBASE, dstbase); 946 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16)); 947 } 948 949 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image) 950 { 951 struct tdfx_par *par = info->par; 952 int size = image->height * ((image->width * image->depth + 7) >> 3); 953 int fifo_free; 954 int i, stride = info->fix.line_length; 955 u32 bpp = info->var.bits_per_pixel; 956 u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); 957 u8 *chardata = (u8 *) image->data; 958 u32 srcfmt; 959 u32 dx = image->dx; 960 u32 dy = image->dy; 961 u32 dstbase = 0; 962 963 if (image->depth != 1) { 964 #ifdef BROKEN_CODE 965 banshee_make_room(par, 6 + ((size + 3) >> 2)); 966 srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) | 967 0x400000; 968 #else 969 cfb_imageblit(info, image); 970 #endif 971 return; 972 } 973 banshee_make_room(par, 9); 974 switch (info->fix.visual) { 975 case FB_VISUAL_PSEUDOCOLOR: 976 tdfx_outl(par, COLORFORE, image->fg_color); 977 tdfx_outl(par, COLORBACK, image->bg_color); 978 break; 979 case FB_VISUAL_TRUECOLOR: 980 default: 981 tdfx_outl(par, COLORFORE, 982 par->palette[image->fg_color]); 983 tdfx_outl(par, COLORBACK, 984 par->palette[image->bg_color]); 985 } 986 #ifdef __BIG_ENDIAN 987 srcfmt = 0x400000 | BIT(20); 988 #else 989 srcfmt = 0x400000; 990 #endif 991 /* assume always image->height < 4096 */ 992 if (dy + image->height > 4095) { 993 dstbase = stride * dy; 994 dy = 0; 995 } 996 /* assume always image->width < 4096 */ 997 if (dx + image->width > 4095) { 998 dstbase += dx * bpp >> 3; 999 dx = 0; 1000 } 1001 1002 tdfx_outl(par, DSTBASE, dstbase); 1003 tdfx_outl(par, SRCXY, 0); 1004 tdfx_outl(par, DSTXY, dx | (dy << 16)); 1005 tdfx_outl(par, COMMAND_2D, 1006 COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24)); 1007 tdfx_outl(par, SRCFORMAT, srcfmt); 1008 tdfx_outl(par, DSTFORMAT, dstfmt); 1009 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16)); 1010 1011 /* A count of how many free FIFO entries we've requested. 1012 * When this goes negative, we need to request more. */ 1013 fifo_free = 0; 1014 1015 /* Send four bytes at a time of data */ 1016 for (i = (size >> 2); i > 0; i--) { 1017 if (--fifo_free < 0) { 1018 fifo_free = 31; 1019 banshee_make_room(par, fifo_free); 1020 } 1021 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata); 1022 chardata += 4; 1023 } 1024 1025 /* Send the leftovers now */ 1026 banshee_make_room(par, 3); 1027 switch (size % 4) { 1028 case 0: 1029 break; 1030 case 1: 1031 tdfx_outl(par, LAUNCH_2D, *chardata); 1032 break; 1033 case 2: 1034 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata); 1035 break; 1036 case 3: 1037 tdfx_outl(par, LAUNCH_2D, 1038 *(u16 *)chardata | (chardata[3] << 24)); 1039 break; 1040 } 1041 } 1042 #endif /* CONFIG_FB_3DFX_ACCEL */ 1043 1044 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1045 { 1046 struct tdfx_par *par = info->par; 1047 u32 vidcfg; 1048 1049 if (!hwcursor) 1050 return -EINVAL; /* just to force soft_cursor() call */ 1051 1052 /* Too large of a cursor or wrong bpp :-( */ 1053 if (cursor->image.width > 64 || 1054 cursor->image.height > 64 || 1055 cursor->image.depth > 1) 1056 return -EINVAL; 1057 1058 vidcfg = tdfx_inl(par, VIDPROCCFG); 1059 if (cursor->enable) 1060 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE); 1061 else 1062 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE); 1063 1064 /* 1065 * If the cursor is not be changed this means either we want the 1066 * current cursor state (if enable is set) or we want to query what 1067 * we can do with the cursor (if enable is not set) 1068 */ 1069 if (!cursor->set) 1070 return 0; 1071 1072 /* fix cursor color - XFree86 forgets to restore it properly */ 1073 if (cursor->set & FB_CUR_SETCMAP) { 1074 struct fb_cmap cmap = info->cmap; 1075 u32 bg_idx = cursor->image.bg_color; 1076 u32 fg_idx = cursor->image.fg_color; 1077 unsigned long bg_color, fg_color; 1078 1079 fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) | 1080 (((u32)cmap.green[fg_idx] & 0xff00) << 0) | 1081 (((u32)cmap.blue[fg_idx] & 0xff00) >> 8); 1082 bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) | 1083 (((u32)cmap.green[bg_idx] & 0xff00) << 0) | 1084 (((u32)cmap.blue[bg_idx] & 0xff00) >> 8); 1085 banshee_make_room(par, 2); 1086 tdfx_outl(par, HWCURC0, bg_color); 1087 tdfx_outl(par, HWCURC1, fg_color); 1088 } 1089 1090 if (cursor->set & FB_CUR_SETPOS) { 1091 int x = cursor->image.dx; 1092 int y = cursor->image.dy - info->var.yoffset; 1093 1094 x += 63; 1095 y += 63; 1096 banshee_make_room(par, 1); 1097 tdfx_outl(par, HWCURLOC, (y << 16) + x); 1098 } 1099 if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) { 1100 /* 1101 * Voodoo 3 and above cards use 2 monochrome cursor patterns. 1102 * The reason is so the card can fetch 8 words at a time 1103 * and are stored on chip for use for the next 8 scanlines. 1104 * This reduces the number of times for access to draw the 1105 * cursor for each screen refresh. 1106 * Each pattern is a bitmap of 64 bit wide and 64 bit high 1107 * (total of 8192 bits or 1024 bytes). The two patterns are 1108 * stored in such a way that pattern 0 always resides in the 1109 * lower half (least significant 64 bits) of a 128 bit word 1110 * and pattern 1 the upper half. If you examine the data of 1111 * the cursor image the graphics card uses then from the 1112 * beginning you see line one of pattern 0, line one of 1113 * pattern 1, line two of pattern 0, line two of pattern 1, 1114 * etc etc. The linear stride for the cursor is always 16 bytes 1115 * (128 bits) which is the maximum cursor width times two for 1116 * the two monochrome patterns. 1117 */ 1118 u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len; 1119 u8 *bitmap = (u8 *)cursor->image.data; 1120 u8 *mask = (u8 *)cursor->mask; 1121 int i; 1122 1123 fb_memset_io(cursorbase, 0, 1024); 1124 1125 for (i = 0; i < cursor->image.height; i++) { 1126 int h = 0; 1127 int j = (cursor->image.width + 7) >> 3; 1128 1129 for (; j > 0; j--) { 1130 u8 data = *mask ^ *bitmap; 1131 if (cursor->rop == ROP_COPY) 1132 data = *mask & *bitmap; 1133 /* Pattern 0. Copy the cursor mask to it */ 1134 fb_writeb(*mask, cursorbase + h); 1135 mask++; 1136 /* Pattern 1. Copy the cursor bitmap to it */ 1137 fb_writeb(data, cursorbase + h + 8); 1138 bitmap++; 1139 h++; 1140 } 1141 cursorbase += 16; 1142 } 1143 } 1144 return 0; 1145 } 1146 1147 static const struct fb_ops tdfxfb_ops = { 1148 .owner = THIS_MODULE, 1149 __FB_DEFAULT_IOMEM_OPS_RDWR, 1150 .fb_check_var = tdfxfb_check_var, 1151 .fb_set_par = tdfxfb_set_par, 1152 .fb_setcolreg = tdfxfb_setcolreg, 1153 .fb_blank = tdfxfb_blank, 1154 .fb_pan_display = tdfxfb_pan_display, 1155 .fb_sync = banshee_wait_idle, 1156 .fb_cursor = tdfxfb_cursor, 1157 #ifdef CONFIG_FB_3DFX_ACCEL 1158 .fb_fillrect = tdfxfb_fillrect, 1159 .fb_copyarea = tdfxfb_copyarea, 1160 .fb_imageblit = tdfxfb_imageblit, 1161 #else 1162 __FB_DEFAULT_IOMEM_OPS_DRAW, 1163 #endif 1164 __FB_DEFAULT_IOMEM_OPS_MMAP, 1165 }; 1166 1167 #ifdef CONFIG_FB_3DFX_I2C 1168 /* The voo GPIO registers don't have individual masks for each bit 1169 so we always have to read before writing. */ 1170 1171 static void tdfxfb_i2c_setscl(void *data, int val) 1172 { 1173 struct tdfxfb_i2c_chan *chan = data; 1174 struct tdfx_par *par = chan->par; 1175 unsigned int r; 1176 1177 r = tdfx_inl(par, VIDSERPARPORT); 1178 if (val) 1179 r |= I2C_SCL_OUT; 1180 else 1181 r &= ~I2C_SCL_OUT; 1182 tdfx_outl(par, VIDSERPARPORT, r); 1183 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1184 } 1185 1186 static void tdfxfb_i2c_setsda(void *data, int val) 1187 { 1188 struct tdfxfb_i2c_chan *chan = data; 1189 struct tdfx_par *par = chan->par; 1190 unsigned int r; 1191 1192 r = tdfx_inl(par, VIDSERPARPORT); 1193 if (val) 1194 r |= I2C_SDA_OUT; 1195 else 1196 r &= ~I2C_SDA_OUT; 1197 tdfx_outl(par, VIDSERPARPORT, r); 1198 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1199 } 1200 1201 /* The GPIO pins are open drain, so the pins always remain outputs. 1202 We rely on the i2c-algo-bit routines to set the pins high before 1203 reading the input from other chips. */ 1204 1205 static int tdfxfb_i2c_getscl(void *data) 1206 { 1207 struct tdfxfb_i2c_chan *chan = data; 1208 struct tdfx_par *par = chan->par; 1209 1210 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN)); 1211 } 1212 1213 static int tdfxfb_i2c_getsda(void *data) 1214 { 1215 struct tdfxfb_i2c_chan *chan = data; 1216 struct tdfx_par *par = chan->par; 1217 1218 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN)); 1219 } 1220 1221 static void tdfxfb_ddc_setscl(void *data, int val) 1222 { 1223 struct tdfxfb_i2c_chan *chan = data; 1224 struct tdfx_par *par = chan->par; 1225 unsigned int r; 1226 1227 r = tdfx_inl(par, VIDSERPARPORT); 1228 if (val) 1229 r |= DDC_SCL_OUT; 1230 else 1231 r &= ~DDC_SCL_OUT; 1232 tdfx_outl(par, VIDSERPARPORT, r); 1233 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1234 } 1235 1236 static void tdfxfb_ddc_setsda(void *data, int val) 1237 { 1238 struct tdfxfb_i2c_chan *chan = data; 1239 struct tdfx_par *par = chan->par; 1240 unsigned int r; 1241 1242 r = tdfx_inl(par, VIDSERPARPORT); 1243 if (val) 1244 r |= DDC_SDA_OUT; 1245 else 1246 r &= ~DDC_SDA_OUT; 1247 tdfx_outl(par, VIDSERPARPORT, r); 1248 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */ 1249 } 1250 1251 static int tdfxfb_ddc_getscl(void *data) 1252 { 1253 struct tdfxfb_i2c_chan *chan = data; 1254 struct tdfx_par *par = chan->par; 1255 1256 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN)); 1257 } 1258 1259 static int tdfxfb_ddc_getsda(void *data) 1260 { 1261 struct tdfxfb_i2c_chan *chan = data; 1262 struct tdfx_par *par = chan->par; 1263 1264 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN)); 1265 } 1266 1267 static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name, 1268 struct device *dev) 1269 { 1270 int rc; 1271 1272 strscpy(chan->adapter.name, name, sizeof(chan->adapter.name)); 1273 chan->adapter.owner = THIS_MODULE; 1274 chan->adapter.algo_data = &chan->algo; 1275 chan->adapter.dev.parent = dev; 1276 chan->algo.setsda = tdfxfb_ddc_setsda; 1277 chan->algo.setscl = tdfxfb_ddc_setscl; 1278 chan->algo.getsda = tdfxfb_ddc_getsda; 1279 chan->algo.getscl = tdfxfb_ddc_getscl; 1280 chan->algo.udelay = 10; 1281 chan->algo.timeout = msecs_to_jiffies(500); 1282 chan->algo.data = chan; 1283 1284 i2c_set_adapdata(&chan->adapter, chan); 1285 1286 rc = i2c_bit_add_bus(&chan->adapter); 1287 if (rc == 0) 1288 DPRINTK("I2C bus %s registered.\n", name); 1289 else 1290 chan->par = NULL; 1291 1292 return rc; 1293 } 1294 1295 static int tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, const char *name, 1296 struct device *dev) 1297 { 1298 int rc; 1299 1300 strscpy(chan->adapter.name, name, sizeof(chan->adapter.name)); 1301 chan->adapter.owner = THIS_MODULE; 1302 chan->adapter.algo_data = &chan->algo; 1303 chan->adapter.dev.parent = dev; 1304 chan->algo.setsda = tdfxfb_i2c_setsda; 1305 chan->algo.setscl = tdfxfb_i2c_setscl; 1306 chan->algo.getsda = tdfxfb_i2c_getsda; 1307 chan->algo.getscl = tdfxfb_i2c_getscl; 1308 chan->algo.udelay = 10; 1309 chan->algo.timeout = msecs_to_jiffies(500); 1310 chan->algo.data = chan; 1311 1312 i2c_set_adapdata(&chan->adapter, chan); 1313 1314 rc = i2c_bit_add_bus(&chan->adapter); 1315 if (rc == 0) 1316 DPRINTK("I2C bus %s registered.\n", name); 1317 else 1318 chan->par = NULL; 1319 1320 return rc; 1321 } 1322 1323 static void tdfxfb_create_i2c_busses(struct fb_info *info) 1324 { 1325 struct tdfx_par *par = info->par; 1326 1327 tdfx_outl(par, VIDINFORMAT, 0x8160); 1328 tdfx_outl(par, VIDSERPARPORT, 0xcffc0020); 1329 1330 par->chan[0].par = par; 1331 par->chan[1].par = par; 1332 1333 tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->device); 1334 tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->device); 1335 } 1336 1337 static void tdfxfb_delete_i2c_busses(struct tdfx_par *par) 1338 { 1339 if (par->chan[0].par) 1340 i2c_del_adapter(&par->chan[0].adapter); 1341 par->chan[0].par = NULL; 1342 1343 if (par->chan[1].par) 1344 i2c_del_adapter(&par->chan[1].adapter); 1345 par->chan[1].par = NULL; 1346 } 1347 1348 static int tdfxfb_probe_i2c_connector(struct tdfx_par *par, 1349 struct fb_monspecs *specs) 1350 { 1351 u8 *edid = NULL; 1352 1353 DPRINTK("Probe DDC Bus\n"); 1354 if (par->chan[0].par) 1355 edid = fb_ddc_read(&par->chan[0].adapter); 1356 1357 if (edid) { 1358 fb_edid_to_monspecs(edid, specs); 1359 kfree(edid); 1360 return 0; 1361 } 1362 return 1; 1363 } 1364 #endif /* CONFIG_FB_3DFX_I2C */ 1365 1366 /** 1367 * tdfxfb_probe - Device Initializiation 1368 * 1369 * @pdev: PCI Device to initialize 1370 * @id: PCI Device ID 1371 * 1372 * Initializes and allocates resources for PCI device @pdev. 1373 * 1374 */ 1375 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1376 { 1377 struct tdfx_par *default_par; 1378 struct fb_info *info; 1379 int err, lpitch; 1380 struct fb_monspecs *specs; 1381 bool found; 1382 1383 err = aperture_remove_conflicting_pci_devices(pdev, "tdfxfb"); 1384 if (err) 1385 return err; 1386 1387 err = pci_enable_device(pdev); 1388 if (err) { 1389 printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err); 1390 return err; 1391 } 1392 1393 info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev); 1394 1395 if (!info) 1396 return -ENOMEM; 1397 1398 default_par = info->par; 1399 info->fix = tdfx_fix; 1400 1401 /* Configure the default fb_fix_screeninfo first */ 1402 switch (pdev->device) { 1403 case PCI_DEVICE_ID_3DFX_BANSHEE: 1404 strcpy(info->fix.id, "3Dfx Banshee"); 1405 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK; 1406 break; 1407 case PCI_DEVICE_ID_3DFX_VOODOO3: 1408 strcpy(info->fix.id, "3Dfx Voodoo3"); 1409 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK; 1410 break; 1411 case PCI_DEVICE_ID_3DFX_VOODOO5: 1412 strcpy(info->fix.id, "3Dfx Voodoo5"); 1413 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK; 1414 break; 1415 } 1416 1417 info->fix.mmio_start = pci_resource_start(pdev, 0); 1418 info->fix.mmio_len = pci_resource_len(pdev, 0); 1419 if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len, 1420 "tdfx regbase")) { 1421 printk(KERN_ERR "tdfxfb: Can't reserve regbase\n"); 1422 goto out_err; 1423 } 1424 1425 default_par->regbase_virt = 1426 ioremap(info->fix.mmio_start, info->fix.mmio_len); 1427 if (!default_par->regbase_virt) { 1428 printk(KERN_ERR "fb: Can't remap %s register area.\n", 1429 info->fix.id); 1430 goto out_err_regbase; 1431 } 1432 1433 info->fix.smem_start = pci_resource_start(pdev, 1); 1434 info->fix.smem_len = do_lfb_size(default_par, pdev->device); 1435 if (!info->fix.smem_len) { 1436 printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id); 1437 goto out_err_regbase; 1438 } 1439 1440 if (!request_mem_region(info->fix.smem_start, 1441 pci_resource_len(pdev, 1), "tdfx smem")) { 1442 printk(KERN_ERR "tdfxfb: Can't reserve smem\n"); 1443 goto out_err_regbase; 1444 } 1445 1446 info->screen_base = ioremap_wc(info->fix.smem_start, 1447 info->fix.smem_len); 1448 if (!info->screen_base) { 1449 printk(KERN_ERR "fb: Can't remap %s framebuffer.\n", 1450 info->fix.id); 1451 goto out_err_screenbase; 1452 } 1453 1454 default_par->iobase = pci_resource_start(pdev, 2); 1455 1456 if (!request_region(pci_resource_start(pdev, 2), 1457 pci_resource_len(pdev, 2), "tdfx iobase")) { 1458 printk(KERN_ERR "tdfxfb: Can't reserve iobase\n"); 1459 goto out_err_screenbase; 1460 } 1461 1462 printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id, 1463 info->fix.smem_len >> 10); 1464 1465 if (!nomtrr) 1466 default_par->wc_cookie= arch_phys_wc_add(info->fix.smem_start, 1467 info->fix.smem_len); 1468 1469 info->fix.ypanstep = nopan ? 0 : 1; 1470 info->fix.ywrapstep = nowrap ? 0 : 1; 1471 1472 info->fbops = &tdfxfb_ops; 1473 info->pseudo_palette = default_par->palette; 1474 info->flags = FBINFO_HWACCEL_YPAN; 1475 #ifdef CONFIG_FB_3DFX_ACCEL 1476 info->flags |= FBINFO_HWACCEL_FILLRECT | 1477 FBINFO_HWACCEL_COPYAREA | 1478 FBINFO_HWACCEL_IMAGEBLIT | 1479 FBINFO_READS_FAST; 1480 #endif 1481 /* reserve 8192 bits for cursor */ 1482 /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */ 1483 if (hwcursor) 1484 info->fix.smem_len = (info->fix.smem_len - 1024) & 1485 (PAGE_MASK << 1); 1486 specs = &info->monspecs; 1487 found = false; 1488 info->var.bits_per_pixel = 8; 1489 #ifdef CONFIG_FB_3DFX_I2C 1490 tdfxfb_create_i2c_busses(info); 1491 err = tdfxfb_probe_i2c_connector(default_par, specs); 1492 1493 if (!err) { 1494 if (specs->modedb == NULL) 1495 DPRINTK("Unable to get Mode Database\n"); 1496 else { 1497 const struct fb_videomode *m; 1498 1499 fb_videomode_to_modelist(specs->modedb, 1500 specs->modedb_len, 1501 &info->modelist); 1502 m = fb_find_best_display(specs, &info->modelist); 1503 if (m) { 1504 fb_videomode_to_var(&info->var, m); 1505 /* fill all other info->var's fields */ 1506 if (tdfxfb_check_var(&info->var, info) < 0) 1507 info->var = tdfx_var; 1508 else 1509 found = true; 1510 } 1511 } 1512 } 1513 #endif 1514 if (!mode_option && !found) 1515 mode_option = "640x480@60"; 1516 1517 if (mode_option) { 1518 err = fb_find_mode(&info->var, info, mode_option, 1519 specs->modedb, specs->modedb_len, 1520 NULL, info->var.bits_per_pixel); 1521 if (!err || err == 4) 1522 info->var = tdfx_var; 1523 } 1524 1525 if (found) { 1526 fb_destroy_modedb(specs->modedb); 1527 specs->modedb = NULL; 1528 } 1529 1530 /* maximize virtual vertical length */ 1531 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3); 1532 info->var.yres_virtual = info->fix.smem_len / lpitch; 1533 if (info->var.yres_virtual < info->var.yres) 1534 goto out_err_iobase; 1535 1536 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { 1537 printk(KERN_ERR "tdfxfb: Can't allocate color map\n"); 1538 goto out_err_iobase; 1539 } 1540 1541 if (register_framebuffer(info) < 0) { 1542 printk(KERN_ERR "tdfxfb: can't register framebuffer\n"); 1543 fb_dealloc_cmap(&info->cmap); 1544 goto out_err_iobase; 1545 } 1546 /* 1547 * Our driver data 1548 */ 1549 pci_set_drvdata(pdev, info); 1550 return 0; 1551 1552 out_err_iobase: 1553 #ifdef CONFIG_FB_3DFX_I2C 1554 tdfxfb_delete_i2c_busses(default_par); 1555 #endif 1556 arch_phys_wc_del(default_par->wc_cookie); 1557 release_region(pci_resource_start(pdev, 2), 1558 pci_resource_len(pdev, 2)); 1559 out_err_screenbase: 1560 if (info->screen_base) 1561 iounmap(info->screen_base); 1562 release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1)); 1563 out_err_regbase: 1564 /* 1565 * Cleanup after anything that was remapped/allocated. 1566 */ 1567 if (default_par->regbase_virt) 1568 iounmap(default_par->regbase_virt); 1569 release_mem_region(info->fix.mmio_start, info->fix.mmio_len); 1570 out_err: 1571 framebuffer_release(info); 1572 return -ENXIO; 1573 } 1574 1575 #ifndef MODULE 1576 static void __init tdfxfb_setup(char *options) 1577 { 1578 char *this_opt; 1579 1580 if (!options || !*options) 1581 return; 1582 1583 while ((this_opt = strsep(&options, ",")) != NULL) { 1584 if (!*this_opt) 1585 continue; 1586 if (!strcmp(this_opt, "nopan")) { 1587 nopan = 1; 1588 } else if (!strcmp(this_opt, "nowrap")) { 1589 nowrap = 1; 1590 } else if (!strncmp(this_opt, "hwcursor=", 9)) { 1591 hwcursor = simple_strtoul(this_opt + 9, NULL, 0); 1592 } else if (!strncmp(this_opt, "nomtrr", 6)) { 1593 nomtrr = 1; 1594 } else { 1595 mode_option = this_opt; 1596 } 1597 } 1598 } 1599 #endif 1600 1601 /** 1602 * tdfxfb_remove - Device removal 1603 * 1604 * @pdev: PCI Device to cleanup 1605 * 1606 * Releases all resources allocated during the course of the driver's 1607 * lifetime for the PCI device @pdev. 1608 * 1609 */ 1610 static void tdfxfb_remove(struct pci_dev *pdev) 1611 { 1612 struct fb_info *info = pci_get_drvdata(pdev); 1613 struct tdfx_par *par = info->par; 1614 1615 unregister_framebuffer(info); 1616 #ifdef CONFIG_FB_3DFX_I2C 1617 tdfxfb_delete_i2c_busses(par); 1618 #endif 1619 arch_phys_wc_del(par->wc_cookie); 1620 iounmap(par->regbase_virt); 1621 iounmap(info->screen_base); 1622 1623 /* Clean up after reserved regions */ 1624 release_region(pci_resource_start(pdev, 2), 1625 pci_resource_len(pdev, 2)); 1626 release_mem_region(pci_resource_start(pdev, 1), 1627 pci_resource_len(pdev, 1)); 1628 release_mem_region(pci_resource_start(pdev, 0), 1629 pci_resource_len(pdev, 0)); 1630 fb_dealloc_cmap(&info->cmap); 1631 framebuffer_release(info); 1632 } 1633 1634 static int __init tdfxfb_init(void) 1635 { 1636 #ifndef MODULE 1637 char *option = NULL; 1638 #endif 1639 1640 if (fb_modesetting_disabled("tdfxfb")) 1641 return -ENODEV; 1642 1643 #ifndef MODULE 1644 if (fb_get_options("tdfxfb", &option)) 1645 return -ENODEV; 1646 1647 tdfxfb_setup(option); 1648 #endif 1649 return pci_register_driver(&tdfxfb_driver); 1650 } 1651 1652 static void __exit tdfxfb_exit(void) 1653 { 1654 pci_unregister_driver(&tdfxfb_driver); 1655 } 1656 1657 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>"); 1658 MODULE_DESCRIPTION("3Dfx framebuffer device driver"); 1659 MODULE_LICENSE("GPL"); 1660 1661 module_param(hwcursor, int, 0644); 1662 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " 1663 "(1=enable, 0=disable, default=1)"); 1664 module_param(mode_option, charp, 0); 1665 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); 1666 module_param(nomtrr, bool, 0); 1667 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)"); 1668 1669 module_init(tdfxfb_init); 1670 module_exit(tdfxfb_exit); 1671