1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/soc/bcm2835-pm.h> 4 5/ { 6 compatible = "brcm,bcm2712"; 7 8 #address-cells = <2>; 9 #size-cells = <2>; 10 11 interrupt-parent = <&gicv2>; 12 13 arm-pmu { 14 compatible = "arm,cortex-a76-pmu"; 15 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 16 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 17 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 18 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 19 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 20 }; 21 22 clocks { 23 /* The oscillator is the root of the clock tree. */ 24 clk_osc: clk-osc { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-output-names = "osc"; 28 clock-frequency = <54000000>; 29 }; 30 31 clk_vpu: clk-vpu { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <750000000>; 35 clock-output-names = "vpu-clock"; 36 }; 37 38 clk_uart: clk-uart { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <9216000>; 42 clock-output-names = "uart-clock"; 43 }; 44 45 clk_emmc2: clk-emmc2 { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <200000000>; 49 clock-output-names = "emmc2-clock"; 50 }; 51 52 clk_sw_baud: clk-sw-baud { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <96000000>; 56 clock-output-names = "sw-baud"; 57 }; 58 59 clk_usb: clk-usb { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <480000000>; 63 clock-output-names = "otg"; 64 }; 65 }; 66 67 cpus: cpus { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 /* Source for L1 d/i cache-line-size, cache-sets, cache-size 72 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en 73 * Source for L2 cache-line-size and cache-sets: 74 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en 75 * and for cache-size: 76 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 77 */ 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a76"; 81 reg = <0x000>; 82 enable-method = "psci"; 83 d-cache-size = <0x10000>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 86 i-cache-size = <0x10000>; 87 i-cache-line-size = <64>; 88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 89 next-level-cache = <&l2_cache_l0>; 90 91 l2_cache_l0: l2-cache { 92 compatible = "cache"; 93 cache-size = <0x80000>; 94 cache-line-size = <64>; 95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_cache>; 99 }; 100 }; 101 102 cpu1: cpu@1 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x100>; 106 enable-method = "psci"; 107 d-cache-size = <0x10000>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 110 i-cache-size = <0x10000>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 113 next-level-cache = <&l2_cache_l1>; 114 115 l2_cache_l1: l2-cache { 116 compatible = "cache"; 117 cache-size = <0x80000>; 118 cache-line-size = <64>; 119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_cache>; 123 }; 124 }; 125 126 cpu2: cpu@2 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a76"; 129 reg = <0x200>; 130 enable-method = "psci"; 131 d-cache-size = <0x10000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 134 i-cache-size = <0x10000>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 137 next-level-cache = <&l2_cache_l2>; 138 139 l2_cache_l2: l2-cache { 140 compatible = "cache"; 141 cache-size = <0x80000>; 142 cache-line-size = <64>; 143 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&l3_cache>; 147 }; 148 }; 149 150 cpu3: cpu@3 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a76"; 153 reg = <0x300>; 154 enable-method = "psci"; 155 d-cache-size = <0x10000>; 156 d-cache-line-size = <64>; 157 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 158 i-cache-size = <0x10000>; 159 i-cache-line-size = <64>; 160 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 161 next-level-cache = <&l2_cache_l3>; 162 163 l2_cache_l3: l2-cache { 164 compatible = "cache"; 165 cache-size = <0x80000>; 166 cache-line-size = <64>; 167 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 168 cache-level = <2>; 169 cache-unified; 170 next-level-cache = <&l3_cache>; 171 }; 172 }; 173 174 /* Source for cache-line-size and cache-sets: 175 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en 176 * Source for cache-size: 177 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 178 */ 179 l3_cache: l3-cache { 180 compatible = "cache"; 181 cache-size = <0x200000>; 182 cache-line-size = <64>; 183 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set 184 cache-level = <3>; 185 cache-unified; 186 }; 187 }; 188 189 psci { 190 method = "smc"; 191 compatible = "arm,psci-1.0", "arm,psci-0.2"; 192 }; 193 194 rmem: reserved-memory { 195 ranges; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 199 atf@0 { 200 reg = <0x0 0x0 0x0 0x80000>; 201 no-map; 202 }; 203 204 cma: linux,cma { 205 compatible = "shared-dma-pool"; 206 size = <0x0 0x4000000>; /* 64MB */ 207 reusable; 208 linux,cma-default; 209 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; 210 }; 211 }; 212 213 soc: soc@107c000000 { 214 compatible = "simple-bus"; 215 ranges = <0x00000000 0x10 0x00000000 0x80000000>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 219 pcie_rescal: reset-controller@119500 { 220 compatible = "brcm,bcm7216-pcie-sata-rescal"; 221 reg = <0x00119500 0x10>; 222 #reset-cells = <0>; 223 }; 224 225 sdio1: mmc@fff000 { 226 compatible = "brcm,bcm2712-sdhci", 227 "brcm,sdhci-brcmstb"; 228 reg = <0x00fff000 0x260>, 229 <0x00fff400 0x200>; 230 reg-names = "host", "cfg"; 231 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&clk_emmc2>; 233 clock-names = "sw_sdio"; 234 mmc-ddr-3_3v; 235 }; 236 237 bcm_reset: reset-controller@1504318 { 238 compatible = "brcm,brcmstb-reset"; 239 reg = <0x01504318 0x30>; 240 #reset-cells = <1>; 241 }; 242 243 system_timer: timer@7c003000 { 244 compatible = "brcm,bcm2835-system-timer"; 245 reg = <0x7c003000 0x1000>; 246 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 250 clock-frequency = <1000000>; 251 }; 252 253 mailbox: mailbox@7c013880 { 254 compatible = "brcm,bcm2835-mbox"; 255 reg = <0x7c013880 0x40>; 256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 257 #mbox-cells = <0>; 258 }; 259 260 uart10: serial@7d001000 { 261 compatible = "arm,pl011", "arm,primecell"; 262 reg = <0x7d001000 0x200>; 263 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&clk_uart>, <&clk_vpu>; 265 clock-names = "uartclk", "apb_pclk"; 266 arm,primecell-periphid = <0x00341011>; 267 status = "disabled"; 268 }; 269 270 pm: watchdog@7d200000 { 271 compatible = "brcm,bcm2712-pm", "brcm,bcm2835-pm-wdt"; 272 reg = <0x7d200000 0x604>; 273 reg-names = "pm"; 274 #power-domain-cells = <1>; 275 #reset-cells = <1>; 276 system-power-controller; 277 }; 278 279 pinctrl: pinctrl@7d504100 { 280 compatible = "brcm,bcm2712c0-pinctrl"; 281 reg = <0x7d504100 0x30>; 282 }; 283 284 gio: gpio@7d508500 { 285 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 286 reg = <0x7d508500 0x40>; 287 interrupt-parent = <&main_irq>; 288 interrupts = <0>; 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 brcm,gpio-bank-widths = <32 22>; 294 }; 295 296 uarta: serial@7d50c000 { 297 compatible = "brcm,bcm7271-uart"; 298 reg = <0x7d50c000 0x20>; 299 reg-names = "uart"; 300 clocks = <&clk_sw_baud>; 301 clock-names = "sw_baud"; 302 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 303 interrupt-names = "uart"; 304 status = "disabled"; 305 }; 306 307 pinctrl_aon: pinctrl@7d510700 { 308 compatible = "brcm,bcm2712c0-aon-pinctrl"; 309 reg = <0x7d510700 0x20>; 310 }; 311 312 random: rng@7d208000 { 313 compatible = "brcm,bcm2711-rng200"; 314 reg = <0x7d208000 0x28>; 315 status = "okay"; 316 }; 317 318 interrupt-controller@7d517000 { 319 compatible = "brcm,bcm7271-l2-intc"; 320 reg = <0x7d517000 0x10>; 321 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 322 interrupt-controller; 323 #interrupt-cells = <1>; 324 }; 325 326 gio_aon: gpio@7d517c00 { 327 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 328 reg = <0x7d517c00 0x40>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 brcm,gpio-bank-widths = <17 6>; 332 /* The lack of 'interrupt-controller' property here is intended: 333 * don't use GIO_AON as an interrupt controller because it will 334 * clash with the firmware monitoring the PMIC interrupt via the VPU. 335 */ 336 }; 337 338 sdio2: mmc@1100000 { 339 compatible = "brcm,bcm2712-sdhci", 340 "brcm,sdhci-brcmstb"; 341 reg = <0x01100000 0x260>, 342 <0x01100400 0x200>; 343 reg-names = "host", "cfg"; 344 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk_emmc2>; 346 clock-names = "sw_sdio"; 347 sdhci-caps-mask = <0x0000C000 0x0>; 348 sdhci-caps = <0x0 0x0>; 349 mmc-ddr-3_3v; 350 status = "disabled"; 351 }; 352 353 gicv2: interrupt-controller@7fff9000 { 354 compatible = "arm,gic-400"; 355 reg = <0x7fff9000 0x1000>, 356 <0x7fffa000 0x2000>, 357 <0x7fffc000 0x2000>, 358 <0x7fffe000 0x2000>; 359 interrupt-controller; 360 #address-cells = <0>; 361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 362 IRQ_TYPE_LEVEL_HIGH)>; 363 #interrupt-cells = <3>; 364 }; 365 366 aon_intr: interrupt-controller@7d510600 { 367 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 368 reg = <0x7d510600 0x30>; 369 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-controller; 371 #interrupt-cells = <1>; 372 }; 373 374 pixelvalve0: pixelvalve@7c410000 { 375 compatible = "brcm,bcm2712-pixelvalve0"; 376 reg = <0x7c410000 0x100>; 377 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 378 status = "disabled"; 379 }; 380 381 pixelvalve1: pixelvalve@7c411000 { 382 compatible = "brcm,bcm2712-pixelvalve1"; 383 reg = <0x7c411000 0x100>; 384 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 385 status = "disabled"; 386 }; 387 388 mop: mop@7c500000 { 389 compatible = "brcm,bcm2712-mop"; 390 reg = <0x7c500000 0x28>; 391 interrupt-parent = <&disp_intr>; 392 interrupts = <1>; 393 status = "disabled"; 394 }; 395 396 moplet: moplet@7c501000 { 397 compatible = "brcm,bcm2712-moplet"; 398 reg = <0x7c501000 0x20>; 399 interrupt-parent = <&disp_intr>; 400 interrupts = <0>; 401 status = "disabled"; 402 }; 403 404 disp_intr: interrupt-controller@7c502000 { 405 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 406 reg = <0x7c502000 0x30>; 407 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 408 interrupt-controller; 409 #interrupt-cells = <1>; 410 status = "disabled"; 411 }; 412 413 dvp: clock@7c700000 { 414 compatible = "brcm,brcm2711-dvp"; 415 reg = <0x7c700000 0x10>; 416 clocks = <&clk_108MHz>; 417 #clock-cells = <1>; 418 #reset-cells = <1>; 419 }; 420 421 ddc0: i2c@7d508200 { 422 compatible = "brcm,brcmstb-i2c"; 423 reg = <0x7d508200 0x58>; 424 interrupt-parent = <&bsc_irq>; 425 interrupts = <1>; 426 clock-frequency = <97500>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 ddc1: i2c@7d508280 { 433 compatible = "brcm,brcmstb-i2c"; 434 reg = <0x7d508280 0x58>; 435 interrupt-parent = <&bsc_irq>; 436 interrupts = <2>; 437 clock-frequency = <97500>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 bsc_irq: interrupt-controller@7d508380 { 444 compatible = "brcm,bcm7271-l2-intc"; 445 reg = <0x7d508380 0x10>; 446 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-controller; 448 #interrupt-cells = <1>; 449 }; 450 451 main_irq: interrupt-controller@7d508400 { 452 compatible = "brcm,bcm7271-l2-intc"; 453 reg = <0x7d508400 0x10>; 454 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-controller; 456 #interrupt-cells = <1>; 457 }; 458 459 hdmi0: hdmi@7c701400 { 460 compatible = "brcm,bcm2712-hdmi0"; 461 reg = <0x7c701400 0x300>, 462 <0x7c701000 0x200>, 463 <0x7c701d00 0x300>, 464 <0x7c702000 0x80>, 465 <0x7c703800 0x200>, 466 <0x7c704000 0x800>, 467 <0x7c700100 0x80>, 468 <0x7d510800 0x100>, 469 <0x7c720000 0x100>; 470 reg-names = "hdmi", 471 "dvp", 472 "phy", 473 "rm", 474 "packet", 475 "metadata", 476 "csc", 477 "cec", 478 "hd"; 479 resets = <&dvp 1>; 480 interrupt-parent = <&aon_intr>; 481 interrupts = <1>, <2>, <3>, 482 <7>, <8>; 483 interrupt-names = "cec-tx", "cec-rx", "cec-low", 484 "hpd-connected", "hpd-removed"; 485 ddc = <&ddc0>; 486 status = "disabled"; 487 }; 488 489 hdmi1: hdmi@7c706400 { 490 compatible = "brcm,bcm2712-hdmi1"; 491 reg = <0x7c706400 0x300>, 492 <0x7c706000 0x200>, 493 <0x7c706d00 0x300>, 494 <0x7c707000 0x80>, 495 <0x7c708800 0x200>, 496 <0x7c709000 0x800>, 497 <0x7c700180 0x80>, 498 <0x7d511000 0x100>, 499 <0x7c720000 0x100>; 500 reg-names = "hdmi", 501 "dvp", 502 "phy", 503 "rm", 504 "packet", 505 "metadata", 506 "csc", 507 "cec", 508 "hd"; 509 resets = <&dvp 2>; 510 interrupt-parent = <&aon_intr>; 511 interrupts = <11>, <12>, <13>, 512 <14>, <15>; 513 interrupt-names = "cec-tx", "cec-rx", "cec-low", 514 "hpd-connected", "hpd-removed"; 515 ddc = <&ddc1>; 516 status = "disabled"; 517 }; 518 519 avs_monitor: avs-monitor@7d542000 { 520 compatible = "brcm,bcm2711-avs-monitor", 521 "syscon", "simple-mfd"; 522 reg = <0x7d542000 0xf00>; 523 status = "okay"; 524 525 thermal: thermal { 526 compatible = "brcm,bcm2711-thermal"; 527 #thermal-sensor-cells = <0>; 528 }; 529 }; 530 }; 531 532 axi: axi { 533 compatible = "simple-bus"; 534 #address-cells = <2>; 535 #size-cells = <2>; 536 537 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 538 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 539 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 540 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 541 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 542 543 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 544 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 545 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 546 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 547 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 548 549 pcie0: pcie@1000100000 { 550 compatible = "brcm,bcm2712-pcie"; 551 reg = <0x10 0x00100000 0x00 0x9310>; 552 device_type = "pci"; 553 linux,pci-domain = <0>; 554 max-link-speed = <2>; 555 num-lanes = <1>; 556 #address-cells = <3>; 557 #interrupt-cells = <1>; 558 #size-cells = <2>; 559 interrupt-parent = <&gicv2>; 560 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "pcie", "msi"; 563 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 565 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 566 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 567 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 568 resets = <&pcie_rescal>, <&bcm_reset 42>; 569 reset-names = "rescal", "bridge"; 570 msi-controller; 571 msi-parent = <&pcie0>; 572 573 ranges = 574 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 575 <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>, 576 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 577 <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>; 578 579 dma-ranges = 580 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 581 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; 582 583 status = "disabled"; 584 }; 585 586 pcie1: pcie@1000110000 { 587 compatible = "brcm,bcm2712-pcie"; 588 reg = <0x10 0x00110000 0x00 0x9310>; 589 device_type = "pci"; 590 linux,pci-domain = <1>; 591 max-link-speed = <2>; 592 num-lanes = <1>; 593 #address-cells = <3>; 594 #interrupt-cells = <1>; 595 #size-cells = <2>; 596 interrupt-parent = <&gicv2>; 597 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "pcie", "msi"; 600 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 601 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 602 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 603 <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 604 <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 605 resets = <&pcie_rescal>, <&bcm_reset 43>; 606 reset-names = "rescal", "bridge"; 607 msi-controller; 608 msi-parent = <&mip1>; 609 610 ranges = 611 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 612 <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>, 613 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 614 <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>; 615 616 dma-ranges = 617 /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */ 618 <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 619 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */ 620 <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>; 621 622 status = "disabled"; 623 }; 624 625 pcie2: pcie@1000120000 { 626 compatible = "brcm,bcm2712-pcie"; 627 reg = <0x10 0x00120000 0x00 0x9310>; 628 device_type = "pci"; 629 linux,pci-domain = <2>; 630 max-link-speed = <2>; 631 num-lanes = <4>; 632 #address-cells = <3>; 633 #interrupt-cells = <1>; 634 #size-cells = <2>; 635 interrupt-parent = <&gicv2>; 636 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 638 interrupt-names = "pcie", "msi"; 639 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 640 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 641 <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 642 <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 643 <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 644 resets = <&pcie_rescal>, <&bcm_reset 44>; 645 reset-names = "rescal", "bridge"; 646 msi-controller; 647 msi-parent = <&mip0>; 648 649 ranges = 650 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 651 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>, 652 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 653 <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>; 654 655 dma-ranges = 656 /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 657 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>, 658 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 659 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 660 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */ 661 <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>; 662 663 status = "disabled"; 664 }; 665 666 iommu4: iommu@1000005200 { 667 /* IOMMU for VC4 (HVS & MPL/TXP), Unicam, PISP-FE, MiniBVN */ 668 compatible = "brcm,bcm2712-iommu"; 669 reg = <0x10 0x5200 0x0 0x80>; 670 #iommu-cells = <0>; 671 brcm,iommu-cache = <&iommuc>; 672 }; 673 674 iommuc: iommuc@1000005b00 { 675 compatible = "brcm,bcm2712-iommuc"; 676 reg = <0x10 0x5b00 0x0 0x80>; 677 }; 678 679 mip0: msi-controller@1000130000 { 680 compatible = "brcm,bcm2712-mip"; 681 reg = <0x10 0x00130000 0x00 0xc0>, 682 <0xff 0xfffff000 0x00 0x1000>; 683 msi-controller; 684 msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; 685 brcm,msi-offset = <0>; 686 }; 687 688 mip1: msi-controller@1000131000 { 689 compatible = "brcm,bcm2712-mip"; 690 reg = <0x10 0x00131000 0x00 0xc0>, 691 <0xff 0xfffff000 0x00 0x1000>; 692 msi-controller; 693 msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; 694 brcm,msi-offset = <8>; 695 }; 696 697 isp: isp@1000880000 { 698 compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe"; 699 reg = <0x10 0x00880000 0x0 0x4000>; 700 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&firmware_clocks 7>; 702 }; 703 704 v3d: gpu@1002000000 { 705 compatible = "brcm,2712-v3d"; 706 reg = <0x10 0x02000000 0x00 0x4000>, 707 <0x10 0x02008000 0x00 0x6000>, 708 <0x10 0x02030800 0x00 0x0700>; 709 reg-names = "hub", "core0", "sms"; 710 711 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 712 resets = <&pm BCM2835_RESET_V3D>; 713 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 715 }; 716 717 usb: usb@1000480000 { 718 compatible = "brcm,bcm2835-usb"; 719 reg = <0x10 0x00480000 0x0 0x10000>; 720 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 clocks = <&clk_usb>; 724 clock-names = "otg"; 725 phys = <&usbphy>; 726 phy-names = "usb2-phy"; 727 status = "disabled"; 728 }; 729 }; 730 731 vc4: gpu { 732 compatible = "brcm,bcm2712-vc6"; 733 status = "disabled"; 734 }; 735 736 timer { 737 compatible = "arm,armv8-timer"; 738 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 739 IRQ_TYPE_LEVEL_LOW)>, 740 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 741 IRQ_TYPE_LEVEL_LOW)>, 742 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 743 IRQ_TYPE_LEVEL_LOW)>, 744 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 745 IRQ_TYPE_LEVEL_LOW)>; 746 }; 747 748 clk_27MHz: clk-27M { 749 #clock-cells = <0>; 750 compatible = "fixed-clock"; 751 clock-frequency = <27000000>; 752 clock-output-names = "27MHz-clock"; 753 }; 754 755 clk_108MHz: clk-108M { 756 #clock-cells = <0>; 757 compatible = "fixed-clock"; 758 clock-frequency = <108000000>; 759 clock-output-names = "108MHz-clock"; 760 }; 761 762 hvs: hvs@107c580000 { 763 compatible = "brcm,bcm2712-hvs"; 764 reg = <0x10 0x7c580000 0x0 0x1a000>; 765 interrupt-parent = <&disp_intr>; 766 interrupts = <2>, <9>, <16>; 767 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; 768 iommus = <&iommu4>; 769 status = "disabled"; 770 }; 771 772 thermal-zones { 773 cpu_thermal: cpu-thermal { 774 polling-delay-passive = <1000>; 775 polling-delay = <1000>; 776 coefficients = <(-550) 450000>; 777 thermal-sensors = <&thermal>; 778 779 thermal_trips: trips { 780 cpu_crit: cpu-crit { 781 temperature = <110000>; 782 hysteresis = <0>; 783 type = "critical"; 784 }; 785 }; 786 787 cooling_maps: cooling-maps { 788 }; 789 }; 790 }; 791 792 usbphy: phy { 793 compatible = "usb-nop-xceiv"; 794 #phy-cells = <0>; 795 }; 796}; 797