1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2022 Schneider Electric
4 *
5 * Clément Léger <clement.leger@bootlin.com>
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bits.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/device/devres.h>
14 #include <linux/mdio.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/pcs-rzn1-miic.h>
18 #include <linux/phylink.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <dt-bindings/net/pcs-rzn1-miic.h>
24 #include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
25
26 #define MIIC_PRCMD 0x0
27 #define MIIC_ESID_CODE 0x4
28
29 #define MIIC_MODCTRL 0x8
30
31 #define MIIC_PHY_LINK 0x14
32
33 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4)
34
35 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0)
36 #define CONV_MODE_10MBPS 0
37 #define CONV_MODE_100MBPS 1
38 #define CONV_MODE_1000MBPS 2
39
40 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2)
41 #define CONV_MODE_MII 0
42 #define CONV_MODE_RMII 1
43 #define CONV_MODE_RGMII 2
44
45 #define MIIC_CONVCTRL_FULLD BIT(8)
46 #define MIIC_CONVCTRL_RGMII_LINK BIT(12)
47 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13)
48 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14)
49
50 #define MIIC_CONVRST 0x114
51 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port)
52 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0)
53
54 #define MIIC_SWCTRL 0x304
55 #define MIIC_SWDUPC 0x308
56
57 #define MIIC_MODCTRL_CONF_CONV_MAX 6
58 #define MIIC_MODCTRL_CONF_NONE -1
59
60 #define MIIC_MAX_NUM_RSTS 2
61
62 /**
63 * struct modctrl_match - Matching table entry for convctrl configuration
64 * See section 8.2.1 of manual.
65 * @mode_cfg: Configuration value for convctrl
66 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN,
67 * then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case
68 * of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then
69 * index 0 - 3 are CONV0 - CONV3.
70 */
71 struct modctrl_match {
72 u32 mode_cfg;
73 u8 conv[MIIC_MODCTRL_CONF_CONV_MAX];
74 };
75
76 static struct modctrl_match modctrl_match_table[] = {
77 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
78 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
79 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
80 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
81 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
82 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
83 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
84 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
85
86 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
87 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
88 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
89 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
90 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
91 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
92 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
93 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
94
95 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
96 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
97 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
98 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
99 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
100 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
101 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
102 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}
103 };
104
105 static const char * const conf_to_string[] = {
106 [MIIC_GMAC1_PORT] = "GMAC1_PORT",
107 [MIIC_GMAC2_PORT] = "GMAC2_PORT",
108 [MIIC_RTOS_PORT] = "RTOS_PORT",
109 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA",
110 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB",
111 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA",
112 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB",
113 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC",
114 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA",
115 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB",
116 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC",
117 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD",
118 [MIIC_HSR_PORTA] = "HSR_PORTA",
119 [MIIC_HSR_PORTB] = "HSR_PORTB",
120 };
121
122 static const char * const index_to_string[] = {
123 "SWITCH_PORTIN",
124 "CONV1",
125 "CONV2",
126 "CONV3",
127 "CONV4",
128 "CONV5",
129 };
130
131 static struct modctrl_match rzt2h_modctrl_match_table[] = {
132 {0x0, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
133 ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
134
135 {0x1, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
136 ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
137
138 {0x2, {ETHSS_GMAC0_PORT, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
139 ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
140
141 {0x3, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
142 ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
143
144 {0x4, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
145 ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
146
147 {0x5, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
148 ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
149
150 {0x6, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
151 ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
152
153 {0x7, {MIIC_MODCTRL_CONF_NONE, ETHSS_GMAC0_PORT, ETHSS_GMAC1_PORT,
154 ETHSS_GMAC2_PORT, MIIC_MODCTRL_CONF_NONE}}
155 };
156
157 static const char * const rzt2h_conf_to_string[] = {
158 [ETHSS_GMAC0_PORT] = "GMAC0_PORT",
159 [ETHSS_GMAC1_PORT] = "GMAC1_PORT",
160 [ETHSS_GMAC2_PORT] = "GMAC2_PORT",
161 [ETHSS_ESC_PORT0] = "ETHERCAT_PORT0",
162 [ETHSS_ESC_PORT1] = "ETHERCAT_PORT1",
163 [ETHSS_ESC_PORT2] = "ETHERCAT_PORT2",
164 [ETHSS_ETHSW_PORT0] = "SWITCH_PORT0",
165 [ETHSS_ETHSW_PORT1] = "SWITCH_PORT1",
166 [ETHSS_ETHSW_PORT2] = "SWITCH_PORT2",
167 };
168
169 static const char * const rzt2h_index_to_string[] = {
170 "SWITCH_PORTIN",
171 "CONV0",
172 "CONV1",
173 "CONV2",
174 "CONV3",
175 };
176
177 static const char * const rzt2h_reset_ids[] = {
178 "rst",
179 "crst",
180 };
181
182 /**
183 * struct miic_phy_link_cfg - MIIC PHY_LINK configuration
184 * @mask: Mask of phy_link bits
185 * @val: Value of phy_link bits
186 */
187 struct miic_phy_link_cfg {
188 u32 mask;
189 u32 val;
190 };
191
192 /**
193 * struct miic - MII converter structure
194 * @base: base address of the MII converter
195 * @dev: Device associated to the MII converter
196 * @lock: Lock used for read-modify-write access
197 * @rsts: Reset controls for the MII converter
198 * @of_data: Pointer to OF data
199 * @link_cfg: MIIC PHY_LINK configuration
200 */
201 struct miic {
202 void __iomem *base;
203 struct device *dev;
204 spinlock_t lock;
205 struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS];
206 const struct miic_of_data *of_data;
207 struct miic_phy_link_cfg link_cfg;
208 };
209
210 enum miic_type {
211 MIIC_TYPE_RZN1,
212 MIIC_TYPE_RZT2H,
213 };
214
215 /**
216 * struct miic_of_data - OF data for MII converter
217 * @match_table: Matching table for convctrl configuration
218 * @match_table_count: Number of entries in the matching table
219 * @conf_conv_count: Number of entries in the conf_conv array
220 * @conf_to_string: String representations of the configuration values
221 * @conf_to_string_count: Number of entries in the conf_to_string array
222 * @index_to_string: String representations of the index values
223 * @index_to_string_count: Number of entries in the index_to_string array
224 * @miic_port_start: MIIC port start number
225 * @miic_port_max: Maximum MIIC supported
226 * @sw_mode_mask: Switch mode mask
227 * @reset_ids: Reset names array
228 * @reset_count: Number of entries in the reset_ids array
229 * @init_unlock_lock_regs: Flag to indicate if registers need to be unlocked
230 * before access.
231 * @miic_write: Function pointer to write a value to a MIIC register
232 * @type: Type of MIIC
233 */
234 struct miic_of_data {
235 struct modctrl_match *match_table;
236 u8 match_table_count;
237 u8 conf_conv_count;
238 const char * const *conf_to_string;
239 u8 conf_to_string_count;
240 const char * const *index_to_string;
241 u8 index_to_string_count;
242 u8 miic_port_start;
243 u8 miic_port_max;
244 u8 sw_mode_mask;
245 const char * const *reset_ids;
246 u8 reset_count;
247 bool init_unlock_lock_regs;
248 void (*miic_write)(struct miic *miic, int offset, u32 value);
249 enum miic_type type;
250 };
251
252 /**
253 * struct miic_port - Per port MII converter struct
254 * @miic: backiling to MII converter structure
255 * @pcs: PCS structure associated to the port
256 * @port: port number
257 * @interface: interface mode of the port
258 */
259 struct miic_port {
260 struct miic *miic;
261 struct phylink_pcs pcs;
262 int port;
263 phy_interface_t interface;
264 };
265
phylink_pcs_to_miic_port(struct phylink_pcs * pcs)266 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs)
267 {
268 return container_of(pcs, struct miic_port, pcs);
269 }
270
miic_unlock_regs(struct miic * miic)271 static void miic_unlock_regs(struct miic *miic)
272 {
273 /* Unprotect register writes */
274 writel(0x00A5, miic->base + MIIC_PRCMD);
275 writel(0x0001, miic->base + MIIC_PRCMD);
276 writel(0xFFFE, miic->base + MIIC_PRCMD);
277 writel(0x0001, miic->base + MIIC_PRCMD);
278 }
279
miic_lock_regs(struct miic * miic)280 static void miic_lock_regs(struct miic *miic)
281 {
282 /* Protect register writes */
283 writel(0x0000, miic->base + MIIC_PRCMD);
284 }
285
miic_reg_writel_unlocked(struct miic * miic,int offset,u32 value)286 static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 value)
287 {
288 writel(value, miic->base + offset);
289 }
290
miic_reg_writel_locked(struct miic * miic,int offset,u32 value)291 static void miic_reg_writel_locked(struct miic *miic, int offset, u32 value)
292 {
293 miic_unlock_regs(miic);
294 writel(value, miic->base + offset);
295 miic_lock_regs(miic);
296 }
297
miic_reg_writel(struct miic * miic,int offset,u32 value)298 static void miic_reg_writel(struct miic *miic, int offset, u32 value)
299 {
300 miic->of_data->miic_write(miic, offset, value);
301 }
302
miic_reg_readl(struct miic * miic,int offset)303 static u32 miic_reg_readl(struct miic *miic, int offset)
304 {
305 return readl(miic->base + offset);
306 }
307
miic_reg_rmw(struct miic * miic,int offset,u32 mask,u32 val)308 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val)
309 {
310 u32 reg;
311
312 spin_lock(&miic->lock);
313
314 reg = miic_reg_readl(miic, offset);
315 reg &= ~mask;
316 reg |= val;
317 miic_reg_writel(miic, offset, reg);
318
319 spin_unlock(&miic->lock);
320 }
321
miic_converter_enable(struct miic * miic,int port,int enable)322 static void miic_converter_enable(struct miic *miic, int port, int enable)
323 {
324 u32 val = 0;
325
326 if (enable)
327 val = MIIC_CONVRST_PHYIF_RST(port);
328
329 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val);
330 }
331
miic_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit)332 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode,
333 phy_interface_t interface,
334 const unsigned long *advertising, bool permit)
335 {
336 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
337 struct miic *miic = miic_port->miic;
338 u32 speed, conv_mode, val, mask;
339 int port = miic_port->port;
340
341 switch (interface) {
342 case PHY_INTERFACE_MODE_RMII:
343 conv_mode = CONV_MODE_RMII;
344 speed = CONV_MODE_100MBPS;
345 break;
346 case PHY_INTERFACE_MODE_RGMII:
347 case PHY_INTERFACE_MODE_RGMII_ID:
348 case PHY_INTERFACE_MODE_RGMII_TXID:
349 case PHY_INTERFACE_MODE_RGMII_RXID:
350 conv_mode = CONV_MODE_RGMII;
351 speed = CONV_MODE_1000MBPS;
352 break;
353 case PHY_INTERFACE_MODE_MII:
354 conv_mode = CONV_MODE_MII;
355 /* When in MII mode, speed should be set to 0 (which is actually
356 * CONV_MODE_10MBPS)
357 */
358 speed = CONV_MODE_10MBPS;
359 break;
360 default:
361 return -EOPNOTSUPP;
362 }
363
364 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode);
365 mask = MIIC_CONVCTRL_CONV_MODE;
366
367 /* Update speed only if we are going to change the interface because
368 * the link might already be up and it would break it if the speed is
369 * changed.
370 */
371 if (interface != miic_port->interface) {
372 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed);
373 mask |= MIIC_CONVCTRL_CONV_SPEED;
374 miic_port->interface = interface;
375 }
376
377 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val);
378 miic_converter_enable(miic, miic_port->port, 1);
379
380 return 0;
381 }
382
miic_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)383 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
384 phy_interface_t interface, int speed, int duplex)
385 {
386 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
387 struct miic *miic = miic_port->miic;
388 u32 conv_speed = 0, val = 0;
389 int port = miic_port->port;
390
391 if (duplex == DUPLEX_FULL)
392 val |= MIIC_CONVCTRL_FULLD;
393
394 /* No speed in MII through-mode */
395 if (interface != PHY_INTERFACE_MODE_MII) {
396 switch (speed) {
397 case SPEED_1000:
398 conv_speed = CONV_MODE_1000MBPS;
399 break;
400 case SPEED_100:
401 conv_speed = CONV_MODE_100MBPS;
402 break;
403 case SPEED_10:
404 conv_speed = CONV_MODE_10MBPS;
405 break;
406 default:
407 return;
408 }
409 }
410
411 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed);
412
413 miic_reg_rmw(miic, MIIC_CONVCTRL(port),
414 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val);
415 }
416
miic_pre_init(struct phylink_pcs * pcs)417 static int miic_pre_init(struct phylink_pcs *pcs)
418 {
419 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
420 struct miic *miic = miic_port->miic;
421 u32 val, mask;
422
423 /* Start RX clock if required */
424 if (pcs->rxc_always_on) {
425 /* In MII through mode, the clock signals will be driven by the
426 * external PHY, which might not be initialized yet. Set RMII
427 * as default mode to ensure that a reference clock signal is
428 * generated.
429 */
430 miic_port->interface = PHY_INTERFACE_MODE_RMII;
431
432 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) |
433 FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS);
434 mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED;
435
436 miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val);
437
438 miic_converter_enable(miic, miic_port->port, 1);
439 }
440
441 return 0;
442 }
443
444 static const struct phylink_pcs_ops miic_phylink_ops = {
445 .pcs_config = miic_config,
446 .pcs_link_up = miic_link_up,
447 .pcs_pre_init = miic_pre_init,
448 };
449
miic_create(struct device * dev,struct device_node * np)450 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
451 {
452 const struct miic_of_data *of_data;
453 struct platform_device *pdev;
454 struct miic_port *miic_port;
455 struct device_node *pcs_np;
456 struct miic *miic;
457 u32 port;
458
459 if (!of_device_is_available(np))
460 return ERR_PTR(-ENODEV);
461
462 if (of_property_read_u32(np, "reg", &port))
463 return ERR_PTR(-EINVAL);
464
465 /* The PCS pdev is attached to the parent node */
466 pcs_np = of_get_parent(np);
467 if (!pcs_np)
468 return ERR_PTR(-ENODEV);
469
470 if (!of_device_is_available(pcs_np)) {
471 of_node_put(pcs_np);
472 return ERR_PTR(-ENODEV);
473 }
474
475 pdev = of_find_device_by_node(pcs_np);
476 of_node_put(pcs_np);
477 if (!pdev || !platform_get_drvdata(pdev)) {
478 if (pdev)
479 put_device(&pdev->dev);
480 return ERR_PTR(-EPROBE_DEFER);
481 }
482
483 miic = platform_get_drvdata(pdev);
484 of_data = miic->of_data;
485 if (port > of_data->miic_port_max || port < of_data->miic_port_start) {
486 put_device(&pdev->dev);
487 return ERR_PTR(-EINVAL);
488 }
489
490 miic_port = kzalloc_obj(*miic_port);
491 if (!miic_port) {
492 put_device(&pdev->dev);
493 return ERR_PTR(-ENOMEM);
494 }
495
496 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
497 put_device(&pdev->dev);
498
499 miic_port->miic = miic;
500 miic_port->port = port - of_data->miic_port_start;
501 miic_port->pcs.ops = &miic_phylink_ops;
502
503 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces);
504 __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces);
505 __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces);
506
507 return &miic_port->pcs;
508 }
509 EXPORT_SYMBOL(miic_create);
510
miic_destroy(struct phylink_pcs * pcs)511 void miic_destroy(struct phylink_pcs *pcs)
512 {
513 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
514
515 miic_converter_enable(miic_port->miic, miic_port->port, 0);
516 kfree(miic_port);
517 }
518 EXPORT_SYMBOL(miic_destroy);
519
miic_init_hw(struct miic * miic,u32 cfg_mode)520 static int miic_init_hw(struct miic *miic, u32 cfg_mode)
521 {
522 u8 sw_mode_mask = miic->of_data->sw_mode_mask;
523 int port;
524
525 /* Unlock write access to accessory registers (cf datasheet). If this
526 * is going to be used in conjunction with the Cortex-M3, this sequence
527 * will have to be moved in register write
528 */
529 if (miic->of_data->init_unlock_lock_regs)
530 miic_unlock_regs(miic);
531
532 /* TODO: Replace with FIELD_PREP() when compile-time constant
533 * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask.
534 */
535 miic_reg_writel(miic, MIIC_MODCTRL,
536 ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
537
538 for (port = 0; port < miic->of_data->miic_port_max; port++) {
539 miic_converter_enable(miic, port, 0);
540 /* Disable speed/duplex control from these registers, datasheet
541 * says switch registers should be used to setup switch port
542 * speed and duplex.
543 */
544 miic_reg_writel(miic, MIIC_SWCTRL, 0x0);
545 miic_reg_writel(miic, MIIC_SWDUPC, 0x0);
546 }
547
548 return 0;
549 }
550
miic_modctrl_match(s8 * table_val,s8 * dt_val,u8 count)551 static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count)
552 {
553 int i;
554
555 for (i = 0; i < count; i++) {
556 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE)
557 continue;
558
559 if (dt_val[i] != table_val[i])
560 return false;
561 }
562
563 return true;
564 }
565
miic_dump_conf(struct miic * miic,s8 * conf)566 static void miic_dump_conf(struct miic *miic, s8 *conf)
567 {
568 const struct miic_of_data *of_data = miic->of_data;
569 const char *conf_name;
570 int i;
571
572 for (i = 0; i < of_data->conf_conv_count; i++) {
573 if (conf[i] != MIIC_MODCTRL_CONF_NONE)
574 conf_name = of_data->conf_to_string[conf[i]];
575 else
576 conf_name = "NONE";
577
578 dev_err(miic->dev, "%s: %s\n",
579 of_data->index_to_string[i], conf_name);
580 }
581 }
582
miic_match_dt_conf(struct miic * miic,s8 * dt_val,u32 * mode_cfg)583 static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg)
584 {
585 const struct miic_of_data *of_data = miic->of_data;
586 struct modctrl_match *table_entry;
587 int i;
588
589 for (i = 0; i < of_data->match_table_count; i++) {
590 table_entry = &of_data->match_table[i];
591
592 if (miic_modctrl_match(table_entry->conv, dt_val,
593 miic->of_data->conf_conv_count)) {
594 *mode_cfg = table_entry->mode_cfg;
595 return 0;
596 }
597 }
598
599 dev_err(miic->dev, "Failed to apply requested configuration\n");
600 miic_dump_conf(miic, dt_val);
601
602 return -EINVAL;
603 }
604
miic_configure_phy_link(struct miic * miic,u32 conf,u32 port,bool active_low)605 static void miic_configure_phy_link(struct miic *miic, u32 conf,
606 u32 port, bool active_low)
607 {
608 bool polarity_active_high;
609 u32 mask, shift;
610
611 /* determine shift and polarity for this conf */
612 if (miic->of_data->type == MIIC_TYPE_RZN1) {
613 switch (conf) {
614 /* switch ports => bits [3:0] (shift 0), active when low */
615 case MIIC_SWITCH_PORTA:
616 case MIIC_SWITCH_PORTB:
617 case MIIC_SWITCH_PORTC:
618 case MIIC_SWITCH_PORTD:
619 shift = 0;
620 polarity_active_high = false;
621 break;
622
623 /* EtherCAT ports => bits [7:4] (shift 4), active when high */
624 case MIIC_ETHERCAT_PORTA:
625 case MIIC_ETHERCAT_PORTB:
626 case MIIC_ETHERCAT_PORTC:
627 shift = 4;
628 polarity_active_high = true;
629 break;
630
631 /* Sercos ports => bits [11:8] (shift 8), active when high */
632 case MIIC_SERCOS_PORTA:
633 case MIIC_SERCOS_PORTB:
634 shift = 8;
635 polarity_active_high = true;
636 break;
637
638 default:
639 return;
640 }
641 } else {
642 switch (conf) {
643 /* ETHSW ports => bits [3:0] (shift 0), active when low */
644 case ETHSS_ETHSW_PORT0:
645 case ETHSS_ETHSW_PORT1:
646 case ETHSS_ETHSW_PORT2:
647 shift = 0;
648 polarity_active_high = false;
649 break;
650
651 /* ESC ports => bits [7:4] (shift 4), active when high */
652 case ETHSS_ESC_PORT0:
653 case ETHSS_ESC_PORT1:
654 case ETHSS_ESC_PORT2:
655 shift = 4;
656 polarity_active_high = true;
657 break;
658
659 default:
660 return;
661 }
662 }
663
664 mask = BIT(port + shift);
665
666 miic->link_cfg.mask |= mask;
667 if (polarity_active_high != active_low)
668 miic->link_cfg.val |= mask;
669 else
670 miic->link_cfg.val &= ~mask;
671 }
672
miic_parse_dt(struct miic * miic,u32 * mode_cfg)673 static int miic_parse_dt(struct miic *miic, u32 *mode_cfg)
674 {
675 struct device_node *np = miic->dev->of_node;
676 struct device_node *conv;
677 bool active_low;
678 int port, ret;
679 s8 *dt_val;
680 u32 conf;
681
682 dt_val = kmalloc_objs(*dt_val, miic->of_data->conf_conv_count);
683 if (!dt_val)
684 return -ENOMEM;
685
686 memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(*dt_val));
687
688 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)
689 dt_val[0] = conf;
690
691 for_each_available_child_of_node(np, conv) {
692 if (of_property_read_u32(conv, "reg", &port))
693 continue;
694
695 if (of_property_read_u32(conv, "renesas,miic-input", &conf))
696 continue;
697
698 /* Adjust for 0 based index */
699 dt_val[port + !miic->of_data->miic_port_start] = conf;
700
701 active_low = of_property_read_bool(conv, "renesas,miic-phy-link-active-low");
702
703 miic_configure_phy_link(miic, conf, port, active_low);
704 }
705
706 ret = miic_match_dt_conf(miic, dt_val, mode_cfg);
707 kfree(dt_val);
708
709 return ret;
710 }
711
miic_reset_control_bulk_assert(void * data)712 static void miic_reset_control_bulk_assert(void *data)
713 {
714 struct miic *miic = data;
715 int ret;
716
717 ret = reset_control_bulk_assert(miic->of_data->reset_count, miic->rsts);
718 if (ret)
719 dev_err(miic->dev, "failed to assert reset lines\n");
720 }
721
miic_reset_control_init(struct miic * miic)722 static int miic_reset_control_init(struct miic *miic)
723 {
724 const struct miic_of_data *of_data = miic->of_data;
725 struct device *dev = miic->dev;
726 int ret;
727 u8 i;
728
729 if (!of_data->reset_count)
730 return 0;
731
732 for (i = 0; i < of_data->reset_count; i++)
733 miic->rsts[i].id = of_data->reset_ids[i];
734
735 ret = devm_reset_control_bulk_get_exclusive(dev, of_data->reset_count,
736 miic->rsts);
737 if (ret)
738 return dev_err_probe(dev, ret,
739 "failed to get bulk reset lines\n");
740
741 ret = reset_control_bulk_deassert(of_data->reset_count, miic->rsts);
742 if (ret)
743 return dev_err_probe(dev, ret,
744 "failed to deassert reset lines\n");
745
746 ret = devm_add_action_or_reset(dev, miic_reset_control_bulk_assert,
747 miic);
748 if (ret)
749 return dev_err_probe(dev, ret, "failed to add reset action\n");
750
751 return 0;
752 }
753
miic_probe(struct platform_device * pdev)754 static int miic_probe(struct platform_device *pdev)
755 {
756 struct device *dev = &pdev->dev;
757 struct miic *miic;
758 u32 mode_cfg;
759 int ret;
760
761 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL);
762 if (!miic)
763 return -ENOMEM;
764
765 miic->of_data = of_device_get_match_data(dev);
766 miic->dev = dev;
767
768 ret = miic_parse_dt(miic, &mode_cfg);
769 if (ret < 0)
770 return ret;
771
772 spin_lock_init(&miic->lock);
773 miic->base = devm_platform_ioremap_resource(pdev, 0);
774 if (IS_ERR(miic->base))
775 return PTR_ERR(miic->base);
776
777 ret = miic_reset_control_init(miic);
778 if (ret)
779 return ret;
780
781 ret = devm_pm_runtime_enable(dev);
782 if (ret < 0)
783 return ret;
784
785 ret = pm_runtime_resume_and_get(dev);
786 if (ret < 0)
787 return ret;
788
789 ret = miic_init_hw(miic, mode_cfg);
790 if (ret)
791 goto disable_runtime_pm;
792
793 miic_reg_rmw(miic, MIIC_PHY_LINK, miic->link_cfg.mask, miic->link_cfg.val);
794
795 /* miic_create() relies on that fact that data are attached to the
796 * platform device to determine if the driver is ready so this needs to
797 * be the last thing to be done after everything is initialized
798 * properly.
799 */
800 platform_set_drvdata(pdev, miic);
801
802 return 0;
803
804 disable_runtime_pm:
805 pm_runtime_put(dev);
806
807 return ret;
808 }
809
miic_remove(struct platform_device * pdev)810 static void miic_remove(struct platform_device *pdev)
811 {
812 pm_runtime_put(&pdev->dev);
813 }
814
815 static struct miic_of_data rzn1_miic_of_data = {
816 .match_table = modctrl_match_table,
817 .match_table_count = ARRAY_SIZE(modctrl_match_table),
818 .conf_conv_count = MIIC_MODCTRL_CONF_CONV_MAX,
819 .conf_to_string = conf_to_string,
820 .conf_to_string_count = ARRAY_SIZE(conf_to_string),
821 .index_to_string = index_to_string,
822 .index_to_string_count = ARRAY_SIZE(index_to_string),
823 .miic_port_start = 1,
824 .miic_port_max = 5,
825 .sw_mode_mask = GENMASK(4, 0),
826 .init_unlock_lock_regs = true,
827 .miic_write = miic_reg_writel_unlocked,
828 .type = MIIC_TYPE_RZN1,
829 };
830
831 static struct miic_of_data rzt2h_miic_of_data = {
832 .match_table = rzt2h_modctrl_match_table,
833 .match_table_count = ARRAY_SIZE(rzt2h_modctrl_match_table),
834 .conf_conv_count = 5,
835 .conf_to_string = rzt2h_conf_to_string,
836 .conf_to_string_count = ARRAY_SIZE(rzt2h_conf_to_string),
837 .index_to_string = rzt2h_index_to_string,
838 .index_to_string_count = ARRAY_SIZE(rzt2h_index_to_string),
839 .miic_port_start = 0,
840 .miic_port_max = 4,
841 .sw_mode_mask = GENMASK(2, 0),
842 .reset_ids = rzt2h_reset_ids,
843 .reset_count = ARRAY_SIZE(rzt2h_reset_ids),
844 .miic_write = miic_reg_writel_locked,
845 .type = MIIC_TYPE_RZT2H,
846 };
847
848 static const struct of_device_id miic_of_mtable[] = {
849 { .compatible = "renesas,r9a09g077-miic", .data = &rzt2h_miic_of_data },
850 { .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data },
851 { /* sentinel */ }
852 };
853 MODULE_DEVICE_TABLE(of, miic_of_mtable);
854
855 static struct platform_driver miic_driver = {
856 .driver = {
857 .name = "rzn1_miic",
858 .suppress_bind_attrs = true,
859 .of_match_table = miic_of_mtable,
860 },
861 .probe = miic_probe,
862 .remove = miic_remove,
863 };
864 module_platform_driver(miic_driver);
865
866 MODULE_LICENSE("GPL");
867 MODULE_DESCRIPTION("Renesas MII converter PCS driver");
868 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>");
869