1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <linux/workqueue.h> 40 #include <net/addrconf.h> 41 #include <rdma/ib_addr.h> 42 #include <rdma/ib_cache.h> 43 #include <rdma/ib_umem.h> 44 #include <rdma/uverbs_ioctl.h> 45 46 #include "hclge_main.h" 47 #include "hns_roce_common.h" 48 #include "hns_roce_device.h" 49 #include "hns_roce_cmd.h" 50 #include "hns_roce_hem.h" 51 #include "hns_roce_hw_v2.h" 52 #include "hns_roce_bond.h" 53 54 #define CREATE_TRACE_POINTS 55 #include "hns_roce_trace.h" 56 57 enum { 58 CMD_RST_PRC_OTHERS, 59 CMD_RST_PRC_SUCCESS, 60 CMD_RST_PRC_EBUSY, 61 }; 62 63 enum ecc_resource_type { 64 ECC_RESOURCE_QPC, 65 ECC_RESOURCE_CQC, 66 ECC_RESOURCE_MPT, 67 ECC_RESOURCE_SRQC, 68 ECC_RESOURCE_GMV, 69 ECC_RESOURCE_QPC_TIMER, 70 ECC_RESOURCE_CQC_TIMER, 71 ECC_RESOURCE_SCCC, 72 ECC_RESOURCE_COUNT, 73 }; 74 75 static const struct { 76 const char *name; 77 u8 read_bt0_op; 78 u8 write_bt0_op; 79 } fmea_ram_res[] = { 80 { "ECC_RESOURCE_QPC", 81 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 82 { "ECC_RESOURCE_CQC", 83 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 84 { "ECC_RESOURCE_MPT", 85 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 86 { "ECC_RESOURCE_SRQC", 87 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 88 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 89 { "ECC_RESOURCE_GMV", 90 0, 0 }, 91 { "ECC_RESOURCE_QPC_TIMER", 92 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 93 { "ECC_RESOURCE_CQC_TIMER", 94 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 95 { "ECC_RESOURCE_SCCC", 96 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 97 }; 98 99 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 100 struct ib_sge *sg) 101 { 102 dseg->lkey = cpu_to_le32(sg->lkey); 103 dseg->addr = cpu_to_le64(sg->addr); 104 dseg->len = cpu_to_le32(sg->length); 105 } 106 107 /* 108 * mapped-value = 1 + real-value 109 * The hns wr opcode real value is start from 0, In order to distinguish between 110 * initialized and uninitialized map values, we plus 1 to the actual value when 111 * defining the mapping, so that the validity can be identified by checking the 112 * mapped value is greater than 0. 113 */ 114 #define HR_OPC_MAP(ib_key, hr_key) \ 115 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 116 117 static const u32 hns_roce_op_code[] = { 118 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 119 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 120 HR_OPC_MAP(SEND, SEND), 121 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 122 HR_OPC_MAP(RDMA_READ, RDMA_READ), 123 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 124 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 125 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 126 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 127 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 128 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 129 }; 130 131 static u32 to_hr_opcode(u32 ib_opcode) 132 { 133 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 134 return HNS_ROCE_V2_WQE_OP_MASK; 135 136 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 137 HNS_ROCE_V2_WQE_OP_MASK; 138 } 139 140 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 141 const struct ib_reg_wr *wr) 142 { 143 struct hns_roce_wqe_frmr_seg *fseg = 144 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 145 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 146 u64 pbl_ba; 147 148 /* use ib_access_flags */ 149 hr_reg_write_bool(fseg, FRMR_BIND_EN, 0); 150 hr_reg_write_bool(fseg, FRMR_ATOMIC, 151 wr->access & IB_ACCESS_REMOTE_ATOMIC); 152 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 153 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 154 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 155 156 /* Data structure reuse may lead to confusion */ 157 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 158 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 159 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 160 161 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 162 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 163 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 164 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 165 166 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 167 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 168 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 169 hr_reg_clear(fseg, FRMR_BLK_MODE); 170 hr_reg_clear(fseg, FRMR_BLOCK_SIZE); 171 hr_reg_clear(fseg, FRMR_ZBVA); 172 } 173 174 static void set_atomic_seg(const struct ib_send_wr *wr, 175 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 176 unsigned int valid_num_sge) 177 { 178 struct hns_roce_v2_wqe_data_seg *dseg = 179 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 180 struct hns_roce_wqe_atomic_seg *aseg = 181 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 182 183 set_data_seg_v2(dseg, wr->sg_list); 184 185 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 186 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 187 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 188 } else { 189 aseg->fetchadd_swap_data = 190 cpu_to_le64(atomic_wr(wr)->compare_add); 191 aseg->cmp_data = 0; 192 } 193 194 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 195 } 196 197 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 198 const struct ib_send_wr *wr, 199 unsigned int *sge_idx, u32 msg_len) 200 { 201 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 202 unsigned int left_len_in_pg; 203 unsigned int idx = *sge_idx; 204 unsigned int i = 0; 205 unsigned int len; 206 void *addr; 207 void *dseg; 208 209 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 210 ibdev_err(ibdev, 211 "no enough extended sge space for inline data.\n"); 212 return -EINVAL; 213 } 214 215 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 216 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 217 len = wr->sg_list[0].length; 218 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 219 220 /* When copying data to extended sge space, the left length in page may 221 * not long enough for current user's sge. So the data should be 222 * splited into several parts, one in the first page, and the others in 223 * the subsequent pages. 224 */ 225 while (1) { 226 if (len <= left_len_in_pg) { 227 memcpy(dseg, addr, len); 228 229 idx += len / HNS_ROCE_SGE_SIZE; 230 231 i++; 232 if (i >= wr->num_sge) 233 break; 234 235 left_len_in_pg -= len; 236 len = wr->sg_list[i].length; 237 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 238 dseg += len; 239 } else { 240 memcpy(dseg, addr, left_len_in_pg); 241 242 len -= left_len_in_pg; 243 addr += left_len_in_pg; 244 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 245 dseg = hns_roce_get_extend_sge(qp, 246 idx & (qp->sge.sge_cnt - 1)); 247 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 248 } 249 } 250 251 *sge_idx = idx; 252 253 return 0; 254 } 255 256 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 257 unsigned int *sge_ind, unsigned int cnt) 258 { 259 struct hns_roce_v2_wqe_data_seg *dseg; 260 unsigned int idx = *sge_ind; 261 262 while (cnt > 0) { 263 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 264 if (likely(sge->length)) { 265 set_data_seg_v2(dseg, sge); 266 idx++; 267 cnt--; 268 } 269 sge++; 270 } 271 272 *sge_ind = idx; 273 } 274 275 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 276 { 277 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 278 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 279 280 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 281 ibdev_err(&hr_dev->ib_dev, 282 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 283 len, qp->max_inline_data, mtu); 284 return false; 285 } 286 287 return true; 288 } 289 290 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 291 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 292 unsigned int *sge_idx) 293 { 294 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 295 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 296 struct ib_device *ibdev = &hr_dev->ib_dev; 297 unsigned int curr_idx = *sge_idx; 298 void *dseg = rc_sq_wqe; 299 unsigned int i; 300 int ret; 301 302 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 303 ibdev_err(ibdev, "invalid inline parameters!\n"); 304 return -EINVAL; 305 } 306 307 if (!check_inl_data_len(qp, msg_len)) 308 return -EINVAL; 309 310 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 311 312 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 313 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 314 315 for (i = 0; i < wr->num_sge; i++) { 316 memcpy(dseg, ((void *)wr->sg_list[i].addr), 317 wr->sg_list[i].length); 318 dseg += wr->sg_list[i].length; 319 } 320 } else { 321 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 322 323 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 324 if (ret) 325 return ret; 326 327 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 328 } 329 330 *sge_idx = curr_idx; 331 332 return 0; 333 } 334 335 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 336 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 337 unsigned int *sge_ind, 338 unsigned int valid_num_sge) 339 { 340 struct hns_roce_v2_wqe_data_seg *dseg = 341 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 342 struct hns_roce_qp *qp = to_hr_qp(ibqp); 343 int j = 0; 344 int i; 345 346 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 347 !!(wr->send_flags & IB_SEND_INLINE)); 348 if (wr->send_flags & IB_SEND_INLINE) 349 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 350 351 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 352 for (i = 0; i < wr->num_sge; i++) { 353 if (likely(wr->sg_list[i].length)) { 354 set_data_seg_v2(dseg, wr->sg_list + i); 355 dseg++; 356 } 357 } 358 } else { 359 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 360 if (likely(wr->sg_list[i].length)) { 361 set_data_seg_v2(dseg, wr->sg_list + i); 362 dseg++; 363 j++; 364 } 365 } 366 367 set_extend_sge(qp, wr->sg_list + i, sge_ind, 368 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 369 } 370 371 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 372 373 return 0; 374 } 375 376 static int check_send_valid(struct hns_roce_dev *hr_dev, 377 struct hns_roce_qp *hr_qp) 378 { 379 if (unlikely(hr_qp->state == IB_QPS_RESET || 380 hr_qp->state == IB_QPS_INIT || 381 hr_qp->state == IB_QPS_RTR)) 382 return -EINVAL; 383 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 384 return -EIO; 385 386 return 0; 387 } 388 389 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 390 unsigned int *sge_len) 391 { 392 unsigned int valid_num = 0; 393 unsigned int len = 0; 394 int i; 395 396 for (i = 0; i < wr->num_sge; i++) { 397 if (likely(wr->sg_list[i].length)) { 398 len += wr->sg_list[i].length; 399 valid_num++; 400 } 401 } 402 403 *sge_len = len; 404 return valid_num; 405 } 406 407 static __le32 get_immtdata(const struct ib_send_wr *wr) 408 { 409 switch (wr->opcode) { 410 case IB_WR_SEND_WITH_IMM: 411 case IB_WR_RDMA_WRITE_WITH_IMM: 412 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 413 default: 414 return 0; 415 } 416 } 417 418 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 419 const struct ib_send_wr *wr) 420 { 421 u32 ib_op = wr->opcode; 422 423 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 424 return -EINVAL; 425 426 ud_sq_wqe->immtdata = get_immtdata(wr); 427 428 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 429 430 return 0; 431 } 432 433 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 434 struct hns_roce_ah *ah) 435 { 436 struct ib_device *ib_dev = ah->ibah.device; 437 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 438 439 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 440 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 441 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 444 445 ud_sq_wqe->sgid_index = ah->av.gid_index; 446 447 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 448 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 449 450 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 451 return 0; 452 453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 454 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 455 456 return 0; 457 } 458 459 static inline int set_ud_wqe(struct hns_roce_qp *qp, 460 const struct ib_send_wr *wr, 461 void *wqe, unsigned int *sge_idx, 462 unsigned int owner_bit) 463 { 464 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 465 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 466 unsigned int curr_idx = *sge_idx; 467 unsigned int valid_num_sge; 468 u32 msg_len = 0; 469 int ret; 470 471 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 472 473 ret = set_ud_opcode(ud_sq_wqe, wr); 474 if (WARN_ON_ONCE(ret)) 475 return ret; 476 477 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 478 479 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 480 !!(wr->send_flags & IB_SEND_SIGNALED)); 481 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 482 !!(wr->send_flags & IB_SEND_SOLICITED)); 483 484 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 487 curr_idx & (qp->sge.sge_cnt - 1)); 488 489 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 490 qp->qkey : ud_wr(wr)->remote_qkey); 491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 492 493 ret = fill_ud_av(ud_sq_wqe, ah); 494 if (ret) 495 return ret; 496 497 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 498 499 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 500 501 /* 502 * The pipeline can sequentially post all valid WQEs into WQ buffer, 503 * including new WQEs waiting for the doorbell to update the PI again. 504 * Therefore, the owner bit of WQE MUST be updated after all fields 505 * and extSGEs have been written into DDR instead of cache. 506 */ 507 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 508 dma_wmb(); 509 510 *sge_idx = curr_idx; 511 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 512 513 return 0; 514 } 515 516 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 517 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 518 const struct ib_send_wr *wr) 519 { 520 u32 ib_op = wr->opcode; 521 int ret = 0; 522 523 rc_sq_wqe->immtdata = get_immtdata(wr); 524 525 switch (ib_op) { 526 case IB_WR_RDMA_READ: 527 case IB_WR_RDMA_WRITE: 528 case IB_WR_RDMA_WRITE_WITH_IMM: 529 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 530 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 531 break; 532 case IB_WR_SEND: 533 case IB_WR_SEND_WITH_IMM: 534 break; 535 case IB_WR_ATOMIC_CMP_AND_SWP: 536 case IB_WR_ATOMIC_FETCH_AND_ADD: 537 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 538 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 539 break; 540 case IB_WR_REG_MR: 541 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 542 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 543 else 544 ret = -EOPNOTSUPP; 545 break; 546 case IB_WR_SEND_WITH_INV: 547 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 548 break; 549 default: 550 ret = -EINVAL; 551 } 552 553 if (unlikely(ret)) 554 return ret; 555 556 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 557 558 return ret; 559 } 560 561 static inline int set_rc_wqe(struct hns_roce_qp *qp, 562 const struct ib_send_wr *wr, 563 void *wqe, unsigned int *sge_idx, 564 unsigned int owner_bit) 565 { 566 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 567 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 568 unsigned int curr_idx = *sge_idx; 569 unsigned int valid_num_sge; 570 u32 msg_len = 0; 571 int ret; 572 573 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 574 575 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 576 577 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 578 if (WARN_ON_ONCE(ret)) 579 return ret; 580 581 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO, 582 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 583 584 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 585 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 586 587 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 588 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 589 590 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 591 curr_idx & (qp->sge.sge_cnt - 1)); 592 593 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 594 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 595 if (msg_len != ATOMIC_WR_LEN) 596 return -EINVAL; 597 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 598 } else if (wr->opcode != IB_WR_REG_MR) { 599 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 600 &curr_idx, valid_num_sge); 601 if (ret) 602 return ret; 603 } 604 605 /* 606 * The pipeline can sequentially post all valid WQEs into WQ buffer, 607 * including new WQEs waiting for the doorbell to update the PI again. 608 * Therefore, the owner bit of WQE MUST be updated after all fields 609 * and extSGEs have been written into DDR instead of cache. 610 */ 611 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 612 dma_wmb(); 613 614 *sge_idx = curr_idx; 615 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 616 617 return ret; 618 } 619 620 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 621 struct hns_roce_qp *qp) 622 { 623 if (unlikely(qp->state == IB_QPS_ERR)) { 624 flush_cqe(hr_dev, qp); 625 } else { 626 struct hns_roce_v2_db sq_db = {}; 627 628 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 629 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 630 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 631 hr_reg_write(&sq_db, DB_SL, qp->sl); 632 633 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 634 } 635 } 636 637 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 638 struct hns_roce_qp *qp) 639 { 640 if (unlikely(qp->state == IB_QPS_ERR)) { 641 flush_cqe(hr_dev, qp); 642 } else { 643 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 644 *qp->rdb.db_record = 645 qp->rq.head & V2_DB_PRODUCER_IDX_M; 646 } else { 647 struct hns_roce_v2_db rq_db = {}; 648 649 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 650 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 651 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 652 653 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 654 qp->rq.db_reg); 655 } 656 } 657 } 658 659 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 660 u64 __iomem *dest) 661 { 662 #define HNS_ROCE_WRITE_TIMES 8 663 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 664 struct hnae3_handle *handle = priv->handle; 665 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 666 int i; 667 668 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 669 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 670 writeq_relaxed(*(val + i), dest + i); 671 } 672 673 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 674 void *wqe) 675 { 676 #define HNS_ROCE_SL_SHIFT 2 677 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 678 679 if (unlikely(qp->state == IB_QPS_ERR)) { 680 flush_cqe(hr_dev, qp); 681 return; 682 } 683 /* All kinds of DirectWQE have the same header field layout */ 684 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 685 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 686 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 687 qp->sl >> HNS_ROCE_SL_SHIFT); 688 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 689 690 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 691 } 692 693 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 694 const struct ib_send_wr *wr, 695 const struct ib_send_wr **bad_wr) 696 { 697 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 698 struct ib_device *ibdev = &hr_dev->ib_dev; 699 struct hns_roce_qp *qp = to_hr_qp(ibqp); 700 unsigned long flags = 0; 701 unsigned int owner_bit; 702 unsigned int sge_idx; 703 unsigned int wqe_idx; 704 void *wqe = NULL; 705 u32 nreq; 706 int ret; 707 708 spin_lock_irqsave(&qp->sq.lock, flags); 709 710 ret = check_send_valid(hr_dev, qp); 711 if (unlikely(ret)) { 712 *bad_wr = wr; 713 nreq = 0; 714 goto out; 715 } 716 717 sge_idx = qp->next_sge; 718 719 for (nreq = 0; wr; ++nreq, wr = wr->next) { 720 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 721 ret = -ENOMEM; 722 *bad_wr = wr; 723 goto out; 724 } 725 726 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 727 728 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 729 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 730 wr->num_sge, qp->sq.max_gs); 731 ret = -EINVAL; 732 *bad_wr = wr; 733 goto out; 734 } 735 736 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 737 qp->sq.wrid[wqe_idx] = wr->wr_id; 738 owner_bit = 739 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 740 741 /* RC and UD share the same DirectWQE field layout */ 742 ((struct hns_roce_v2_rc_send_wqe *)wqe)->byte_4 = 0; 743 744 /* Corresponding to the QP type, wqe process separately */ 745 if (ibqp->qp_type == IB_QPT_RC) 746 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 747 else 748 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 749 750 trace_hns_sq_wqe(qp->qpn, wqe_idx, wqe, 1 << qp->sq.wqe_shift, 751 wr->wr_id, TRACE_SQ); 752 if (unlikely(ret)) { 753 *bad_wr = wr; 754 goto out; 755 } 756 } 757 758 out: 759 if (likely(nreq)) { 760 qp->sq.head += nreq; 761 qp->next_sge = sge_idx; 762 763 if (nreq == 1 && !ret && 764 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 765 write_dwqe(hr_dev, qp, wqe); 766 else 767 update_sq_db(hr_dev, qp); 768 } 769 770 spin_unlock_irqrestore(&qp->sq.lock, flags); 771 772 return ret; 773 } 774 775 static int check_recv_valid(struct hns_roce_dev *hr_dev, 776 struct hns_roce_qp *hr_qp) 777 { 778 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 779 return -EIO; 780 781 if (hr_qp->state == IB_QPS_RESET) 782 return -EINVAL; 783 784 return 0; 785 } 786 787 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 788 u32 max_sge, bool rsv) 789 { 790 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 791 u32 i, cnt; 792 793 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 794 /* Skip zero-length sge */ 795 if (!wr->sg_list[i].length) 796 continue; 797 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 798 cnt++; 799 } 800 801 /* Fill a reserved sge to make hw stop reading remaining segments */ 802 if (rsv) { 803 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 804 dseg[cnt].addr = 0; 805 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 806 } else { 807 /* Clear remaining segments to make ROCEE ignore sges */ 808 if (cnt < max_sge) 809 memset(dseg + cnt, 0, 810 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 811 } 812 } 813 814 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 815 u32 wqe_idx, u32 max_sge) 816 { 817 void *wqe = NULL; 818 819 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 820 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 821 822 trace_hns_rq_wqe(hr_qp->qpn, wqe_idx, wqe, 1 << hr_qp->rq.wqe_shift, 823 wr->wr_id, TRACE_RQ); 824 } 825 826 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 827 const struct ib_recv_wr *wr, 828 const struct ib_recv_wr **bad_wr) 829 { 830 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 831 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 832 struct ib_device *ibdev = &hr_dev->ib_dev; 833 u32 wqe_idx, nreq, max_sge; 834 unsigned long flags; 835 int ret; 836 837 spin_lock_irqsave(&hr_qp->rq.lock, flags); 838 839 ret = check_recv_valid(hr_dev, hr_qp); 840 if (unlikely(ret)) { 841 *bad_wr = wr; 842 nreq = 0; 843 goto out; 844 } 845 846 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 847 for (nreq = 0; wr; ++nreq, wr = wr->next) { 848 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 849 hr_qp->ibqp.recv_cq))) { 850 ret = -ENOMEM; 851 *bad_wr = wr; 852 goto out; 853 } 854 855 if (unlikely(wr->num_sge > max_sge)) { 856 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 857 wr->num_sge, max_sge); 858 ret = -EINVAL; 859 *bad_wr = wr; 860 goto out; 861 } 862 863 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 864 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 865 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 866 } 867 868 out: 869 if (likely(nreq)) { 870 hr_qp->rq.head += nreq; 871 872 update_rq_db(hr_dev, hr_qp); 873 } 874 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 875 876 return ret; 877 } 878 879 static int hns_roce_push_drain_wr(struct hns_roce_wq *wq, struct ib_cq *cq, 880 u64 wr_id) 881 { 882 unsigned long flags; 883 int ret = 0; 884 885 spin_lock_irqsave(&wq->lock, flags); 886 if (hns_roce_wq_overflow(wq, 1, cq)) { 887 ret = -ENOMEM; 888 goto out; 889 } 890 891 wq->wrid[wq->head & (wq->wqe_cnt - 1)] = wr_id; 892 wq->head++; 893 894 out: 895 spin_unlock_irqrestore(&wq->lock, flags); 896 return ret; 897 } 898 899 struct hns_roce_drain_cqe { 900 struct ib_cqe cqe; 901 struct completion done; 902 }; 903 904 static void hns_roce_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) 905 { 906 struct hns_roce_drain_cqe *cqe = container_of(wc->wr_cqe, 907 struct hns_roce_drain_cqe, 908 cqe); 909 complete(&cqe->done); 910 } 911 912 static void handle_drain_completion(struct ib_cq *ibcq, 913 struct hns_roce_drain_cqe *drain, 914 struct hns_roce_dev *hr_dev) 915 { 916 #define TIMEOUT (HZ / 10) 917 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 918 unsigned long flags; 919 bool triggered; 920 921 if (ibcq->poll_ctx == IB_POLL_DIRECT) { 922 while (wait_for_completion_timeout(&drain->done, TIMEOUT) <= 0) 923 ib_process_cq_direct(ibcq, -1); 924 return; 925 } 926 927 if (hr_dev->state < HNS_ROCE_DEVICE_STATE_RST_DOWN) 928 goto waiting_done; 929 930 spin_lock_irqsave(&hr_cq->lock, flags); 931 triggered = hr_cq->is_armed; 932 hr_cq->is_armed = 1; 933 spin_unlock_irqrestore(&hr_cq->lock, flags); 934 935 /* Triggered means this cq is processing or has been processed 936 * by hns_roce_handle_device_err() or this function. We need to 937 * cancel the already invoked comp_handler() to avoid concurrency. 938 * If it has not been triggered, we can directly invoke 939 * comp_handler(). 940 */ 941 if (triggered) { 942 switch (ibcq->poll_ctx) { 943 case IB_POLL_SOFTIRQ: 944 irq_poll_disable(&ibcq->iop); 945 irq_poll_enable(&ibcq->iop); 946 break; 947 case IB_POLL_WORKQUEUE: 948 case IB_POLL_UNBOUND_WORKQUEUE: 949 cancel_work_sync(&ibcq->work); 950 break; 951 default: 952 WARN_ON_ONCE(1); 953 } 954 } 955 956 if (ibcq->comp_handler) 957 ibcq->comp_handler(ibcq, ibcq->cq_context); 958 959 waiting_done: 960 if (ibcq->comp_handler) 961 wait_for_completion(&drain->done); 962 } 963 964 static void hns_roce_v2_drain_rq(struct ib_qp *ibqp) 965 { 966 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 967 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 968 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 969 struct hns_roce_drain_cqe rdrain = {}; 970 const struct ib_recv_wr *bad_rwr; 971 struct ib_cq *cq = ibqp->recv_cq; 972 struct ib_recv_wr rwr = {}; 973 int ret; 974 975 ret = ib_modify_qp(ibqp, &attr, IB_QP_STATE); 976 if (ret && hr_dev->state < HNS_ROCE_DEVICE_STATE_RST_DOWN) { 977 ibdev_err_ratelimited(&hr_dev->ib_dev, 978 "failed to modify qp during drain rq, ret = %d.\n", 979 ret); 980 return; 981 } 982 983 rwr.wr_cqe = &rdrain.cqe; 984 rdrain.cqe.done = hns_roce_drain_qp_done; 985 init_completion(&rdrain.done); 986 987 if (hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN) 988 ret = hns_roce_push_drain_wr(&hr_qp->rq, cq, rwr.wr_id); 989 else 990 ret = hns_roce_v2_post_recv(ibqp, &rwr, &bad_rwr); 991 if (ret) { 992 ibdev_err_ratelimited(&hr_dev->ib_dev, 993 "failed to post recv for drain rq, ret = %d.\n", 994 ret); 995 return; 996 } 997 998 handle_drain_completion(cq, &rdrain, hr_dev); 999 } 1000 1001 static void hns_roce_v2_drain_sq(struct ib_qp *ibqp) 1002 { 1003 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1004 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; 1005 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1006 struct hns_roce_drain_cqe sdrain = {}; 1007 const struct ib_send_wr *bad_swr; 1008 struct ib_cq *cq = ibqp->send_cq; 1009 struct ib_rdma_wr swr = { 1010 .wr = { 1011 .next = NULL, 1012 { .wr_cqe = &sdrain.cqe, }, 1013 .opcode = IB_WR_RDMA_WRITE, 1014 }, 1015 }; 1016 int ret; 1017 1018 ret = ib_modify_qp(ibqp, &attr, IB_QP_STATE); 1019 if (ret && hr_dev->state < HNS_ROCE_DEVICE_STATE_RST_DOWN) { 1020 ibdev_err_ratelimited(&hr_dev->ib_dev, 1021 "failed to modify qp during drain sq, ret = %d.\n", 1022 ret); 1023 return; 1024 } 1025 1026 sdrain.cqe.done = hns_roce_drain_qp_done; 1027 init_completion(&sdrain.done); 1028 1029 if (hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN) 1030 ret = hns_roce_push_drain_wr(&hr_qp->sq, cq, swr.wr.wr_id); 1031 else 1032 ret = hns_roce_v2_post_send(ibqp, &swr.wr, &bad_swr); 1033 if (ret) { 1034 ibdev_err_ratelimited(&hr_dev->ib_dev, 1035 "failed to post send for drain sq, ret = %d.\n", 1036 ret); 1037 return; 1038 } 1039 1040 handle_drain_completion(cq, &sdrain, hr_dev); 1041 } 1042 1043 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 1044 { 1045 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 1046 } 1047 1048 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 1049 { 1050 return hns_roce_buf_offset(idx_que->mtr.kmem, 1051 n << idx_que->entry_shift); 1052 } 1053 1054 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 1055 { 1056 /* always called with interrupts disabled. */ 1057 spin_lock(&srq->lock); 1058 1059 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 1060 srq->idx_que.tail++; 1061 1062 spin_unlock(&srq->lock); 1063 } 1064 1065 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 1066 { 1067 struct hns_roce_idx_que *idx_que = &srq->idx_que; 1068 1069 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 1070 } 1071 1072 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 1073 const struct ib_recv_wr *wr) 1074 { 1075 struct ib_device *ib_dev = srq->ibsrq.device; 1076 1077 if (unlikely(wr->num_sge > max_sge)) { 1078 ibdev_err(ib_dev, 1079 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 1080 wr->num_sge, max_sge); 1081 return -EINVAL; 1082 } 1083 1084 if (unlikely(hns_roce_srqwq_overflow(srq))) { 1085 ibdev_err(ib_dev, 1086 "failed to check srqwq status, srqwq is full.\n"); 1087 return -ENOMEM; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 1094 { 1095 struct hns_roce_idx_que *idx_que = &srq->idx_que; 1096 u32 pos; 1097 1098 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 1099 if (unlikely(pos == srq->wqe_cnt)) 1100 return -ENOSPC; 1101 1102 bitmap_set(idx_que->bitmap, pos, 1); 1103 *wqe_idx = pos; 1104 return 0; 1105 } 1106 1107 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 1108 { 1109 struct hns_roce_idx_que *idx_que = &srq->idx_que; 1110 unsigned int head; 1111 __le32 *buf; 1112 1113 head = idx_que->head & (srq->wqe_cnt - 1); 1114 1115 buf = get_idx_buf(idx_que, head); 1116 *buf = cpu_to_le32(wqe_idx); 1117 1118 idx_que->head++; 1119 } 1120 1121 static void update_srq_db(struct hns_roce_srq *srq) 1122 { 1123 struct hns_roce_dev *hr_dev = to_hr_dev(srq->ibsrq.device); 1124 struct hns_roce_v2_db db = {}; 1125 1126 hr_reg_write(&db, DB_TAG, srq->srqn); 1127 hr_reg_write(&db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 1128 hr_reg_write(&db, DB_PI, srq->idx_que.head); 1129 1130 hns_roce_write64(hr_dev, (__le32 *)&db, srq->db_reg); 1131 } 1132 1133 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 1134 const struct ib_recv_wr *wr, 1135 const struct ib_recv_wr **bad_wr) 1136 { 1137 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 1138 unsigned long flags; 1139 int ret = 0; 1140 u32 max_sge; 1141 u32 wqe_idx; 1142 void *wqe; 1143 u32 nreq; 1144 1145 spin_lock_irqsave(&srq->lock, flags); 1146 1147 max_sge = srq->max_gs - srq->rsv_sge; 1148 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1149 ret = check_post_srq_valid(srq, max_sge, wr); 1150 if (ret) { 1151 *bad_wr = wr; 1152 break; 1153 } 1154 1155 ret = get_srq_wqe_idx(srq, &wqe_idx); 1156 if (unlikely(ret)) { 1157 *bad_wr = wr; 1158 break; 1159 } 1160 1161 wqe = get_srq_wqe_buf(srq, wqe_idx); 1162 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1163 fill_wqe_idx(srq, wqe_idx); 1164 srq->wrid[wqe_idx] = wr->wr_id; 1165 1166 trace_hns_srq_wqe(srq->srqn, wqe_idx, wqe, 1 << srq->wqe_shift, 1167 wr->wr_id, TRACE_SRQ); 1168 } 1169 1170 if (likely(nreq)) { 1171 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) 1172 *srq->rdb.db_record = srq->idx_que.head & 1173 V2_DB_PRODUCER_IDX_M; 1174 else 1175 update_srq_db(srq); 1176 } 1177 1178 spin_unlock_irqrestore(&srq->lock, flags); 1179 1180 return ret; 1181 } 1182 1183 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1184 unsigned long instance_stage, 1185 unsigned long reset_stage) 1186 { 1187 /* When hardware reset has been completed once or more, we should stop 1188 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1189 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1190 * stage of soft reset process, we should exit with error, and then 1191 * HNAE3_INIT_CLIENT related process can rollback the operation like 1192 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1193 * process will exit with error to notify NIC driver to reschedule soft 1194 * reset process once again. 1195 */ 1196 hr_dev->is_reset = true; 1197 hr_dev->dis_db = true; 1198 1199 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1200 instance_stage == HNS_ROCE_STATE_INIT) 1201 return CMD_RST_PRC_EBUSY; 1202 1203 return CMD_RST_PRC_SUCCESS; 1204 } 1205 1206 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1207 unsigned long instance_stage, 1208 unsigned long reset_stage) 1209 { 1210 #define HW_RESET_TIMEOUT_US 1000000 1211 #define HW_RESET_SLEEP_US 1000 1212 1213 struct hns_roce_v2_priv *priv = hr_dev->priv; 1214 struct hnae3_handle *handle = priv->handle; 1215 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1216 unsigned long val; 1217 int ret; 1218 1219 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1220 * doorbell to hardware. If now in .init_instance() function, we should 1221 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1222 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1223 * related process can rollback the operation like notifing hardware to 1224 * free resources, HNAE3_INIT_CLIENT related process will exit with 1225 * error to notify NIC driver to reschedule soft reset process once 1226 * again. 1227 */ 1228 hr_dev->dis_db = true; 1229 1230 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1231 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1232 HW_RESET_TIMEOUT_US, false, handle); 1233 if (!ret) 1234 hr_dev->is_reset = true; 1235 1236 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1237 instance_stage == HNS_ROCE_STATE_INIT) 1238 return CMD_RST_PRC_EBUSY; 1239 1240 return CMD_RST_PRC_SUCCESS; 1241 } 1242 1243 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1244 { 1245 struct hns_roce_v2_priv *priv = hr_dev->priv; 1246 struct hnae3_handle *handle = priv->handle; 1247 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1248 1249 /* When software reset is detected at .init_instance() function, we 1250 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1251 * with error. 1252 */ 1253 hr_dev->dis_db = true; 1254 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1255 hr_dev->is_reset = true; 1256 1257 return CMD_RST_PRC_EBUSY; 1258 } 1259 1260 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1261 struct hnae3_handle *handle) 1262 { 1263 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1264 unsigned long instance_stage; /* the current instance stage */ 1265 unsigned long reset_stage; /* the current reset stage */ 1266 unsigned long reset_cnt; 1267 bool sw_resetting; 1268 bool hw_resetting; 1269 1270 /* Get information about reset from NIC driver or RoCE driver itself, 1271 * the meaning of the following variables from NIC driver are described 1272 * as below: 1273 * reset_cnt -- The count value of completed hardware reset. 1274 * hw_resetting -- Whether hardware device is resetting now. 1275 * sw_resetting -- Whether NIC's software reset process is running now. 1276 */ 1277 instance_stage = handle->rinfo.instance_state; 1278 reset_stage = handle->rinfo.reset_state; 1279 reset_cnt = ops->ae_dev_reset_cnt(handle); 1280 if (reset_cnt != hr_dev->reset_cnt) 1281 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1282 reset_stage); 1283 1284 hw_resetting = ops->get_cmdq_stat(handle); 1285 if (hw_resetting) 1286 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1287 reset_stage); 1288 1289 sw_resetting = ops->ae_dev_resetting(handle); 1290 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1291 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1292 1293 return CMD_RST_PRC_OTHERS; 1294 } 1295 1296 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1297 { 1298 struct hns_roce_v2_priv *priv = hr_dev->priv; 1299 struct hnae3_handle *handle = priv->handle; 1300 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1301 1302 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1303 return true; 1304 1305 if (ops->get_hw_reset_stat(handle)) 1306 return true; 1307 1308 if (ops->ae_dev_resetting(handle)) 1309 return true; 1310 1311 return false; 1312 } 1313 1314 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1315 { 1316 struct hns_roce_v2_priv *priv = hr_dev->priv; 1317 u32 status; 1318 1319 if (hr_dev->is_reset) 1320 status = CMD_RST_PRC_SUCCESS; 1321 else 1322 status = check_aedev_reset_status(hr_dev, priv->handle); 1323 1324 *busy = (status == CMD_RST_PRC_EBUSY); 1325 1326 return status == CMD_RST_PRC_OTHERS; 1327 } 1328 1329 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1330 struct hns_roce_v2_cmq_ring *ring) 1331 { 1332 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1333 1334 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1335 &ring->desc_dma_addr, GFP_KERNEL); 1336 if (!ring->desc) 1337 return -ENOMEM; 1338 1339 return 0; 1340 } 1341 1342 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1343 struct hns_roce_v2_cmq_ring *ring) 1344 { 1345 dma_free_coherent(hr_dev->dev, 1346 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1347 ring->desc, ring->desc_dma_addr); 1348 1349 ring->desc_dma_addr = 0; 1350 } 1351 1352 static int init_csq(struct hns_roce_dev *hr_dev, 1353 struct hns_roce_v2_cmq_ring *csq) 1354 { 1355 dma_addr_t dma; 1356 int ret; 1357 1358 csq->desc_num = CMD_CSQ_DESC_NUM; 1359 spin_lock_init(&csq->lock); 1360 csq->flag = TYPE_CSQ; 1361 csq->head = 0; 1362 1363 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1364 if (ret) 1365 return ret; 1366 1367 dma = csq->desc_dma_addr; 1368 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1369 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1370 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1371 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1372 1373 /* Make sure to write CI first and then PI */ 1374 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1375 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1376 1377 return 0; 1378 } 1379 1380 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1381 { 1382 struct hns_roce_v2_priv *priv = hr_dev->priv; 1383 int ret; 1384 1385 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1386 1387 ret = init_csq(hr_dev, &priv->cmq.csq); 1388 if (ret) 1389 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1390 1391 return ret; 1392 } 1393 1394 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1395 { 1396 struct hns_roce_v2_priv *priv = hr_dev->priv; 1397 1398 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1399 } 1400 1401 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1402 enum hns_roce_opcode_type opcode, 1403 bool is_read) 1404 { 1405 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1406 desc->opcode = cpu_to_le16(opcode); 1407 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1408 if (is_read) 1409 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1410 else 1411 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1412 } 1413 1414 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1415 { 1416 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1417 struct hns_roce_v2_priv *priv = hr_dev->priv; 1418 1419 return tail == priv->cmq.csq.head; 1420 } 1421 1422 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1423 { 1424 struct hns_roce_v2_priv *priv = hr_dev->priv; 1425 struct hnae3_handle *handle = priv->handle; 1426 1427 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1428 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1429 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1430 } 1431 1432 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1433 { 1434 struct hns_roce_cmd_errcode errcode_table[] = { 1435 {CMD_EXEC_SUCCESS, 0}, 1436 {CMD_NO_AUTH, -EPERM}, 1437 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1438 {CMD_CRQ_FULL, -EXFULL}, 1439 {CMD_NEXT_ERR, -ENOSR}, 1440 {CMD_NOT_EXEC, -ENOTBLK}, 1441 {CMD_PARA_ERR, -EINVAL}, 1442 {CMD_RESULT_ERR, -ERANGE}, 1443 {CMD_TIMEOUT, -ETIME}, 1444 {CMD_HILINK_ERR, -ENOLINK}, 1445 {CMD_INFO_ILLEGAL, -ENXIO}, 1446 {CMD_INVALID, -EBADR}, 1447 }; 1448 u16 i; 1449 1450 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1451 if (desc_ret == errcode_table[i].return_status) 1452 return errcode_table[i].errno; 1453 return -EIO; 1454 } 1455 1456 static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) 1457 { 1458 static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = { 1459 {HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT}, 1460 }; 1461 int i; 1462 1463 for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++) 1464 if (cmdq_tx_timeout[i].opcode == opcode) 1465 return cmdq_tx_timeout[i].tx_timeout; 1466 1467 return tx_timeout; 1468 } 1469 1470 static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u32 tx_timeout) 1471 { 1472 u32 timeout = 0; 1473 1474 do { 1475 if (hns_roce_cmq_csq_done(hr_dev)) 1476 break; 1477 udelay(1); 1478 } while (++timeout < tx_timeout); 1479 } 1480 1481 static int __hns_roce_cmq_send_one(struct hns_roce_dev *hr_dev, 1482 struct hns_roce_cmq_desc *desc, 1483 int num, u32 tx_timeout) 1484 { 1485 struct hns_roce_v2_priv *priv = hr_dev->priv; 1486 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1487 u16 desc_ret; 1488 u32 tail; 1489 int ret; 1490 int i; 1491 1492 tail = csq->head; 1493 1494 for (i = 0; i < num; i++) { 1495 trace_hns_cmdq_req(hr_dev, &desc[i]); 1496 1497 csq->desc[csq->head++] = desc[i]; 1498 if (csq->head == csq->desc_num) 1499 csq->head = 0; 1500 } 1501 1502 /* Write to hardware */ 1503 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1504 1505 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]); 1506 1507 hns_roce_wait_csq_done(hr_dev, tx_timeout); 1508 if (hns_roce_cmq_csq_done(hr_dev)) { 1509 ret = 0; 1510 for (i = 0; i < num; i++) { 1511 trace_hns_cmdq_resp(hr_dev, &csq->desc[tail]); 1512 1513 /* check the result of hardware write back */ 1514 desc_ret = le16_to_cpu(csq->desc[tail++].retval); 1515 if (tail == csq->desc_num) 1516 tail = 0; 1517 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1518 continue; 1519 1520 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1521 } 1522 } else { 1523 /* FW/HW reset or incorrect number of desc */ 1524 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1525 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1526 csq->head, tail); 1527 csq->head = tail; 1528 1529 update_cmdq_status(hr_dev); 1530 1531 ret = -EAGAIN; 1532 } 1533 1534 if (ret) 1535 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_ERR_CNT]); 1536 1537 return ret; 1538 } 1539 1540 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1541 struct hns_roce_cmq_desc *desc, int num) 1542 { 1543 struct hns_roce_v2_priv *priv = hr_dev->priv; 1544 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1545 u16 opcode = le16_to_cpu(desc->opcode); 1546 u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout); 1547 u8 try_cnt = HNS_ROCE_OPC_POST_MB_TRY_CNT; 1548 u32 rsv_tail; 1549 int ret; 1550 int i; 1551 1552 while (try_cnt) { 1553 try_cnt--; 1554 1555 spin_lock_bh(&csq->lock); 1556 rsv_tail = csq->head; 1557 ret = __hns_roce_cmq_send_one(hr_dev, desc, num, tx_timeout); 1558 if (opcode == HNS_ROCE_OPC_POST_MB && ret == -ETIME && 1559 try_cnt) { 1560 spin_unlock_bh(&csq->lock); 1561 mdelay(HNS_ROCE_OPC_POST_MB_RETRY_GAP_MSEC); 1562 continue; 1563 } 1564 1565 for (i = 0; i < num; i++) { 1566 desc[i] = csq->desc[rsv_tail++]; 1567 if (rsv_tail == csq->desc_num) 1568 rsv_tail = 0; 1569 } 1570 spin_unlock_bh(&csq->lock); 1571 break; 1572 } 1573 1574 if (ret) 1575 dev_err_ratelimited(hr_dev->dev, 1576 "Cmdq IO error, opcode = 0x%x, return = %d.\n", 1577 opcode, ret); 1578 1579 return ret; 1580 } 1581 1582 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1583 struct hns_roce_cmq_desc *desc, int num) 1584 { 1585 bool busy; 1586 int ret; 1587 1588 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1589 return -EIO; 1590 1591 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1592 return busy ? -EBUSY : 0; 1593 1594 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1595 if (ret) { 1596 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1597 return busy ? -EBUSY : 0; 1598 } 1599 1600 return ret; 1601 } 1602 1603 static enum hns_roce_opcode_type 1604 get_bond_opcode(enum hns_roce_bond_cmd_type bond_type) 1605 { 1606 switch (bond_type) { 1607 case HNS_ROCE_SET_BOND: 1608 return HNS_ROCE_OPC_SET_BOND_INFO; 1609 case HNS_ROCE_CHANGE_BOND: 1610 return HNS_ROCE_OPC_CHANGE_ACTIVE_PORT; 1611 case HNS_ROCE_CLEAR_BOND: 1612 return HNS_ROCE_OPC_CLEAR_BOND_INFO; 1613 default: 1614 WARN(true, "Invalid bond type %d!\n", bond_type); 1615 return HNS_ROCE_OPC_SET_BOND_INFO; 1616 } 1617 } 1618 1619 static enum hns_roce_bond_hashtype 1620 get_bond_hashtype(enum netdev_lag_hash netdev_hashtype) 1621 { 1622 switch (netdev_hashtype) { 1623 case NETDEV_LAG_HASH_L2: 1624 return BOND_HASH_L2; 1625 case NETDEV_LAG_HASH_L34: 1626 return BOND_HASH_L34; 1627 case NETDEV_LAG_HASH_L23: 1628 return BOND_HASH_L23; 1629 default: 1630 WARN(true, "Invalid hash type %d!\n", netdev_hashtype); 1631 return BOND_HASH_L2; 1632 } 1633 } 1634 1635 int hns_roce_cmd_bond(struct hns_roce_bond_group *bond_grp, 1636 enum hns_roce_bond_cmd_type bond_type) 1637 { 1638 enum hns_roce_opcode_type opcode = get_bond_opcode(bond_type); 1639 struct hns_roce_bond_info *slave_info; 1640 struct hns_roce_cmq_desc desc = {}; 1641 int ret; 1642 1643 slave_info = (struct hns_roce_bond_info *)desc.data; 1644 hns_roce_cmq_setup_basic_desc(&desc, opcode, false); 1645 1646 slave_info->bond_id = cpu_to_le32(bond_grp->bond_id); 1647 if (bond_type == HNS_ROCE_CLEAR_BOND) 1648 goto out; 1649 1650 if (bond_grp->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) { 1651 slave_info->bond_mode = cpu_to_le32(BOND_MODE_1); 1652 if (bond_grp->active_slave_num != 1) 1653 ibdev_warn(&bond_grp->main_hr_dev->ib_dev, 1654 "active slave cnt(%u) in Mode 1 is invalid.\n", 1655 bond_grp->active_slave_num); 1656 } else { 1657 slave_info->bond_mode = cpu_to_le32(BOND_MODE_2_4); 1658 slave_info->hash_policy = 1659 cpu_to_le32(get_bond_hashtype(bond_grp->hash_type)); 1660 } 1661 1662 slave_info->active_slave_cnt = cpu_to_le32(bond_grp->active_slave_num); 1663 slave_info->active_slave_mask = cpu_to_le32(bond_grp->active_slave_map); 1664 slave_info->slave_mask = cpu_to_le32(bond_grp->slave_map); 1665 1666 out: 1667 ret = hns_roce_cmq_send(bond_grp->main_hr_dev, &desc, 1); 1668 if (ret) 1669 ibdev_err(&bond_grp->main_hr_dev->ib_dev, 1670 "cmq bond type(%d) failed, ret = %d.\n", 1671 bond_type, ret); 1672 1673 return ret; 1674 } 1675 1676 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1677 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1678 { 1679 struct hns_roce_cmd_mailbox *mbox; 1680 int ret; 1681 1682 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1683 if (IS_ERR(mbox)) 1684 return PTR_ERR(mbox); 1685 1686 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1687 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1688 return ret; 1689 } 1690 1691 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1692 { 1693 struct hns_roce_query_version *resp; 1694 struct hns_roce_cmq_desc desc; 1695 int ret; 1696 1697 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1698 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1699 if (ret) 1700 return ret; 1701 1702 resp = (struct hns_roce_query_version *)desc.data; 1703 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1704 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1705 1706 return 0; 1707 } 1708 1709 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1710 struct hnae3_handle *handle) 1711 { 1712 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1713 unsigned long end; 1714 1715 hr_dev->dis_db = true; 1716 1717 dev_warn(hr_dev->dev, 1718 "func clear is pending, device in resetting state.\n"); 1719 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1720 while (end) { 1721 if (!ops->get_hw_reset_stat(handle)) { 1722 hr_dev->is_reset = true; 1723 dev_info(hr_dev->dev, 1724 "func clear success after reset.\n"); 1725 return; 1726 } 1727 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1728 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1729 } 1730 1731 dev_warn(hr_dev->dev, "func clear failed.\n"); 1732 } 1733 1734 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1735 struct hnae3_handle *handle) 1736 { 1737 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1738 unsigned long end; 1739 1740 hr_dev->dis_db = true; 1741 1742 dev_warn(hr_dev->dev, 1743 "func clear is pending, device in resetting state.\n"); 1744 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1745 while (end) { 1746 if (ops->ae_dev_reset_cnt(handle) != 1747 hr_dev->reset_cnt) { 1748 hr_dev->is_reset = true; 1749 dev_info(hr_dev->dev, 1750 "func clear success after sw reset\n"); 1751 return; 1752 } 1753 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1754 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1755 } 1756 1757 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1758 } 1759 1760 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1761 int flag) 1762 { 1763 struct hns_roce_v2_priv *priv = hr_dev->priv; 1764 struct hnae3_handle *handle = priv->handle; 1765 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1766 1767 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1768 hr_dev->dis_db = true; 1769 hr_dev->is_reset = true; 1770 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1771 return; 1772 } 1773 1774 if (ops->get_hw_reset_stat(handle)) { 1775 func_clr_hw_resetting_state(hr_dev, handle); 1776 return; 1777 } 1778 1779 if (ops->ae_dev_resetting(handle) && 1780 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1781 func_clr_sw_resetting_state(hr_dev, handle); 1782 return; 1783 } 1784 1785 if (retval && !flag) 1786 dev_warn(hr_dev->dev, 1787 "func clear read failed, ret = %d.\n", retval); 1788 1789 dev_warn(hr_dev->dev, "func clear failed.\n"); 1790 } 1791 1792 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1793 { 1794 bool fclr_write_fail_flag = false; 1795 struct hns_roce_func_clear *resp; 1796 struct hns_roce_cmq_desc desc; 1797 unsigned long end; 1798 int ret = 0; 1799 1800 if (check_device_is_in_reset(hr_dev)) 1801 goto out; 1802 1803 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1804 resp = (struct hns_roce_func_clear *)desc.data; 1805 resp->rst_funcid_en = cpu_to_le32(vf_id); 1806 1807 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1808 if (ret) { 1809 fclr_write_fail_flag = true; 1810 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1811 ret); 1812 goto out; 1813 } 1814 1815 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1816 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1817 while (end) { 1818 if (check_device_is_in_reset(hr_dev)) 1819 goto out; 1820 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1821 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1822 1823 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1824 true); 1825 1826 resp->rst_funcid_en = cpu_to_le32(vf_id); 1827 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1828 if (ret) 1829 continue; 1830 1831 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1832 if (vf_id == 0) 1833 hr_dev->is_reset = true; 1834 return; 1835 } 1836 } 1837 1838 out: 1839 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1840 } 1841 1842 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1843 { 1844 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1845 struct hns_roce_cmq_desc desc[2]; 1846 struct hns_roce_cmq_req *req_a; 1847 1848 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1849 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1850 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1851 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1852 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1853 1854 return hns_roce_cmq_send(hr_dev, desc, 2); 1855 } 1856 1857 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1858 { 1859 int ret; 1860 int i; 1861 1862 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1863 return; 1864 1865 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1866 __hns_roce_function_clear(hr_dev, i); 1867 1868 if (i == 0) 1869 continue; 1870 1871 ret = hns_roce_free_vf_resource(hr_dev, i); 1872 if (ret) 1873 ibdev_err(&hr_dev->ib_dev, 1874 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1875 i, ret); 1876 } 1877 } 1878 1879 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1880 { 1881 struct hns_roce_cmq_desc desc; 1882 int ret; 1883 1884 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1885 false); 1886 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1887 if (ret) 1888 ibdev_err(&hr_dev->ib_dev, 1889 "failed to clear extended doorbell info, ret = %d.\n", 1890 ret); 1891 1892 return ret; 1893 } 1894 1895 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1896 { 1897 struct hns_roce_query_fw_info *resp; 1898 struct hns_roce_cmq_desc desc; 1899 int ret; 1900 1901 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1902 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1903 if (ret) 1904 return ret; 1905 1906 resp = (struct hns_roce_query_fw_info *)desc.data; 1907 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1908 1909 return 0; 1910 } 1911 1912 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1913 { 1914 struct hns_roce_cmq_desc desc; 1915 int ret; 1916 1917 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1918 hr_dev->func_num = 1; 1919 return 0; 1920 } 1921 1922 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1923 true); 1924 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1925 if (ret) { 1926 hr_dev->func_num = 1; 1927 return ret; 1928 } 1929 1930 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1931 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1932 1933 return 0; 1934 } 1935 1936 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1937 u64 *stats, u32 port, int *num_counters) 1938 { 1939 #define CNT_PER_DESC 3 1940 struct hns_roce_cmq_desc *desc; 1941 int bd_idx, cnt_idx; 1942 __le64 *cnt_data; 1943 int desc_num; 1944 int ret; 1945 int i; 1946 1947 if (port > hr_dev->caps.num_ports) 1948 return -EINVAL; 1949 1950 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1951 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1952 if (!desc) 1953 return -ENOMEM; 1954 1955 for (i = 0; i < desc_num; i++) { 1956 hns_roce_cmq_setup_basic_desc(&desc[i], 1957 HNS_ROCE_OPC_QUERY_COUNTER, true); 1958 if (i != desc_num - 1) 1959 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1960 } 1961 1962 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1963 if (ret) { 1964 ibdev_err(&hr_dev->ib_dev, 1965 "failed to get counter, ret = %d.\n", ret); 1966 goto err_out; 1967 } 1968 1969 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1970 bd_idx = i / CNT_PER_DESC; 1971 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC && 1972 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT))) 1973 break; 1974 1975 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1976 cnt_idx = i % CNT_PER_DESC; 1977 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1978 } 1979 *num_counters = i; 1980 1981 err_out: 1982 kfree(desc); 1983 return ret; 1984 } 1985 1986 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1987 { 1988 struct hns_roce_cmq_desc desc; 1989 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1990 u32 clock_cycles_of_1us; 1991 1992 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1993 false); 1994 1995 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1996 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1997 else 1998 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1999 2000 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 2001 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 2002 2003 return hns_roce_cmq_send(hr_dev, &desc, 1); 2004 } 2005 2006 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 2007 { 2008 struct hns_roce_cmq_desc desc[2]; 2009 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2010 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2011 struct hns_roce_caps *caps = &hr_dev->caps; 2012 enum hns_roce_opcode_type opcode; 2013 u32 func_num; 2014 int ret; 2015 2016 if (is_vf) { 2017 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 2018 func_num = 1; 2019 } else { 2020 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 2021 func_num = hr_dev->func_num; 2022 } 2023 2024 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 2025 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2026 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 2027 2028 ret = hns_roce_cmq_send(hr_dev, desc, 2); 2029 if (ret) 2030 return ret; 2031 2032 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 2033 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 2034 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 2035 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 2036 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 2037 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 2038 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 2039 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 2040 2041 if (is_vf) { 2042 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 2043 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 2044 func_num; 2045 } else { 2046 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 2047 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 2048 func_num; 2049 } 2050 2051 return 0; 2052 } 2053 2054 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 2055 { 2056 struct hns_roce_cmq_desc desc; 2057 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2058 struct hns_roce_caps *caps = &hr_dev->caps; 2059 int ret; 2060 2061 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 2062 true); 2063 2064 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 2065 if (ret) 2066 return ret; 2067 2068 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 2069 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 2070 2071 return 0; 2072 } 2073 2074 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 2075 { 2076 struct device *dev = hr_dev->dev; 2077 int ret; 2078 2079 ret = load_func_res_caps(hr_dev, false); 2080 if (ret) { 2081 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 2082 return ret; 2083 } 2084 2085 ret = load_pf_timer_res_caps(hr_dev); 2086 if (ret) 2087 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 2088 ret); 2089 2090 return ret; 2091 } 2092 2093 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 2094 { 2095 struct device *dev = hr_dev->dev; 2096 int ret; 2097 2098 ret = load_func_res_caps(hr_dev, true); 2099 if (ret) 2100 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 2101 2102 return ret; 2103 } 2104 2105 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 2106 u32 vf_id) 2107 { 2108 struct hns_roce_vf_switch *swt; 2109 struct hns_roce_cmq_desc desc; 2110 int ret; 2111 2112 swt = (struct hns_roce_vf_switch *)desc.data; 2113 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 2114 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 2115 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 2116 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 2117 if (ret) 2118 return ret; 2119 2120 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 2121 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 2122 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 2123 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 2124 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 2125 2126 return hns_roce_cmq_send(hr_dev, &desc, 1); 2127 } 2128 2129 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 2130 { 2131 u32 vf_id; 2132 int ret; 2133 2134 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 2135 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 2136 if (ret) 2137 return ret; 2138 } 2139 return 0; 2140 } 2141 2142 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 2143 { 2144 struct hns_roce_cmq_desc desc[2]; 2145 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2146 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2147 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 2148 struct hns_roce_caps *caps = &hr_dev->caps; 2149 2150 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2151 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2152 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2153 2154 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 2155 2156 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 2157 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 2158 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 2159 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 2160 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 2161 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 2162 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 2163 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 2164 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 2165 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 2166 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 2167 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 2168 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 2169 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 2170 2171 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2172 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 2173 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 2174 vf_id * caps->gmv_bt_num); 2175 } else { 2176 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 2177 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 2178 vf_id * caps->sgid_bt_num); 2179 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 2180 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 2181 vf_id * caps->smac_bt_num); 2182 } 2183 2184 return hns_roce_cmq_send(hr_dev, desc, 2); 2185 } 2186 2187 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 2188 { 2189 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2190 u32 vf_id; 2191 int ret; 2192 2193 for (vf_id = 0; vf_id < func_num; vf_id++) { 2194 ret = config_vf_hem_resource(hr_dev, vf_id); 2195 if (ret) { 2196 dev_err(hr_dev->dev, 2197 "failed to config vf-%u hem res, ret = %d.\n", 2198 vf_id, ret); 2199 return ret; 2200 } 2201 } 2202 2203 return 0; 2204 } 2205 2206 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 2207 { 2208 struct hns_roce_cmq_desc desc; 2209 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2210 struct hns_roce_caps *caps = &hr_dev->caps; 2211 2212 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 2213 2214 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 2215 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 2216 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 2217 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 2218 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 2219 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 2220 2221 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 2222 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 2223 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 2224 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 2225 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 2226 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 2227 2228 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 2229 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 2230 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 2231 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 2232 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 2233 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 2234 2235 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 2236 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 2237 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 2238 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 2239 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 2240 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 2241 2242 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 2243 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 2244 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 2245 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 2246 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 2247 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 2248 2249 return hns_roce_cmq_send(hr_dev, &desc, 1); 2250 } 2251 2252 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2253 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2254 { 2255 u64 obj_per_chunk; 2256 u64 bt_chunk_size = PAGE_SIZE; 2257 u64 buf_chunk_size = PAGE_SIZE; 2258 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2259 2260 *buf_page_size = 0; 2261 *bt_page_size = 0; 2262 2263 switch (hop_num) { 2264 case 3: 2265 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2266 (bt_chunk_size / BA_BYTE_LEN) * 2267 (bt_chunk_size / BA_BYTE_LEN) * 2268 obj_per_chunk_default; 2269 break; 2270 case 2: 2271 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2272 (bt_chunk_size / BA_BYTE_LEN) * 2273 obj_per_chunk_default; 2274 break; 2275 case 1: 2276 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2277 obj_per_chunk_default; 2278 break; 2279 case HNS_ROCE_HOP_NUM_0: 2280 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2281 break; 2282 default: 2283 pr_err("table %u not support hop_num = %u!\n", hem_type, 2284 hop_num); 2285 return; 2286 } 2287 2288 if (hem_type >= HEM_TYPE_MTT) 2289 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2290 else 2291 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2292 } 2293 2294 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2295 { 2296 struct hns_roce_caps *caps = &hr_dev->caps; 2297 2298 /* EQ */ 2299 caps->eqe_ba_pg_sz = 0; 2300 caps->eqe_buf_pg_sz = 0; 2301 2302 /* Link Table */ 2303 caps->llm_buf_pg_sz = 0; 2304 2305 /* MR */ 2306 caps->mpt_ba_pg_sz = 0; 2307 caps->mpt_buf_pg_sz = 0; 2308 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2309 caps->pbl_buf_pg_sz = 0; 2310 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2311 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2312 HEM_TYPE_MTPT); 2313 2314 /* QP */ 2315 caps->qpc_ba_pg_sz = 0; 2316 caps->qpc_buf_pg_sz = 0; 2317 caps->qpc_timer_ba_pg_sz = 0; 2318 caps->qpc_timer_buf_pg_sz = 0; 2319 caps->sccc_ba_pg_sz = 0; 2320 caps->sccc_buf_pg_sz = 0; 2321 caps->mtt_ba_pg_sz = 0; 2322 caps->mtt_buf_pg_sz = 0; 2323 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2324 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2325 HEM_TYPE_QPC); 2326 2327 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2328 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2329 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2330 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2331 2332 /* CQ */ 2333 caps->cqc_ba_pg_sz = 0; 2334 caps->cqc_buf_pg_sz = 0; 2335 caps->cqc_timer_ba_pg_sz = 0; 2336 caps->cqc_timer_buf_pg_sz = 0; 2337 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2338 caps->cqe_buf_pg_sz = 0; 2339 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2340 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2341 HEM_TYPE_CQC); 2342 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2343 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2344 2345 /* SRQ */ 2346 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2347 caps->srqc_ba_pg_sz = 0; 2348 caps->srqc_buf_pg_sz = 0; 2349 caps->srqwqe_ba_pg_sz = 0; 2350 caps->srqwqe_buf_pg_sz = 0; 2351 caps->idx_ba_pg_sz = 0; 2352 caps->idx_buf_pg_sz = 0; 2353 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2354 caps->srqc_hop_num, caps->srqc_bt_num, 2355 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2356 HEM_TYPE_SRQC); 2357 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2358 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2359 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2360 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2361 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2362 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2363 } 2364 2365 /* GMV */ 2366 caps->gmv_ba_pg_sz = 0; 2367 caps->gmv_buf_pg_sz = 0; 2368 } 2369 2370 /* Apply all loaded caps before setting to hardware */ 2371 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2372 { 2373 #define MAX_GID_TBL_LEN 256 2374 struct hns_roce_caps *caps = &hr_dev->caps; 2375 struct hns_roce_v2_priv *priv = hr_dev->priv; 2376 2377 /* The following configurations don't need to be got from firmware. */ 2378 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2379 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2380 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2381 2382 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2383 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2384 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2385 2386 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2387 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2388 2389 if (!caps->num_comp_vectors) 2390 caps->num_comp_vectors = 2391 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2392 (u32)priv->handle->rinfo.num_vectors - 2393 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2394 2395 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2396 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2397 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2398 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2399 2400 /* The following configurations will be overwritten */ 2401 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2402 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2403 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2404 2405 /* The following configurations are not got from firmware */ 2406 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2407 2408 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2409 2410 /* It's meaningless to support excessively large gid_table_len, 2411 * as the type of sgid_index in kernel struct ib_global_route 2412 * and userspace struct ibv_global_route are u8/uint8_t (0-255). 2413 */ 2414 caps->gid_table_len[0] = min_t(u32, MAX_GID_TBL_LEN, 2415 caps->gmv_bt_num * 2416 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz)); 2417 2418 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2419 caps->gmv_entry_sz); 2420 } else { 2421 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2422 2423 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2424 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2425 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2426 caps->gid_table_len[0] /= func_num; 2427 } 2428 2429 if (hr_dev->is_vf) { 2430 caps->default_aeq_arm_st = 0x3; 2431 caps->default_ceq_arm_st = 0x3; 2432 caps->default_ceq_max_cnt = 0x1; 2433 caps->default_ceq_period = 0x10; 2434 caps->default_aeq_max_cnt = 0x1; 2435 caps->default_aeq_period = 0x10; 2436 } 2437 2438 set_hem_page_size(hr_dev); 2439 } 2440 2441 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2442 { 2443 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM] = {}; 2444 struct hns_roce_caps *caps = &hr_dev->caps; 2445 struct hns_roce_query_pf_caps_a *resp_a; 2446 struct hns_roce_query_pf_caps_b *resp_b; 2447 struct hns_roce_query_pf_caps_c *resp_c; 2448 struct hns_roce_query_pf_caps_d *resp_d; 2449 struct hns_roce_query_pf_caps_e *resp_e; 2450 struct hns_roce_query_pf_caps_f *resp_f; 2451 enum hns_roce_opcode_type cmd; 2452 int ctx_hop_num; 2453 int pbl_hop_num; 2454 int cmd_num; 2455 int ret; 2456 int i; 2457 2458 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2459 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2460 cmd_num = hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 2461 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM_HIP08 : 2462 HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; 2463 2464 for (i = 0; i < cmd_num - 1; i++) { 2465 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2466 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2467 } 2468 2469 hns_roce_cmq_setup_basic_desc(&desc[cmd_num - 1], cmd, true); 2470 desc[cmd_num - 1].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2471 2472 ret = hns_roce_cmq_send(hr_dev, desc, cmd_num); 2473 if (ret) 2474 return ret; 2475 2476 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2477 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2478 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2479 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2480 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2481 resp_f = (struct hns_roce_query_pf_caps_f *)desc[5].data; 2482 2483 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2484 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2485 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2486 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2487 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2488 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2489 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2490 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2491 caps->num_other_vectors = resp_a->num_other_vectors; 2492 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2493 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2494 2495 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2496 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2497 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2498 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2499 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2500 caps->idx_entry_sz = resp_b->idx_entry_sz; 2501 caps->sccc_sz = resp_b->sccc_sz; 2502 caps->max_mtu = resp_b->max_mtu; 2503 caps->min_cqes = resp_b->min_cqes; 2504 caps->min_wqes = resp_b->min_wqes; 2505 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2506 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2507 caps->phy_num_uars = resp_b->phy_num_uars; 2508 ctx_hop_num = resp_b->ctx_hop_num; 2509 pbl_hop_num = resp_b->pbl_hop_num; 2510 2511 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2512 2513 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2514 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2515 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2516 2517 if (hr_dev->is_vf) 2518 caps->flags &= ~HNS_ROCE_CAP_FLAG_BOND; 2519 2520 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2521 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2522 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2523 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2524 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2525 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2526 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2527 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2528 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2529 2530 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2531 caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP); 2532 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2533 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2534 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2535 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2536 caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG); 2537 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2538 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2539 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2540 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2541 2542 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2543 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2544 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2545 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2546 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2547 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2548 2549 caps->max_ack_req_msg_len = le32_to_cpu(resp_f->max_ack_req_msg_len); 2550 2551 caps->qpc_hop_num = ctx_hop_num; 2552 caps->sccc_hop_num = ctx_hop_num; 2553 caps->srqc_hop_num = ctx_hop_num; 2554 caps->cqc_hop_num = ctx_hop_num; 2555 caps->mpt_hop_num = ctx_hop_num; 2556 caps->mtt_hop_num = pbl_hop_num; 2557 caps->cqe_hop_num = pbl_hop_num; 2558 caps->srqwqe_hop_num = pbl_hop_num; 2559 caps->idx_hop_num = pbl_hop_num; 2560 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2561 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2562 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2563 2564 if (!(caps->page_size_cap & PAGE_SIZE)) 2565 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2566 2567 if (!hr_dev->is_vf) { 2568 caps->cqe_sz = resp_a->cqe_sz; 2569 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2570 caps->default_aeq_arm_st = 2571 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2572 caps->default_ceq_arm_st = 2573 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2574 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2575 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2576 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2577 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2584 { 2585 struct hns_roce_cmq_desc desc; 2586 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2587 2588 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2589 false); 2590 2591 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2592 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2593 2594 return hns_roce_cmq_send(hr_dev, &desc, 1); 2595 } 2596 2597 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2598 { 2599 struct hns_roce_caps *caps = &hr_dev->caps; 2600 int ret; 2601 2602 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2603 return 0; 2604 2605 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2606 caps->qpc_sz); 2607 if (ret) { 2608 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2609 return ret; 2610 } 2611 2612 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2613 caps->sccc_sz); 2614 if (ret) 2615 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2616 2617 return ret; 2618 } 2619 2620 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2621 { 2622 struct device *dev = hr_dev->dev; 2623 int ret; 2624 2625 hr_dev->func_num = 1; 2626 2627 ret = hns_roce_query_caps(hr_dev); 2628 if (ret) { 2629 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2630 return ret; 2631 } 2632 2633 ret = hns_roce_query_vf_resource(hr_dev); 2634 if (ret) { 2635 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2636 return ret; 2637 } 2638 2639 apply_func_caps(hr_dev); 2640 2641 ret = hns_roce_v2_set_bt(hr_dev); 2642 if (ret) 2643 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2644 2645 return ret; 2646 } 2647 2648 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2649 { 2650 struct device *dev = hr_dev->dev; 2651 int ret; 2652 2653 ret = hns_roce_query_func_info(hr_dev); 2654 if (ret) { 2655 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2656 return ret; 2657 } 2658 2659 ret = hns_roce_config_global_param(hr_dev); 2660 if (ret) { 2661 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2662 return ret; 2663 } 2664 2665 ret = hns_roce_set_vf_switch_param(hr_dev); 2666 if (ret) { 2667 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2668 return ret; 2669 } 2670 2671 ret = hns_roce_query_caps(hr_dev); 2672 if (ret) { 2673 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2674 return ret; 2675 } 2676 2677 ret = hns_roce_query_pf_resource(hr_dev); 2678 if (ret) { 2679 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2680 return ret; 2681 } 2682 2683 apply_func_caps(hr_dev); 2684 2685 ret = hns_roce_alloc_vf_resource(hr_dev); 2686 if (ret) { 2687 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2688 return ret; 2689 } 2690 2691 ret = hns_roce_v2_set_bt(hr_dev); 2692 if (ret) { 2693 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2694 return ret; 2695 } 2696 2697 /* Configure the size of QPC, SCCC, etc. */ 2698 return hns_roce_config_entry_size(hr_dev); 2699 } 2700 2701 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2702 { 2703 struct device *dev = hr_dev->dev; 2704 int ret; 2705 2706 ret = hns_roce_cmq_query_hw_info(hr_dev); 2707 if (ret) { 2708 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2709 return ret; 2710 } 2711 2712 ret = hns_roce_query_fw_ver(hr_dev); 2713 if (ret) { 2714 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2715 return ret; 2716 } 2717 2718 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2719 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2720 2721 if (hr_dev->is_vf) 2722 return hns_roce_v2_vf_profile(hr_dev); 2723 else 2724 return hns_roce_v2_pf_profile(hr_dev); 2725 } 2726 2727 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2728 { 2729 u32 i, next_ptr, page_num; 2730 __le64 *entry = cfg_buf; 2731 dma_addr_t addr; 2732 u64 val; 2733 2734 page_num = data_buf->npages; 2735 for (i = 0; i < page_num; i++) { 2736 addr = hns_roce_buf_page(data_buf, i); 2737 if (i == (page_num - 1)) 2738 next_ptr = 0; 2739 else 2740 next_ptr = i + 1; 2741 2742 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2743 entry[i] = cpu_to_le64(val); 2744 } 2745 } 2746 2747 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2748 struct hns_roce_link_table *table) 2749 { 2750 struct hns_roce_cmq_desc desc[2]; 2751 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2752 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2753 struct hns_roce_buf *buf = table->buf; 2754 enum hns_roce_opcode_type opcode; 2755 dma_addr_t addr; 2756 2757 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2758 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2759 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2760 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2761 2762 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2763 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2764 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2765 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2766 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2767 2768 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2769 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2770 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2771 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2772 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2773 2774 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2775 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2776 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2777 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2778 2779 return hns_roce_cmq_send(hr_dev, desc, 2); 2780 } 2781 2782 static struct hns_roce_link_table * 2783 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2784 { 2785 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2786 struct hns_roce_v2_priv *priv = hr_dev->priv; 2787 struct hns_roce_link_table *link_tbl; 2788 u32 pg_shift, size, min_size; 2789 2790 link_tbl = &priv->ext_llm; 2791 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2792 size = hr_dev->caps.num_qps * hr_dev->func_num * 2793 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2794 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2795 2796 /* Alloc data table */ 2797 size = max(size, min_size); 2798 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2799 if (IS_ERR(link_tbl->buf)) 2800 return ERR_PTR(-ENOMEM); 2801 2802 /* Alloc config table */ 2803 size = link_tbl->buf->npages * sizeof(u64); 2804 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2805 &link_tbl->table.map, 2806 GFP_KERNEL); 2807 if (!link_tbl->table.buf) { 2808 hns_roce_buf_free(hr_dev, link_tbl->buf); 2809 return ERR_PTR(-ENOMEM); 2810 } 2811 2812 return link_tbl; 2813 } 2814 2815 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2816 struct hns_roce_link_table *tbl) 2817 { 2818 if (tbl->buf) { 2819 u32 size = tbl->buf->npages * sizeof(u64); 2820 2821 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2822 tbl->table.map); 2823 } 2824 2825 hns_roce_buf_free(hr_dev, tbl->buf); 2826 } 2827 2828 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2829 { 2830 struct hns_roce_link_table *link_tbl; 2831 int ret; 2832 2833 link_tbl = alloc_link_table_buf(hr_dev); 2834 if (IS_ERR(link_tbl)) 2835 return -ENOMEM; 2836 2837 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2838 ret = -EINVAL; 2839 goto err_alloc; 2840 } 2841 2842 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2843 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2844 if (ret) 2845 goto err_alloc; 2846 2847 return 0; 2848 2849 err_alloc: 2850 free_link_table_buf(hr_dev, link_tbl); 2851 return ret; 2852 } 2853 2854 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2855 { 2856 struct hns_roce_v2_priv *priv = hr_dev->priv; 2857 2858 free_link_table_buf(hr_dev, &priv->ext_llm); 2859 } 2860 2861 static void free_dip_entry(struct hns_roce_dev *hr_dev) 2862 { 2863 struct hns_roce_dip *hr_dip; 2864 unsigned long idx; 2865 2866 xa_lock(&hr_dev->qp_table.dip_xa); 2867 2868 xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) { 2869 __xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx); 2870 kfree(hr_dip); 2871 } 2872 2873 xa_unlock(&hr_dev->qp_table.dip_xa); 2874 } 2875 2876 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2877 { 2878 struct hns_roce_v2_priv *priv = hr_dev->priv; 2879 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2880 struct ib_device *ibdev = &hr_dev->ib_dev; 2881 struct hns_roce_pd *hr_pd; 2882 struct ib_pd *pd; 2883 2884 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2885 if (!hr_pd) 2886 return NULL; 2887 pd = &hr_pd->ibpd; 2888 pd->device = ibdev; 2889 2890 if (hns_roce_alloc_pd(pd, NULL)) { 2891 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2892 kfree(hr_pd); 2893 return NULL; 2894 } 2895 free_mr->rsv_pd = to_hr_pd(pd); 2896 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2897 free_mr->rsv_pd->ibpd.uobject = NULL; 2898 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2899 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2900 2901 return pd; 2902 } 2903 2904 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2905 { 2906 struct hns_roce_v2_priv *priv = hr_dev->priv; 2907 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2908 struct ib_device *ibdev = &hr_dev->ib_dev; 2909 struct ib_cq_init_attr cq_init_attr = {}; 2910 struct hns_roce_cq *hr_cq; 2911 struct ib_cq *cq; 2912 2913 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2914 2915 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2916 if (!hr_cq) 2917 return NULL; 2918 2919 cq = &hr_cq->ib_cq; 2920 cq->device = ibdev; 2921 2922 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2923 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2924 kfree(hr_cq); 2925 return NULL; 2926 } 2927 free_mr->rsv_cq = to_hr_cq(cq); 2928 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2929 free_mr->rsv_cq->ib_cq.uobject = NULL; 2930 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2931 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2932 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2933 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2934 2935 return cq; 2936 } 2937 2938 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2939 struct ib_qp_init_attr *init_attr, int i) 2940 { 2941 struct hns_roce_v2_priv *priv = hr_dev->priv; 2942 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2943 struct ib_device *ibdev = &hr_dev->ib_dev; 2944 struct hns_roce_qp *hr_qp; 2945 struct ib_qp *qp; 2946 int ret; 2947 2948 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2949 if (!hr_qp) 2950 return -ENOMEM; 2951 2952 qp = &hr_qp->ibqp; 2953 qp->device = ibdev; 2954 2955 ret = hns_roce_create_qp(qp, init_attr, NULL); 2956 if (ret) { 2957 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2958 kfree(hr_qp); 2959 return ret; 2960 } 2961 2962 free_mr->rsv_qp[i] = hr_qp; 2963 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2964 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2965 2966 return 0; 2967 } 2968 2969 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2970 { 2971 struct hns_roce_v2_priv *priv = hr_dev->priv; 2972 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2973 struct ib_qp *qp; 2974 int i; 2975 2976 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2977 if (free_mr->rsv_qp[i]) { 2978 qp = &free_mr->rsv_qp[i]->ibqp; 2979 hns_roce_v2_destroy_qp(qp, NULL); 2980 kfree(free_mr->rsv_qp[i]); 2981 free_mr->rsv_qp[i] = NULL; 2982 } 2983 } 2984 2985 if (free_mr->rsv_cq) { 2986 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2987 kfree(free_mr->rsv_cq); 2988 free_mr->rsv_cq = NULL; 2989 } 2990 2991 if (free_mr->rsv_pd) { 2992 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2993 kfree(free_mr->rsv_pd); 2994 free_mr->rsv_pd = NULL; 2995 } 2996 2997 mutex_destroy(&free_mr->mutex); 2998 } 2999 3000 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 3001 { 3002 struct hns_roce_v2_priv *priv = hr_dev->priv; 3003 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3004 struct ib_qp_init_attr qp_init_attr = {}; 3005 struct ib_pd *pd; 3006 struct ib_cq *cq; 3007 int ret; 3008 int i; 3009 3010 pd = free_mr_init_pd(hr_dev); 3011 if (!pd) 3012 return -ENOMEM; 3013 3014 cq = free_mr_init_cq(hr_dev); 3015 if (!cq) { 3016 ret = -ENOMEM; 3017 goto create_failed_cq; 3018 } 3019 3020 qp_init_attr.qp_type = IB_QPT_RC; 3021 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 3022 qp_init_attr.send_cq = cq; 3023 qp_init_attr.recv_cq = cq; 3024 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3025 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 3026 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 3027 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 3028 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 3029 3030 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 3031 if (ret) 3032 goto create_failed_qp; 3033 } 3034 3035 return 0; 3036 3037 create_failed_qp: 3038 for (i--; i >= 0; i--) { 3039 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 3040 kfree(free_mr->rsv_qp[i]); 3041 } 3042 hns_roce_destroy_cq(cq, NULL); 3043 kfree(cq); 3044 3045 create_failed_cq: 3046 hns_roce_dealloc_pd(pd, NULL); 3047 kfree(pd); 3048 3049 return ret; 3050 } 3051 3052 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 3053 struct ib_qp_attr *attr, int sl_num) 3054 { 3055 struct hns_roce_v2_priv *priv = hr_dev->priv; 3056 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3057 struct ib_device *ibdev = &hr_dev->ib_dev; 3058 struct hns_roce_qp *hr_qp; 3059 int loopback; 3060 int mask; 3061 int ret; 3062 3063 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 3064 hr_qp->free_mr_en = 1; 3065 hr_qp->ibqp.device = ibdev; 3066 hr_qp->ibqp.qp_type = IB_QPT_RC; 3067 3068 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 3069 attr->qp_state = IB_QPS_INIT; 3070 attr->port_num = 1; 3071 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 3072 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 3073 IB_QPS_INIT, NULL); 3074 if (ret) { 3075 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n", 3076 ret); 3077 return ret; 3078 } 3079 3080 loopback = hr_dev->loop_idc; 3081 /* Set qpc lbi = 1 incidate loopback IO */ 3082 hr_dev->loop_idc = 1; 3083 3084 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 3085 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 3086 attr->qp_state = IB_QPS_RTR; 3087 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 3088 attr->path_mtu = IB_MTU_256; 3089 attr->dest_qp_num = hr_qp->qpn; 3090 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 3091 3092 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 3093 3094 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 3095 IB_QPS_RTR, NULL); 3096 hr_dev->loop_idc = loopback; 3097 if (ret) { 3098 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 3099 ret); 3100 return ret; 3101 } 3102 3103 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 3104 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 3105 attr->qp_state = IB_QPS_RTS; 3106 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 3107 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 3108 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 3109 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 3110 IB_QPS_RTS, NULL); 3111 if (ret) 3112 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 3113 ret); 3114 3115 return ret; 3116 } 3117 3118 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 3119 { 3120 struct hns_roce_v2_priv *priv = hr_dev->priv; 3121 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3122 struct ib_qp_attr attr = {}; 3123 int ret; 3124 int i; 3125 3126 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 3127 rdma_ah_set_static_rate(&attr.ah_attr, 3); 3128 rdma_ah_set_port_num(&attr.ah_attr, 1); 3129 3130 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3131 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 3132 if (ret) 3133 return ret; 3134 } 3135 3136 return 0; 3137 } 3138 3139 static int free_mr_init(struct hns_roce_dev *hr_dev) 3140 { 3141 struct hns_roce_v2_priv *priv = hr_dev->priv; 3142 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3143 int ret; 3144 3145 mutex_init(&free_mr->mutex); 3146 3147 ret = free_mr_alloc_res(hr_dev); 3148 if (ret) { 3149 mutex_destroy(&free_mr->mutex); 3150 return ret; 3151 } 3152 3153 ret = free_mr_modify_qp(hr_dev); 3154 if (ret) 3155 goto err_modify_qp; 3156 3157 return 0; 3158 3159 err_modify_qp: 3160 free_mr_exit(hr_dev); 3161 3162 return ret; 3163 } 3164 3165 static int get_hem_table(struct hns_roce_dev *hr_dev) 3166 { 3167 unsigned int qpc_count; 3168 unsigned int cqc_count; 3169 unsigned int gmv_count; 3170 int ret; 3171 int i; 3172 3173 /* Alloc memory for source address table buffer space chunk */ 3174 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 3175 gmv_count++) { 3176 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 3177 if (ret) 3178 goto err_gmv_failed; 3179 } 3180 3181 if (hr_dev->is_vf) 3182 return 0; 3183 3184 /* Alloc memory for QPC Timer buffer space chunk */ 3185 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 3186 qpc_count++) { 3187 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 3188 qpc_count); 3189 if (ret) { 3190 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 3191 goto err_qpc_timer_failed; 3192 } 3193 } 3194 3195 /* Alloc memory for CQC Timer buffer space chunk */ 3196 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 3197 cqc_count++) { 3198 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 3199 cqc_count); 3200 if (ret) { 3201 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 3202 goto err_cqc_timer_failed; 3203 } 3204 } 3205 3206 return 0; 3207 3208 err_cqc_timer_failed: 3209 for (i = 0; i < cqc_count; i++) 3210 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 3211 3212 err_qpc_timer_failed: 3213 for (i = 0; i < qpc_count; i++) 3214 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 3215 3216 err_gmv_failed: 3217 for (i = 0; i < gmv_count; i++) 3218 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 3219 3220 return ret; 3221 } 3222 3223 static void put_hem_table(struct hns_roce_dev *hr_dev) 3224 { 3225 int i; 3226 3227 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 3228 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 3229 3230 if (hr_dev->is_vf) 3231 return; 3232 3233 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 3234 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 3235 3236 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 3237 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 3238 } 3239 3240 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 3241 { 3242 int ret; 3243 3244 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 3245 ret = free_mr_init(hr_dev); 3246 if (ret) { 3247 dev_err(hr_dev->dev, "failed to init free mr!\n"); 3248 return ret; 3249 } 3250 } 3251 3252 /* The hns ROCEE requires the extdb info to be cleared before using */ 3253 ret = hns_roce_clear_extdb_list_info(hr_dev); 3254 if (ret) 3255 goto err_clear_extdb_failed; 3256 3257 ret = get_hem_table(hr_dev); 3258 if (ret) 3259 goto err_get_hem_table_failed; 3260 3261 if (hr_dev->is_vf) 3262 return 0; 3263 3264 ret = hns_roce_init_link_table(hr_dev); 3265 if (ret) { 3266 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 3267 goto err_llm_init_failed; 3268 } 3269 3270 return 0; 3271 3272 err_llm_init_failed: 3273 put_hem_table(hr_dev); 3274 err_get_hem_table_failed: 3275 hns_roce_function_clear(hr_dev); 3276 err_clear_extdb_failed: 3277 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3278 free_mr_exit(hr_dev); 3279 3280 return ret; 3281 } 3282 3283 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 3284 { 3285 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3286 free_mr_exit(hr_dev); 3287 3288 hns_roce_function_clear(hr_dev); 3289 3290 if (!hr_dev->is_vf) 3291 hns_roce_free_link_table(hr_dev); 3292 3293 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3294 free_dip_entry(hr_dev); 3295 } 3296 3297 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 3298 struct hns_roce_mbox_msg *mbox_msg) 3299 { 3300 struct hns_roce_cmq_desc desc; 3301 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 3302 3303 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 3304 3305 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 3306 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 3307 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 3308 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 3309 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 3310 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 3311 mbox_msg->token); 3312 3313 return hns_roce_cmq_send(hr_dev, &desc, 1); 3314 } 3315 3316 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 3317 u8 *complete_status) 3318 { 3319 struct hns_roce_mbox_status *mb_st; 3320 struct hns_roce_cmq_desc desc; 3321 unsigned long end; 3322 int ret = -EBUSY; 3323 u32 status; 3324 bool busy; 3325 3326 mb_st = (struct hns_roce_mbox_status *)desc.data; 3327 end = msecs_to_jiffies(timeout) + jiffies; 3328 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 3329 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 3330 return -EIO; 3331 3332 status = 0; 3333 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3334 true); 3335 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3336 if (!ret) { 3337 status = le32_to_cpu(mb_st->mb_status_hw_run); 3338 /* No pending message exists in ROCEE mbox. */ 3339 if (!(status & MB_ST_HW_RUN_M)) 3340 break; 3341 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3342 break; 3343 } 3344 3345 if (time_after(jiffies, end)) { 3346 dev_err_ratelimited(hr_dev->dev, 3347 "failed to wait mbox status 0x%x\n", 3348 status); 3349 return -ETIMEDOUT; 3350 } 3351 3352 cond_resched(); 3353 ret = -EBUSY; 3354 } 3355 3356 if (!ret) { 3357 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3358 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3359 /* Ignore all errors if the mbox is unavailable. */ 3360 ret = 0; 3361 *complete_status = MB_ST_COMPLETE_M; 3362 } 3363 3364 return ret; 3365 } 3366 3367 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3368 struct hns_roce_mbox_msg *mbox_msg) 3369 { 3370 u8 status = 0; 3371 int ret; 3372 3373 /* Waiting for the mbox to be idle */ 3374 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3375 &status); 3376 if (unlikely(ret)) { 3377 dev_err_ratelimited(hr_dev->dev, 3378 "failed to check post mbox status = 0x%x, ret = %d.\n", 3379 status, ret); 3380 return ret; 3381 } 3382 3383 /* Post new message to mbox */ 3384 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3385 if (ret) 3386 dev_err_ratelimited(hr_dev->dev, 3387 "failed to post mailbox, ret = %d.\n", ret); 3388 3389 return ret; 3390 } 3391 3392 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3393 { 3394 u8 status = 0; 3395 int ret; 3396 3397 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3398 &status); 3399 if (!ret) { 3400 if (status != MB_ST_COMPLETE_SUCC) 3401 return -EBUSY; 3402 } else { 3403 dev_err_ratelimited(hr_dev->dev, 3404 "failed to check mbox status = 0x%x, ret = %d.\n", 3405 status, ret); 3406 } 3407 3408 return ret; 3409 } 3410 3411 static void copy_gid(void *dest, const union ib_gid *gid) 3412 { 3413 #define GID_SIZE 4 3414 const union ib_gid *src = gid; 3415 __le32 (*p)[GID_SIZE] = dest; 3416 int i; 3417 3418 if (!gid) 3419 src = &zgid; 3420 3421 for (i = 0; i < GID_SIZE; i++) 3422 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3423 } 3424 3425 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3426 int gid_index, const union ib_gid *gid, 3427 enum hns_roce_sgid_type sgid_type) 3428 { 3429 struct hns_roce_cmq_desc desc; 3430 struct hns_roce_cfg_sgid_tb *sgid_tb = 3431 (struct hns_roce_cfg_sgid_tb *)desc.data; 3432 3433 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3434 3435 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3436 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3437 3438 copy_gid(&sgid_tb->vf_sgid_l, gid); 3439 3440 return hns_roce_cmq_send(hr_dev, &desc, 1); 3441 } 3442 3443 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3444 int gid_index, const union ib_gid *gid, 3445 enum hns_roce_sgid_type sgid_type, 3446 const struct ib_gid_attr *attr) 3447 { 3448 struct hns_roce_cmq_desc desc[2]; 3449 struct hns_roce_cfg_gmv_tb_a *tb_a = 3450 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3451 struct hns_roce_cfg_gmv_tb_b *tb_b = 3452 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3453 3454 u16 vlan_id = VLAN_CFI_MASK; 3455 u8 mac[ETH_ALEN] = {}; 3456 int ret; 3457 3458 if (gid) { 3459 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3460 if (ret) 3461 return ret; 3462 } 3463 3464 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3465 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3466 3467 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3468 3469 copy_gid(&tb_a->vf_sgid_l, gid); 3470 3471 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3472 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3473 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3474 3475 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3476 3477 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3478 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3479 3480 return hns_roce_cmq_send(hr_dev, desc, 2); 3481 } 3482 3483 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3484 const union ib_gid *gid, 3485 const struct ib_gid_attr *attr) 3486 { 3487 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3488 int ret; 3489 3490 if (gid) { 3491 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3492 if (ipv6_addr_v4mapped((void *)gid)) 3493 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3494 else 3495 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3496 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3497 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3498 } 3499 } 3500 3501 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3502 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3503 else 3504 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3505 3506 if (ret) 3507 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3508 ret); 3509 3510 return ret; 3511 } 3512 3513 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3514 const u8 *addr) 3515 { 3516 struct hns_roce_cmq_desc desc; 3517 struct hns_roce_cfg_smac_tb *smac_tb = 3518 (struct hns_roce_cfg_smac_tb *)desc.data; 3519 u16 reg_smac_h; 3520 u32 reg_smac_l; 3521 3522 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3523 3524 reg_smac_l = *(u32 *)(&addr[0]); 3525 reg_smac_h = *(u16 *)(&addr[4]); 3526 3527 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3528 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3529 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3530 3531 return hns_roce_cmq_send(hr_dev, &desc, 1); 3532 } 3533 3534 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3535 struct hns_roce_v2_mpt_entry *mpt_entry, 3536 struct hns_roce_mr *mr) 3537 { 3538 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3539 struct ib_device *ibdev = &hr_dev->ib_dev; 3540 dma_addr_t pbl_ba; 3541 int ret; 3542 int i; 3543 3544 ret = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3545 min_t(int, ARRAY_SIZE(pages), mr->npages)); 3546 if (ret) { 3547 ibdev_err(ibdev, "failed to find PBL mtr, ret = %d.\n", ret); 3548 return ret; 3549 } 3550 3551 /* Aligned to the hardware address access unit */ 3552 for (i = 0; i < ARRAY_SIZE(pages); i++) 3553 pages[i] >>= MPT_PBL_BUF_ADDR_S; 3554 3555 pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3556 3557 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3558 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> MPT_PBL_BA_ADDR_S); 3559 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3560 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3561 3562 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3563 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3564 3565 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3566 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3567 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3568 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3569 3570 return 0; 3571 } 3572 3573 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3574 void *mb_buf, struct hns_roce_mr *mr) 3575 { 3576 struct hns_roce_v2_mpt_entry *mpt_entry; 3577 3578 mpt_entry = mb_buf; 3579 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3580 3581 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3582 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3583 3584 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3585 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3586 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3587 mr->access & IB_ACCESS_REMOTE_READ); 3588 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3589 mr->access & IB_ACCESS_REMOTE_WRITE); 3590 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3591 mr->access & IB_ACCESS_LOCAL_WRITE); 3592 3593 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3594 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3595 mpt_entry->lkey = cpu_to_le32(mr->key); 3596 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3597 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3598 3599 if (mr->type != MR_TYPE_MR) 3600 hr_reg_enable(mpt_entry, MPT_PA); 3601 3602 if (mr->type == MR_TYPE_DMA) 3603 return 0; 3604 3605 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3606 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3607 3608 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3609 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3610 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3611 3612 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3613 } 3614 3615 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3616 struct hns_roce_mr *mr, int flags, 3617 void *mb_buf) 3618 { 3619 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3620 u32 mr_access_flags = mr->access; 3621 int ret = 0; 3622 3623 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3624 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3625 3626 if (flags & IB_MR_REREG_ACCESS) { 3627 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3628 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3629 hr_reg_write(mpt_entry, MPT_RR_EN, 3630 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3631 hr_reg_write(mpt_entry, MPT_RW_EN, 3632 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3633 hr_reg_write(mpt_entry, MPT_LW_EN, 3634 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3635 } 3636 3637 if (flags & IB_MR_REREG_TRANS) { 3638 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3639 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3640 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3641 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3642 3643 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3644 } 3645 3646 return ret; 3647 } 3648 3649 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 3650 { 3651 dma_addr_t pbl_ba = hns_roce_get_mtr_ba(&mr->pbl_mtr); 3652 struct hns_roce_v2_mpt_entry *mpt_entry; 3653 3654 mpt_entry = mb_buf; 3655 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3656 3657 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3658 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3659 3660 hr_reg_enable(mpt_entry, MPT_RA_EN); 3661 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3662 3663 hr_reg_enable(mpt_entry, MPT_FRE); 3664 hr_reg_enable(mpt_entry, MPT_BPD); 3665 hr_reg_clear(mpt_entry, MPT_PA); 3666 3667 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3668 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3669 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3670 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3671 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3672 3673 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3674 3675 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3676 MPT_PBL_BA_ADDR_S)); 3677 hr_reg_write(mpt_entry, MPT_PBL_BA_H, 3678 upper_32_bits(pbl_ba >> MPT_PBL_BA_ADDR_S)); 3679 3680 return 0; 3681 } 3682 3683 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3684 { 3685 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3686 struct ib_device *ibdev = &hr_dev->ib_dev; 3687 const struct ib_send_wr *bad_wr; 3688 struct ib_rdma_wr rdma_wr = {}; 3689 struct ib_send_wr *send_wr; 3690 int ret; 3691 3692 send_wr = &rdma_wr.wr; 3693 send_wr->opcode = IB_WR_RDMA_WRITE; 3694 3695 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3696 if (ret) { 3697 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3698 ret); 3699 return ret; 3700 } 3701 3702 return 0; 3703 } 3704 3705 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3706 struct ib_wc *wc); 3707 3708 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3709 { 3710 struct hns_roce_v2_priv *priv = hr_dev->priv; 3711 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3712 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3713 struct ib_device *ibdev = &hr_dev->ib_dev; 3714 struct hns_roce_qp *hr_qp; 3715 unsigned long end; 3716 int cqe_cnt = 0; 3717 int npolled; 3718 int ret; 3719 int i; 3720 3721 /* 3722 * If the device initialization is not complete or in the uninstall 3723 * process, then there is no need to execute free mr. 3724 */ 3725 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3726 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3727 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3728 return; 3729 3730 mutex_lock(&free_mr->mutex); 3731 3732 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3733 hr_qp = free_mr->rsv_qp[i]; 3734 3735 ret = free_mr_post_send_lp_wqe(hr_qp); 3736 if (ret) { 3737 ibdev_err_ratelimited(ibdev, 3738 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3739 hr_qp->qpn, ret); 3740 break; 3741 } 3742 3743 cqe_cnt++; 3744 } 3745 3746 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3747 while (cqe_cnt) { 3748 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3749 if (npolled < 0) { 3750 ibdev_err_ratelimited(ibdev, 3751 "failed to poll cqe for free mr, remain %d cqe.\n", 3752 cqe_cnt); 3753 goto out; 3754 } 3755 3756 if (time_after(jiffies, end)) { 3757 ibdev_err_ratelimited(ibdev, 3758 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3759 cqe_cnt); 3760 goto out; 3761 } 3762 cqe_cnt -= npolled; 3763 } 3764 3765 out: 3766 mutex_unlock(&free_mr->mutex); 3767 } 3768 3769 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3770 { 3771 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3772 free_mr_send_cmd_to_hw(hr_dev); 3773 } 3774 3775 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3776 { 3777 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3778 } 3779 3780 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3781 { 3782 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3783 3784 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3785 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3786 NULL; 3787 } 3788 3789 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3790 struct hns_roce_cq *hr_cq) 3791 { 3792 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3793 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3794 } else { 3795 struct hns_roce_v2_db cq_db = {}; 3796 3797 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3798 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3799 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3800 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3801 3802 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3803 } 3804 } 3805 3806 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3807 struct hns_roce_srq *srq) 3808 { 3809 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3810 struct hns_roce_v2_cqe *cqe, *dest; 3811 u32 prod_index; 3812 int nfreed = 0; 3813 int wqe_index; 3814 u8 owner_bit; 3815 3816 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3817 ++prod_index) { 3818 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3819 break; 3820 } 3821 3822 /* 3823 * Now backwards through the CQ, removing CQ entries 3824 * that match our QP by overwriting them with next entries. 3825 */ 3826 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3827 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3828 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3829 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3830 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3831 hns_roce_free_srq_wqe(srq, wqe_index); 3832 } 3833 ++nfreed; 3834 } else if (nfreed) { 3835 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3836 hr_cq->ib_cq.cqe); 3837 owner_bit = hr_reg_read(dest, CQE_OWNER); 3838 memcpy(dest, cqe, hr_cq->cqe_size); 3839 hr_reg_write(dest, CQE_OWNER, owner_bit); 3840 } 3841 } 3842 3843 if (nfreed) { 3844 hr_cq->cons_index += nfreed; 3845 update_cq_db(hr_dev, hr_cq); 3846 } 3847 } 3848 3849 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3850 struct hns_roce_srq *srq) 3851 { 3852 spin_lock_irq(&hr_cq->lock); 3853 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3854 spin_unlock_irq(&hr_cq->lock); 3855 } 3856 3857 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3858 struct hns_roce_cq *hr_cq, void *mb_buf, 3859 u64 *mtts, dma_addr_t dma_handle) 3860 { 3861 struct hns_roce_v2_cq_context *cq_context; 3862 3863 cq_context = mb_buf; 3864 memset(cq_context, 0, sizeof(*cq_context)); 3865 3866 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3867 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3868 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3869 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3870 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3871 3872 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3873 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3874 3875 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3876 hr_reg_enable(cq_context, CQC_STASH); 3877 3878 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3879 to_hr_hw_page_addr(mtts[0])); 3880 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3881 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3882 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3883 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3884 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3885 to_hr_hw_page_addr(mtts[1])); 3886 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3887 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3888 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3889 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3890 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3891 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3892 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> CQC_CQE_BA_L_S); 3893 hr_reg_write(cq_context, CQC_CQE_BA_H, dma_handle >> CQC_CQE_BA_H_S); 3894 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3895 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3896 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3897 ((u32)hr_cq->db.dma) >> 1); 3898 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3899 hr_cq->db.dma >> CQC_CQE_DB_RECORD_ADDR_H_S); 3900 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3901 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3902 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3903 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3904 } 3905 3906 static bool left_sw_wc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) 3907 { 3908 struct hns_roce_qp *hr_qp; 3909 3910 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3911 if (hr_qp->sq.head != hr_qp->sq.tail) 3912 return true; 3913 } 3914 3915 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3916 if (hr_qp->rq.head != hr_qp->rq.tail) 3917 return true; 3918 } 3919 3920 return false; 3921 } 3922 3923 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3924 enum ib_cq_notify_flags flags) 3925 { 3926 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3927 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3928 struct hns_roce_v2_db cq_db = {}; 3929 u32 notify_flag; 3930 3931 if (hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN) { 3932 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && 3933 left_sw_wc(hr_dev, hr_cq)) 3934 return 1; 3935 return 0; 3936 } 3937 /* 3938 * flags = 0, then notify_flag : next 3939 * flags = 1, then notify flag : solocited 3940 */ 3941 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3942 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3943 3944 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3945 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3946 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3947 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3948 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3949 3950 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3951 3952 return 0; 3953 } 3954 3955 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3956 int num_entries, struct ib_wc *wc) 3957 { 3958 unsigned int left; 3959 int npolled = 0; 3960 3961 left = wq->head - wq->tail; 3962 if (left == 0) 3963 return 0; 3964 3965 left = min_t(unsigned int, (unsigned int)num_entries, left); 3966 while (npolled < left) { 3967 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3968 wc->status = IB_WC_WR_FLUSH_ERR; 3969 wc->vendor_err = 0; 3970 wc->qp = &hr_qp->ibqp; 3971 3972 wq->tail++; 3973 wc++; 3974 npolled++; 3975 } 3976 3977 return npolled; 3978 } 3979 3980 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3981 struct ib_wc *wc) 3982 { 3983 struct hns_roce_qp *hr_qp; 3984 int npolled = 0; 3985 3986 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3987 npolled += sw_comp(hr_qp, &hr_qp->sq, 3988 num_entries - npolled, wc + npolled); 3989 if (npolled >= num_entries) 3990 goto out; 3991 } 3992 3993 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3994 npolled += sw_comp(hr_qp, &hr_qp->rq, 3995 num_entries - npolled, wc + npolled); 3996 if (npolled >= num_entries) 3997 goto out; 3998 } 3999 4000 out: 4001 return npolled; 4002 } 4003 4004 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 4005 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 4006 struct ib_wc *wc) 4007 { 4008 static const struct { 4009 u32 cqe_status; 4010 enum ib_wc_status wc_status; 4011 } map[] = { 4012 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 4013 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 4014 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 4015 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 4016 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 4017 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 4018 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 4019 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 4020 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 4021 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 4022 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 4023 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 4024 IB_WC_RETRY_EXC_ERR }, 4025 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 4026 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 4027 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 4028 }; 4029 4030 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 4031 int i; 4032 4033 wc->status = IB_WC_GENERAL_ERR; 4034 for (i = 0; i < ARRAY_SIZE(map); i++) 4035 if (cqe_status == map[i].cqe_status) { 4036 wc->status = map[i].wc_status; 4037 break; 4038 } 4039 4040 if (likely(wc->status == IB_WC_SUCCESS || 4041 wc->status == IB_WC_WR_FLUSH_ERR)) 4042 return; 4043 4044 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 4045 cqe_status); 4046 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 4047 cq->cqe_size, false); 4048 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 4049 4050 /* 4051 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 4052 * the standard protocol, the driver must ignore it and needn't to set 4053 * the QP to an error state. 4054 */ 4055 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 4056 return; 4057 4058 flush_cqe(hr_dev, qp); 4059 } 4060 4061 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 4062 struct hns_roce_qp **cur_qp) 4063 { 4064 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 4065 struct hns_roce_qp *hr_qp = *cur_qp; 4066 u32 qpn; 4067 4068 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 4069 4070 if (!hr_qp || qpn != hr_qp->qpn) { 4071 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 4072 if (unlikely(!hr_qp)) { 4073 ibdev_err(&hr_dev->ib_dev, 4074 "CQ %06lx with entry for unknown QPN %06x\n", 4075 hr_cq->cqn, qpn); 4076 return -EINVAL; 4077 } 4078 *cur_qp = hr_qp; 4079 } 4080 4081 return 0; 4082 } 4083 4084 /* 4085 * mapped-value = 1 + real-value 4086 * The ib wc opcode's real value is start from 0, In order to distinguish 4087 * between initialized and uninitialized map values, we plus 1 to the actual 4088 * value when defining the mapping, so that the validity can be identified by 4089 * checking whether the mapped value is greater than 0. 4090 */ 4091 #define HR_WC_OP_MAP(hr_key, ib_key) \ 4092 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 4093 4094 static const u32 wc_send_op_map[] = { 4095 HR_WC_OP_MAP(SEND, SEND), 4096 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 4097 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 4098 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 4099 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 4100 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 4101 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 4102 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 4103 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 4104 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 4105 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 4106 }; 4107 4108 static int to_ib_wc_send_op(u32 hr_opcode) 4109 { 4110 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 4111 return -EINVAL; 4112 4113 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 4114 -EINVAL; 4115 } 4116 4117 static const u32 wc_recv_op_map[] = { 4118 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 4119 HR_WC_OP_MAP(SEND, RECV), 4120 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 4121 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 4122 }; 4123 4124 static int to_ib_wc_recv_op(u32 hr_opcode) 4125 { 4126 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 4127 return -EINVAL; 4128 4129 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 4130 -EINVAL; 4131 } 4132 4133 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 4134 { 4135 u32 hr_opcode; 4136 int ib_opcode; 4137 4138 wc->wc_flags = 0; 4139 4140 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 4141 switch (hr_opcode) { 4142 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 4143 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 4144 break; 4145 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 4146 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 4147 wc->wc_flags |= IB_WC_WITH_IMM; 4148 break; 4149 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 4150 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 4151 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 4152 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 4153 wc->byte_len = 8; 4154 break; 4155 default: 4156 break; 4157 } 4158 4159 ib_opcode = to_ib_wc_send_op(hr_opcode); 4160 if (ib_opcode < 0) 4161 wc->status = IB_WC_GENERAL_ERR; 4162 else 4163 wc->opcode = ib_opcode; 4164 } 4165 4166 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 4167 { 4168 u32 hr_opcode; 4169 int ib_opcode; 4170 4171 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 4172 4173 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 4174 switch (hr_opcode) { 4175 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 4176 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 4177 wc->wc_flags = IB_WC_WITH_IMM; 4178 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 4179 break; 4180 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 4181 wc->wc_flags = IB_WC_WITH_INVALIDATE; 4182 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 4183 break; 4184 default: 4185 wc->wc_flags = 0; 4186 } 4187 4188 ib_opcode = to_ib_wc_recv_op(hr_opcode); 4189 if (ib_opcode < 0) 4190 wc->status = IB_WC_GENERAL_ERR; 4191 else 4192 wc->opcode = ib_opcode; 4193 4194 wc->sl = hr_reg_read(cqe, CQE_SL); 4195 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 4196 wc->slid = 0; 4197 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 4198 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 4199 wc->pkey_index = 0; 4200 4201 if (hr_reg_read(cqe, CQE_VID_VLD)) { 4202 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 4203 wc->wc_flags |= IB_WC_WITH_VLAN; 4204 } else { 4205 wc->vlan_id = 0xffff; 4206 } 4207 4208 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 4209 4210 return 0; 4211 } 4212 4213 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 4214 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 4215 { 4216 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 4217 struct hns_roce_qp *qp = *cur_qp; 4218 struct hns_roce_srq *srq = NULL; 4219 struct hns_roce_v2_cqe *cqe; 4220 struct hns_roce_wq *wq; 4221 int is_send; 4222 u16 wqe_idx; 4223 int ret; 4224 4225 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 4226 if (!cqe) 4227 return -EAGAIN; 4228 4229 ++hr_cq->cons_index; 4230 /* Memory barrier */ 4231 rmb(); 4232 4233 ret = get_cur_qp(hr_cq, cqe, &qp); 4234 if (ret) 4235 return ret; 4236 4237 wc->qp = &qp->ibqp; 4238 wc->vendor_err = 0; 4239 4240 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 4241 4242 is_send = !hr_reg_read(cqe, CQE_S_R); 4243 if (is_send) { 4244 wq = &qp->sq; 4245 4246 /* If sg_signal_bit is set, tail pointer will be updated to 4247 * the WQE corresponding to the current CQE. 4248 */ 4249 if (qp->sq_signal_bits) 4250 wq->tail += (wqe_idx - (u16)wq->tail) & 4251 (wq->wqe_cnt - 1); 4252 4253 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4254 ++wq->tail; 4255 4256 fill_send_wc(wc, cqe); 4257 } else { 4258 if (qp->ibqp.srq) { 4259 srq = to_hr_srq(qp->ibqp.srq); 4260 wc->wr_id = srq->wrid[wqe_idx]; 4261 hns_roce_free_srq_wqe(srq, wqe_idx); 4262 } else { 4263 wq = &qp->rq; 4264 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 4265 ++wq->tail; 4266 } 4267 4268 ret = fill_recv_wc(wc, cqe); 4269 } 4270 4271 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 4272 if (unlikely(wc->status != IB_WC_SUCCESS)) 4273 return 0; 4274 4275 return ret; 4276 } 4277 4278 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 4279 struct ib_wc *wc) 4280 { 4281 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 4282 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 4283 struct hns_roce_qp *cur_qp = NULL; 4284 unsigned long flags; 4285 int npolled; 4286 4287 spin_lock_irqsave(&hr_cq->lock, flags); 4288 4289 /* 4290 * When the device starts to reset, the state is RST_DOWN. At this time, 4291 * there may still be some valid CQEs in the hardware that are not 4292 * polled. Therefore, it is not allowed to switch to the software mode 4293 * immediately. When the state changes to UNINIT, CQE no longer exists 4294 * in the hardware, and then switch to software mode. 4295 */ 4296 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 4297 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 4298 goto out; 4299 } 4300 4301 for (npolled = 0; npolled < num_entries; ++npolled) { 4302 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 4303 break; 4304 } 4305 4306 if (npolled) 4307 update_cq_db(hr_dev, hr_cq); 4308 4309 out: 4310 spin_unlock_irqrestore(&hr_cq->lock, flags); 4311 4312 return npolled; 4313 } 4314 4315 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4316 u32 step_idx, u8 *mbox_cmd) 4317 { 4318 u8 cmd; 4319 4320 switch (type) { 4321 case HEM_TYPE_QPC: 4322 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4323 break; 4324 case HEM_TYPE_MTPT: 4325 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4326 break; 4327 case HEM_TYPE_CQC: 4328 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4329 break; 4330 case HEM_TYPE_SRQC: 4331 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4332 break; 4333 case HEM_TYPE_SCCC: 4334 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4335 break; 4336 case HEM_TYPE_QPC_TIMER: 4337 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4338 break; 4339 case HEM_TYPE_CQC_TIMER: 4340 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4341 break; 4342 default: 4343 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4344 return -EINVAL; 4345 } 4346 4347 *mbox_cmd = cmd + step_idx; 4348 4349 return 0; 4350 } 4351 4352 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4353 dma_addr_t base_addr) 4354 { 4355 struct hns_roce_cmq_desc desc; 4356 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4357 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4358 u64 addr = to_hr_hw_page_addr(base_addr); 4359 4360 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4361 4362 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4363 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4364 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4365 4366 return hns_roce_cmq_send(hr_dev, &desc, 1); 4367 } 4368 4369 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4370 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4371 { 4372 int ret; 4373 u8 cmd; 4374 4375 if (unlikely(hem_type == HEM_TYPE_GMV)) 4376 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4377 4378 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4379 return 0; 4380 4381 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4382 if (ret < 0) 4383 return ret; 4384 4385 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4386 } 4387 4388 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4389 struct hns_roce_hem_table *table, int obj, 4390 u32 step_idx) 4391 { 4392 struct hns_roce_hem_mhop mhop; 4393 struct hns_roce_hem *hem; 4394 unsigned long mhop_obj = obj; 4395 int i, j, k; 4396 int ret = 0; 4397 u64 hem_idx = 0; 4398 u64 l1_idx = 0; 4399 u64 bt_ba = 0; 4400 u32 chunk_ba_num; 4401 u32 hop_num; 4402 4403 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4404 return 0; 4405 4406 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4407 i = mhop.l0_idx; 4408 j = mhop.l1_idx; 4409 k = mhop.l2_idx; 4410 hop_num = mhop.hop_num; 4411 chunk_ba_num = mhop.bt_chunk_size / 8; 4412 4413 if (hop_num == 2) { 4414 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4415 k; 4416 l1_idx = i * chunk_ba_num + j; 4417 } else if (hop_num == 1) { 4418 hem_idx = i * chunk_ba_num + j; 4419 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4420 hem_idx = i; 4421 } 4422 4423 if (table->type == HEM_TYPE_SCCC) 4424 obj = mhop.l0_idx; 4425 4426 if (check_whether_last_step(hop_num, step_idx)) { 4427 hem = table->hem[hem_idx]; 4428 4429 ret = set_hem_to_hw(hr_dev, obj, hem->dma, table->type, step_idx); 4430 } else { 4431 if (step_idx == 0) 4432 bt_ba = table->bt_l0_dma_addr[i]; 4433 else if (step_idx == 1 && hop_num == 2) 4434 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4435 4436 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4437 } 4438 4439 return ret; 4440 } 4441 4442 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4443 struct hns_roce_hem_table *table, 4444 int tag, u32 step_idx) 4445 { 4446 struct hns_roce_cmd_mailbox *mailbox; 4447 struct device *dev = hr_dev->dev; 4448 u8 cmd = 0xff; 4449 int ret; 4450 4451 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4452 return 0; 4453 4454 switch (table->type) { 4455 case HEM_TYPE_QPC: 4456 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4457 break; 4458 case HEM_TYPE_MTPT: 4459 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4460 break; 4461 case HEM_TYPE_CQC: 4462 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4463 break; 4464 case HEM_TYPE_SRQC: 4465 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4466 break; 4467 case HEM_TYPE_SCCC: 4468 case HEM_TYPE_QPC_TIMER: 4469 case HEM_TYPE_CQC_TIMER: 4470 case HEM_TYPE_GMV: 4471 return 0; 4472 default: 4473 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4474 table->type); 4475 return 0; 4476 } 4477 4478 cmd += step_idx; 4479 4480 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4481 if (IS_ERR(mailbox)) 4482 return PTR_ERR(mailbox); 4483 4484 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4485 4486 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4487 return ret; 4488 } 4489 4490 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4491 struct hns_roce_v2_qp_context *context, 4492 struct hns_roce_v2_qp_context *qpc_mask, 4493 struct hns_roce_qp *hr_qp) 4494 { 4495 struct hns_roce_cmd_mailbox *mailbox; 4496 int qpc_size; 4497 int ret; 4498 4499 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4500 if (IS_ERR(mailbox)) 4501 return PTR_ERR(mailbox); 4502 4503 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4504 qpc_size = hr_dev->caps.qpc_sz; 4505 memcpy(mailbox->buf, context, qpc_size); 4506 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4507 4508 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4509 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4510 4511 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4512 4513 return ret; 4514 } 4515 4516 static void set_access_flags(struct hns_roce_qp *hr_qp, 4517 struct hns_roce_v2_qp_context *context, 4518 struct hns_roce_v2_qp_context *qpc_mask, 4519 const struct ib_qp_attr *attr, int attr_mask) 4520 { 4521 u8 dest_rd_atomic; 4522 u32 access_flags; 4523 4524 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4525 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4526 4527 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4528 attr->qp_access_flags : hr_qp->atomic_rd_en; 4529 4530 if (!dest_rd_atomic) 4531 access_flags &= IB_ACCESS_REMOTE_WRITE; 4532 4533 hr_reg_write_bool(context, QPC_RRE, 4534 access_flags & IB_ACCESS_REMOTE_READ); 4535 hr_reg_clear(qpc_mask, QPC_RRE); 4536 4537 hr_reg_write_bool(context, QPC_RWE, 4538 access_flags & IB_ACCESS_REMOTE_WRITE); 4539 hr_reg_clear(qpc_mask, QPC_RWE); 4540 4541 hr_reg_write_bool(context, QPC_ATE, 4542 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4543 hr_reg_clear(qpc_mask, QPC_ATE); 4544 hr_reg_write_bool(context, QPC_EXT_ATE, 4545 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4546 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4547 } 4548 4549 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4550 struct hns_roce_v2_qp_context *context) 4551 { 4552 hr_reg_write(context, QPC_SGE_SHIFT, 4553 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4554 hr_qp->sge.sge_shift)); 4555 4556 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4557 4558 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4559 } 4560 4561 static inline int get_cqn(struct ib_cq *ib_cq) 4562 { 4563 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4564 } 4565 4566 static inline int get_pdn(struct ib_pd *ib_pd) 4567 { 4568 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4569 } 4570 4571 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4572 struct hns_roce_v2_qp_context *context) 4573 { 4574 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4575 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4576 4577 /* 4578 * In v2 engine, software pass context and context mask to hardware 4579 * when modifying qp. If software need modify some fields in context, 4580 * we should set all bits of the relevant fields in context mask to 4581 * 0 at the same time, else set them to 0x1. 4582 */ 4583 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4584 4585 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4586 4587 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4588 4589 set_qpc_wqe_cnt(hr_qp, context); 4590 4591 /* No VLAN need to set 0xFFF */ 4592 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4593 4594 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4595 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4596 4597 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4598 } 4599 4600 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4601 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4602 4603 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4604 hr_reg_enable(context, QPC_OWNER_MODE); 4605 4606 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4607 lower_32_bits(hr_qp->rdb.dma) >> 1); 4608 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4609 upper_32_bits(hr_qp->rdb.dma)); 4610 4611 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4612 4613 if (ibqp->srq) { 4614 hr_reg_enable(context, QPC_SRQ_EN); 4615 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4616 } 4617 4618 hr_reg_enable(context, QPC_FRE); 4619 4620 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4621 4622 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4623 return; 4624 4625 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4626 hr_reg_enable(&context->ext, QPCEX_STASH); 4627 } 4628 4629 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4630 struct hns_roce_v2_qp_context *context, 4631 struct hns_roce_v2_qp_context *qpc_mask) 4632 { 4633 /* 4634 * In v2 engine, software pass context and context mask to hardware 4635 * when modifying qp. If software need modify some fields in context, 4636 * we should set all bits of the relevant fields in context mask to 4637 * 0 at the same time, else set them to 0x1. 4638 */ 4639 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4640 hr_reg_clear(qpc_mask, QPC_TST); 4641 4642 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4643 hr_reg_clear(qpc_mask, QPC_PD); 4644 4645 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4646 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4647 4648 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4649 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4650 4651 if (ibqp->srq) { 4652 hr_reg_enable(context, QPC_SRQ_EN); 4653 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4654 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4655 hr_reg_clear(qpc_mask, QPC_SRQN); 4656 } 4657 } 4658 4659 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4660 struct hns_roce_qp *hr_qp, 4661 struct hns_roce_v2_qp_context *context, 4662 struct hns_roce_v2_qp_context *qpc_mask) 4663 { 4664 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4665 u64 wqe_sge_ba; 4666 int ret; 4667 4668 /* Search qp buf's mtts */ 4669 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4670 MTT_MIN_COUNT); 4671 if (hr_qp->rq.wqe_cnt && ret) { 4672 ibdev_err(&hr_dev->ib_dev, 4673 "failed to find QP(0x%lx) RQ WQE buf, ret = %d.\n", 4674 hr_qp->qpn, ret); 4675 return ret; 4676 } 4677 4678 wqe_sge_ba = hns_roce_get_mtr_ba(&hr_qp->mtr); 4679 4680 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4681 qpc_mask->wqe_sge_ba = 0; 4682 4683 /* 4684 * In v2 engine, software pass context and context mask to hardware 4685 * when modifying qp. If software need modify some fields in context, 4686 * we should set all bits of the relevant fields in context mask to 4687 * 0 at the same time, else set them to 0x1. 4688 */ 4689 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4690 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4691 4692 hr_reg_write(context, QPC_SQ_HOP_NUM, 4693 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4694 hr_qp->sq.wqe_cnt)); 4695 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4696 4697 hr_reg_write(context, QPC_SGE_HOP_NUM, 4698 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4699 hr_qp->sge.sge_cnt)); 4700 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4701 4702 hr_reg_write(context, QPC_RQ_HOP_NUM, 4703 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4704 hr_qp->rq.wqe_cnt)); 4705 4706 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4707 4708 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4709 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4710 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4711 4712 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4713 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4714 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4715 4716 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4717 qpc_mask->rq_cur_blk_addr = 0; 4718 4719 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4720 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4721 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4722 4723 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4724 context->rq_nxt_blk_addr = 4725 cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4726 qpc_mask->rq_nxt_blk_addr = 0; 4727 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4728 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4729 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4730 } 4731 4732 return 0; 4733 } 4734 4735 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4736 struct hns_roce_qp *hr_qp, 4737 struct hns_roce_v2_qp_context *context, 4738 struct hns_roce_v2_qp_context *qpc_mask) 4739 { 4740 struct ib_device *ibdev = &hr_dev->ib_dev; 4741 u64 sge_cur_blk = 0; 4742 u64 sq_cur_blk = 0; 4743 int ret; 4744 4745 /* search qp buf's mtts */ 4746 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->sq.offset, 4747 &sq_cur_blk, 1); 4748 if (ret) { 4749 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ WQE buf, ret = %d.\n", 4750 hr_qp->qpn, ret); 4751 return ret; 4752 } 4753 if (hr_qp->sge.sge_cnt > 0) { 4754 ret = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4755 hr_qp->sge.offset, &sge_cur_blk, 1); 4756 if (ret) { 4757 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf, ret = %d.\n", 4758 hr_qp->qpn, ret); 4759 return ret; 4760 } 4761 } 4762 4763 /* 4764 * In v2 engine, software pass context and context mask to hardware 4765 * when modifying qp. If software need modify some fields in context, 4766 * we should set all bits of the relevant fields in context mask to 4767 * 0 at the same time, else set them to 0x1. 4768 */ 4769 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4770 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4771 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4772 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4773 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4774 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4775 4776 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4777 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4778 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4779 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4780 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4781 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4782 4783 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4784 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4785 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4786 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4787 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4788 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4789 4790 return 0; 4791 } 4792 4793 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4794 const struct ib_qp_attr *attr) 4795 { 4796 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4797 return IB_MTU_4096; 4798 4799 return attr->path_mtu; 4800 } 4801 4802 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4803 const struct ib_qp_attr *attr, int attr_mask, 4804 struct hns_roce_v2_qp_context *context, 4805 struct hns_roce_v2_qp_context *qpc_mask, 4806 struct ib_udata *udata) 4807 { 4808 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4809 struct hns_roce_ucontext, ibucontext); 4810 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4811 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4812 struct ib_device *ibdev = &hr_dev->ib_dev; 4813 dma_addr_t trrl_ba; 4814 dma_addr_t irrl_ba; 4815 enum ib_mtu ib_mtu; 4816 u8 ack_req_freq; 4817 const u8 *smac; 4818 int lp_msg_len; 4819 u8 lp_pktn_ini; 4820 u64 *mtts; 4821 u8 *dmac; 4822 u32 port; 4823 int mtu; 4824 int ret; 4825 4826 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4827 if (ret) { 4828 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4829 return ret; 4830 } 4831 4832 /* Search IRRL's mtts */ 4833 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4834 hr_qp->qpn, &irrl_ba); 4835 if (!mtts) { 4836 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4837 return -EINVAL; 4838 } 4839 4840 /* Search TRRL's mtts */ 4841 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4842 hr_qp->qpn, &trrl_ba); 4843 if (!mtts) { 4844 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4845 return -EINVAL; 4846 } 4847 4848 if (attr_mask & IB_QP_ALT_PATH) { 4849 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4850 attr_mask); 4851 return -EINVAL; 4852 } 4853 4854 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> QPC_TRRL_BA_L_S); 4855 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4856 context->trrl_ba = cpu_to_le32(trrl_ba >> QPC_TRRL_BA_M_S); 4857 qpc_mask->trrl_ba = 0; 4858 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> QPC_TRRL_BA_H_S); 4859 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4860 4861 context->irrl_ba = cpu_to_le32(irrl_ba >> QPC_IRRL_BA_L_S); 4862 qpc_mask->irrl_ba = 0; 4863 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> QPC_IRRL_BA_H_S); 4864 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4865 4866 hr_reg_enable(context, QPC_RMT_E2E); 4867 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4868 4869 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4870 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4871 4872 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4873 4874 smac = (const u8 *)hr_dev->dev_addr[port]; 4875 dmac = (u8 *)attr->ah_attr.roce.dmac; 4876 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4877 if (ether_addr_equal_unaligned(dmac, smac) || 4878 hr_dev->loop_idc == 0x1) { 4879 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4880 hr_reg_clear(qpc_mask, QPC_LBI); 4881 } 4882 4883 if (attr_mask & IB_QP_DEST_QPN) { 4884 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4885 hr_reg_clear(qpc_mask, QPC_DQPN); 4886 } 4887 4888 memcpy(&context->dmac, dmac, sizeof(u32)); 4889 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4890 qpc_mask->dmac = 0; 4891 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4892 4893 ib_mtu = get_mtu(ibqp, attr); 4894 hr_qp->path_mtu = ib_mtu; 4895 4896 mtu = ib_mtu_enum_to_int(ib_mtu); 4897 if (WARN_ON(mtu <= 0)) 4898 return -EINVAL; 4899 #define MIN_LP_MSG_LEN 1024 4900 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4901 lp_msg_len = max(mtu, MIN_LP_MSG_LEN); 4902 lp_pktn_ini = ilog2(lp_msg_len / mtu); 4903 4904 if (attr_mask & IB_QP_PATH_MTU) { 4905 hr_reg_write(context, QPC_MTU, ib_mtu); 4906 hr_reg_clear(qpc_mask, QPC_MTU); 4907 } 4908 4909 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4910 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4911 4912 /* 4913 * There are several constraints for ACK_REQ_FREQ: 4914 * 1. mtu * (2 ^ ACK_REQ_FREQ) should not be too large, otherwise 4915 * it may cause some unexpected retries when sending large 4916 * payload. 4917 * 2. ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI. 4918 * 3. ACK_REQ_FREQ must be equal to LP_PKTN_INI when using LDCP 4919 * or HC3 congestion control algorithm. 4920 */ 4921 if (hr_qp->cong_type == CONG_TYPE_LDCP || 4922 hr_qp->cong_type == CONG_TYPE_HC3 || 4923 hr_dev->caps.max_ack_req_msg_len < lp_msg_len) 4924 ack_req_freq = lp_pktn_ini; 4925 else 4926 ack_req_freq = ilog2(hr_dev->caps.max_ack_req_msg_len / mtu); 4927 hr_reg_write(context, QPC_ACK_REQ_FREQ, ack_req_freq); 4928 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4929 4930 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4931 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4932 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4933 4934 context->rq_rnr_timer = 0; 4935 qpc_mask->rq_rnr_timer = 0; 4936 4937 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4938 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4939 4940 #define MAX_LP_SGEN 3 4941 /* rocee send 2^lp_sgen_ini segs every time */ 4942 hr_reg_write(context, QPC_LP_SGEN_INI, MAX_LP_SGEN); 4943 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4944 4945 if (udata && ibqp->qp_type == IB_QPT_RC && 4946 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4947 hr_reg_write_bool(context, QPC_RQIE, 4948 hr_dev->caps.flags & 4949 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4950 hr_reg_clear(qpc_mask, QPC_RQIE); 4951 } 4952 4953 if (udata && 4954 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4955 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4956 hr_reg_write_bool(context, QPC_CQEIE, 4957 hr_dev->caps.flags & 4958 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4959 hr_reg_clear(qpc_mask, QPC_CQEIE); 4960 4961 hr_reg_write(context, QPC_CQEIS, 0); 4962 hr_reg_clear(qpc_mask, QPC_CQEIS); 4963 } 4964 4965 return 0; 4966 } 4967 4968 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, 4969 struct hns_roce_v2_qp_context *context, 4970 struct hns_roce_v2_qp_context *qpc_mask) 4971 { 4972 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4973 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4974 struct ib_device *ibdev = &hr_dev->ib_dev; 4975 int ret; 4976 4977 /* Not support alternate path and path migration */ 4978 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4979 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4980 return -EINVAL; 4981 } 4982 4983 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4984 if (ret) { 4985 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4986 return ret; 4987 } 4988 4989 /* 4990 * Set some fields in context to zero, Because the default values 4991 * of all fields in context are zero, we need not set them to 0 again. 4992 * but we should set the relevant fields of context mask to 0. 4993 */ 4994 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4995 4996 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4997 4998 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4999 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 5000 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 5001 5002 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 5003 5004 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 5005 5006 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 5007 5008 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 5009 5010 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 5011 5012 return 0; 5013 } 5014 5015 static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn) 5016 { 5017 struct hns_roce_dip *hr_dip; 5018 int ret; 5019 5020 hr_dip = xa_load(dip_xa, qpn); 5021 if (hr_dip) 5022 return 0; 5023 5024 hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL); 5025 if (!hr_dip) 5026 return -ENOMEM; 5027 5028 ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL)); 5029 if (ret) 5030 kfree(hr_dip); 5031 5032 return ret; 5033 } 5034 5035 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 5036 u32 *dip_idx) 5037 { 5038 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5039 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5040 struct xarray *dip_xa = &hr_dev->qp_table.dip_xa; 5041 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5042 struct hns_roce_dip *hr_dip; 5043 unsigned long idx; 5044 int ret = 0; 5045 5046 ret = alloc_dip_entry(dip_xa, ibqp->qp_num); 5047 if (ret) 5048 return ret; 5049 5050 xa_lock(dip_xa); 5051 5052 xa_for_each(dip_xa, idx, hr_dip) { 5053 if (hr_dip->qp_cnt && 5054 !memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) { 5055 *dip_idx = hr_dip->dip_idx; 5056 hr_dip->qp_cnt++; 5057 hr_qp->dip = hr_dip; 5058 goto out; 5059 } 5060 } 5061 5062 /* If no dgid is found, a new dip and a mapping between dgid and 5063 * dip_idx will be created. 5064 */ 5065 xa_for_each(dip_xa, idx, hr_dip) { 5066 if (hr_dip->qp_cnt) 5067 continue; 5068 5069 *dip_idx = idx; 5070 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5071 hr_dip->dip_idx = idx; 5072 hr_dip->qp_cnt++; 5073 hr_qp->dip = hr_dip; 5074 break; 5075 } 5076 5077 /* This should never happen. */ 5078 if (WARN_ON_ONCE(!hr_qp->dip)) 5079 ret = -ENOSPC; 5080 5081 out: 5082 xa_unlock(dip_xa); 5083 return ret; 5084 } 5085 5086 enum { 5087 CONG_DCQCN, 5088 CONG_WINDOW, 5089 }; 5090 5091 enum { 5092 UNSUPPORT_CONG_LEVEL, 5093 SUPPORT_CONG_LEVEL, 5094 }; 5095 5096 enum { 5097 CONG_LDCP, 5098 CONG_HC3, 5099 }; 5100 5101 enum { 5102 DIP_INVALID, 5103 DIP_VALID, 5104 }; 5105 5106 enum { 5107 WND_LIMIT, 5108 WND_UNLIMIT, 5109 }; 5110 5111 static int check_cong_type(struct ib_qp *ibqp, 5112 struct hns_roce_congestion_algorithm *cong_alg) 5113 { 5114 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5115 5116 /* different congestion types match different configurations */ 5117 switch (hr_qp->cong_type) { 5118 case CONG_TYPE_DCQCN: 5119 cong_alg->alg_sel = CONG_DCQCN; 5120 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 5121 cong_alg->dip_vld = DIP_INVALID; 5122 cong_alg->wnd_mode_sel = WND_LIMIT; 5123 break; 5124 case CONG_TYPE_LDCP: 5125 cong_alg->alg_sel = CONG_WINDOW; 5126 cong_alg->alg_sub_sel = CONG_LDCP; 5127 cong_alg->dip_vld = DIP_INVALID; 5128 cong_alg->wnd_mode_sel = WND_UNLIMIT; 5129 break; 5130 case CONG_TYPE_HC3: 5131 cong_alg->alg_sel = CONG_WINDOW; 5132 cong_alg->alg_sub_sel = CONG_HC3; 5133 cong_alg->dip_vld = DIP_INVALID; 5134 cong_alg->wnd_mode_sel = WND_LIMIT; 5135 break; 5136 case CONG_TYPE_DIP: 5137 cong_alg->alg_sel = CONG_DCQCN; 5138 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 5139 cong_alg->dip_vld = DIP_VALID; 5140 cong_alg->wnd_mode_sel = WND_LIMIT; 5141 break; 5142 default: 5143 hr_qp->cong_type = CONG_TYPE_DCQCN; 5144 cong_alg->alg_sel = CONG_DCQCN; 5145 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 5146 cong_alg->dip_vld = DIP_INVALID; 5147 cong_alg->wnd_mode_sel = WND_LIMIT; 5148 break; 5149 } 5150 5151 return 0; 5152 } 5153 5154 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 5155 struct hns_roce_v2_qp_context *context, 5156 struct hns_roce_v2_qp_context *qpc_mask) 5157 { 5158 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5159 struct hns_roce_congestion_algorithm cong_field; 5160 struct ib_device *ibdev = ibqp->device; 5161 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5162 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5163 u32 dip_idx = 0; 5164 int ret; 5165 5166 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 5167 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 5168 return 0; 5169 5170 ret = check_cong_type(ibqp, &cong_field); 5171 if (ret) 5172 return ret; 5173 5174 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 5175 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 5176 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 5177 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 5178 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 5179 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 5180 cong_field.alg_sub_sel); 5181 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 5182 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 5183 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 5184 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 5185 cong_field.wnd_mode_sel); 5186 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 5187 5188 /* if dip is disabled, there is no need to set dip idx */ 5189 if (cong_field.dip_vld == 0) 5190 return 0; 5191 5192 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 5193 if (ret) { 5194 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 5195 return ret; 5196 } 5197 5198 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 5199 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 5200 5201 return 0; 5202 } 5203 5204 static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, 5205 u8 *tc_mode, u8 *priority) 5206 { 5207 struct hns_roce_v2_priv *priv = hr_dev->priv; 5208 struct hnae3_handle *handle = priv->handle; 5209 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 5210 5211 if (!ops->get_dscp_prio) 5212 return -EOPNOTSUPP; 5213 5214 return ops->get_dscp_prio(handle, dscp, tc_mode, priority); 5215 } 5216 5217 bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) 5218 { 5219 u32 max_sl; 5220 5221 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 5222 if (unlikely(sl > max_sl)) { 5223 ibdev_err_ratelimited(&hr_dev->ib_dev, 5224 "failed to set SL(%u). Shouldn't be larger than %u.\n", 5225 sl, max_sl); 5226 return false; 5227 } 5228 5229 return true; 5230 } 5231 5232 static int hns_roce_set_sl(struct ib_qp *ibqp, 5233 const struct ib_qp_attr *attr, 5234 struct hns_roce_v2_qp_context *context, 5235 struct hns_roce_v2_qp_context *qpc_mask) 5236 { 5237 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5238 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5239 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5240 struct ib_device *ibdev = &hr_dev->ib_dev; 5241 int ret; 5242 5243 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 5244 5245 if (grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 5246 ret = hns_roce_hw_v2_get_dscp(hr_dev, 5247 get_tclass(&attr->ah_attr.grh), 5248 &hr_qp->tc_mode, &hr_qp->priority); 5249 if (ret && ret != -EOPNOTSUPP) { 5250 ibdev_err_ratelimited(ibdev, 5251 "failed to get dscp, ret = %d.\n", 5252 ret); 5253 return ret; 5254 } 5255 5256 if (hr_qp->tc_mode == HNAE3_TC_MAP_MODE_DSCP) 5257 hr_qp->sl = hr_qp->priority; 5258 } 5259 5260 if (!check_sl_valid(hr_dev, hr_qp->sl)) 5261 return -EINVAL; 5262 5263 hr_reg_write(context, QPC_SL, hr_qp->sl); 5264 hr_reg_clear(qpc_mask, QPC_SL); 5265 5266 return 0; 5267 } 5268 5269 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 5270 const struct ib_qp_attr *attr, 5271 int attr_mask, 5272 struct hns_roce_v2_qp_context *context, 5273 struct hns_roce_v2_qp_context *qpc_mask) 5274 { 5275 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 5276 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5277 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5278 struct ib_device *ibdev = &hr_dev->ib_dev; 5279 const struct ib_gid_attr *gid_attr = NULL; 5280 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 5281 int is_roce_protocol; 5282 u16 vlan_id = 0xffff; 5283 bool is_udp = false; 5284 u8 ib_port; 5285 u8 hr_port; 5286 int ret; 5287 5288 /* 5289 * If free_mr_en of qp is set, it means that this qp comes from 5290 * free mr. This qp will perform the loopback operation. 5291 * In the loopback scenario, only sl needs to be set. 5292 */ 5293 if (hr_qp->free_mr_en) { 5294 if (!check_sl_valid(hr_dev, sl)) 5295 return -EINVAL; 5296 hr_reg_write(context, QPC_SL, sl); 5297 hr_reg_clear(qpc_mask, QPC_SL); 5298 hr_qp->sl = sl; 5299 return 0; 5300 } 5301 5302 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 5303 hr_port = ib_port - 1; 5304 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 5305 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 5306 5307 if (is_roce_protocol) { 5308 gid_attr = attr->ah_attr.grh.sgid_attr; 5309 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 5310 if (ret) 5311 return ret; 5312 5313 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 5314 } 5315 5316 /* Only HIP08 needs to set the vlan_en bits in QPC */ 5317 if (vlan_id < VLAN_N_VID && 5318 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5319 hr_reg_enable(context, QPC_RQ_VLAN_EN); 5320 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 5321 hr_reg_enable(context, QPC_SQ_VLAN_EN); 5322 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 5323 } 5324 5325 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 5326 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 5327 5328 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 5329 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 5330 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 5331 return -EINVAL; 5332 } 5333 5334 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 5335 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 5336 return -EINVAL; 5337 } 5338 5339 hr_reg_write(context, QPC_UDPSPN, 5340 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 5341 attr->dest_qp_num) : 5342 0); 5343 5344 hr_reg_clear(qpc_mask, QPC_UDPSPN); 5345 5346 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 5347 5348 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 5349 5350 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 5351 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 5352 5353 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 5354 if (ret) 5355 return ret; 5356 5357 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 5358 hr_reg_clear(qpc_mask, QPC_TC); 5359 5360 hr_reg_write(context, QPC_FL, grh->flow_label); 5361 hr_reg_clear(qpc_mask, QPC_FL); 5362 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 5363 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 5364 5365 return hns_roce_set_sl(ibqp, attr, context, qpc_mask); 5366 } 5367 5368 static bool check_qp_state(enum ib_qp_state cur_state, 5369 enum ib_qp_state new_state) 5370 { 5371 static const bool sm[][IB_QPS_ERR + 1] = { 5372 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 5373 [IB_QPS_INIT] = true }, 5374 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 5375 [IB_QPS_INIT] = true, 5376 [IB_QPS_RTR] = true, 5377 [IB_QPS_ERR] = true }, 5378 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 5379 [IB_QPS_RTS] = true, 5380 [IB_QPS_ERR] = true }, 5381 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 5382 [IB_QPS_RTS] = true, 5383 [IB_QPS_ERR] = true }, 5384 [IB_QPS_SQD] = {}, 5385 [IB_QPS_SQE] = {}, 5386 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 5387 [IB_QPS_ERR] = true } 5388 }; 5389 5390 return sm[cur_state][new_state]; 5391 } 5392 5393 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 5394 const struct ib_qp_attr *attr, 5395 int attr_mask, 5396 enum ib_qp_state cur_state, 5397 enum ib_qp_state new_state, 5398 struct hns_roce_v2_qp_context *context, 5399 struct hns_roce_v2_qp_context *qpc_mask, 5400 struct ib_udata *udata) 5401 { 5402 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5403 int ret = 0; 5404 5405 if (!check_qp_state(cur_state, new_state)) 5406 return -EINVAL; 5407 5408 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 5409 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 5410 modify_qp_reset_to_init(ibqp, context); 5411 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 5412 modify_qp_init_to_init(ibqp, context, qpc_mask); 5413 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5414 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5415 qpc_mask, udata); 5416 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5417 ret = modify_qp_rtr_to_rts(ibqp, attr_mask, context, qpc_mask); 5418 } 5419 5420 return ret; 5421 } 5422 5423 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5424 { 5425 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5426 #define QP_ACK_TIMEOUT_MAX 31 5427 5428 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5429 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5430 ibdev_warn(&hr_dev->ib_dev, 5431 "local ACK timeout shall be 0 to 20.\n"); 5432 return false; 5433 } 5434 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5435 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5436 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5437 ibdev_warn(&hr_dev->ib_dev, 5438 "local ACK timeout shall be 0 to 31.\n"); 5439 return false; 5440 } 5441 } 5442 5443 return true; 5444 } 5445 5446 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5447 const struct ib_qp_attr *attr, 5448 int attr_mask, 5449 struct hns_roce_v2_qp_context *context, 5450 struct hns_roce_v2_qp_context *qpc_mask) 5451 { 5452 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5453 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5454 int ret = 0; 5455 u8 timeout; 5456 5457 if (attr_mask & IB_QP_AV) { 5458 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5459 qpc_mask); 5460 if (ret) 5461 return ret; 5462 } 5463 5464 if (attr_mask & IB_QP_TIMEOUT) { 5465 timeout = attr->timeout; 5466 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5467 hr_reg_write(context, QPC_AT, timeout); 5468 hr_reg_clear(qpc_mask, QPC_AT); 5469 } 5470 } 5471 5472 if (attr_mask & IB_QP_RETRY_CNT) { 5473 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5474 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5475 5476 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5477 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5478 } 5479 5480 if (attr_mask & IB_QP_RNR_RETRY) { 5481 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5482 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5483 5484 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5485 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5486 } 5487 5488 if (attr_mask & IB_QP_SQ_PSN) { 5489 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5490 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5491 5492 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5493 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5494 5495 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5496 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5497 5498 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5499 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5500 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5501 5502 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5503 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5504 5505 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5506 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5507 } 5508 5509 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5510 attr->max_dest_rd_atomic) { 5511 hr_reg_write(context, QPC_RR_MAX, 5512 fls(attr->max_dest_rd_atomic - 1)); 5513 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5514 } 5515 5516 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5517 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5518 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5519 } 5520 5521 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5522 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5523 5524 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5525 hr_reg_write(context, QPC_MIN_RNR_TIME, 5526 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5527 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5528 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5529 } 5530 5531 if (attr_mask & IB_QP_RQ_PSN) { 5532 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5533 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5534 5535 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5536 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5537 } 5538 5539 if (attr_mask & IB_QP_QKEY) { 5540 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5541 qpc_mask->qkey_xrcd = 0; 5542 hr_qp->qkey = attr->qkey; 5543 } 5544 5545 return ret; 5546 } 5547 5548 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5549 const struct ib_qp_attr *attr, 5550 int attr_mask) 5551 { 5552 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5553 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5554 5555 if (attr_mask & IB_QP_ACCESS_FLAGS) 5556 hr_qp->atomic_rd_en = attr->qp_access_flags; 5557 5558 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5559 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5560 if (attr_mask & IB_QP_PORT) { 5561 hr_qp->port = attr->port_num - 1; 5562 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5563 } 5564 } 5565 5566 static void clear_qp(struct hns_roce_qp *hr_qp) 5567 { 5568 struct ib_qp *ibqp = &hr_qp->ibqp; 5569 5570 if (ibqp->send_cq) 5571 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5572 hr_qp->qpn, NULL); 5573 5574 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5575 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5576 hr_qp->qpn, ibqp->srq ? 5577 to_hr_srq(ibqp->srq) : NULL); 5578 5579 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5580 *hr_qp->rdb.db_record = 0; 5581 5582 hr_qp->rq.head = 0; 5583 hr_qp->rq.tail = 0; 5584 hr_qp->sq.head = 0; 5585 hr_qp->sq.tail = 0; 5586 hr_qp->next_sge = 0; 5587 } 5588 5589 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5590 struct hns_roce_v2_qp_context *context, 5591 struct hns_roce_v2_qp_context *qpc_mask) 5592 { 5593 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5594 unsigned long sq_flag = 0; 5595 unsigned long rq_flag = 0; 5596 5597 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5598 return; 5599 5600 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5601 trace_hns_sq_flush_cqe(hr_qp->qpn, hr_qp->sq.head, TRACE_SQ); 5602 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5603 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5604 hr_qp->state = IB_QPS_ERR; 5605 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5606 5607 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5608 return; 5609 5610 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5611 trace_hns_rq_flush_cqe(hr_qp->qpn, hr_qp->rq.head, TRACE_RQ); 5612 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5613 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5614 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5615 } 5616 5617 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5618 const struct ib_qp_attr *attr, 5619 int attr_mask, enum ib_qp_state cur_state, 5620 enum ib_qp_state new_state, struct ib_udata *udata) 5621 { 5622 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5623 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5624 struct hns_roce_v2_qp_context *context; 5625 struct hns_roce_v2_qp_context *qpc_mask; 5626 struct ib_device *ibdev = &hr_dev->ib_dev; 5627 int ret = -ENOMEM; 5628 5629 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5630 return -EOPNOTSUPP; 5631 5632 /* 5633 * In v2 engine, software pass context and context mask to hardware 5634 * when modifying qp. If software need modify some fields in context, 5635 * we should set all bits of the relevant fields in context mask to 5636 * 0 at the same time, else set them to 0x1. 5637 */ 5638 context = kvzalloc(sizeof(*context), GFP_KERNEL); 5639 qpc_mask = kvzalloc(sizeof(*qpc_mask), GFP_KERNEL); 5640 if (!context || !qpc_mask) 5641 goto out; 5642 5643 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5644 5645 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5646 new_state, context, qpc_mask, udata); 5647 if (ret) 5648 goto out; 5649 5650 /* When QP state is err, SQ and RQ WQE should be flushed */ 5651 if (new_state == IB_QPS_ERR) 5652 v2_set_flushed_fields(ibqp, context, qpc_mask); 5653 5654 /* Configure the optional fields */ 5655 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5656 qpc_mask); 5657 if (ret) 5658 goto out; 5659 5660 hr_reg_write_bool(context, QPC_INV_CREDIT, 5661 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5662 ibqp->srq); 5663 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5664 5665 /* Every status migrate must change state */ 5666 hr_reg_write(context, QPC_QP_ST, new_state); 5667 hr_reg_clear(qpc_mask, QPC_QP_ST); 5668 5669 /* SW pass context to HW */ 5670 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5671 if (ret) { 5672 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret); 5673 goto out; 5674 } 5675 5676 hr_qp->state = new_state; 5677 5678 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5679 5680 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5681 clear_qp(hr_qp); 5682 5683 out: 5684 kvfree(qpc_mask); 5685 kvfree(context); 5686 return ret; 5687 } 5688 5689 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5690 { 5691 static const enum ib_qp_state map[] = { 5692 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5693 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5694 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5695 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5696 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5697 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5698 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5699 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5700 }; 5701 5702 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5703 } 5704 5705 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5706 void *buffer) 5707 { 5708 struct hns_roce_cmd_mailbox *mailbox; 5709 int ret; 5710 5711 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5712 if (IS_ERR(mailbox)) 5713 return PTR_ERR(mailbox); 5714 5715 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5716 qpn); 5717 if (ret) 5718 goto out; 5719 5720 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5721 5722 out: 5723 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5724 return ret; 5725 } 5726 5727 static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, 5728 void *buffer) 5729 { 5730 struct hns_roce_srq_context *context; 5731 struct hns_roce_cmd_mailbox *mailbox; 5732 int ret; 5733 5734 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5735 if (IS_ERR(mailbox)) 5736 return PTR_ERR(mailbox); 5737 5738 context = mailbox->buf; 5739 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SRQC, 5740 srqn); 5741 if (ret) 5742 goto out; 5743 5744 memcpy(buffer, context, sizeof(*context)); 5745 5746 out: 5747 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5748 return ret; 5749 } 5750 5751 static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 sccn, 5752 void *buffer) 5753 { 5754 struct hns_roce_v2_scc_context *context; 5755 struct hns_roce_cmd_mailbox *mailbox; 5756 int ret; 5757 5758 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5759 if (IS_ERR(mailbox)) 5760 return PTR_ERR(mailbox); 5761 5762 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_SCCC, 5763 sccn); 5764 if (ret) 5765 goto out; 5766 5767 context = mailbox->buf; 5768 memcpy(buffer, context, sizeof(*context)); 5769 5770 out: 5771 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5772 return ret; 5773 } 5774 5775 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5776 struct hns_roce_v2_qp_context *context) 5777 { 5778 u8 timeout; 5779 5780 timeout = (u8)hr_reg_read(context, QPC_AT); 5781 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5782 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5783 5784 return timeout; 5785 } 5786 5787 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5788 int qp_attr_mask, 5789 struct ib_qp_init_attr *qp_init_attr) 5790 { 5791 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5792 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5793 struct hns_roce_v2_qp_context context = {}; 5794 struct ib_device *ibdev = &hr_dev->ib_dev; 5795 int tmp_qp_state; 5796 int state; 5797 int ret; 5798 5799 memset(qp_attr, 0, sizeof(*qp_attr)); 5800 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5801 5802 mutex_lock(&hr_qp->mutex); 5803 5804 if (hr_qp->state == IB_QPS_RESET) { 5805 qp_attr->qp_state = IB_QPS_RESET; 5806 ret = 0; 5807 goto done; 5808 } 5809 5810 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5811 if (ret) { 5812 ibdev_err_ratelimited(ibdev, 5813 "failed to query QPC, ret = %d.\n", 5814 ret); 5815 ret = -EINVAL; 5816 goto out; 5817 } 5818 5819 state = hr_reg_read(&context, QPC_QP_ST); 5820 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5821 if (tmp_qp_state == -1) { 5822 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n"); 5823 ret = -EINVAL; 5824 goto out; 5825 } 5826 hr_qp->state = (u8)tmp_qp_state; 5827 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5828 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5829 qp_attr->path_mig_state = IB_MIG_ARMED; 5830 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5831 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5832 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5833 5834 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5835 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5836 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5837 qp_attr->qp_access_flags = 5838 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5839 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5840 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5841 5842 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5843 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5844 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5845 struct ib_global_route *grh = 5846 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5847 5848 rdma_ah_set_sl(&qp_attr->ah_attr, 5849 hr_reg_read(&context, QPC_SL)); 5850 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5851 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5852 grh->flow_label = hr_reg_read(&context, QPC_FL); 5853 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5854 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5855 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5856 5857 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5858 } 5859 5860 qp_attr->port_num = hr_qp->port + 1; 5861 qp_attr->sq_draining = 0; 5862 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5863 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5864 5865 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5866 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5867 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5868 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5869 5870 done: 5871 qp_attr->cur_qp_state = qp_attr->qp_state; 5872 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5873 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5874 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5875 5876 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5877 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5878 5879 qp_init_attr->qp_context = ibqp->qp_context; 5880 qp_init_attr->qp_type = ibqp->qp_type; 5881 qp_init_attr->recv_cq = ibqp->recv_cq; 5882 qp_init_attr->send_cq = ibqp->send_cq; 5883 qp_init_attr->srq = ibqp->srq; 5884 qp_init_attr->cap = qp_attr->cap; 5885 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5886 5887 out: 5888 mutex_unlock(&hr_qp->mutex); 5889 return ret; 5890 } 5891 5892 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5893 { 5894 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5895 hr_qp->ibqp.qp_type == IB_QPT_UD || 5896 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5897 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5898 hr_qp->state != IB_QPS_RESET); 5899 } 5900 5901 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5902 struct hns_roce_qp *hr_qp, 5903 struct ib_udata *udata) 5904 { 5905 struct ib_device *ibdev = &hr_dev->ib_dev; 5906 struct hns_roce_cq *send_cq, *recv_cq; 5907 unsigned long flags; 5908 int ret = 0; 5909 5910 if (modify_qp_is_ok(hr_qp)) { 5911 /* Modify qp to reset before destroying qp */ 5912 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5913 hr_qp->state, IB_QPS_RESET, udata); 5914 if (ret) 5915 ibdev_err_ratelimited(ibdev, 5916 "failed to modify QP to RST, ret = %d.\n", 5917 ret); 5918 } 5919 5920 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5921 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5922 5923 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5924 hns_roce_lock_cqs(send_cq, recv_cq); 5925 5926 if (!udata) { 5927 if (recv_cq) 5928 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5929 (hr_qp->ibqp.srq ? 5930 to_hr_srq(hr_qp->ibqp.srq) : 5931 NULL)); 5932 5933 if (send_cq && send_cq != recv_cq) 5934 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5935 } 5936 5937 hns_roce_qp_remove(hr_dev, hr_qp); 5938 5939 hns_roce_unlock_cqs(send_cq, recv_cq); 5940 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5941 5942 return ret; 5943 } 5944 5945 static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev, 5946 struct hns_roce_qp *hr_qp) 5947 { 5948 struct hns_roce_dip *hr_dip = hr_qp->dip; 5949 5950 if (!hr_dip) 5951 return; 5952 5953 xa_lock(&hr_dev->qp_table.dip_xa); 5954 5955 hr_dip->qp_cnt--; 5956 if (!hr_dip->qp_cnt) 5957 memset(hr_dip->dgid, 0, GID_LEN_V2); 5958 5959 xa_unlock(&hr_dev->qp_table.dip_xa); 5960 } 5961 5962 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5963 { 5964 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5965 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5966 unsigned long flags; 5967 int ret; 5968 5969 /* Make sure flush_cqe() is completed */ 5970 spin_lock_irqsave(&hr_qp->flush_lock, flags); 5971 set_bit(HNS_ROCE_STOP_FLUSH_FLAG, &hr_qp->flush_flag); 5972 spin_unlock_irqrestore(&hr_qp->flush_lock, flags); 5973 flush_work(&hr_qp->flush_work.work); 5974 5975 if (hr_qp->cong_type == CONG_TYPE_DIP) 5976 put_dip_ctx_idx(hr_dev, hr_qp); 5977 5978 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5979 if (ret) 5980 ibdev_err_ratelimited(&hr_dev->ib_dev, 5981 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5982 hr_qp->qpn, ret); 5983 5984 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5985 5986 return 0; 5987 } 5988 5989 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5990 struct hns_roce_qp *hr_qp) 5991 { 5992 struct ib_device *ibdev = &hr_dev->ib_dev; 5993 struct hns_roce_sccc_clr_done *resp; 5994 struct hns_roce_sccc_clr *clr; 5995 struct hns_roce_cmq_desc desc; 5996 int ret, i; 5997 5998 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5999 return 0; 6000 6001 mutex_lock(&hr_dev->qp_table.scc_mutex); 6002 6003 /* set scc ctx clear done flag */ 6004 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 6005 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6006 if (ret) { 6007 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 6008 goto out; 6009 } 6010 6011 /* clear scc context */ 6012 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 6013 clr = (struct hns_roce_sccc_clr *)desc.data; 6014 clr->qpn = cpu_to_le32(hr_qp->qpn); 6015 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6016 if (ret) { 6017 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 6018 goto out; 6019 } 6020 6021 /* query scc context clear is done or not */ 6022 resp = (struct hns_roce_sccc_clr_done *)desc.data; 6023 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 6024 hns_roce_cmq_setup_basic_desc(&desc, 6025 HNS_ROCE_OPC_QUERY_SCCC, true); 6026 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6027 if (ret) { 6028 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 6029 ret); 6030 goto out; 6031 } 6032 6033 if (resp->clr_done) 6034 goto out; 6035 6036 msleep(20); 6037 } 6038 6039 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 6040 ret = -ETIMEDOUT; 6041 6042 out: 6043 mutex_unlock(&hr_dev->qp_table.scc_mutex); 6044 return ret; 6045 } 6046 6047 #define DMA_IDX_SHIFT 3 6048 #define DMA_WQE_SHIFT 3 6049 6050 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 6051 struct hns_roce_srq_context *ctx) 6052 { 6053 struct hns_roce_idx_que *idx_que = &srq->idx_que; 6054 struct ib_device *ibdev = srq->ibsrq.device; 6055 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 6056 u64 mtts_idx[MTT_MIN_COUNT] = {}; 6057 dma_addr_t dma_handle_idx; 6058 int ret; 6059 6060 /* Get physical address of idx que buf */ 6061 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 6062 ARRAY_SIZE(mtts_idx)); 6063 if (ret) { 6064 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 6065 ret); 6066 return ret; 6067 } 6068 6069 dma_handle_idx = hns_roce_get_mtr_ba(&idx_que->mtr); 6070 6071 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 6072 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 6073 6074 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 6075 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 6076 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 6077 6078 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 6079 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 6080 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 6081 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 6082 6083 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 6084 to_hr_hw_page_addr(mtts_idx[0])); 6085 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 6086 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 6087 6088 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 6089 to_hr_hw_page_addr(mtts_idx[1])); 6090 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 6091 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 6092 6093 return 0; 6094 } 6095 6096 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 6097 { 6098 struct ib_device *ibdev = srq->ibsrq.device; 6099 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 6100 struct hns_roce_srq_context *ctx = mb_buf; 6101 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 6102 dma_addr_t dma_handle_wqe; 6103 int ret; 6104 6105 memset(ctx, 0, sizeof(*ctx)); 6106 6107 /* Get the physical address of srq buf */ 6108 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 6109 ARRAY_SIZE(mtts_wqe)); 6110 if (ret) { 6111 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 6112 ret); 6113 return ret; 6114 } 6115 6116 dma_handle_wqe = hns_roce_get_mtr_ba(&srq->buf_mtr); 6117 6118 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 6119 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 6120 srq->ibsrq.srq_type == IB_SRQT_XRC); 6121 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 6122 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 6123 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 6124 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 6125 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 6126 hr_reg_write(ctx, SRQC_RQWS, 6127 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 6128 6129 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 6130 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 6131 srq->wqe_cnt)); 6132 6133 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 6134 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 6135 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 6136 6137 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 6138 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 6139 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 6140 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 6141 6142 if (srq->cap_flags & HNS_ROCE_SRQ_CAP_RECORD_DB) { 6143 hr_reg_enable(ctx, SRQC_DB_RECORD_EN); 6144 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_L, 6145 lower_32_bits(srq->rdb.dma) >> 1); 6146 hr_reg_write(ctx, SRQC_DB_RECORD_ADDR_H, 6147 upper_32_bits(srq->rdb.dma)); 6148 } 6149 6150 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 6151 } 6152 6153 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 6154 struct ib_srq_attr *srq_attr, 6155 enum ib_srq_attr_mask srq_attr_mask, 6156 struct ib_udata *udata) 6157 { 6158 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 6159 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 6160 struct hns_roce_srq_context *srq_context; 6161 struct hns_roce_srq_context *srqc_mask; 6162 struct hns_roce_cmd_mailbox *mailbox; 6163 int ret = 0; 6164 6165 /* Resizing SRQs is not supported yet */ 6166 if (srq_attr_mask & IB_SRQ_MAX_WR) { 6167 ret = -EOPNOTSUPP; 6168 goto out; 6169 } 6170 6171 if (srq_attr_mask & IB_SRQ_LIMIT) { 6172 if (srq_attr->srq_limit > srq->wqe_cnt) { 6173 ret = -EINVAL; 6174 goto out; 6175 } 6176 6177 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6178 if (IS_ERR(mailbox)) { 6179 ret = PTR_ERR(mailbox); 6180 goto out; 6181 } 6182 6183 srq_context = mailbox->buf; 6184 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 6185 6186 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 6187 6188 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 6189 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 6190 6191 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 6192 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 6193 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6194 if (ret) 6195 ibdev_err(&hr_dev->ib_dev, 6196 "failed to handle cmd of modifying SRQ, ret = %d.\n", 6197 ret); 6198 } 6199 6200 out: 6201 if (ret) 6202 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_SRQ_MODIFY_ERR_CNT]); 6203 6204 return ret; 6205 } 6206 6207 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 6208 { 6209 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 6210 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 6211 struct hns_roce_srq_context *srq_context; 6212 struct hns_roce_cmd_mailbox *mailbox; 6213 int ret; 6214 6215 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6216 if (IS_ERR(mailbox)) 6217 return PTR_ERR(mailbox); 6218 6219 srq_context = mailbox->buf; 6220 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 6221 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 6222 if (ret) { 6223 ibdev_err(&hr_dev->ib_dev, 6224 "failed to process cmd of querying SRQ, ret = %d.\n", 6225 ret); 6226 goto out; 6227 } 6228 6229 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 6230 attr->max_wr = srq->wqe_cnt; 6231 attr->max_sge = srq->max_gs - srq->rsv_sge; 6232 6233 out: 6234 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6235 return ret; 6236 } 6237 6238 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 6239 { 6240 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 6241 struct hns_roce_v2_cq_context *cq_context; 6242 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 6243 struct hns_roce_v2_cq_context *cqc_mask; 6244 struct hns_roce_cmd_mailbox *mailbox; 6245 int ret; 6246 6247 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6248 ret = PTR_ERR_OR_ZERO(mailbox); 6249 if (ret) 6250 goto err_out; 6251 6252 cq_context = mailbox->buf; 6253 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 6254 6255 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 6256 6257 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 6258 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 6259 6260 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6261 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6262 dev_info(hr_dev->dev, 6263 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 6264 cq_period); 6265 cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 6266 } 6267 cq_period *= HNS_ROCE_CLOCK_ADJUST; 6268 } 6269 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 6270 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 6271 6272 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 6273 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 6274 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6275 if (ret) 6276 ibdev_err_ratelimited(&hr_dev->ib_dev, 6277 "failed to process cmd when modifying CQ, ret = %d.\n", 6278 ret); 6279 6280 err_out: 6281 if (ret) 6282 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CQ_MODIFY_ERR_CNT]); 6283 6284 return ret; 6285 } 6286 6287 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 6288 void *buffer) 6289 { 6290 struct hns_roce_v2_cq_context *context; 6291 struct hns_roce_cmd_mailbox *mailbox; 6292 int ret; 6293 6294 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6295 if (IS_ERR(mailbox)) 6296 return PTR_ERR(mailbox); 6297 6298 context = mailbox->buf; 6299 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 6300 HNS_ROCE_CMD_QUERY_CQC, cqn); 6301 if (ret) { 6302 ibdev_err_ratelimited(&hr_dev->ib_dev, 6303 "failed to process cmd when querying CQ, ret = %d.\n", 6304 ret); 6305 goto err_mailbox; 6306 } 6307 6308 memcpy(buffer, context, sizeof(*context)); 6309 6310 err_mailbox: 6311 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6312 6313 return ret; 6314 } 6315 6316 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 6317 void *buffer) 6318 { 6319 struct hns_roce_v2_mpt_entry *context; 6320 struct hns_roce_cmd_mailbox *mailbox; 6321 int ret; 6322 6323 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6324 if (IS_ERR(mailbox)) 6325 return PTR_ERR(mailbox); 6326 6327 context = mailbox->buf; 6328 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 6329 key_to_hw_index(key)); 6330 if (ret) { 6331 ibdev_err(&hr_dev->ib_dev, 6332 "failed to process cmd when querying MPT, ret = %d.\n", 6333 ret); 6334 goto err_mailbox; 6335 } 6336 6337 memcpy(buffer, context, sizeof(*context)); 6338 6339 err_mailbox: 6340 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6341 6342 return ret; 6343 } 6344 6345 static void dump_aeqe_log(struct hns_roce_work *irq_work) 6346 { 6347 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6348 struct ib_device *ibdev = &hr_dev->ib_dev; 6349 6350 switch (irq_work->event_type) { 6351 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6352 ibdev_info(ibdev, "path migrated succeeded.\n"); 6353 break; 6354 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6355 ibdev_warn(ibdev, "path migration failed.\n"); 6356 break; 6357 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6358 break; 6359 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6360 ibdev_dbg(ibdev, "send queue drained.\n"); 6361 break; 6362 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6363 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 6364 irq_work->queue_num, irq_work->sub_type); 6365 break; 6366 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6367 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 6368 irq_work->queue_num); 6369 break; 6370 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6371 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 6372 irq_work->queue_num, irq_work->sub_type); 6373 break; 6374 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6375 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 6376 break; 6377 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6378 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 6379 break; 6380 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6381 ibdev_err(ibdev, "SRQ catas error.\n"); 6382 break; 6383 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6384 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 6385 break; 6386 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6387 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 6388 break; 6389 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 6390 ibdev_warn(ibdev, "DB overflow.\n"); 6391 break; 6392 case HNS_ROCE_EVENT_TYPE_MB: 6393 break; 6394 case HNS_ROCE_EVENT_TYPE_FLR: 6395 ibdev_warn(ibdev, "function level reset.\n"); 6396 break; 6397 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6398 ibdev_err(ibdev, "xrc domain violation error.\n"); 6399 break; 6400 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6401 ibdev_err(ibdev, "invalid xrceth error.\n"); 6402 break; 6403 default: 6404 ibdev_info(ibdev, "Undefined event %d.\n", 6405 irq_work->event_type); 6406 break; 6407 } 6408 } 6409 6410 static void hns_roce_irq_work_handle(struct work_struct *work) 6411 { 6412 struct hns_roce_work *irq_work = 6413 container_of(work, struct hns_roce_work, work); 6414 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 6415 int event_type = irq_work->event_type; 6416 u32 queue_num = irq_work->queue_num; 6417 6418 switch (event_type) { 6419 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 6420 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 6421 case HNS_ROCE_EVENT_TYPE_COMM_EST: 6422 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 6423 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6424 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 6425 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6426 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6427 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6428 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6429 hns_roce_qp_event(hr_dev, queue_num, event_type); 6430 break; 6431 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 6432 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 6433 hns_roce_srq_event(hr_dev, queue_num, event_type); 6434 break; 6435 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 6436 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 6437 hns_roce_cq_event(hr_dev, queue_num, event_type); 6438 break; 6439 default: 6440 break; 6441 } 6442 6443 dump_aeqe_log(irq_work); 6444 6445 kfree(irq_work); 6446 } 6447 6448 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 6449 struct hns_roce_eq *eq, u32 queue_num) 6450 { 6451 struct hns_roce_work *irq_work; 6452 6453 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 6454 if (!irq_work) 6455 return; 6456 6457 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 6458 irq_work->hr_dev = hr_dev; 6459 irq_work->event_type = eq->event_type; 6460 irq_work->sub_type = eq->sub_type; 6461 irq_work->queue_num = queue_num; 6462 queue_work(hr_dev->irq_workq, &irq_work->work); 6463 } 6464 6465 static void update_eq_db(struct hns_roce_eq *eq) 6466 { 6467 struct hns_roce_dev *hr_dev = eq->hr_dev; 6468 struct hns_roce_v2_db eq_db = {}; 6469 6470 if (eq->type_flag == HNS_ROCE_AEQ) { 6471 hr_reg_write(&eq_db, EQ_DB_CMD, 6472 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6473 HNS_ROCE_EQ_DB_CMD_AEQ : 6474 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 6475 } else { 6476 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 6477 6478 hr_reg_write(&eq_db, EQ_DB_CMD, 6479 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 6480 HNS_ROCE_EQ_DB_CMD_CEQ : 6481 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 6482 } 6483 6484 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 6485 6486 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 6487 } 6488 6489 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 6490 { 6491 struct hns_roce_aeqe *aeqe; 6492 6493 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 6494 (eq->cons_index & (eq->entries - 1)) * 6495 eq->eqe_size); 6496 6497 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 6498 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 6499 } 6500 6501 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 6502 struct hns_roce_eq *eq) 6503 { 6504 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 6505 irqreturn_t aeqe_found = IRQ_NONE; 6506 int num_aeqes = 0; 6507 int event_type; 6508 u32 queue_num; 6509 int sub_type; 6510 6511 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) { 6512 /* Make sure we read AEQ entry after we have checked the 6513 * ownership bit 6514 */ 6515 dma_rmb(); 6516 6517 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 6518 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 6519 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 6520 6521 switch (event_type) { 6522 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 6523 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 6524 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 6525 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 6526 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 6527 hns_roce_flush_cqe(hr_dev, queue_num); 6528 break; 6529 case HNS_ROCE_EVENT_TYPE_MB: 6530 hns_roce_cmd_event(hr_dev, 6531 le16_to_cpu(aeqe->event.cmd.token), 6532 aeqe->event.cmd.status, 6533 le64_to_cpu(aeqe->event.cmd.out_param)); 6534 break; 6535 default: 6536 break; 6537 } 6538 6539 eq->event_type = event_type; 6540 eq->sub_type = sub_type; 6541 ++eq->cons_index; 6542 aeqe_found = IRQ_HANDLED; 6543 trace_hns_ae_info(event_type, aeqe, eq->eqe_size); 6544 6545 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_AEQE_CNT]); 6546 6547 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6548 6549 aeqe = next_aeqe_sw_v2(eq); 6550 ++num_aeqes; 6551 } 6552 6553 update_eq_db(eq); 6554 6555 return IRQ_RETVAL(aeqe_found); 6556 } 6557 6558 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6559 { 6560 struct hns_roce_ceqe *ceqe; 6561 6562 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6563 (eq->cons_index & (eq->entries - 1)) * 6564 eq->eqe_size); 6565 6566 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6567 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6568 } 6569 6570 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) 6571 { 6572 queue_work(system_bh_wq, &eq->work); 6573 6574 return IRQ_HANDLED; 6575 } 6576 6577 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6578 { 6579 struct hns_roce_eq *eq = eq_ptr; 6580 struct hns_roce_dev *hr_dev = eq->hr_dev; 6581 irqreturn_t int_work; 6582 6583 if (eq->type_flag == HNS_ROCE_CEQ) 6584 /* Completion event interrupt */ 6585 int_work = hns_roce_v2_ceq_int(eq); 6586 else 6587 /* Asynchronous event interrupt */ 6588 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6589 6590 return IRQ_RETVAL(int_work); 6591 } 6592 6593 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6594 u32 int_st) 6595 { 6596 struct pci_dev *pdev = hr_dev->pci_dev; 6597 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6598 const struct hnae3_ae_ops *ops = ae_dev->ops; 6599 enum hnae3_reset_type reset_type; 6600 irqreturn_t int_work = IRQ_NONE; 6601 u32 int_en; 6602 6603 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6604 6605 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6606 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6607 6608 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6609 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6610 6611 reset_type = hr_dev->is_vf ? 6612 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET; 6613 6614 /* Set reset level for reset_event() */ 6615 if (ops->set_default_reset_request) 6616 ops->set_default_reset_request(ae_dev, reset_type); 6617 if (ops->reset_event) 6618 ops->reset_event(pdev, NULL); 6619 6620 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6621 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6622 6623 int_work = IRQ_HANDLED; 6624 } else { 6625 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6626 } 6627 6628 return IRQ_RETVAL(int_work); 6629 } 6630 6631 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6632 struct fmea_ram_ecc *ecc_info) 6633 { 6634 struct hns_roce_cmq_desc desc; 6635 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6636 int ret; 6637 6638 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6639 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6640 if (ret) 6641 return ret; 6642 6643 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6644 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6645 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6646 6647 return 0; 6648 } 6649 6650 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6651 { 6652 struct hns_roce_cmq_desc desc; 6653 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6654 u32 addr_upper; 6655 u32 addr_low; 6656 int ret; 6657 6658 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6659 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6660 6661 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6662 if (ret) { 6663 dev_err(hr_dev->dev, 6664 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6665 return ret; 6666 } 6667 6668 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6669 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6670 6671 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6672 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6673 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6674 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6675 6676 return hns_roce_cmq_send(hr_dev, &desc, 1); 6677 } 6678 6679 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6680 { 6681 if (res_type == ECC_RESOURCE_QPC_TIMER || 6682 res_type == ECC_RESOURCE_CQC_TIMER || 6683 res_type == ECC_RESOURCE_SCCC) 6684 return le64_to_cpu(*data); 6685 6686 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT; 6687 } 6688 6689 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6690 u32 index) 6691 { 6692 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6693 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6694 struct hns_roce_cmd_mailbox *mailbox; 6695 u64 addr; 6696 int ret; 6697 6698 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6699 if (IS_ERR(mailbox)) 6700 return PTR_ERR(mailbox); 6701 6702 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6703 if (ret) { 6704 dev_err(hr_dev->dev, 6705 "failed to execute cmd to read fmea ram, ret = %d.\n", 6706 ret); 6707 goto out; 6708 } 6709 6710 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6711 6712 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6713 if (ret) 6714 dev_err(hr_dev->dev, 6715 "failed to execute cmd to write fmea ram, ret = %d.\n", 6716 ret); 6717 6718 out: 6719 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6720 return ret; 6721 } 6722 6723 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6724 struct fmea_ram_ecc *ecc_info) 6725 { 6726 u32 res_type = ecc_info->res_type; 6727 u32 index = ecc_info->index; 6728 int ret; 6729 6730 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6731 6732 if (res_type >= ECC_RESOURCE_COUNT) { 6733 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6734 res_type); 6735 return; 6736 } 6737 6738 if (res_type == ECC_RESOURCE_GMV) 6739 ret = fmea_recover_gmv(hr_dev, index); 6740 else 6741 ret = fmea_recover_others(hr_dev, res_type, index); 6742 if (ret) 6743 dev_err(hr_dev->dev, 6744 "failed to recover %s, index = %u, ret = %d.\n", 6745 fmea_ram_res[res_type].name, index, ret); 6746 } 6747 6748 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6749 { 6750 struct hns_roce_dev *hr_dev = 6751 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6752 struct fmea_ram_ecc ecc_info = {}; 6753 6754 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6755 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6756 return; 6757 } 6758 6759 if (!ecc_info.is_ecc_err) { 6760 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6761 return; 6762 } 6763 6764 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6765 } 6766 6767 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6768 { 6769 struct hns_roce_dev *hr_dev = dev_id; 6770 irqreturn_t int_work = IRQ_NONE; 6771 u32 int_st; 6772 6773 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6774 6775 if (int_st) { 6776 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6777 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6778 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6779 int_work = IRQ_HANDLED; 6780 } else { 6781 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6782 } 6783 6784 return IRQ_RETVAL(int_work); 6785 } 6786 6787 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6788 int eq_num, u32 enable_flag) 6789 { 6790 int i; 6791 6792 for (i = 0; i < eq_num; i++) 6793 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6794 i * EQ_REG_OFFSET, enable_flag); 6795 6796 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6797 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6798 } 6799 6800 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6801 { 6802 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6803 } 6804 6805 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6806 struct hns_roce_eq *eq) 6807 { 6808 struct device *dev = hr_dev->dev; 6809 int eqn = eq->eqn; 6810 int ret; 6811 u8 cmd; 6812 6813 if (eqn < hr_dev->caps.num_comp_vectors) 6814 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6815 else 6816 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6817 6818 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6819 if (ret) 6820 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6821 6822 free_eq_buf(hr_dev, eq); 6823 } 6824 6825 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6826 { 6827 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6828 eq->cons_index = 0; 6829 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6830 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6831 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6832 eq->shift = ilog2((unsigned int)eq->entries); 6833 } 6834 6835 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6836 void *mb_buf) 6837 { 6838 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6839 struct hns_roce_eq_context *eqc; 6840 u64 bt_ba = 0; 6841 int ret; 6842 6843 eqc = mb_buf; 6844 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6845 6846 init_eq_config(hr_dev, eq); 6847 6848 /* if not multi-hop, eqe buffer only use one trunk */ 6849 ret = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, 6850 ARRAY_SIZE(eqe_ba)); 6851 if (ret) { 6852 dev_err(hr_dev->dev, "failed to find EQE mtr, ret = %d\n", ret); 6853 return ret; 6854 } 6855 6856 bt_ba = hns_roce_get_mtr_ba(&eq->mtr); 6857 6858 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6859 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6860 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6861 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6862 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6863 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6864 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6865 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6866 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6867 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6868 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6869 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6870 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6871 6872 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6873 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6874 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6875 eq->eq_period); 6876 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6877 } 6878 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6879 } 6880 6881 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6882 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6883 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6884 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6885 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6886 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6887 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6888 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6889 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6890 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6891 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6892 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6893 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6894 6895 return 0; 6896 } 6897 6898 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6899 { 6900 struct hns_roce_buf_attr buf_attr = {}; 6901 int err; 6902 6903 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6904 eq->hop_num = 0; 6905 else 6906 eq->hop_num = hr_dev->caps.eqe_hop_num; 6907 6908 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6909 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6910 buf_attr.region[0].hopnum = eq->hop_num; 6911 buf_attr.region_count = 1; 6912 6913 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6914 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6915 0); 6916 if (err) 6917 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6918 6919 return err; 6920 } 6921 6922 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6923 struct hns_roce_eq *eq, u8 eq_cmd) 6924 { 6925 struct hns_roce_cmd_mailbox *mailbox; 6926 int ret; 6927 6928 /* Allocate mailbox memory */ 6929 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6930 if (IS_ERR(mailbox)) 6931 return PTR_ERR(mailbox); 6932 6933 ret = alloc_eq_buf(hr_dev, eq); 6934 if (ret) 6935 goto free_cmd_mbox; 6936 6937 ret = config_eqc(hr_dev, eq, mailbox->buf); 6938 if (ret) 6939 goto err_cmd_mbox; 6940 6941 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6942 if (ret) { 6943 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6944 goto err_cmd_mbox; 6945 } 6946 6947 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6948 6949 return 0; 6950 6951 err_cmd_mbox: 6952 free_eq_buf(hr_dev, eq); 6953 6954 free_cmd_mbox: 6955 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6956 6957 return ret; 6958 } 6959 6960 static void hns_roce_ceq_work(struct work_struct *work) 6961 { 6962 struct hns_roce_eq *eq = from_work(eq, work, work); 6963 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6964 struct hns_roce_dev *hr_dev = eq->hr_dev; 6965 int ceqe_num = 0; 6966 u32 cqn; 6967 6968 while (ceqe && ceqe_num < hr_dev->caps.ceqe_depth) { 6969 /* Make sure we read CEQ entry after we have checked the 6970 * ownership bit 6971 */ 6972 dma_rmb(); 6973 6974 cqn = hr_reg_read(ceqe, CEQE_CQN); 6975 6976 hns_roce_cq_completion(hr_dev, cqn); 6977 6978 ++eq->cons_index; 6979 ++ceqe_num; 6980 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CEQE_CNT]); 6981 6982 ceqe = next_ceqe_sw_v2(eq); 6983 } 6984 6985 update_eq_db(eq); 6986 } 6987 6988 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6989 int comp_num, int aeq_num, int other_num) 6990 { 6991 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6992 int i, j; 6993 int ret; 6994 6995 for (i = 0; i < irq_num; i++) { 6996 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6997 GFP_KERNEL); 6998 if (!hr_dev->irq_names[i]) { 6999 ret = -ENOMEM; 7000 goto err_kzalloc_failed; 7001 } 7002 } 7003 7004 /* irq contains: abnormal + AEQ + CEQ */ 7005 for (j = 0; j < other_num; j++) 7006 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 7007 "hns-%s-abn-%d", pci_name(hr_dev->pci_dev), j); 7008 7009 for (j = other_num; j < (other_num + aeq_num); j++) 7010 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 7011 "hns-%s-aeq-%d", pci_name(hr_dev->pci_dev), j - other_num); 7012 7013 for (j = (other_num + aeq_num); j < irq_num; j++) 7014 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 7015 "hns-%s-ceq-%d", pci_name(hr_dev->pci_dev), 7016 j - other_num - aeq_num); 7017 7018 for (j = 0; j < irq_num; j++) { 7019 if (j < other_num) { 7020 ret = request_irq(hr_dev->irq[j], 7021 hns_roce_v2_msix_interrupt_abn, 7022 0, hr_dev->irq_names[j], hr_dev); 7023 } else if (j < (other_num + comp_num)) { 7024 INIT_WORK(&eq_table->eq[j - other_num].work, 7025 hns_roce_ceq_work); 7026 ret = request_irq(eq_table->eq[j - other_num].irq, 7027 hns_roce_v2_msix_interrupt_eq, 7028 0, hr_dev->irq_names[j + aeq_num], 7029 &eq_table->eq[j - other_num]); 7030 } else { 7031 ret = request_irq(eq_table->eq[j - other_num].irq, 7032 hns_roce_v2_msix_interrupt_eq, 7033 0, hr_dev->irq_names[j - comp_num], 7034 &eq_table->eq[j - other_num]); 7035 } 7036 7037 if (ret) { 7038 dev_err(hr_dev->dev, "request irq error!\n"); 7039 goto err_request_failed; 7040 } 7041 } 7042 7043 return 0; 7044 7045 err_request_failed: 7046 for (j -= 1; j >= 0; j--) { 7047 if (j < other_num) { 7048 free_irq(hr_dev->irq[j], hr_dev); 7049 continue; 7050 } 7051 free_irq(eq_table->eq[j - other_num].irq, 7052 &eq_table->eq[j - other_num]); 7053 if (j < other_num + comp_num) 7054 cancel_work_sync(&eq_table->eq[j - other_num].work); 7055 } 7056 7057 err_kzalloc_failed: 7058 for (i -= 1; i >= 0; i--) 7059 kfree(hr_dev->irq_names[i]); 7060 7061 return ret; 7062 } 7063 7064 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 7065 { 7066 int irq_num; 7067 int eq_num; 7068 int i; 7069 7070 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 7071 irq_num = eq_num + hr_dev->caps.num_other_vectors; 7072 7073 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 7074 free_irq(hr_dev->irq[i], hr_dev); 7075 7076 for (i = 0; i < eq_num; i++) { 7077 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 7078 if (i < hr_dev->caps.num_comp_vectors) 7079 cancel_work_sync(&hr_dev->eq_table.eq[i].work); 7080 } 7081 7082 for (i = 0; i < irq_num; i++) 7083 kfree(hr_dev->irq_names[i]); 7084 } 7085 7086 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 7087 { 7088 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 7089 struct device *dev = hr_dev->dev; 7090 struct hns_roce_eq *eq; 7091 int other_num; 7092 int comp_num; 7093 int aeq_num; 7094 int irq_num; 7095 int eq_num; 7096 u8 eq_cmd; 7097 int ret; 7098 int i; 7099 7100 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET) 7101 return -EINVAL; 7102 7103 other_num = hr_dev->caps.num_other_vectors; 7104 comp_num = hr_dev->caps.num_comp_vectors; 7105 aeq_num = hr_dev->caps.num_aeq_vectors; 7106 7107 eq_num = comp_num + aeq_num; 7108 irq_num = eq_num + other_num; 7109 7110 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 7111 if (!eq_table->eq) 7112 return -ENOMEM; 7113 7114 /* create eq */ 7115 for (i = 0; i < eq_num; i++) { 7116 eq = &eq_table->eq[i]; 7117 eq->hr_dev = hr_dev; 7118 eq->eqn = i; 7119 if (i < comp_num) { 7120 /* CEQ */ 7121 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 7122 eq->type_flag = HNS_ROCE_CEQ; 7123 eq->entries = hr_dev->caps.ceqe_depth; 7124 eq->eqe_size = hr_dev->caps.ceqe_size; 7125 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 7126 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 7127 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 7128 } else { 7129 /* AEQ */ 7130 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 7131 eq->type_flag = HNS_ROCE_AEQ; 7132 eq->entries = hr_dev->caps.aeqe_depth; 7133 eq->eqe_size = hr_dev->caps.aeqe_size; 7134 eq->irq = hr_dev->irq[i - comp_num + other_num]; 7135 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 7136 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 7137 } 7138 7139 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 7140 if (ret) { 7141 dev_err(dev, "failed to create eq.\n"); 7142 goto err_create_eq_fail; 7143 } 7144 } 7145 7146 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 7147 7148 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 7149 WQ_MEM_RECLAIM); 7150 if (!hr_dev->irq_workq) { 7151 dev_err(dev, "failed to create irq workqueue.\n"); 7152 ret = -ENOMEM; 7153 goto err_create_eq_fail; 7154 } 7155 7156 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 7157 other_num); 7158 if (ret) { 7159 dev_err(dev, "failed to request irq.\n"); 7160 goto err_request_irq_fail; 7161 } 7162 7163 /* enable irq */ 7164 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 7165 7166 return 0; 7167 7168 err_request_irq_fail: 7169 destroy_workqueue(hr_dev->irq_workq); 7170 7171 err_create_eq_fail: 7172 for (i -= 1; i >= 0; i--) 7173 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 7174 kfree(eq_table->eq); 7175 7176 return ret; 7177 } 7178 7179 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 7180 { 7181 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 7182 int eq_num; 7183 int i; 7184 7185 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 7186 7187 /* Disable irq */ 7188 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 7189 7190 __hns_roce_free_irq(hr_dev); 7191 destroy_workqueue(hr_dev->irq_workq); 7192 7193 for (i = 0; i < eq_num; i++) 7194 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 7195 7196 kfree(eq_table->eq); 7197 } 7198 7199 static const struct ib_device_ops hns_roce_v2_dev_ops = { 7200 .destroy_qp = hns_roce_v2_destroy_qp, 7201 .modify_cq = hns_roce_v2_modify_cq, 7202 .poll_cq = hns_roce_v2_poll_cq, 7203 .post_recv = hns_roce_v2_post_recv, 7204 .post_send = hns_roce_v2_post_send, 7205 .query_qp = hns_roce_v2_query_qp, 7206 .req_notify_cq = hns_roce_v2_req_notify_cq, 7207 .drain_rq = hns_roce_v2_drain_rq, 7208 .drain_sq = hns_roce_v2_drain_sq, 7209 }; 7210 7211 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 7212 .modify_srq = hns_roce_v2_modify_srq, 7213 .post_srq_recv = hns_roce_v2_post_srq_recv, 7214 .query_srq = hns_roce_v2_query_srq, 7215 }; 7216 7217 static const struct hns_roce_hw hns_roce_hw_v2 = { 7218 .cmq_init = hns_roce_v2_cmq_init, 7219 .cmq_exit = hns_roce_v2_cmq_exit, 7220 .hw_profile = hns_roce_v2_profile, 7221 .hw_init = hns_roce_v2_init, 7222 .hw_exit = hns_roce_v2_exit, 7223 .post_mbox = v2_post_mbox, 7224 .poll_mbox_done = v2_poll_mbox_done, 7225 .chk_mbox_avail = v2_chk_mbox_is_avail, 7226 .set_gid = hns_roce_v2_set_gid, 7227 .set_mac = hns_roce_v2_set_mac, 7228 .write_mtpt = hns_roce_v2_write_mtpt, 7229 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 7230 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 7231 .write_cqc = hns_roce_v2_write_cqc, 7232 .set_hem = hns_roce_v2_set_hem, 7233 .clear_hem = hns_roce_v2_clear_hem, 7234 .modify_qp = hns_roce_v2_modify_qp, 7235 .dereg_mr = hns_roce_v2_dereg_mr, 7236 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 7237 .init_eq = hns_roce_v2_init_eq_table, 7238 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 7239 .write_srqc = hns_roce_v2_write_srqc, 7240 .query_cqc = hns_roce_v2_query_cqc, 7241 .query_qpc = hns_roce_v2_query_qpc, 7242 .query_mpt = hns_roce_v2_query_mpt, 7243 .query_srqc = hns_roce_v2_query_srqc, 7244 .query_sccc = hns_roce_v2_query_sccc, 7245 .query_hw_counter = hns_roce_hw_v2_query_counter, 7246 .get_dscp = hns_roce_hw_v2_get_dscp, 7247 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 7248 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 7249 }; 7250 7251 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 7252 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 7253 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 7254 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 7255 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 7256 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 7257 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 7258 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 7259 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 7260 /* required last entry */ 7261 {0, } 7262 }; 7263 7264 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 7265 7266 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 7267 struct hnae3_handle *handle) 7268 { 7269 struct hns_roce_v2_priv *priv = hr_dev->priv; 7270 const struct pci_device_id *id; 7271 int i; 7272 7273 hr_dev->pci_dev = handle->pdev; 7274 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 7275 hr_dev->is_vf = id->driver_data; 7276 hr_dev->dev = &handle->pdev->dev; 7277 hr_dev->hw = &hns_roce_hw_v2; 7278 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 7279 hr_dev->odb_offset = hr_dev->sdb_offset; 7280 7281 /* Get info from NIC driver. */ 7282 hr_dev->reg_base = handle->rinfo.roce_io_base; 7283 hr_dev->mem_base = handle->rinfo.roce_mem_base; 7284 hr_dev->caps.num_ports = 1; 7285 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 7286 hr_dev->iboe.phy_port[0] = 0; 7287 7288 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 7289 hr_dev->iboe.netdevs[0]->dev_addr); 7290 7291 for (i = 0; i < handle->rinfo.num_vectors; i++) 7292 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 7293 i + handle->rinfo.base_vector); 7294 7295 /* cmd issue mode: 0 is poll, 1 is event */ 7296 hr_dev->cmd_mod = 1; 7297 hr_dev->loop_idc = 0; 7298 7299 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 7300 priv->handle = handle; 7301 } 7302 7303 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7304 { 7305 struct hns_roce_dev *hr_dev; 7306 int ret; 7307 7308 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 7309 if (!hr_dev) 7310 return -ENOMEM; 7311 7312 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 7313 if (!hr_dev->priv) { 7314 ret = -ENOMEM; 7315 goto error_failed_kzalloc; 7316 } 7317 7318 hns_roce_hw_v2_get_cfg(hr_dev, handle); 7319 7320 ret = hns_roce_init(hr_dev); 7321 if (ret) { 7322 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 7323 goto error_failed_roce_init; 7324 } 7325 7326 handle->priv = hr_dev; 7327 7328 return 0; 7329 7330 error_failed_roce_init: 7331 kfree(hr_dev->priv); 7332 7333 error_failed_kzalloc: 7334 ib_dealloc_device(&hr_dev->ib_dev); 7335 7336 return ret; 7337 } 7338 7339 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7340 bool reset, bool bond_cleanup) 7341 { 7342 struct hns_roce_dev *hr_dev = handle->priv; 7343 7344 if (!hr_dev) 7345 return; 7346 7347 handle->priv = NULL; 7348 7349 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 7350 hns_roce_handle_device_err(hr_dev); 7351 7352 hns_roce_exit(hr_dev, bond_cleanup); 7353 kfree(hr_dev->priv); 7354 ib_dealloc_device(&hr_dev->ib_dev); 7355 } 7356 7357 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 7358 { 7359 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 7360 const struct pci_device_id *id; 7361 struct device *dev = &handle->pdev->dev; 7362 int ret; 7363 7364 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 7365 7366 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 7367 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7368 goto reset_chk_err; 7369 } 7370 7371 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 7372 if (!id) 7373 return 0; 7374 7375 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 7376 return 0; 7377 7378 ret = __hns_roce_hw_v2_init_instance(handle); 7379 if (ret) { 7380 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7381 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 7382 if (ops->ae_dev_resetting(handle) || 7383 ops->get_hw_reset_stat(handle)) 7384 goto reset_chk_err; 7385 else 7386 return ret; 7387 } 7388 7389 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 7390 7391 return 0; 7392 7393 reset_chk_err: 7394 dev_err(dev, "Device is busy in resetting state.\n" 7395 "please retry later.\n"); 7396 7397 return -EBUSY; 7398 } 7399 7400 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 7401 bool reset) 7402 { 7403 /* Suspend bond to avoid concurrency */ 7404 hns_roce_bond_suspend(handle); 7405 7406 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7407 goto out; 7408 7409 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 7410 7411 __hns_roce_hw_v2_uninit_instance(handle, reset, true); 7412 7413 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7414 7415 out: 7416 hns_roce_bond_resume(handle); 7417 } 7418 7419 struct hns_roce_dev 7420 *hns_roce_bond_init_client(struct hns_roce_bond_group *bond_grp, 7421 int func_idx) 7422 { 7423 struct hnae3_handle *handle; 7424 int ret; 7425 7426 handle = bond_grp->bond_func_info[func_idx].handle; 7427 if (!handle || !handle->client) 7428 return NULL; 7429 7430 ret = hns_roce_hw_v2_init_instance(handle); 7431 if (ret) 7432 return NULL; 7433 7434 return handle->priv; 7435 } 7436 7437 void hns_roce_bond_uninit_client(struct hns_roce_bond_group *bond_grp, 7438 int func_idx) 7439 { 7440 struct hnae3_handle *handle = bond_grp->bond_func_info[func_idx].handle; 7441 7442 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 7443 return; 7444 7445 handle->rinfo.instance_state = HNS_ROCE_STATE_BOND_UNINIT; 7446 7447 __hns_roce_hw_v2_uninit_instance(handle, false, false); 7448 7449 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 7450 } 7451 7452 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 7453 { 7454 struct hns_roce_dev *hr_dev; 7455 7456 /* Suspend bond to avoid concurrency */ 7457 hns_roce_bond_suspend(handle); 7458 7459 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 7460 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7461 return 0; 7462 } 7463 7464 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 7465 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 7466 7467 hr_dev = handle->priv; 7468 if (!hr_dev) 7469 return 0; 7470 7471 hr_dev->active = false; 7472 hr_dev->dis_db = true; 7473 7474 rdma_user_mmap_disassociate(&hr_dev->ib_dev); 7475 7476 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 7477 7478 return 0; 7479 } 7480 7481 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 7482 { 7483 struct device *dev = &handle->pdev->dev; 7484 int ret; 7485 7486 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 7487 &handle->rinfo.state)) { 7488 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7489 hns_roce_bond_resume(handle); 7490 return 0; 7491 } 7492 7493 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 7494 7495 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 7496 ret = __hns_roce_hw_v2_init_instance(handle); 7497 if (ret) { 7498 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 7499 * callback function, RoCE Engine reinitialize. If RoCE reinit 7500 * failed, we should inform NIC driver. 7501 */ 7502 handle->priv = NULL; 7503 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 7504 } else { 7505 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 7506 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 7507 } 7508 7509 hns_roce_bond_resume(handle); 7510 return ret; 7511 } 7512 7513 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 7514 { 7515 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 7516 return 0; 7517 7518 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 7519 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 7520 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 7521 __hns_roce_hw_v2_uninit_instance(handle, false, false); 7522 7523 return 0; 7524 } 7525 7526 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 7527 enum hnae3_reset_notify_type type) 7528 { 7529 int ret = 0; 7530 7531 switch (type) { 7532 case HNAE3_DOWN_CLIENT: 7533 ret = hns_roce_hw_v2_reset_notify_down(handle); 7534 break; 7535 case HNAE3_INIT_CLIENT: 7536 ret = hns_roce_hw_v2_reset_notify_init(handle); 7537 break; 7538 case HNAE3_UNINIT_CLIENT: 7539 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 7540 break; 7541 default: 7542 break; 7543 } 7544 7545 return ret; 7546 } 7547 7548 static void hns_roce_hw_v2_link_status_change(struct hnae3_handle *handle, 7549 bool linkup) 7550 { 7551 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 7552 struct net_device *netdev = handle->rinfo.netdev; 7553 7554 if (linkup || !hr_dev) 7555 return; 7556 7557 /* For bond device, the link status depends on the upper netdev, 7558 * and the upper device's link status depends on all the slaves' 7559 * netdev but not only one. So bond device cannot get a correct 7560 * link status from this path. 7561 */ 7562 if (hns_roce_get_bond_grp(netdev, get_hr_bus_num(hr_dev))) 7563 return; 7564 7565 ib_dispatch_port_state_event(&hr_dev->ib_dev, netdev); 7566 } 7567 7568 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7569 .init_instance = hns_roce_hw_v2_init_instance, 7570 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7571 .link_status_change = hns_roce_hw_v2_link_status_change, 7572 .reset_notify = hns_roce_hw_v2_reset_notify, 7573 }; 7574 7575 static struct hnae3_client hns_roce_hw_v2_client = { 7576 .name = "hns_roce_hw_v2", 7577 .type = HNAE3_CLIENT_ROCE, 7578 .ops = &hns_roce_hw_v2_ops, 7579 }; 7580 7581 static int __init hns_roce_hw_v2_init(void) 7582 { 7583 hns_roce_init_debugfs(); 7584 return hnae3_register_client(&hns_roce_hw_v2_client); 7585 } 7586 7587 static void __exit hns_roce_hw_v2_exit(void) 7588 { 7589 hns_roce_dealloc_bond_grp(); 7590 hnae3_unregister_client(&hns_roce_hw_v2_client); 7591 hns_roce_cleanup_debugfs(); 7592 } 7593 7594 module_init(hns_roce_hw_v2_init); 7595 module_exit(hns_roce_hw_v2_exit); 7596 7597 MODULE_LICENSE("Dual BSD/GPL"); 7598 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 7599 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 7600 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 7601 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 7602