1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MHI PCI driver - MHI over PCI controller driver
4 *
5 * This module is a generic driver for registering MHI-over-PCI devices,
6 * such as PCIe QCOM modems.
7 *
8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/mhi.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/timer.h>
18 #include <linux/workqueue.h>
19
20 #define MHI_PCI_DEFAULT_BAR_NUM 0
21
22 #define MHI_POST_RESET_DELAY_MS 2000
23
24 #define HEALTH_CHECK_PERIOD (HZ * 2)
25
26 /* PCI VID definitions */
27 #define PCI_VENDOR_ID_THALES 0x1269
28 #define PCI_VENDOR_ID_QUECTEL 0x1eac
29 #define PCI_VENDOR_ID_NETPRISMA 0x203e
30
31 #define MHI_EDL_DB 91
32 #define MHI_EDL_COOKIE 0xEDEDEDED
33
34 /**
35 * struct mhi_pci_dev_info - MHI PCI device specific information
36 * @config: MHI controller configuration
37 * @name: name of the PCI module
38 * @fw: firmware path (if any)
39 * @edl: emergency download mode firmware path (if any)
40 * @edl_trigger: capable of triggering EDL mode in the device (if supported)
41 * @bar_num: PCI base address register to use for MHI MMIO register space
42 * @dma_data_width: DMA transfer word size (32 or 64 bits)
43 * @mru_default: default MRU size for MBIM network packets
44 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
45 * of inband wake support (such as sdx24)
46 * @no_m3: M3 not supported
47 */
48 struct mhi_pci_dev_info {
49 const struct mhi_controller_config *config;
50 const char *name;
51 const char *fw;
52 const char *edl;
53 bool edl_trigger;
54 unsigned int bar_num;
55 unsigned int dma_data_width;
56 unsigned int mru_default;
57 bool sideband_wake;
58 bool no_m3;
59 };
60
61 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
62 { \
63 .num = ch_num, \
64 .name = ch_name, \
65 .num_elements = el_count, \
66 .event_ring = ev_ring, \
67 .dir = DMA_TO_DEVICE, \
68 .ee_mask = BIT(MHI_EE_AMSS), \
69 .pollcfg = 0, \
70 .doorbell = MHI_DB_BRST_DISABLE, \
71 .lpm_notify = false, \
72 .offload_channel = false, \
73 .doorbell_mode_switch = false, \
74 } \
75
76 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
77 { \
78 .num = ch_num, \
79 .name = ch_name, \
80 .num_elements = el_count, \
81 .event_ring = ev_ring, \
82 .dir = DMA_FROM_DEVICE, \
83 .ee_mask = BIT(MHI_EE_AMSS), \
84 .pollcfg = 0, \
85 .doorbell = MHI_DB_BRST_DISABLE, \
86 .lpm_notify = false, \
87 .offload_channel = false, \
88 .doorbell_mode_switch = false, \
89 }
90
91 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
92 { \
93 .num = ch_num, \
94 .name = ch_name, \
95 .num_elements = el_count, \
96 .event_ring = ev_ring, \
97 .dir = DMA_FROM_DEVICE, \
98 .ee_mask = BIT(MHI_EE_AMSS), \
99 .pollcfg = 0, \
100 .doorbell = MHI_DB_BRST_DISABLE, \
101 .lpm_notify = false, \
102 .offload_channel = false, \
103 .doorbell_mode_switch = false, \
104 .auto_queue = true, \
105 }
106
107 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
108 { \
109 .num_elements = el_count, \
110 .irq_moderation_ms = 0, \
111 .irq = (ev_ring) + 1, \
112 .priority = 1, \
113 .mode = MHI_DB_BRST_DISABLE, \
114 .data_type = MHI_ER_CTRL, \
115 .hardware_event = false, \
116 .client_managed = false, \
117 .offload_channel = false, \
118 }
119
120 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \
121 { \
122 .num = ch_num, \
123 .name = ch_name, \
124 .num_elements = el_count, \
125 .event_ring = ev_ring, \
126 .dir = DMA_TO_DEVICE, \
127 .ee_mask = BIT(MHI_EE_AMSS), \
128 .pollcfg = 0, \
129 .doorbell = MHI_DB_BRST_ENABLE, \
130 .lpm_notify = false, \
131 .offload_channel = false, \
132 .doorbell_mode_switch = true, \
133 } \
134
135 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \
136 { \
137 .num = ch_num, \
138 .name = ch_name, \
139 .num_elements = el_count, \
140 .event_ring = ev_ring, \
141 .dir = DMA_FROM_DEVICE, \
142 .ee_mask = BIT(MHI_EE_AMSS), \
143 .pollcfg = 0, \
144 .doorbell = MHI_DB_BRST_ENABLE, \
145 .lpm_notify = false, \
146 .offload_channel = false, \
147 .doorbell_mode_switch = true, \
148 }
149
150 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
151 { \
152 .num = ch_num, \
153 .name = ch_name, \
154 .num_elements = el_count, \
155 .event_ring = ev_ring, \
156 .dir = DMA_TO_DEVICE, \
157 .ee_mask = BIT(MHI_EE_SBL), \
158 .pollcfg = 0, \
159 .doorbell = MHI_DB_BRST_DISABLE, \
160 .lpm_notify = false, \
161 .offload_channel = false, \
162 .doorbell_mode_switch = false, \
163 } \
164
165 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
166 { \
167 .num = ch_num, \
168 .name = ch_name, \
169 .num_elements = el_count, \
170 .event_ring = ev_ring, \
171 .dir = DMA_FROM_DEVICE, \
172 .ee_mask = BIT(MHI_EE_SBL), \
173 .pollcfg = 0, \
174 .doorbell = MHI_DB_BRST_DISABLE, \
175 .lpm_notify = false, \
176 .offload_channel = false, \
177 .doorbell_mode_switch = false, \
178 }
179
180 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \
181 { \
182 .num = ch_num, \
183 .name = ch_name, \
184 .num_elements = el_count, \
185 .event_ring = ev_ring, \
186 .dir = DMA_TO_DEVICE, \
187 .ee_mask = BIT(MHI_EE_FP), \
188 .pollcfg = 0, \
189 .doorbell = MHI_DB_BRST_DISABLE, \
190 .lpm_notify = false, \
191 .offload_channel = false, \
192 .doorbell_mode_switch = false, \
193 } \
194
195 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \
196 { \
197 .num = ch_num, \
198 .name = ch_name, \
199 .num_elements = el_count, \
200 .event_ring = ev_ring, \
201 .dir = DMA_FROM_DEVICE, \
202 .ee_mask = BIT(MHI_EE_FP), \
203 .pollcfg = 0, \
204 .doorbell = MHI_DB_BRST_DISABLE, \
205 .lpm_notify = false, \
206 .offload_channel = false, \
207 .doorbell_mode_switch = false, \
208 }
209
210 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
211 { \
212 .num_elements = el_count, \
213 .irq_moderation_ms = 5, \
214 .irq = (ev_ring) + 1, \
215 .priority = 1, \
216 .mode = MHI_DB_BRST_DISABLE, \
217 .data_type = MHI_ER_DATA, \
218 .hardware_event = false, \
219 .client_managed = false, \
220 .offload_channel = false, \
221 }
222
223 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \
224 { \
225 .num_elements = el_count, \
226 .irq_moderation_ms = 0, \
227 .irq = (ev_ring) + 1, \
228 .priority = 1, \
229 .mode = MHI_DB_BRST_DISABLE, \
230 .data_type = MHI_ER_DATA, \
231 .hardware_event = false, \
232 .client_managed = false, \
233 .offload_channel = false, \
234 }
235
236 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
237 { \
238 .num_elements = el_count, \
239 .irq_moderation_ms = 1, \
240 .irq = (ev_ring) + 1, \
241 .priority = 1, \
242 .mode = MHI_DB_BRST_DISABLE, \
243 .data_type = MHI_ER_DATA, \
244 .hardware_event = true, \
245 .client_managed = false, \
246 .offload_channel = false, \
247 .channel = ch_num, \
248 }
249
250 static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
251 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2),
252 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2),
253 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1),
254 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1),
255 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3),
256 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3),
257 MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3),
258 MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4),
259 MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4),
260 MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4),
261 MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4),
262 MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4),
263 MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4),
264 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5),
265 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5),
266 };
267
268 static struct mhi_event_config mhi_qcom_qdu100_events[] = {
269 /* first ring is control+data ring */
270 MHI_EVENT_CONFIG_CTRL(0, 64),
271 /* SAHARA dedicated event ring */
272 MHI_EVENT_CONFIG_SW_DATA(1, 256),
273 /* Software channels dedicated event ring */
274 MHI_EVENT_CONFIG_SW_DATA(2, 64),
275 MHI_EVENT_CONFIG_SW_DATA(3, 256),
276 MHI_EVENT_CONFIG_SW_DATA(4, 256),
277 /* Software IP channels dedicated event ring */
278 MHI_EVENT_CONFIG_SW_DATA(5, 512),
279 MHI_EVENT_CONFIG_SW_DATA(6, 512),
280 MHI_EVENT_CONFIG_SW_DATA(7, 512),
281 };
282
283 static const struct mhi_controller_config mhi_qcom_qdu100_config = {
284 .max_channels = 128,
285 .timeout_ms = 120000,
286 .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels),
287 .ch_cfg = mhi_qcom_qdu100_channels,
288 .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events),
289 .event_cfg = mhi_qcom_qdu100_events,
290 };
291
292 static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
293 .name = "qcom-qdu100",
294 .fw = "qcom/qdu100/xbl_s.melf",
295 .edl_trigger = true,
296 .config = &mhi_qcom_qdu100_config,
297 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
298 .dma_data_width = 32,
299 .sideband_wake = false,
300 .no_m3 = true,
301 };
302
303 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = {
304 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1),
305 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2),
306 };
307
308 static struct mhi_event_config mhi_qcom_sa8775p_events[] = {
309 /* first ring is control+data ring */
310 MHI_EVENT_CONFIG_CTRL(0, 64),
311 /* Software channels dedicated event ring */
312 MHI_EVENT_CONFIG_SW_DATA(1, 64),
313 MHI_EVENT_CONFIG_SW_DATA(2, 64),
314 };
315
316 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
317 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
318 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
319 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
320 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
321 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
322 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
323 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
324 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
325 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
326 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
327 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2),
328 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3),
329 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4),
330 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5),
331 };
332
333 static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
334 /* first ring is control+data ring */
335 MHI_EVENT_CONFIG_CTRL(0, 64),
336 /* DIAG dedicated event ring */
337 MHI_EVENT_CONFIG_DATA(1, 128),
338 /* Software channels dedicated event ring */
339 MHI_EVENT_CONFIG_SW_DATA(2, 64),
340 MHI_EVENT_CONFIG_SW_DATA(3, 64),
341 /* Hardware channels request dedicated hardware event rings */
342 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100),
343 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101)
344 };
345
346 static const struct mhi_controller_config mhi_qcom_sa8775p_config = {
347 .max_channels = 128,
348 .timeout_ms = 8000,
349 .num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels),
350 .ch_cfg = mhi_qcom_sa8775p_channels,
351 .num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events),
352 .event_cfg = mhi_qcom_sa8775p_events,
353 };
354
355 static const struct mhi_controller_config modem_qcom_v2_mhiv_config = {
356 .max_channels = 128,
357 .timeout_ms = 8000,
358 .ready_timeout_ms = 50000,
359 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
360 .ch_cfg = modem_qcom_v1_mhi_channels,
361 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
362 .event_cfg = modem_qcom_v1_mhi_events,
363 };
364
365 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
366 .max_channels = 128,
367 .timeout_ms = 8000,
368 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
369 .ch_cfg = modem_qcom_v1_mhi_channels,
370 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
371 .event_cfg = modem_qcom_v1_mhi_events,
372 };
373
374 static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = {
375 .name = "qcom-sa8775p",
376 .edl_trigger = false,
377 .config = &mhi_qcom_sa8775p_config,
378 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
379 .dma_data_width = 32,
380 .mru_default = 32768,
381 .sideband_wake = false,
382 };
383
384 static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = {
385 .name = "qcom-sdx75m",
386 .fw = "qcom/sdx75m/xbl.elf",
387 .edl = "qcom/sdx75m/edl.mbn",
388 .edl_trigger = true,
389 .config = &modem_qcom_v2_mhiv_config,
390 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
391 .dma_data_width = 32,
392 .sideband_wake = false,
393 };
394
395 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
396 .name = "qcom-sdx65m",
397 .fw = "qcom/sdx65m/xbl.elf",
398 .edl = "qcom/sdx65m/edl.mbn",
399 .edl_trigger = true,
400 .config = &modem_qcom_v1_mhiv_config,
401 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
402 .dma_data_width = 32,
403 .sideband_wake = false,
404 };
405
406 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
407 .name = "qcom-sdx55m",
408 .fw = "qcom/sdx55m/sbl1.mbn",
409 .edl = "qcom/sdx55m/edl.mbn",
410 .edl_trigger = true,
411 .config = &modem_qcom_v1_mhiv_config,
412 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
413 .dma_data_width = 32,
414 .mru_default = 32768,
415 .sideband_wake = false,
416 };
417
418 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
419 .name = "qcom-sdx24",
420 .edl = "qcom/prog_firehose_sdx24.mbn",
421 .config = &modem_qcom_v1_mhiv_config,
422 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
423 .dma_data_width = 32,
424 .sideband_wake = true,
425 };
426
427 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
428 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
429 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
430 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
431 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
432 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
433 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
434 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
435 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
436 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
437 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
438 /* The EDL firmware is a flash-programmer exposing firehose protocol */
439 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
440 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
441 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
442 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
443 };
444
445 static struct mhi_event_config mhi_quectel_em1xx_events[] = {
446 MHI_EVENT_CONFIG_CTRL(0, 128),
447 MHI_EVENT_CONFIG_DATA(1, 128),
448 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
449 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
450 };
451
452 static const struct mhi_controller_config modem_quectel_em1xx_config = {
453 .max_channels = 128,
454 .timeout_ms = 20000,
455 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
456 .ch_cfg = mhi_quectel_em1xx_channels,
457 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
458 .event_cfg = mhi_quectel_em1xx_events,
459 };
460
461 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
462 .name = "quectel-em1xx",
463 .edl = "qcom/prog_firehose_sdx24.mbn",
464 .config = &modem_quectel_em1xx_config,
465 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
466 .dma_data_width = 32,
467 .mru_default = 32768,
468 .sideband_wake = true,
469 };
470
471 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = {
472 .name = "quectel-rm5xx",
473 .edl = "qcom/prog_firehose_sdx6x.elf",
474 .config = &modem_quectel_em1xx_config,
475 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
476 .dma_data_width = 32,
477 .mru_default = 32768,
478 .sideband_wake = true,
479 };
480
481 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
482 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
483 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
484 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
485 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
486 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
487 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
488 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
489 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
490 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
491 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
492 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
493 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
494 };
495
496 static const struct mhi_channel_config mhi_foxconn_sdx61_channels[] = {
497 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
498 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
499 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
500 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
501 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
502 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
503 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
504 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
505 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
506 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
507 MHI_CHANNEL_CONFIG_UL(50, "NMEA", 32, 0),
508 MHI_CHANNEL_CONFIG_DL(51, "NMEA", 32, 0),
509 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
510 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
511 };
512
513 static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
514 MHI_EVENT_CONFIG_CTRL(0, 128),
515 MHI_EVENT_CONFIG_DATA(1, 128),
516 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
517 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
518 };
519
520 static const struct mhi_controller_config modem_foxconn_sdx55_config = {
521 .max_channels = 128,
522 .timeout_ms = 20000,
523 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
524 .ch_cfg = mhi_foxconn_sdx55_channels,
525 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
526 .event_cfg = mhi_foxconn_sdx55_events,
527 };
528
529 static const struct mhi_controller_config modem_foxconn_sdx61_config = {
530 .max_channels = 128,
531 .timeout_ms = 20000,
532 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx61_channels),
533 .ch_cfg = mhi_foxconn_sdx61_channels,
534 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
535 .event_cfg = mhi_foxconn_sdx55_events,
536 };
537
538 static const struct mhi_controller_config modem_foxconn_sdx72_config = {
539 .max_channels = 128,
540 .timeout_ms = 20000,
541 .ready_timeout_ms = 50000,
542 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
543 .ch_cfg = mhi_foxconn_sdx55_channels,
544 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
545 .event_cfg = mhi_foxconn_sdx55_events,
546 };
547
548 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
549 .name = "foxconn-sdx55",
550 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn",
551 .edl_trigger = true,
552 .config = &modem_foxconn_sdx55_config,
553 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
554 .dma_data_width = 32,
555 .mru_default = 32768,
556 .sideband_wake = false,
557 };
558
559 static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = {
560 .name = "foxconn-t99w175",
561 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn",
562 .edl_trigger = true,
563 .config = &modem_foxconn_sdx55_config,
564 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
565 .dma_data_width = 32,
566 .mru_default = 32768,
567 .sideband_wake = false,
568 };
569
570 static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = {
571 .name = "foxconn-dw5930e",
572 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn",
573 .edl_trigger = true,
574 .config = &modem_foxconn_sdx55_config,
575 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
576 .dma_data_width = 32,
577 .mru_default = 32768,
578 .sideband_wake = false,
579 };
580
581 static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = {
582 .name = "foxconn-t99w368",
583 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf",
584 .edl_trigger = true,
585 .config = &modem_foxconn_sdx55_config,
586 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
587 .dma_data_width = 32,
588 .mru_default = 32768,
589 .sideband_wake = false,
590 };
591
592 static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = {
593 .name = "foxconn-t99w373",
594 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf",
595 .edl_trigger = true,
596 .config = &modem_foxconn_sdx55_config,
597 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
598 .dma_data_width = 32,
599 .mru_default = 32768,
600 .sideband_wake = false,
601 };
602
603 static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = {
604 .name = "foxconn-t99w510",
605 .edl = "qcom/sdx24m/foxconn/prog_firehose_sdx24.mbn",
606 .edl_trigger = true,
607 .config = &modem_foxconn_sdx55_config,
608 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
609 .dma_data_width = 32,
610 .mru_default = 32768,
611 .sideband_wake = false,
612 };
613
614 static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = {
615 .name = "foxconn-dw5932e",
616 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf",
617 .edl_trigger = true,
618 .config = &modem_foxconn_sdx55_config,
619 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
620 .dma_data_width = 32,
621 .mru_default = 32768,
622 .sideband_wake = false,
623 };
624
625 static const struct mhi_pci_dev_info mhi_foxconn_t99w640_info = {
626 .name = "foxconn-t99w640",
627 .edl = "qcom/sdx72m/foxconn/edl.mbn",
628 .edl_trigger = true,
629 .config = &modem_foxconn_sdx72_config,
630 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
631 .dma_data_width = 32,
632 .mru_default = 32768,
633 .sideband_wake = false,
634 };
635
636 static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = {
637 .name = "foxconn-dw5934e",
638 .edl = "qcom/sdx72m/foxconn/edl.mbn",
639 .edl_trigger = true,
640 .config = &modem_foxconn_sdx72_config,
641 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
642 .dma_data_width = 32,
643 .mru_default = 32768,
644 .sideband_wake = false,
645 };
646
647 static const struct mhi_pci_dev_info mhi_foxconn_t99w696_info = {
648 .name = "foxconn-t99w696",
649 .edl = "qcom/sdx61/foxconn/prog_firehose_lite.elf",
650 .edl_trigger = true,
651 .config = &modem_foxconn_sdx61_config,
652 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
653 .dma_data_width = 32,
654 .mru_default = 32768,
655 .sideband_wake = false,
656 };
657
658 static const struct mhi_channel_config mhi_mv3x_channels[] = {
659 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0),
660 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0),
661 /* MBIM Control Channel */
662 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0),
663 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0),
664 /* MBIM Data Channel */
665 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2),
666 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3),
667 };
668
669 static struct mhi_event_config mhi_mv3x_events[] = {
670 MHI_EVENT_CONFIG_CTRL(0, 256),
671 MHI_EVENT_CONFIG_DATA(1, 256),
672 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
673 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101),
674 };
675
676 static const struct mhi_controller_config modem_mv3x_config = {
677 .max_channels = 128,
678 .timeout_ms = 20000,
679 .num_channels = ARRAY_SIZE(mhi_mv3x_channels),
680 .ch_cfg = mhi_mv3x_channels,
681 .num_events = ARRAY_SIZE(mhi_mv3x_events),
682 .event_cfg = mhi_mv3x_events,
683 };
684
685 static const struct mhi_pci_dev_info mhi_mv31_info = {
686 .name = "cinterion-mv31",
687 .config = &modem_mv3x_config,
688 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
689 .dma_data_width = 32,
690 .mru_default = 32768,
691 };
692
693 static const struct mhi_pci_dev_info mhi_mv32_info = {
694 .name = "cinterion-mv32",
695 .config = &modem_mv3x_config,
696 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
697 .dma_data_width = 32,
698 .mru_default = 32768,
699 };
700
701 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = {
702 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
703 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0),
704 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0),
705 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0),
706 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0),
707 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0),
708 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
709 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
710 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
711 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
712 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1),
713 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2),
714 };
715
716 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = {
717 /* first ring is control+data and DIAG ring */
718 MHI_EVENT_CONFIG_CTRL(0, 2048),
719 /* Hardware channels request dedicated hardware event rings */
720 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100),
721 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101)
722 };
723
724 static const struct mhi_controller_config modem_sierra_em919x_config = {
725 .max_channels = 128,
726 .timeout_ms = 24000,
727 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels),
728 .ch_cfg = mhi_sierra_em919x_channels,
729 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events),
730 .event_cfg = modem_sierra_em919x_mhi_events,
731 };
732
733 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = {
734 .name = "sierra-em919x",
735 .config = &modem_sierra_em919x_config,
736 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
737 .dma_data_width = 32,
738 .mru_default = 32768,
739 .sideband_wake = false,
740 };
741
742 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = {
743 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
744 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
745 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0),
746 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0),
747 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1),
748 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2),
749 };
750
751 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = {
752 MHI_EVENT_CONFIG_CTRL(0, 128),
753 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100),
754 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101)
755 };
756
757 static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = {
758 .max_channels = 128,
759 .timeout_ms = 20000,
760 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels),
761 .ch_cfg = mhi_telit_fn980_hw_v1_channels,
762 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events),
763 .event_cfg = mhi_telit_fn980_hw_v1_events,
764 };
765
766 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = {
767 .name = "telit-fn980-hwv1",
768 .fw = "qcom/sdx55m/sbl1.mbn",
769 .edl = "qcom/sdx55m/edl.mbn",
770 .config = &modem_telit_fn980_hw_v1_config,
771 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
772 .dma_data_width = 32,
773 .mru_default = 32768,
774 .sideband_wake = false,
775 };
776
777 static const struct mhi_channel_config mhi_telit_fn990_channels[] = {
778 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
779 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
780 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1),
781 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1),
782 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
783 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
784 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
785 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
786 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1),
787 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1),
788 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
789 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
790 };
791
792 static struct mhi_event_config mhi_telit_fn990_events[] = {
793 MHI_EVENT_CONFIG_CTRL(0, 128),
794 MHI_EVENT_CONFIG_DATA(1, 128),
795 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
796 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
797 };
798
799 static const struct mhi_controller_config modem_telit_fn990_config = {
800 .max_channels = 128,
801 .timeout_ms = 20000,
802 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels),
803 .ch_cfg = mhi_telit_fn990_channels,
804 .num_events = ARRAY_SIZE(mhi_telit_fn990_events),
805 .event_cfg = mhi_telit_fn990_events,
806 };
807
808 static const struct mhi_pci_dev_info mhi_telit_fn990_info = {
809 .name = "telit-fn990",
810 .config = &modem_telit_fn990_config,
811 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
812 .dma_data_width = 32,
813 .sideband_wake = false,
814 .mru_default = 32768,
815 };
816
817 static const struct mhi_pci_dev_info mhi_telit_fe990a_info = {
818 .name = "telit-fe990a",
819 .config = &modem_telit_fn990_config,
820 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
821 .dma_data_width = 32,
822 .sideband_wake = false,
823 .mru_default = 32768,
824 };
825
826 static const struct mhi_channel_config mhi_telit_fn920c04_channels[] = {
827 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
828 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
829 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1),
830 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1),
831 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
832 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
833 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
834 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
835 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
836 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
837 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1),
838 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1),
839 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
840 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
841 };
842
843 static const struct mhi_controller_config modem_telit_fn920c04_config = {
844 .max_channels = 128,
845 .timeout_ms = 50000,
846 .num_channels = ARRAY_SIZE(mhi_telit_fn920c04_channels),
847 .ch_cfg = mhi_telit_fn920c04_channels,
848 .num_events = ARRAY_SIZE(mhi_telit_fn990_events),
849 .event_cfg = mhi_telit_fn990_events,
850 };
851
852 static const struct mhi_pci_dev_info mhi_telit_fn920c04_info = {
853 .name = "telit-fn920c04",
854 .config = &modem_telit_fn920c04_config,
855 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
856 .dma_data_width = 32,
857 .sideband_wake = false,
858 .mru_default = 32768,
859 .edl_trigger = true,
860 };
861
862 static const struct mhi_pci_dev_info mhi_telit_fn990b40_info = {
863 .name = "telit-fn990b40",
864 .config = &modem_telit_fn920c04_config,
865 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
866 .dma_data_width = 32,
867 .sideband_wake = false,
868 .mru_default = 32768,
869 .edl_trigger = true,
870 };
871
872 static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = {
873 .name = "netprisma-lcur57",
874 .edl = "qcom/prog_firehose_sdx24.mbn",
875 .config = &modem_quectel_em1xx_config,
876 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
877 .dma_data_width = 32,
878 .mru_default = 32768,
879 .sideband_wake = true,
880 };
881
882 static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = {
883 .name = "netprisma-fcun69",
884 .edl = "qcom/prog_firehose_sdx6x.elf",
885 .config = &modem_quectel_em1xx_config,
886 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
887 .dma_data_width = 32,
888 .mru_default = 32768,
889 .sideband_wake = true,
890 };
891
892 /* Keep the list sorted based on the PID. New VID should be added as the last entry */
893 static const struct pci_device_id mhi_pci_id_table[] = {
894 {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116),
895 .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info },
896 /* Telit FN920C04 (sdx35) */
897 {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020),
898 .driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info },
899 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
900 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
901 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c),
902 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
903 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */
904 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200),
905 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info },
906 /* EM929x (sdx65), use the same configuration as EM919x */
907 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x18d7, 0x0301),
908 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info },
909 /* Telit FN980 hardware revision v1 */
910 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000),
911 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info },
912 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
913 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
914 /* Telit FN990 */
915 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010),
916 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
917 /* Telit FE990A */
918 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015),
919 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info },
920 /* Foxconn T99W696.01, Lenovo Generic SKU */
921 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, 0xe142),
922 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info },
923 /* Foxconn T99W696.02, Lenovo X1 Carbon SKU */
924 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, 0xe143),
925 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info },
926 /* Foxconn T99W696.03, Lenovo X1 2in1 SKU */
927 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, 0xe144),
928 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info },
929 /* Foxconn T99W696.04, Lenovo PRC SKU */
930 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, 0xe145),
931 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info },
932 /* Foxconn T99W696.00, Foxconn SKU */
933 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, 0xe146),
934 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info },
935 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
936 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
937 /* Telit FN990B40 (sdx72) */
938 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x201a),
939 .driver_data = (kernel_ulong_t) &mhi_telit_fn990b40_info },
940 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309),
941 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info },
942 /* QDU100, x100-DU */
943 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601),
944 .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info },
945 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
946 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
947 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
948 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
949 /* RM520N-GL (sdx6x), eSIM */
950 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004),
951 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info },
952 /* RM520N-GL (sdx6x), Lenovo variant */
953 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007),
954 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info },
955 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */
956 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
957 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */
958 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
959 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
960 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
961 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info },
962 /* DW5930e (sdx55), With eSIM, It's also T99W175 */
963 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
964 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info },
965 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
966 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
967 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info },
968 /* T99W175 (sdx55), Based on Qualcomm new baseline */
969 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf),
970 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info },
971 /* T99W175 (sdx55) */
972 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3),
973 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info },
974 /* T99W368 (sdx65) */
975 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8),
976 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info },
977 /* T99W373 (sdx62) */
978 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9),
979 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info },
980 /* T99W510 (sdx24), variant 1 */
981 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0),
982 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info },
983 /* T99W510 (sdx24), variant 2 */
984 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1),
985 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info },
986 /* T99W510 (sdx24), variant 3 */
987 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2),
988 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info },
989 /* DW5932e-eSIM (sdx62), With eSIM */
990 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5),
991 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info },
992 /* DW5932e (sdx62), Non-eSIM */
993 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9),
994 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info },
995 /* T99W640 (sdx72) */
996 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118),
997 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w640_info },
998 /* DW5934e(sdx72), With eSIM */
999 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d),
1000 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info },
1001 /* DW5934e(sdx72), Non-eSIM */
1002 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e),
1003 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info },
1004 /* MV31-W (Cinterion) */
1005 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3),
1006 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
1007 /* MV31-W (Cinterion), based on new baseline */
1008 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4),
1009 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
1010 /* MV32-WA (Cinterion) */
1011 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba),
1012 .driver_data = (kernel_ulong_t) &mhi_mv32_info },
1013 /* MV32-WB (Cinterion) */
1014 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb),
1015 .driver_data = (kernel_ulong_t) &mhi_mv32_info },
1016 /* T99W175 (sdx55), HP variant */
1017 { PCI_DEVICE(0x03f0, 0x0a6c),
1018 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info },
1019 /* NETPRISMA LCUR57 (SDX24) */
1020 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1000),
1021 .driver_data = (kernel_ulong_t) &mhi_netprisma_lcur57_info },
1022 /* NETPRISMA FCUN69 (SDX6X) */
1023 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001),
1024 .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info },
1025 { }
1026 };
1027 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
1028
1029 enum mhi_pci_device_status {
1030 MHI_PCI_DEV_STARTED,
1031 MHI_PCI_DEV_SUSPENDED,
1032 };
1033
1034 struct mhi_pci_device {
1035 struct mhi_controller mhi_cntrl;
1036 struct pci_saved_state *pci_state;
1037 struct work_struct recovery_work;
1038 struct timer_list health_check_timer;
1039 unsigned long status;
1040 };
1041
mhi_pci_read_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 * out)1042 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
1043 void __iomem *addr, u32 *out)
1044 {
1045 *out = readl(addr);
1046 return 0;
1047 }
1048
mhi_pci_write_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 val)1049 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
1050 void __iomem *addr, u32 val)
1051 {
1052 writel(val, addr);
1053 }
1054
mhi_pci_status_cb(struct mhi_controller * mhi_cntrl,enum mhi_callback cb)1055 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
1056 enum mhi_callback cb)
1057 {
1058 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
1059
1060 /* Nothing to do for now */
1061 switch (cb) {
1062 case MHI_CB_FATAL_ERROR:
1063 case MHI_CB_SYS_ERROR:
1064 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);
1065 pm_runtime_forbid(&pdev->dev);
1066 break;
1067 case MHI_CB_EE_MISSION_MODE:
1068 pm_runtime_allow(&pdev->dev);
1069 break;
1070 default:
1071 break;
1072 }
1073 }
1074
mhi_pci_wake_get_nop(struct mhi_controller * mhi_cntrl,bool force)1075 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force)
1076 {
1077 /* no-op */
1078 }
1079
mhi_pci_wake_put_nop(struct mhi_controller * mhi_cntrl,bool override)1080 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override)
1081 {
1082 /* no-op */
1083 }
1084
mhi_pci_wake_toggle_nop(struct mhi_controller * mhi_cntrl)1085 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl)
1086 {
1087 /* no-op */
1088 }
1089
mhi_pci_is_alive(struct mhi_controller * mhi_cntrl)1090 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl)
1091 {
1092 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
1093 u16 vendor = 0;
1094
1095 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor))
1096 return false;
1097
1098 if (vendor == (u16) ~0 || vendor == 0)
1099 return false;
1100
1101 return true;
1102 }
1103
mhi_pci_claim(struct mhi_controller * mhi_cntrl,unsigned int bar_num,u64 dma_mask)1104 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
1105 unsigned int bar_num, u64 dma_mask)
1106 {
1107 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
1108 int err;
1109
1110 err = pcim_enable_device(pdev);
1111 if (err) {
1112 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
1113 return err;
1114 }
1115
1116 mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev));
1117 if (IS_ERR(mhi_cntrl->regs)) {
1118 err = PTR_ERR(mhi_cntrl->regs);
1119 dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
1120 return err;
1121 }
1122 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
1123
1124 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
1125 if (err) {
1126 dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
1127 return err;
1128 }
1129
1130 pci_set_master(pdev);
1131
1132 return 0;
1133 }
1134
mhi_pci_get_irqs(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * mhi_cntrl_config)1135 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
1136 const struct mhi_controller_config *mhi_cntrl_config)
1137 {
1138 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
1139 int nr_vectors, i;
1140 int *irq;
1141
1142 /*
1143 * Alloc one MSI vector for BHI + one vector per event ring, ideally...
1144 * No explicit pci_free_irq_vectors required, done by pcim_release.
1145 */
1146 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
1147
1148 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI);
1149 if (nr_vectors < 0) {
1150 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
1151 nr_vectors);
1152 return nr_vectors;
1153 }
1154
1155 if (nr_vectors < mhi_cntrl->nr_irqs) {
1156 dev_warn(&pdev->dev, "using shared MSI\n");
1157
1158 /* Patch msi vectors, use only one (shared) */
1159 for (i = 0; i < mhi_cntrl_config->num_events; i++)
1160 mhi_cntrl_config->event_cfg[i].irq = 0;
1161 mhi_cntrl->nr_irqs = 1;
1162 }
1163
1164 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
1165 if (!irq)
1166 return -ENOMEM;
1167
1168 for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
1169 int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
1170
1171 irq[i] = pci_irq_vector(pdev, vector);
1172 }
1173
1174 mhi_cntrl->irq = irq;
1175
1176 return 0;
1177 }
1178
mhi_pci_runtime_get(struct mhi_controller * mhi_cntrl)1179 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
1180 {
1181 /* The runtime_get() MHI callback means:
1182 * Do whatever is requested to leave M3.
1183 */
1184 return pm_runtime_get(mhi_cntrl->cntrl_dev);
1185 }
1186
mhi_pci_runtime_put(struct mhi_controller * mhi_cntrl)1187 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
1188 {
1189 /* The runtime_put() MHI callback means:
1190 * Device can be moved in M3 state.
1191 */
1192 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);
1193 pm_runtime_put(mhi_cntrl->cntrl_dev);
1194 }
1195
mhi_pci_recovery_work(struct work_struct * work)1196 static void mhi_pci_recovery_work(struct work_struct *work)
1197 {
1198 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device,
1199 recovery_work);
1200 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1201 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
1202 int err;
1203
1204 dev_warn(&pdev->dev, "device recovery started\n");
1205
1206 timer_delete(&mhi_pdev->health_check_timer);
1207 pm_runtime_forbid(&pdev->dev);
1208
1209 /* Clean up MHI state */
1210 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1211 mhi_power_down(mhi_cntrl, false);
1212 mhi_unprepare_after_power_down(mhi_cntrl);
1213 }
1214
1215 pci_set_power_state(pdev, PCI_D0);
1216 pci_load_saved_state(pdev, mhi_pdev->pci_state);
1217 pci_restore_state(pdev);
1218
1219 if (!mhi_pci_is_alive(mhi_cntrl))
1220 goto err_try_reset;
1221
1222 err = mhi_prepare_for_power_up(mhi_cntrl);
1223 if (err)
1224 goto err_try_reset;
1225
1226 err = mhi_sync_power_up(mhi_cntrl);
1227 if (err)
1228 goto err_unprepare;
1229
1230 dev_dbg(&pdev->dev, "Recovery completed\n");
1231
1232 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
1233 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1234 return;
1235
1236 err_unprepare:
1237 mhi_unprepare_after_power_down(mhi_cntrl);
1238 err_try_reset:
1239 err = pci_try_reset_function(pdev);
1240 if (err)
1241 dev_err(&pdev->dev, "Recovery failed: %d\n", err);
1242 }
1243
health_check(struct timer_list * t)1244 static void health_check(struct timer_list *t)
1245 {
1246 struct mhi_pci_device *mhi_pdev = timer_container_of(mhi_pdev, t,
1247 health_check_timer);
1248 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1249
1250 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1251 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
1252 return;
1253
1254 if (!mhi_pci_is_alive(mhi_cntrl)) {
1255 dev_err(mhi_cntrl->cntrl_dev, "Device died\n");
1256 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1257 return;
1258 }
1259
1260 /* reschedule in two seconds */
1261 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1262 }
1263
mhi_pci_generic_edl_trigger(struct mhi_controller * mhi_cntrl)1264 static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl)
1265 {
1266 void __iomem *base = mhi_cntrl->regs;
1267 void __iomem *edl_db;
1268 int ret;
1269 u32 val;
1270
1271 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev);
1272 if (ret) {
1273 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n");
1274 return ret;
1275 }
1276
1277 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0);
1278 mhi_cntrl->runtime_get(mhi_cntrl);
1279
1280 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val);
1281 if (ret)
1282 goto err_get_chdb;
1283
1284 edl_db = base + val + (8 * MHI_EDL_DB);
1285
1286 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE));
1287 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE));
1288
1289 mhi_soc_reset(mhi_cntrl);
1290
1291 err_get_chdb:
1292 mhi_cntrl->runtime_put(mhi_cntrl);
1293 mhi_device_put(mhi_cntrl->mhi_dev);
1294
1295 return ret;
1296 }
1297
mhi_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1298 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1299 {
1300 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
1301 const struct mhi_controller_config *mhi_cntrl_config;
1302 struct mhi_pci_device *mhi_pdev;
1303 struct mhi_controller *mhi_cntrl;
1304 int err;
1305
1306 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name);
1307
1308 /* mhi_pdev.mhi_cntrl must be zero-initialized */
1309 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);
1310 if (!mhi_pdev)
1311 return -ENOMEM;
1312
1313 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);
1314 timer_setup(&mhi_pdev->health_check_timer, health_check, 0);
1315
1316 mhi_cntrl_config = info->config;
1317 mhi_cntrl = &mhi_pdev->mhi_cntrl;
1318
1319 mhi_cntrl->cntrl_dev = &pdev->dev;
1320 mhi_cntrl->iova_start = 0;
1321 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);
1322 mhi_cntrl->fw_image = info->fw;
1323 mhi_cntrl->edl_image = info->edl;
1324
1325 mhi_cntrl->read_reg = mhi_pci_read_reg;
1326 mhi_cntrl->write_reg = mhi_pci_write_reg;
1327 mhi_cntrl->status_cb = mhi_pci_status_cb;
1328 mhi_cntrl->runtime_get = mhi_pci_runtime_get;
1329 mhi_cntrl->runtime_put = mhi_pci_runtime_put;
1330 mhi_cntrl->mru = info->mru_default;
1331 mhi_cntrl->name = info->name;
1332
1333 if (info->edl_trigger)
1334 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger;
1335
1336 if (info->sideband_wake) {
1337 mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
1338 mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
1339 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
1340 }
1341
1342 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
1343 if (err)
1344 return err;
1345
1346 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
1347 if (err)
1348 return err;
1349
1350 pci_set_drvdata(pdev, mhi_pdev);
1351
1352 /* Have stored pci confspace at hand for restore in sudden PCI error.
1353 * cache the state locally and discard the PCI core one.
1354 */
1355 pci_save_state(pdev);
1356 mhi_pdev->pci_state = pci_store_saved_state(pdev);
1357 pci_load_saved_state(pdev, NULL);
1358
1359 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
1360 if (err)
1361 return err;
1362
1363 /* MHI bus does not power up the controller by default */
1364 err = mhi_prepare_for_power_up(mhi_cntrl);
1365 if (err) {
1366 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
1367 goto err_unregister;
1368 }
1369
1370 err = mhi_sync_power_up(mhi_cntrl);
1371 if (err) {
1372 dev_err(&pdev->dev, "failed to power up MHI controller\n");
1373 goto err_unprepare;
1374 }
1375
1376 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
1377
1378 /* start health check */
1379 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1380
1381 /* Allow runtime suspend only if both PME from D3Hot and M3 are supported */
1382 if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) {
1383 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1384 pm_runtime_use_autosuspend(&pdev->dev);
1385 pm_runtime_mark_last_busy(&pdev->dev);
1386 pm_runtime_put_noidle(&pdev->dev);
1387 }
1388
1389 return 0;
1390
1391 err_unprepare:
1392 mhi_unprepare_after_power_down(mhi_cntrl);
1393 err_unregister:
1394 mhi_unregister_controller(mhi_cntrl);
1395
1396 return err;
1397 }
1398
mhi_pci_remove(struct pci_dev * pdev)1399 static void mhi_pci_remove(struct pci_dev *pdev)
1400 {
1401 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1402 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1403
1404 timer_delete_sync(&mhi_pdev->health_check_timer);
1405 cancel_work_sync(&mhi_pdev->recovery_work);
1406
1407 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1408 mhi_power_down(mhi_cntrl, true);
1409 mhi_unprepare_after_power_down(mhi_cntrl);
1410 }
1411
1412 /* balancing probe put_noidle */
1413 if (pci_pme_capable(pdev, PCI_D3hot))
1414 pm_runtime_get_noresume(&pdev->dev);
1415
1416 mhi_unregister_controller(mhi_cntrl);
1417 }
1418
mhi_pci_shutdown(struct pci_dev * pdev)1419 static void mhi_pci_shutdown(struct pci_dev *pdev)
1420 {
1421 mhi_pci_remove(pdev);
1422 pci_set_power_state(pdev, PCI_D3hot);
1423 }
1424
mhi_pci_reset_prepare(struct pci_dev * pdev)1425 static void mhi_pci_reset_prepare(struct pci_dev *pdev)
1426 {
1427 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1428 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1429
1430 dev_info(&pdev->dev, "reset\n");
1431
1432 timer_delete(&mhi_pdev->health_check_timer);
1433
1434 /* Clean up MHI state */
1435 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1436 mhi_power_down(mhi_cntrl, false);
1437 mhi_unprepare_after_power_down(mhi_cntrl);
1438 }
1439
1440 /* cause internal device reset */
1441 mhi_soc_reset(mhi_cntrl);
1442
1443 /* Be sure device reset has been executed */
1444 msleep(MHI_POST_RESET_DELAY_MS);
1445 }
1446
mhi_pci_reset_done(struct pci_dev * pdev)1447 static void mhi_pci_reset_done(struct pci_dev *pdev)
1448 {
1449 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1450 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1451 int err;
1452
1453 /* Restore initial known working PCI state */
1454 pci_load_saved_state(pdev, mhi_pdev->pci_state);
1455 pci_restore_state(pdev);
1456
1457 /* Is device status available ? */
1458 if (!mhi_pci_is_alive(mhi_cntrl)) {
1459 dev_err(&pdev->dev, "reset failed\n");
1460 return;
1461 }
1462
1463 err = mhi_prepare_for_power_up(mhi_cntrl);
1464 if (err) {
1465 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
1466 return;
1467 }
1468
1469 err = mhi_sync_power_up(mhi_cntrl);
1470 if (err) {
1471 dev_err(&pdev->dev, "failed to power up MHI controller\n");
1472 mhi_unprepare_after_power_down(mhi_cntrl);
1473 return;
1474 }
1475
1476 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
1477 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1478 }
1479
mhi_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)1480 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev,
1481 pci_channel_state_t state)
1482 {
1483 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1484 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1485
1486 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);
1487
1488 if (state == pci_channel_io_perm_failure)
1489 return PCI_ERS_RESULT_DISCONNECT;
1490
1491 /* Clean up MHI state */
1492 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1493 mhi_power_down(mhi_cntrl, false);
1494 mhi_unprepare_after_power_down(mhi_cntrl);
1495 } else {
1496 /* Nothing to do */
1497 return PCI_ERS_RESULT_RECOVERED;
1498 }
1499
1500 pci_disable_device(pdev);
1501
1502 return PCI_ERS_RESULT_NEED_RESET;
1503 }
1504
mhi_pci_slot_reset(struct pci_dev * pdev)1505 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev)
1506 {
1507 if (pci_enable_device(pdev)) {
1508 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
1509 return PCI_ERS_RESULT_DISCONNECT;
1510 }
1511
1512 return PCI_ERS_RESULT_RECOVERED;
1513 }
1514
mhi_pci_io_resume(struct pci_dev * pdev)1515 static void mhi_pci_io_resume(struct pci_dev *pdev)
1516 {
1517 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1518
1519 dev_err(&pdev->dev, "PCI slot reset done\n");
1520
1521 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1522 }
1523
1524 static const struct pci_error_handlers mhi_pci_err_handler = {
1525 .error_detected = mhi_pci_error_detected,
1526 .slot_reset = mhi_pci_slot_reset,
1527 .resume = mhi_pci_io_resume,
1528 .reset_prepare = mhi_pci_reset_prepare,
1529 .reset_done = mhi_pci_reset_done,
1530 };
1531
mhi_pci_runtime_suspend(struct device * dev)1532 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev)
1533 {
1534 struct pci_dev *pdev = to_pci_dev(dev);
1535 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1536 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1537 int err;
1538
1539 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
1540 return 0;
1541
1542 timer_delete(&mhi_pdev->health_check_timer);
1543 cancel_work_sync(&mhi_pdev->recovery_work);
1544
1545 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1546 mhi_cntrl->ee != MHI_EE_AMSS)
1547 goto pci_suspend; /* Nothing to do at MHI level */
1548
1549 /* Transition to M3 state */
1550 err = mhi_pm_suspend(mhi_cntrl);
1551 if (err) {
1552 dev_err(&pdev->dev, "failed to suspend device: %d\n", err);
1553 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);
1554 return -EBUSY;
1555 }
1556
1557 pci_suspend:
1558 pci_disable_device(pdev);
1559 pci_wake_from_d3(pdev, true);
1560
1561 return 0;
1562 }
1563
mhi_pci_runtime_resume(struct device * dev)1564 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev)
1565 {
1566 struct pci_dev *pdev = to_pci_dev(dev);
1567 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1568 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1569 int err;
1570
1571 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
1572 return 0;
1573
1574 err = pci_enable_device(pdev);
1575 if (err)
1576 goto err_recovery;
1577
1578 pci_set_master(pdev);
1579 pci_wake_from_d3(pdev, false);
1580
1581 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1582 mhi_cntrl->ee != MHI_EE_AMSS)
1583 return 0; /* Nothing to do at MHI level */
1584
1585 /* Exit M3, transition to M0 state */
1586 err = mhi_pm_resume(mhi_cntrl);
1587 if (err) {
1588 dev_err(&pdev->dev, "failed to resume device: %d\n", err);
1589 goto err_recovery;
1590 }
1591
1592 /* Resume health check */
1593 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1594
1595 /* It can be a remote wakeup (no mhi runtime_get), update access time */
1596 pm_runtime_mark_last_busy(dev);
1597
1598 return 0;
1599
1600 err_recovery:
1601 /* Do not fail to not mess up our PCI device state, the device likely
1602 * lost power (d3cold) and we simply need to reset it from the recovery
1603 * procedure, trigger the recovery asynchronously to prevent system
1604 * suspend exit delaying.
1605 */
1606 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1607 pm_runtime_mark_last_busy(dev);
1608
1609 return 0;
1610 }
1611
mhi_pci_suspend(struct device * dev)1612 static int __maybe_unused mhi_pci_suspend(struct device *dev)
1613 {
1614 pm_runtime_disable(dev);
1615 return mhi_pci_runtime_suspend(dev);
1616 }
1617
mhi_pci_resume(struct device * dev)1618 static int __maybe_unused mhi_pci_resume(struct device *dev)
1619 {
1620 int ret;
1621
1622 /* Depending the platform, device may have lost power (d3cold), we need
1623 * to resume it now to check its state and recover when necessary.
1624 */
1625 ret = mhi_pci_runtime_resume(dev);
1626 pm_runtime_enable(dev);
1627
1628 return ret;
1629 }
1630
mhi_pci_freeze(struct device * dev)1631 static int __maybe_unused mhi_pci_freeze(struct device *dev)
1632 {
1633 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1634 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1635
1636 /* We want to stop all operations, hibernation does not guarantee that
1637 * device will be in the same state as before freezing, especially if
1638 * the intermediate restore kernel reinitializes MHI device with new
1639 * context.
1640 */
1641 flush_work(&mhi_pdev->recovery_work);
1642 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1643 mhi_power_down(mhi_cntrl, true);
1644 mhi_unprepare_after_power_down(mhi_cntrl);
1645 }
1646
1647 return 0;
1648 }
1649
mhi_pci_restore(struct device * dev)1650 static int __maybe_unused mhi_pci_restore(struct device *dev)
1651 {
1652 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1653
1654 /* Reinitialize the device */
1655 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1656
1657 return 0;
1658 }
1659
1660 static const struct dev_pm_ops mhi_pci_pm_ops = {
1661 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
1662 #ifdef CONFIG_PM_SLEEP
1663 .suspend = mhi_pci_suspend,
1664 .resume = mhi_pci_resume,
1665 .freeze = mhi_pci_freeze,
1666 .thaw = mhi_pci_restore,
1667 .poweroff = mhi_pci_freeze,
1668 .restore = mhi_pci_restore,
1669 #endif
1670 };
1671
1672 static struct pci_driver mhi_pci_driver = {
1673 .name = "mhi-pci-generic",
1674 .id_table = mhi_pci_id_table,
1675 .probe = mhi_pci_probe,
1676 .remove = mhi_pci_remove,
1677 .shutdown = mhi_pci_shutdown,
1678 .err_handler = &mhi_pci_err_handler,
1679 .driver.pm = &mhi_pci_pm_ops
1680 };
1681 module_pci_driver(mhi_pci_driver);
1682
1683 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
1684 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
1685 MODULE_LICENSE("GPL");
1686