1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2010 Matt Turner. 4 * Copyright 2012 Red Hat 5 * 6 * Authors: Matthew Garrett 7 * Matt Turner 8 * Dave Airlie 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/iosys-map.h> 13 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_color_mgmt.h> 17 #include <drm/drm_damage_helper.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_format_helper.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_framebuffer.h> 22 #include <drm/drm_gem_atomic_helper.h> 23 #include <drm/drm_gem_framebuffer_helper.h> 24 #include <drm/drm_panic.h> 25 #include <drm/drm_print.h> 26 27 #include "mgag200_ddc.h" 28 #include "mgag200_drv.h" 29 30 /* 31 * This file contains setup code for the CRTC. 32 */ 33 34 static void mgag200_set_gamma_lut(struct drm_crtc *crtc, unsigned int index, 35 u16 red, u16 green, u16 blue) 36 { 37 struct drm_device *dev = crtc->dev; 38 struct mga_device *mdev = to_mga_device(dev); 39 u8 i8 = index & 0xff; 40 u8 r8 = red >> 8; 41 u8 g8 = green >> 8; 42 u8 b8 = blue >> 8; 43 44 if (drm_WARN_ON_ONCE(dev, index != i8)) 45 return; /* driver bug */ 46 47 WREG8(DAC_INDEX + MGA1064_INDEX, i8); 48 WREG8(DAC_INDEX + MGA1064_COL_PAL, r8); 49 WREG8(DAC_INDEX + MGA1064_COL_PAL, g8); 50 WREG8(DAC_INDEX + MGA1064_COL_PAL, b8); 51 } 52 53 void mgag200_crtc_fill_gamma(struct mga_device *mdev, 54 const struct drm_format_info *format) 55 { 56 struct drm_crtc *crtc = &mdev->crtc; 57 58 switch (format->format) { 59 case DRM_FORMAT_C8: 60 drm_crtc_fill_palette_8(crtc, mgag200_set_gamma_lut); 61 break; 62 case DRM_FORMAT_XRGB1555: 63 drm_crtc_fill_gamma_555(crtc, mgag200_set_gamma_lut); 64 break; 65 case DRM_FORMAT_RGB565: 66 drm_crtc_fill_gamma_565(crtc, mgag200_set_gamma_lut); 67 break; 68 case DRM_FORMAT_RGB888: 69 case DRM_FORMAT_XRGB8888: 70 drm_crtc_fill_gamma_888(crtc, mgag200_set_gamma_lut); 71 break; 72 default: 73 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 74 &format->format); 75 break; 76 } 77 } 78 79 void mgag200_crtc_load_gamma(struct mga_device *mdev, 80 const struct drm_format_info *format, 81 struct drm_color_lut *lut) 82 { 83 struct drm_crtc *crtc = &mdev->crtc; 84 85 switch (format->format) { 86 case DRM_FORMAT_C8: 87 drm_crtc_load_palette_8(crtc, lut, mgag200_set_gamma_lut); 88 break; 89 case DRM_FORMAT_XRGB1555: 90 drm_crtc_load_gamma_555_from_888(crtc, lut, mgag200_set_gamma_lut); 91 break; 92 case DRM_FORMAT_RGB565: 93 drm_crtc_load_gamma_565_from_888(crtc, lut, mgag200_set_gamma_lut); 94 break; 95 case DRM_FORMAT_RGB888: 96 case DRM_FORMAT_XRGB8888: 97 drm_crtc_load_gamma_888(crtc, lut, mgag200_set_gamma_lut); 98 break; 99 default: 100 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", 101 &format->format); 102 break; 103 } 104 } 105 106 static inline void mga_wait_vsync(struct mga_device *mdev) 107 { 108 unsigned long timeout = jiffies + HZ/10; 109 unsigned int status = 0; 110 111 do { 112 status = RREG32(MGAREG_STATUS); 113 } while ((status & 0x08) && time_before(jiffies, timeout)); 114 timeout = jiffies + HZ/10; 115 status = 0; 116 do { 117 status = RREG32(MGAREG_STATUS); 118 } while (!(status & 0x08) && time_before(jiffies, timeout)); 119 } 120 121 static inline void mga_wait_busy(struct mga_device *mdev) 122 { 123 unsigned long timeout = jiffies + HZ; 124 unsigned int status = 0; 125 do { 126 status = RREG8(MGAREG_STATUS + 2); 127 } while ((status & 0x01) && time_before(jiffies, timeout)); 128 } 129 130 /* 131 * This is how the framebuffer base address is stored in g200 cards: 132 * * Assume @offset is the gpu_addr variable of the framebuffer object 133 * * Then addr is the number of _pixels_ (not bytes) from the start of 134 * VRAM to the first pixel we want to display. (divided by 2 for 32bit 135 * framebuffers) 136 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers 137 * addr<20> -> CRTCEXT0<6> 138 * addr<19-16> -> CRTCEXT0<3-0> 139 * addr<15-8> -> CRTCC<7-0> 140 * addr<7-0> -> CRTCD<7-0> 141 * 142 * CRTCEXT0 has to be programmed last to trigger an update and make the 143 * new addr variable take effect. 144 */ 145 static void mgag200_set_startadd(struct mga_device *mdev, 146 unsigned long offset) 147 { 148 struct drm_device *dev = &mdev->base; 149 u32 startadd; 150 u8 crtcc, crtcd, crtcext0; 151 152 startadd = offset / 8; 153 154 if (startadd > 0) 155 drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd); 156 157 /* 158 * Can't store addresses any higher than that, but we also 159 * don't have more than 16 MiB of memory, so it should be fine. 160 */ 161 drm_WARN_ON(dev, startadd > 0x1fffff); 162 163 RREG_ECRT(0x00, crtcext0); 164 165 crtcc = (startadd >> 8) & 0xff; 166 crtcd = startadd & 0xff; 167 crtcext0 &= 0xb0; 168 crtcext0 |= ((startadd >> 14) & BIT(6)) | 169 ((startadd >> 16) & 0x0f); 170 171 WREG_CRT(0x0c, crtcc); 172 WREG_CRT(0x0d, crtcd); 173 WREG_ECRT(0x00, crtcext0); 174 } 175 176 /* 177 * Set the opmode for the hardware swapper for Big-Endian processor 178 * support for the frame buffer aperture and DMAWIN space. 179 */ 180 static void mgag200_set_datasiz(struct mga_device *mdev, u32 format) 181 { 182 #if defined(__BIG_ENDIAN) 183 u32 opmode = RREG32(MGAREG_OPMODE); 184 185 opmode &= ~(GENMASK(17, 16) | GENMASK(9, 8) | GENMASK(3, 2)); 186 187 /* Big-endian byte-swapping */ 188 switch (format) { 189 case DRM_FORMAT_XRGB1555: 190 case DRM_FORMAT_RGB565: 191 opmode |= 0x10100; 192 break; 193 case DRM_FORMAT_XRGB8888: 194 opmode |= 0x20200; 195 break; 196 } 197 WREG32(MGAREG_OPMODE, opmode); 198 #endif 199 } 200 201 void mgag200_init_registers(struct mga_device *mdev) 202 { 203 u8 crtc11, misc; 204 205 WREG_SEQ(2, 0x0f); 206 WREG_SEQ(3, 0x00); 207 WREG_SEQ(4, 0x0e); 208 209 WREG_CRT(10, 0); 210 WREG_CRT(11, 0); 211 WREG_CRT(12, 0); 212 WREG_CRT(13, 0); 213 WREG_CRT(14, 0); 214 WREG_CRT(15, 0); 215 216 RREG_CRT(0x11, crtc11); 217 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | 218 MGAREG_CRTC11_VINTEN | 219 MGAREG_CRTC11_VINTCLR); 220 WREG_CRT(0x11, crtc11); 221 222 misc = RREG8(MGA_MISC_IN); 223 misc |= MGAREG_MISC_IOADSEL; 224 WREG8(MGA_MISC_OUT, misc); 225 } 226 227 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode, 228 bool set_vidrst) 229 { 230 unsigned int hdispend, hsyncstr, hsyncend, htotal, hblkstr, hblkend; 231 unsigned int vdispend, vsyncstr, vsyncend, vtotal, vblkstr, vblkend; 232 unsigned int linecomp; 233 u8 misc, crtcext1, crtcext2, crtcext5; 234 235 hdispend = mode->crtc_hdisplay / 8 - 1; 236 hsyncstr = mode->crtc_hsync_start / 8 - 1; 237 hsyncend = mode->crtc_hsync_end / 8 - 1; 238 htotal = mode->crtc_htotal / 8 - 1; 239 /* Work around hardware quirk */ 240 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) 241 htotal++; 242 hblkstr = mode->crtc_hblank_start / 8 - 1; 243 hblkend = htotal; 244 245 vdispend = mode->crtc_vdisplay - 1; 246 vsyncstr = mode->crtc_vsync_start - 1; 247 vsyncend = mode->crtc_vsync_end - 1; 248 vtotal = mode->crtc_vtotal - 2; 249 vblkstr = mode->crtc_vblank_start - 1; 250 vblkend = vtotal + 1; 251 252 linecomp = vdispend; 253 254 misc = RREG8(MGA_MISC_IN); 255 256 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 257 misc |= MGAREG_MISC_HSYNCPOL; 258 else 259 misc &= ~MGAREG_MISC_HSYNCPOL; 260 261 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 262 misc |= MGAREG_MISC_VSYNCPOL; 263 else 264 misc &= ~MGAREG_MISC_VSYNCPOL; 265 266 crtcext1 = (((htotal - 4) & 0x100) >> 8) | 267 ((hblkstr & 0x100) >> 7) | 268 ((hsyncstr & 0x100) >> 6) | 269 (hblkend & 0x40); 270 if (set_vidrst) 271 crtcext1 |= MGAREG_CRTCEXT1_VRSTEN | 272 MGAREG_CRTCEXT1_HRSTEN; 273 274 crtcext2 = ((vtotal & 0xc00) >> 10) | 275 ((vdispend & 0x400) >> 8) | 276 ((vblkstr & 0xc00) >> 7) | 277 ((vsyncstr & 0xc00) >> 5) | 278 ((linecomp & 0x400) >> 3); 279 crtcext5 = 0x00; 280 281 WREG_CRT(0x00, htotal - 4); 282 WREG_CRT(0x01, hdispend); 283 WREG_CRT(0x02, hblkstr); 284 WREG_CRT(0x03, (hblkend & 0x1f) | 0x80); 285 WREG_CRT(0x04, hsyncstr); 286 WREG_CRT(0x05, ((hblkend & 0x20) << 2) | (hsyncend & 0x1f)); 287 WREG_CRT(0x06, vtotal & 0xff); 288 WREG_CRT(0x07, ((vtotal & 0x100) >> 8) | 289 ((vdispend & 0x100) >> 7) | 290 ((vsyncstr & 0x100) >> 6) | 291 ((vblkstr & 0x100) >> 5) | 292 ((linecomp & 0x100) >> 4) | 293 ((vtotal & 0x200) >> 4) | 294 ((vdispend & 0x200) >> 3) | 295 ((vsyncstr & 0x200) >> 2)); 296 WREG_CRT(0x09, ((vblkstr & 0x200) >> 4) | 297 ((linecomp & 0x200) >> 3)); 298 WREG_CRT(0x10, vsyncstr & 0xff); 299 WREG_CRT(0x11, (vsyncend & 0x0f) | 0x20); 300 WREG_CRT(0x12, vdispend & 0xff); 301 WREG_CRT(0x14, 0); 302 WREG_CRT(0x15, vblkstr & 0xff); 303 WREG_CRT(0x16, vblkend & 0xff); 304 WREG_CRT(0x17, 0xc3); 305 WREG_CRT(0x18, linecomp & 0xff); 306 307 WREG_ECRT(0x01, crtcext1); 308 WREG_ECRT(0x02, crtcext2); 309 WREG_ECRT(0x05, crtcext5); 310 311 WREG8(MGA_MISC_OUT, misc); 312 } 313 314 static void mgag200_set_offset(struct mga_device *mdev, 315 const struct drm_framebuffer *fb) 316 { 317 u8 crtc13, crtcext0; 318 u32 offset = fb->pitches[0] / 16; 319 320 RREG_ECRT(0, crtcext0); 321 322 crtc13 = offset & 0xff; 323 324 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK; 325 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK; 326 327 WREG_CRT(0x13, crtc13); 328 WREG_ECRT(0x00, crtcext0); 329 } 330 331 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format) 332 { 333 u8 xmulctrl = 0; 334 u8 crtcext3; 335 336 RREG_ECRT(3, crtcext3); 337 338 switch (format->format) { 339 case DRM_FORMAT_C8: 340 crtcext3 &= ~MGAREG_CRTCEXT3_SCALE_MASK; 341 crtcext3 |= 0x0; 342 break; 343 case DRM_FORMAT_XRGB1555: 344 case DRM_FORMAT_RGB565: 345 crtcext3 &= ~MGAREG_CRTCEXT3_SCALE_MASK; 346 crtcext3 |= 0x01; 347 break; 348 case DRM_FORMAT_RGB888: 349 crtcext3 &= ~MGAREG_CRTCEXT3_SCALE_MASK; 350 crtcext3 |= 0x02; 351 break; 352 case DRM_FORMAT_XRGB8888: 353 crtcext3 &= ~MGAREG_CRTCEXT3_SCALE_MASK; 354 crtcext3 |= 0x03; 355 break; 356 } 357 358 switch (format->format) { 359 case DRM_FORMAT_C8: 360 xmulctrl = MGA1064_MUL_CTL_8bits; 361 break; 362 case DRM_FORMAT_XRGB1555: 363 xmulctrl = MGA1064_MUL_CTL_15bits; 364 break; 365 case DRM_FORMAT_RGB565: 366 xmulctrl = MGA1064_MUL_CTL_16bits; 367 break; 368 case DRM_FORMAT_RGB888: 369 xmulctrl = MGA1064_MUL_CTL_24bits; 370 break; 371 case DRM_FORMAT_XRGB8888: 372 xmulctrl = MGA1064_MUL_CTL_32_24bits; 373 break; 374 } 375 376 WREG_DAC(MGA1064_MUL_CTL, xmulctrl); 377 378 WREG_GFX(0, 0x00); 379 WREG_GFX(1, 0x00); 380 WREG_GFX(2, 0x00); 381 WREG_GFX(3, 0x00); 382 WREG_GFX(4, 0x00); 383 WREG_GFX(5, 0x40); 384 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode), 385 * so that it doesn't hang when running kexec/kdump on G200_SE rev42. 386 */ 387 WREG_GFX(6, 0x0d); 388 WREG_GFX(7, 0x0f); 389 WREG_GFX(8, 0x0f); 390 391 WREG_ECRT(3, crtcext3); 392 } 393 394 void mgag200_enable_display(struct mga_device *mdev) 395 { 396 u8 seq0, crtcext1; 397 398 RREG_SEQ(0x00, seq0); 399 seq0 |= MGAREG_SEQ0_SYNCRST | 400 MGAREG_SEQ0_ASYNCRST; 401 WREG_SEQ(0x00, seq0); 402 403 /* 404 * TODO: replace busy waiting with vblank IRQ; put 405 * msleep(50) before changing SCROFF 406 */ 407 mga_wait_vsync(mdev); 408 mga_wait_busy(mdev); 409 410 RREG_ECRT(0x01, crtcext1); 411 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF; 412 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF; 413 WREG_ECRT(0x01, crtcext1); 414 } 415 416 static void mgag200_disable_display(struct mga_device *mdev) 417 { 418 u8 seq0, crtcext1; 419 420 RREG_SEQ(0x00, seq0); 421 seq0 &= ~MGAREG_SEQ0_SYNCRST; 422 WREG_SEQ(0x00, seq0); 423 424 /* 425 * TODO: replace busy waiting with vblank IRQ; put 426 * msleep(50) before changing SCROFF 427 */ 428 mga_wait_vsync(mdev); 429 mga_wait_busy(mdev); 430 431 RREG_ECRT(0x01, crtcext1); 432 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF | 433 MGAREG_CRTCEXT1_HSYNCOFF; 434 WREG_ECRT(0x01, crtcext1); 435 } 436 437 static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap, 438 struct drm_framebuffer *fb, struct drm_rect *clip) 439 { 440 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 441 442 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip)); 443 drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip); 444 } 445 446 /* 447 * Primary plane 448 */ 449 450 const uint32_t mgag200_primary_plane_formats[] = { 451 DRM_FORMAT_XRGB8888, 452 DRM_FORMAT_RGB565, 453 DRM_FORMAT_XRGB1555, 454 DRM_FORMAT_RGB888, 455 DRM_FORMAT_C8, 456 }; 457 458 const size_t mgag200_primary_plane_formats_size = ARRAY_SIZE(mgag200_primary_plane_formats); 459 460 const uint64_t mgag200_primary_plane_fmtmods[] = { 461 DRM_FORMAT_MOD_LINEAR, 462 DRM_FORMAT_MOD_INVALID 463 }; 464 465 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane, 466 struct drm_atomic_commit *new_state) 467 { 468 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); 469 struct drm_framebuffer *new_fb = new_plane_state->fb; 470 struct drm_framebuffer *fb = NULL; 471 struct drm_crtc *new_crtc = new_plane_state->crtc; 472 struct drm_crtc_state *new_crtc_state = NULL; 473 struct mgag200_crtc_state *new_mgag200_crtc_state; 474 int ret; 475 476 if (new_crtc) 477 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_crtc); 478 479 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 480 DRM_PLANE_NO_SCALING, 481 DRM_PLANE_NO_SCALING, 482 false, true); 483 if (ret) 484 return ret; 485 else if (!new_plane_state->visible) 486 return 0; 487 488 if (plane->state) 489 fb = plane->state->fb; 490 491 if (!fb || (fb->format != new_fb->format)) 492 new_crtc_state->mode_changed = true; /* update PLL settings */ 493 494 new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state); 495 new_mgag200_crtc_state->format = new_fb->format; 496 497 return 0; 498 } 499 500 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane, 501 struct drm_atomic_commit *old_state) 502 { 503 struct drm_device *dev = plane->dev; 504 struct mga_device *mdev = to_mga_device(dev); 505 struct drm_plane_state *plane_state = plane->state; 506 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(old_state, plane); 507 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 508 struct drm_framebuffer *fb = plane_state->fb; 509 struct drm_atomic_helper_damage_iter iter; 510 struct drm_rect damage; 511 512 mgag200_set_datasiz(mdev, fb->format->format); 513 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 514 drm_atomic_for_each_plane_damage(&iter, &damage) { 515 mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage); 516 } 517 518 /* Always scanout image at VRAM offset 0 */ 519 mgag200_set_startadd(mdev, (u32)0); 520 mgag200_set_offset(mdev, fb); 521 } 522 523 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane, 524 struct drm_atomic_commit *state) 525 { 526 struct drm_device *dev = plane->dev; 527 struct mga_device *mdev = to_mga_device(dev); 528 u8 seq1; 529 530 RREG_SEQ(0x01, seq1); 531 seq1 &= ~MGAREG_SEQ1_SCROFF; 532 WREG_SEQ(0x01, seq1); 533 msleep(20); 534 } 535 536 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane, 537 struct drm_atomic_commit *old_state) 538 { 539 struct drm_device *dev = plane->dev; 540 struct mga_device *mdev = to_mga_device(dev); 541 u8 seq1; 542 543 RREG_SEQ(0x01, seq1); 544 seq1 |= MGAREG_SEQ1_SCROFF; 545 WREG_SEQ(0x01, seq1); 546 msleep(20); 547 } 548 549 int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane, 550 struct drm_scanout_buffer *sb) 551 { 552 struct mga_device *mdev = to_mga_device(plane->dev); 553 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram); 554 555 if (plane->state && plane->state->fb) { 556 sb->format = plane->state->fb->format; 557 sb->width = plane->state->fb->width; 558 sb->height = plane->state->fb->height; 559 sb->pitch[0] = plane->state->fb->pitches[0]; 560 sb->map[0] = map; 561 return 0; 562 } 563 return -ENODEV; 564 } 565 566 /* 567 * CRTC 568 */ 569 570 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc, 571 const struct drm_display_mode *mode) 572 { 573 struct mga_device *mdev = to_mga_device(crtc->dev); 574 const struct mgag200_device_info *info = mdev->info; 575 576 /* 577 * Some devices have additional limits on the size of the 578 * display mode. 579 */ 580 if (mode->hdisplay > info->max_hdisplay) 581 return MODE_VIRTUAL_X; 582 if (mode->vdisplay > info->max_vdisplay) 583 return MODE_VIRTUAL_Y; 584 585 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 || 586 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) { 587 return MODE_H_ILLEGAL; 588 } 589 590 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || 591 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || 592 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || 593 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { 594 return MODE_BAD; 595 } 596 597 return MODE_OK; 598 } 599 600 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *new_state) 601 { 602 struct drm_device *dev = crtc->dev; 603 struct mga_device *mdev = to_mga_device(dev); 604 const struct mgag200_device_funcs *funcs = mdev->funcs; 605 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 606 struct drm_property_blob *new_gamma_lut = new_crtc_state->gamma_lut; 607 int ret; 608 609 if (!new_crtc_state->enable) 610 return 0; 611 612 ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state); 613 if (ret) 614 return ret; 615 616 if (new_crtc_state->mode_changed) { 617 if (funcs->pixpllc_atomic_check) { 618 ret = funcs->pixpllc_atomic_check(crtc, new_state); 619 if (ret) 620 return ret; 621 } 622 } 623 624 if (new_crtc_state->color_mgmt_changed && new_gamma_lut) { 625 if (new_gamma_lut->length != MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) { 626 drm_dbg(dev, "Wrong size for gamma_lut %zu\n", new_gamma_lut->length); 627 return -EINVAL; 628 } 629 } 630 631 return 0; 632 } 633 634 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_commit *old_state) 635 { 636 struct drm_crtc_state *crtc_state = crtc->state; 637 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 638 struct drm_device *dev = crtc->dev; 639 struct mga_device *mdev = to_mga_device(dev); 640 641 if (crtc_state->enable && crtc_state->color_mgmt_changed) { 642 const struct drm_format_info *format = mgag200_crtc_state->format; 643 644 if (crtc_state->gamma_lut) 645 mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data); 646 else 647 mgag200_crtc_fill_gamma(mdev, format); 648 } 649 } 650 651 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_commit *old_state) 652 { 653 struct drm_device *dev = crtc->dev; 654 struct mga_device *mdev = to_mga_device(dev); 655 const struct mgag200_device_funcs *funcs = mdev->funcs; 656 struct drm_crtc_state *crtc_state = crtc->state; 657 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 658 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 659 const struct drm_format_info *format = mgag200_crtc_state->format; 660 661 mgag200_set_format_regs(mdev, format); 662 mgag200_set_mode_regs(mdev, adjusted_mode, mgag200_crtc_state->set_vidrst); 663 664 if (funcs->pixpllc_atomic_update) 665 funcs->pixpllc_atomic_update(crtc, old_state); 666 667 if (crtc_state->gamma_lut) 668 mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data); 669 else 670 mgag200_crtc_fill_gamma(mdev, format); 671 672 mgag200_enable_display(mdev); 673 } 674 675 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_commit *old_state) 676 { 677 struct mga_device *mdev = to_mga_device(crtc->dev); 678 679 mgag200_disable_display(mdev); 680 } 681 682 void mgag200_crtc_reset(struct drm_crtc *crtc) 683 { 684 struct mgag200_crtc_state *mgag200_crtc_state; 685 686 if (crtc->state) 687 crtc->funcs->atomic_destroy_state(crtc, crtc->state); 688 689 mgag200_crtc_state = kzalloc_obj(*mgag200_crtc_state); 690 if (mgag200_crtc_state) 691 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base); 692 else 693 __drm_atomic_helper_crtc_reset(crtc, NULL); 694 } 695 696 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 697 { 698 struct drm_crtc_state *crtc_state = crtc->state; 699 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 700 struct mgag200_crtc_state *new_mgag200_crtc_state; 701 702 if (!crtc_state) 703 return NULL; 704 705 new_mgag200_crtc_state = kzalloc_obj(*new_mgag200_crtc_state); 706 if (!new_mgag200_crtc_state) 707 return NULL; 708 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base); 709 710 new_mgag200_crtc_state->format = mgag200_crtc_state->format; 711 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc, 712 sizeof(new_mgag200_crtc_state->pixpllc)); 713 new_mgag200_crtc_state->set_vidrst = mgag200_crtc_state->set_vidrst; 714 715 return &new_mgag200_crtc_state->base; 716 } 717 718 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) 719 { 720 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state); 721 722 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base); 723 kfree(mgag200_crtc_state); 724 } 725 726 /* 727 * Mode config 728 */ 729 730 static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_commit *state) 731 { 732 struct mga_device *mdev = to_mga_device(state->dev); 733 734 /* 735 * Concurrent operations could possibly trigger a call to 736 * drm_connector_helper_funcs.get_modes by trying to read the 737 * display modes. Protect access to I/O registers by acquiring 738 * the I/O-register lock. 739 */ 740 mutex_lock(&mdev->rmmio_lock); 741 drm_atomic_helper_commit_tail(state); 742 mutex_unlock(&mdev->rmmio_lock); 743 } 744 745 static const struct drm_mode_config_helper_funcs mgag200_mode_config_helper_funcs = { 746 .atomic_commit_tail = mgag200_mode_config_helper_atomic_commit_tail, 747 }; 748 749 /* Calculates a mode's required memory bandwidth (in KiB/sec). */ 750 static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode, 751 unsigned int bits_per_pixel) 752 { 753 uint32_t total_area, divisor; 754 uint64_t active_area, pixels_per_second, bandwidth; 755 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8; 756 757 divisor = 1024; 758 759 if (!mode->htotal || !mode->vtotal || !mode->clock) 760 return 0; 761 762 active_area = mode->hdisplay * mode->vdisplay; 763 total_area = mode->htotal * mode->vtotal; 764 765 pixels_per_second = active_area * mode->clock * 1000; 766 do_div(pixels_per_second, total_area); 767 768 bandwidth = pixels_per_second * bytes_per_pixel * 100; 769 do_div(bandwidth, divisor); 770 771 return (uint32_t)bandwidth; 772 } 773 774 static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev, 775 const struct drm_display_mode *mode) 776 { 777 static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888 778 struct mga_device *mdev = to_mga_device(dev); 779 unsigned long fbsize, fbpages, max_fbpages; 780 const struct mgag200_device_info *info = mdev->info; 781 782 max_fbpages = mdev->vram_available >> PAGE_SHIFT; 783 784 fbsize = mode->hdisplay * mode->vdisplay * max_bpp; 785 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); 786 787 if (fbpages > max_fbpages) 788 return MODE_MEM; 789 790 /* 791 * Test the mode's required memory bandwidth if the device 792 * specifies a maximum. Not all devices do though. 793 */ 794 if (info->max_mem_bandwidth) { 795 uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8); 796 797 if (mode_bandwidth > (info->max_mem_bandwidth * 1024)) 798 return MODE_BAD; 799 } 800 801 return MODE_OK; 802 } 803 804 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = { 805 .fb_create = drm_gem_fb_create_with_dirty, 806 .mode_valid = mgag200_mode_config_mode_valid, 807 .atomic_check = drm_atomic_helper_check, 808 .atomic_commit = drm_atomic_helper_commit, 809 }; 810 811 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available) 812 { 813 struct drm_device *dev = &mdev->base; 814 int ret; 815 816 mdev->vram_available = vram_available; 817 818 ret = drmm_mode_config_init(dev); 819 if (ret) { 820 drm_err(dev, "drmm_mode_config_init() failed: %d\n", ret); 821 return ret; 822 } 823 824 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; 825 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; 826 dev->mode_config.preferred_depth = 24; 827 dev->mode_config.funcs = &mgag200_mode_config_funcs; 828 dev->mode_config.helper_private = &mgag200_mode_config_helper_funcs; 829 830 return 0; 831 } 832