1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD Platform Management Framework Driver
4 *
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #include <linux/array_size.h>
12 #include <linux/cleanup.h>
13 #include <linux/debugfs.h>
14 #include <linux/dev_printk.h>
15 #include <linux/iopoll.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/power_supply.h>
21 #include <asm/amd/node.h>
22 #include "pmf.h"
23
24 /* PMF-SMU communication registers */
25 #define AMD_PMF_REGISTER_MESSAGE 0xA18
26 #define AMD_PMF_REGISTER_RESPONSE 0xA78
27 #define AMD_PMF_REGISTER_ARGUMENT 0xA58
28
29 /* PMF-SMU communication registers for 1AH_M80H */
30 #define AMD_PMF_REGISTER_MESSAGE_V2 0xA04
31 #define AMD_PMF_REGISTER_RESPONSE_V2 0xA08
32 #define AMD_PMF_REGISTER_ARGUMENT0_V2 0xA0C
33 #define AMD_PMF_REGISTER_ARGUMENT1_V2 0xAAC
34 #define AMD_PMF_REGISTER_ARGUMENT2_V2 0xAB0
35
36 /* Base address of SMU for mapping physical address to virtual address */
37 #define AMD_PMF_MAPPING_SIZE 0x01000
38 #define AMD_PMF_BASE_ADDR_OFFSET 0x10000
39 #define AMD_PMF_BASE_ADDR_LO 0x13B102E8
40 #define AMD_PMF_BASE_ADDR_HI 0x13B102EC
41 #define AMD_PMF_BASE_ADDR_LO_MASK GENMASK(15, 0)
42 #define AMD_PMF_BASE_ADDR_HI_MASK GENMASK(31, 20)
43
44 /* SMU Response Codes */
45 #define AMD_PMF_RESULT_OK 0x01
46 #define AMD_PMF_RESULT_CMD_REJECT_BUSY 0xFC
47 #define AMD_PMF_RESULT_CMD_REJECT_PREREQ 0xFD
48 #define AMD_PMF_RESULT_CMD_UNKNOWN 0xFE
49 #define AMD_PMF_RESULT_FAILED 0xFF
50
51 #define PMF_MSG_DELAY_MIN_US 50
52 #define RESPONSE_REGISTER_LOOP_MAX 20000
53
54 #define DELAY_MIN_US 2000
55 #define DELAY_MAX_US 3000
56
57 /* override Metrics Table sample size time (in ms) */
58 int metrics_table_loop_ms = 1000;
59 module_param(metrics_table_loop_ms, int, 0644);
60 MODULE_PARM_DESC(metrics_table_loop_ms, "Metrics Table sample size time (default = 1000ms)");
61
62 /* Force load on supported older platforms */
63 static bool force_load;
64 module_param(force_load, bool, 0444);
65 MODULE_PARM_DESC(force_load, "Force load this driver on supported older platforms (experimental)");
66
67 static bool smart_pc_support = true;
68 module_param(smart_pc_support, bool, 0444);
69 MODULE_PARM_DESC(smart_pc_support, "Smart PC Support (default = true)");
70
amd_pmf_supports_accumulator_metrics(struct amd_pmf_dev * pdev)71 static bool amd_pmf_supports_accumulator_metrics(struct amd_pmf_dev *pdev)
72 {
73 switch (pdev->cpu_id) {
74 case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT:
75 return true;
76 default:
77 return false;
78 }
79 }
80
amd_pmf_pwr_src_notify_call(struct notifier_block * nb,unsigned long event,void * data)81 static int amd_pmf_pwr_src_notify_call(struct notifier_block *nb, unsigned long event, void *data)
82 {
83 struct amd_pmf_dev *pmf = container_of(nb, struct amd_pmf_dev, pwr_src_notifier);
84
85 if (event != PSY_EVENT_PROP_CHANGED)
86 return NOTIFY_OK;
87
88 if (is_apmf_func_supported(pmf, APMF_FUNC_AUTO_MODE) ||
89 is_apmf_func_supported(pmf, APMF_FUNC_DYN_SLIDER_DC) ||
90 is_apmf_func_supported(pmf, APMF_FUNC_DYN_SLIDER_AC)) {
91 if ((pmf->amt_enabled || pmf->cnqf_enabled) && is_pprof_balanced(pmf))
92 return NOTIFY_DONE;
93 }
94
95 if (is_apmf_func_supported(pmf, APMF_FUNC_STATIC_SLIDER_GRANULAR))
96 amd_pmf_set_sps_power_limits(pmf);
97
98 if (is_apmf_func_supported(pmf, APMF_FUNC_OS_POWER_SLIDER_UPDATE))
99 amd_pmf_power_slider_update_event(pmf);
100
101 return NOTIFY_OK;
102 }
103
current_power_limits_show(struct seq_file * seq,void * unused)104 static int current_power_limits_show(struct seq_file *seq, void *unused)
105 {
106 struct amd_pmf_dev *dev = seq->private;
107 struct amd_pmf_static_slider_granular table;
108 int mode, src = 0;
109
110 mode = amd_pmf_get_pprof_modes(dev);
111 if (mode < 0)
112 return mode;
113
114 src = amd_pmf_get_power_source();
115 amd_pmf_update_slider(dev, SLIDER_OP_GET, mode, &table);
116 seq_printf(seq, "spl:%u fppt:%u sppt:%u sppt_apu_only:%u stt_min:%u stt[APU]:%u stt[HS2]: %u\n",
117 table.prop[src][mode].spl,
118 table.prop[src][mode].fppt,
119 table.prop[src][mode].sppt,
120 table.prop[src][mode].sppt_apu_only,
121 table.prop[src][mode].stt_min,
122 table.prop[src][mode].stt_skin_temp[STT_TEMP_APU],
123 table.prop[src][mode].stt_skin_temp[STT_TEMP_HS2]);
124 return 0;
125 }
126 DEFINE_SHOW_ATTRIBUTE(current_power_limits);
127
amd_pmf_dbgfs_unregister(struct amd_pmf_dev * dev)128 static void amd_pmf_dbgfs_unregister(struct amd_pmf_dev *dev)
129 {
130 debugfs_remove_recursive(dev->dbgfs_dir);
131 }
132
amd_pmf_dbgfs_register(struct amd_pmf_dev * dev)133 static void amd_pmf_dbgfs_register(struct amd_pmf_dev *dev)
134 {
135 dev->dbgfs_dir = debugfs_create_dir("amd_pmf", NULL);
136 if (dev->pmf_if_version == PMF_IF_V1)
137 debugfs_create_file("current_power_limits", 0644, dev->dbgfs_dir, dev,
138 ¤t_power_limits_fops);
139 }
140
amd_pmf_get_power_source(void)141 int amd_pmf_get_power_source(void)
142 {
143 if (power_supply_is_system_supplied() > 0)
144 return POWER_SOURCE_AC;
145 else
146 return POWER_SOURCE_DC;
147 }
148
amd_pmf_reg_read(struct amd_pmf_dev * dev,int reg_offset)149 static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset)
150 {
151 return ioread32(dev->regbase + reg_offset);
152 }
153
amd_pmf_reg_write(struct amd_pmf_dev * dev,int reg_offset,u32 val)154 static inline void amd_pmf_reg_write(struct amd_pmf_dev *dev, int reg_offset, u32 val)
155 {
156 iowrite32(val, dev->regbase + reg_offset);
157 }
158
amd_pmf_dump_registers(struct amd_pmf_dev * dev)159 static void __maybe_unused amd_pmf_dump_registers(struct amd_pmf_dev *dev)
160 {
161 u32 value;
162
163 value = amd_pmf_reg_read(dev, dev->smu_regs->resp_reg);
164 dev_dbg(dev->dev, "AMD_PMF_REGISTER_RESPONSE:%x\n", value);
165
166 value = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg[0]);
167 dev_dbg(dev->dev, "AMD_PMF_REGISTER_ARGUMENT:%d\n", value);
168 if (amd_pmf_supports_accumulator_metrics(dev)) {
169 value = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg[1]);
170 dev_dbg(dev->dev, "AMD_PMF_REGISTER_ARGUMENT1:%d\n", value);
171 value = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg[2]);
172 dev_dbg(dev->dev, "AMD_PMF_REGISTER_ARGUMENT2:%d\n", value);
173 }
174
175 value = amd_pmf_reg_read(dev, dev->smu_regs->msg_reg);
176 dev_dbg(dev->dev, "AMD_PMF_REGISTER_MESSAGE:%x\n", value);
177 }
178
179 /**
180 * fixp_q88_fromint: Convert integer to Q8.8
181 * @val: input value
182 *
183 * Converts an integer into binary fixed point format where 8 bits
184 * are used for integer and 8 bits are used for the decimal.
185 *
186 * Return: unsigned integer converted to Q8.8 format
187 */
fixp_q88_fromint(u32 val)188 u32 fixp_q88_fromint(u32 val)
189 {
190 return val << 8;
191 }
192
amd_pmf_send_cmd(struct amd_pmf_dev * dev,u8 message,bool get,u32 arg,u32 * data)193 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data)
194 {
195 int rc;
196 u32 val;
197
198 guard(mutex)(&dev->lock);
199
200 /* Wait until we get a valid response */
201 rc = readx_poll_timeout(ioread32, dev->regbase + dev->smu_regs->resp_reg,
202 val, val != 0, PMF_MSG_DELAY_MIN_US,
203 PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
204 if (rc) {
205 dev_err(dev->dev, "failed to talk to SMU\n");
206 return rc;
207 }
208
209 /* Write zero to response register */
210 amd_pmf_reg_write(dev, dev->smu_regs->resp_reg, 0);
211
212 /* Write argument into argument register */
213 amd_pmf_reg_write(dev, dev->smu_regs->arg_reg[0], arg);
214
215 /* Write message ID to message ID register */
216 amd_pmf_reg_write(dev, dev->smu_regs->msg_reg, message);
217
218 /* Wait until we get a valid response */
219 rc = readx_poll_timeout(ioread32, dev->regbase + dev->smu_regs->resp_reg,
220 val, val != 0, PMF_MSG_DELAY_MIN_US,
221 PMF_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
222 if (rc) {
223 dev_err(dev->dev, "SMU response timed out\n");
224 return rc;
225 }
226
227 switch (val) {
228 case AMD_PMF_RESULT_OK:
229 if (get) {
230 /* PMFW may take longer time to return back the data */
231 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
232 *data = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg[0]);
233 if (amd_pmf_supports_accumulator_metrics(dev) &&
234 message == GET_1AH_M80H_METRICS_TABLE_DRAM_ADDR) {
235 dev->dram_addr.hi = amd_pmf_reg_read(dev,
236 dev->smu_regs->arg_reg[1]);
237 dev->dram_addr.size = amd_pmf_reg_read(dev,
238 dev->smu_regs->arg_reg[2]);
239 }
240 }
241 break;
242 case AMD_PMF_RESULT_CMD_REJECT_BUSY:
243 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
244 rc = -EBUSY;
245 break;
246 case AMD_PMF_RESULT_CMD_UNKNOWN:
247 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
248 rc = -EINVAL;
249 break;
250 case AMD_PMF_RESULT_CMD_REJECT_PREREQ:
251 case AMD_PMF_RESULT_FAILED:
252 default:
253 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
254 rc = -EIO;
255 break;
256 }
257
258 amd_pmf_dump_registers(dev);
259 return rc;
260 }
261
262 /* RMB, PS, 1AH_M20H and 1AH_M60H share the same v1 SMU mailbox registers */
263 static const struct amd_pmf_smu_regs amd_pmf_smu_regs_v1 = {
264 .msg_reg = AMD_PMF_REGISTER_MESSAGE,
265 .resp_reg = AMD_PMF_REGISTER_RESPONSE,
266 .arg_reg = { AMD_PMF_REGISTER_ARGUMENT, 0, 0 },
267 };
268
269 /* 1AH_M80H uses an extended mailbox with three argument registers */
270 static const struct amd_pmf_smu_regs amd_pmf_smu_regs_v2 = {
271 .msg_reg = AMD_PMF_REGISTER_MESSAGE_V2,
272 .resp_reg = AMD_PMF_REGISTER_RESPONSE_V2,
273 .arg_reg = {
274 AMD_PMF_REGISTER_ARGUMENT0_V2,
275 AMD_PMF_REGISTER_ARGUMENT1_V2,
276 AMD_PMF_REGISTER_ARGUMENT2_V2,
277 },
278 };
279
280 static const struct pci_device_id pmf_pci_ids[] = {
281 { PCI_DEVICE_DATA(AMD, CPU_ID_RMB, &amd_pmf_smu_regs_v1) },
282 { PCI_DEVICE_DATA(AMD, CPU_ID_PS, &amd_pmf_smu_regs_v1) },
283 { PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, &amd_pmf_smu_regs_v1) },
284 { PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, &amd_pmf_smu_regs_v1) },
285 { PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_pmf_smu_regs_v2) },
286 { }
287 };
288
amd_pmf_reinit_ta(struct amd_pmf_dev * pdev)289 static int amd_pmf_reinit_ta(struct amd_pmf_dev *pdev)
290 {
291 bool status;
292 int ret, i;
293
294 for (i = 0; i < ARRAY_SIZE(amd_pmf_ta_uuid); i++) {
295 ret = amd_pmf_tee_init(pdev, &amd_pmf_ta_uuid[i]);
296 if (ret) {
297 dev_err(pdev->dev, "TEE init failed for UUID[%d] ret: %d\n", i, ret);
298 return ret;
299 }
300
301 ret = amd_pmf_start_policy_engine(pdev);
302 dev_dbg(pdev->dev, "start policy engine ret: %d (UUID idx: %d)\n", ret, i);
303 status = ret == TA_PMF_TYPE_SUCCESS;
304 if (status)
305 break;
306 amd_pmf_tee_deinit(pdev);
307 }
308
309 return 0;
310 }
311
amd_pmf_restore_handler(struct device * dev)312 static int amd_pmf_restore_handler(struct device *dev)
313 {
314 struct amd_pmf_dev *pdev = dev_get_drvdata(dev);
315 int ret;
316
317 if (pdev->buf) {
318 ret = amd_pmf_set_dram_addr(pdev, false);
319 if (ret)
320 return ret;
321 }
322
323 if (pdev->smart_pc_enabled)
324 amd_pmf_reinit_ta(pdev);
325
326 return 0;
327 }
328
amd_pmf_freeze_handler(struct device * dev)329 static int amd_pmf_freeze_handler(struct device *dev)
330 {
331 struct amd_pmf_dev *pdev = dev_get_drvdata(dev);
332
333 if (!pdev->smart_pc_enabled)
334 return 0;
335
336 cancel_delayed_work_sync(&pdev->pb_work);
337 /* Clear all TEE resources */
338 amd_pmf_tee_deinit(pdev);
339 pdev->session_id = 0;
340
341 return 0;
342 }
343
amd_pmf_suspend_handler(struct device * dev)344 static int amd_pmf_suspend_handler(struct device *dev)
345 {
346 struct amd_pmf_dev *pdev = dev_get_drvdata(dev);
347
348 if (pdev->smart_pc_enabled)
349 cancel_delayed_work_sync(&pdev->pb_work);
350
351 if (is_apmf_func_supported(pdev, APMF_FUNC_SBIOS_HEARTBEAT_V2))
352 amd_pmf_notify_sbios_heartbeat_event_v2(pdev, ON_SUSPEND);
353
354 return 0;
355 }
356
amd_pmf_resume_handler(struct device * dev)357 static int amd_pmf_resume_handler(struct device *dev)
358 {
359 struct amd_pmf_dev *pdev = dev_get_drvdata(dev);
360 int ret;
361
362 if (pdev->buf) {
363 ret = amd_pmf_set_dram_addr(pdev, false);
364 if (ret)
365 return ret;
366 }
367
368 if (is_apmf_func_supported(pdev, APMF_FUNC_SBIOS_HEARTBEAT_V2))
369 amd_pmf_notify_sbios_heartbeat_event_v2(pdev, ON_RESUME);
370
371 if (pdev->smart_pc_enabled)
372 schedule_delayed_work(&pdev->pb_work, msecs_to_jiffies(2000));
373
374 return 0;
375 }
376
377 static const struct dev_pm_ops amd_pmf_pm = {
378 .suspend = amd_pmf_suspend_handler,
379 .resume = amd_pmf_resume_handler,
380 .freeze = amd_pmf_freeze_handler,
381 .restore = amd_pmf_restore_handler,
382 };
383
amd_pmf_init_features(struct amd_pmf_dev * dev)384 static void amd_pmf_init_features(struct amd_pmf_dev *dev)
385 {
386 int ret;
387
388 /* Enable Static Slider */
389 if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) ||
390 is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) {
391 amd_pmf_init_sps(dev);
392 dev->pwr_src_notifier.notifier_call = amd_pmf_pwr_src_notify_call;
393 power_supply_reg_notifier(&dev->pwr_src_notifier);
394 dev_dbg(dev->dev, "SPS enabled and Platform Profiles registered\n");
395 }
396
397 if (smart_pc_support) {
398 amd_pmf_init_smart_pc(dev);
399 if (dev->smart_pc_enabled) {
400 dev_dbg(dev->dev, "Smart PC Solution Enabled\n");
401 /* If Smart PC is enabled, no need to check for other features */
402 return;
403 }
404 } else {
405 dev->smart_pc_enabled = false;
406 }
407
408 if (is_apmf_func_supported(dev, APMF_FUNC_AUTO_MODE)) {
409 amd_pmf_init_auto_mode(dev);
410 dev_dbg(dev->dev, "Auto Mode Init done\n");
411 } else if (is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_AC) ||
412 is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_DC)) {
413 ret = amd_pmf_init_cnqf(dev);
414 if (ret)
415 dev_warn(dev->dev, "CnQF Init failed\n");
416 }
417 }
418
amd_pmf_deinit_features(struct amd_pmf_dev * dev)419 static void amd_pmf_deinit_features(struct amd_pmf_dev *dev)
420 {
421 if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) ||
422 is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) {
423 power_supply_unreg_notifier(&dev->pwr_src_notifier);
424 }
425
426 if (dev->smart_pc_enabled) {
427 amd_pmf_deinit_smart_pc(dev);
428 } else if (is_apmf_func_supported(dev, APMF_FUNC_AUTO_MODE)) {
429 amd_pmf_deinit_auto_mode(dev);
430 } else if (is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_AC) ||
431 is_apmf_func_supported(dev, APMF_FUNC_DYN_SLIDER_DC)) {
432 amd_pmf_deinit_cnqf(dev);
433 }
434 }
435
amd_pmf_get_smu_mb_offset(struct amd_pmf_dev * pdev,struct pci_dev * rdev)436 static int amd_pmf_get_smu_mb_offset(struct amd_pmf_dev *pdev, struct pci_dev *rdev)
437 {
438 const struct pci_device_id *id;
439
440 id = pci_match_id(pmf_pci_ids, rdev);
441 if (!id)
442 return -ENODEV;
443
444 pdev->smu_regs = (const struct amd_pmf_smu_regs *)id->driver_data;
445
446 return 0;
447 }
448
449 static const struct acpi_device_id amd_pmf_acpi_ids[] = {
450 {"AMDI0100", 0x100},
451 {"AMDI0102", 0},
452 {"AMDI0103", 0},
453 {"AMDI0105", 0},
454 {"AMDI0107", 0},
455 {"AMDI0108", 0},
456 {"AMDI0109", 0},
457 { }
458 };
459 MODULE_DEVICE_TABLE(acpi, amd_pmf_acpi_ids);
460
amd_pmf_probe(struct platform_device * pdev)461 static int amd_pmf_probe(struct platform_device *pdev)
462 {
463 const struct acpi_device_id *id;
464 struct amd_pmf_dev *dev;
465 struct pci_dev *rdev;
466 u32 base_addr_lo;
467 u32 base_addr_hi;
468 u64 base_addr;
469 u32 val;
470 int err;
471
472 id = acpi_match_device(amd_pmf_acpi_ids, &pdev->dev);
473 if (!id)
474 return -ENODEV;
475
476 if (id->driver_data == 0x100 && !force_load)
477 return -ENODEV;
478
479 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
480 if (!dev)
481 return -ENOMEM;
482
483 dev->dev = &pdev->dev;
484
485 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
486 if (!rdev || !pci_match_id(pmf_pci_ids, rdev)) {
487 pci_dev_put(rdev);
488 return -ENODEV;
489 }
490
491 dev->cpu_id = rdev->device;
492
493 err = amd_smn_read(0, AMD_PMF_BASE_ADDR_LO, &val);
494 if (err) {
495 pci_dev_put(rdev);
496 return dev_err_probe(dev->dev, pcibios_err_to_errno(err),
497 "error in reading from 0x%x\n", AMD_PMF_BASE_ADDR_LO);
498 }
499
500 base_addr_lo = val & AMD_PMF_BASE_ADDR_HI_MASK;
501
502 err = amd_smn_read(0, AMD_PMF_BASE_ADDR_HI, &val);
503 if (err) {
504 pci_dev_put(rdev);
505 return dev_err_probe(dev->dev, pcibios_err_to_errno(err),
506 "error in reading from 0x%x\n", AMD_PMF_BASE_ADDR_HI);
507 }
508
509 base_addr_hi = val & AMD_PMF_BASE_ADDR_LO_MASK;
510 pci_dev_put(rdev);
511 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
512
513 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMF_BASE_ADDR_OFFSET,
514 AMD_PMF_MAPPING_SIZE);
515 if (!dev->regbase)
516 return -ENOMEM;
517
518 err = devm_mutex_init(dev->dev, &dev->lock);
519 if (err)
520 return err;
521
522 err = devm_mutex_init(dev->dev, &dev->update_mutex);
523 if (err)
524 return err;
525
526 err = devm_mutex_init(dev->dev, &dev->cb_mutex);
527 if (err)
528 return err;
529
530 err = devm_mutex_init(dev->dev, &dev->cbi_mutex);
531 if (err)
532 return err;
533
534 err = devm_mutex_init(dev->dev, &dev->metrics_mutex);
535 if (err)
536 return err;
537
538 /* Populate smu_regs with SoC-specific SMU mailbox register offsets */
539 err = amd_pmf_get_smu_mb_offset(dev, rdev);
540 if (err)
541 return err;
542
543 if (amd_pmf_supports_accumulator_metrics(dev)) {
544 err = amd_pmf_get_tbl_dram_addr(dev);
545 if (err)
546 return err;
547 }
548
549 apmf_acpi_init(dev);
550 platform_set_drvdata(pdev, dev);
551 amd_pmf_dbgfs_register(dev);
552 amd_pmf_init_features(dev);
553 apmf_install_handler(dev);
554 if (is_apmf_func_supported(dev, APMF_FUNC_SBIOS_HEARTBEAT_V2))
555 amd_pmf_notify_sbios_heartbeat_event_v2(dev, ON_LOAD);
556
557 amd_pmf_set_device(dev->dev);
558
559 err = amd_pmf_cdev_register(dev);
560 if (err)
561 dev_warn(dev->dev, "failed to register util interface: %d\n", err);
562
563 dev_info(dev->dev, "registered PMF device successfully\n");
564
565 return 0;
566 }
567
amd_pmf_remove(struct platform_device * pdev)568 static void amd_pmf_remove(struct platform_device *pdev)
569 {
570 struct amd_pmf_dev *dev = platform_get_drvdata(pdev);
571
572 amd_pmf_cdev_unregister();
573 amd_pmf_deinit_features(dev);
574 if (is_apmf_func_supported(dev, APMF_FUNC_SBIOS_HEARTBEAT_V2))
575 amd_pmf_notify_sbios_heartbeat_event_v2(dev, ON_UNLOAD);
576 apmf_acpi_deinit(dev);
577 amd_pmf_dbgfs_unregister(dev);
578 }
579
580 static const struct attribute_group *amd_pmf_driver_groups[] = {
581 &cnqf_feature_attribute_group,
582 NULL,
583 };
584
585 static struct platform_driver amd_pmf_driver = {
586 .driver = {
587 .name = "amd-pmf",
588 .acpi_match_table = amd_pmf_acpi_ids,
589 .dev_groups = amd_pmf_driver_groups,
590 .pm = pm_sleep_ptr(&amd_pmf_pm),
591 },
592 .probe = amd_pmf_probe,
593 .remove = amd_pmf_remove,
594 };
595 module_platform_driver(amd_pmf_driver);
596
597 MODULE_LICENSE("GPL");
598 MODULE_DESCRIPTION("AMD Platform Management Framework Driver");
599 MODULE_SOFTDEP("pre: amdtee");
600