1 /*
2 * Driver for Amlogic Meson SPI communication controller (SPICC)
3 *
4 * Copyright (C) BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/device.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/reset.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/dma-mapping.h>
25
26 /*
27 * There are two modes for data transmission: PIO and DMA.
28 * When bits_per_word is 8, 16, 24, or 32, data is transferred using PIO mode.
29 * When bits_per_word is 64, DMA mode is used by default.
30 *
31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made
32 * up of one or more DMA bursts. The DMA burst implementation mechanism is,
33 * For TX, when the number of words in TXFIFO is less than the preset
34 * reading threshold, SPICC starts a reading DMA burst, which reads the preset
35 * number of words from TX buffer, then writes them into TXFIFO.
36 * For RX, when the number of words in RXFIFO is greater than the preset
37 * writing threshold, SPICC starts a writing request burst, which reads the
38 * preset number of words from RXFIFO, then write them into RX buffer.
39 * DMA works if the transfer meets the following conditions,
40 * - 64 bits per word
41 * - The transfer length in word must be multiples of the dma_burst_len, and
42 * the dma_burst_len should be one of 8,7...2, otherwise, it will be split
43 * into several SPI bursts by this driver
44 */
45
46 #define SPICC_MAX_BURST 128
47
48 /* Register Map */
49 #define SPICC_RXDATA 0x00
50
51 #define SPICC_TXDATA 0x04
52
53 #define SPICC_CONREG 0x08
54 #define SPICC_ENABLE BIT(0)
55 #define SPICC_MODE_MASTER BIT(1)
56 #define SPICC_XCH BIT(2)
57 #define SPICC_SMC BIT(3)
58 #define SPICC_POL BIT(4)
59 #define SPICC_PHA BIT(5)
60 #define SPICC_SSCTL BIT(6)
61 #define SPICC_SSPOL BIT(7)
62 #define SPICC_DRCTL_MASK GENMASK(9, 8)
63 #define SPICC_DRCTL_IGNORE 0
64 #define SPICC_DRCTL_FALLING 1
65 #define SPICC_DRCTL_LOWLEVEL 2
66 #define SPICC_CS_MASK GENMASK(13, 12)
67 #define SPICC_DATARATE_MASK GENMASK(18, 16)
68 #define SPICC_DATARATE_DIV4 0
69 #define SPICC_DATARATE_DIV8 1
70 #define SPICC_DATARATE_DIV16 2
71 #define SPICC_DATARATE_DIV32 3
72 #define SPICC_BITLENGTH_MASK GENMASK(24, 19)
73 #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
74
75 #define SPICC_INTREG 0x0c
76 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
77 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
78 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
79 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
80 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
81 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
82 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
83 #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
84
85 #define SPICC_DMAREG 0x10
86 #define SPICC_DMA_ENABLE BIT(0)
87 #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
88 #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
89 #define SPICC_READ_BURST_MASK GENMASK(14, 11)
90 #define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
91 #define SPICC_DMA_URGENT BIT(19)
92 #define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
93 #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
94
95 #define SPICC_STATREG 0x14
96 #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
97 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
98 #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
99 #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
100 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
101 #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
102 #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
103 #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
104
105 #define SPICC_PERIODREG 0x18
106 #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
107
108 #define SPICC_TESTREG 0x1c
109 #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
110 #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
111 #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
112 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
113 #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
114 #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
115 #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
116 #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
117 #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
118 #define SPICC_MO_NO_DELAY 0
119 #define SPICC_MO_DELAY_1_CYCLE 1
120 #define SPICC_MO_DELAY_2_CYCLE 2
121 #define SPICC_MO_DELAY_3_CYCLE 3
122 #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
123 #define SPICC_MI_NO_DELAY 0
124 #define SPICC_MI_DELAY_1_CYCLE 1
125 #define SPICC_MI_DELAY_2_CYCLE 2
126 #define SPICC_MI_DELAY_3_CYCLE 3
127 #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
128 #define SPICC_CAP_AHEAD_2_CYCLE 0
129 #define SPICC_CAP_AHEAD_1_CYCLE 1
130 #define SPICC_CAP_NO_DELAY 2
131 #define SPICC_CAP_DELAY_1_CYCLE 3
132 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
133 #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
134
135 #define SPICC_DRADDR 0x20 /* Read Address of DMA */
136
137 #define SPICC_DWADDR 0x24 /* Write Address of DMA */
138
139 #define SPICC_LD_CNTL0 0x28
140 #define VSYNC_IRQ_SRC_SELECT BIT(0)
141 #define DMA_EN_SET_BY_VSYNC BIT(2)
142 #define XCH_EN_SET_BY_VSYNC BIT(3)
143 #define DMA_READ_COUNTER_EN BIT(4)
144 #define DMA_WRITE_COUNTER_EN BIT(5)
145 #define DMA_RADDR_LOAD_BY_VSYNC BIT(6)
146 #define DMA_WADDR_LOAD_BY_VSYNC BIT(7)
147 #define DMA_ADDR_LOAD_FROM_LD_ADDR BIT(8)
148
149 #define SPICC_LD_CNTL1 0x2c
150 #define DMA_READ_COUNTER GENMASK(15, 0)
151 #define DMA_WRITE_COUNTER GENMASK(31, 16)
152 #define DMA_BURST_LEN_DEFAULT 8
153 #define DMA_BURST_COUNT_MAX 0xffff
154 #define SPI_BURST_LEN_MAX (DMA_BURST_LEN_DEFAULT * DMA_BURST_COUNT_MAX)
155
156 #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
157 #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
158 #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
159 #define SPICC_ENH_DATARATE_EN BIT(24)
160 #define SPICC_ENH_MOSI_OEN BIT(25)
161 #define SPICC_ENH_CLK_OEN BIT(26)
162 #define SPICC_ENH_CS_OEN BIT(27)
163 #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
164 #define SPICC_ENH_MAIN_CLK_AO BIT(29)
165
166 #define writel_bits_relaxed(mask, val, addr) \
167 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
168
169 struct meson_spicc_data {
170 unsigned int max_speed_hz;
171 unsigned int min_speed_hz;
172 unsigned int fifo_size;
173 bool has_oen;
174 bool has_enhance_clk_div;
175 bool has_pclk;
176 };
177
178 struct meson_spicc_device {
179 struct spi_controller *host;
180 struct platform_device *pdev;
181 void __iomem *base;
182 struct clk *core;
183 struct clk *pclk;
184 struct clk_divider pow2_div;
185 struct clk *clk;
186 struct spi_message *message;
187 struct spi_transfer *xfer;
188 struct completion done;
189 const struct meson_spicc_data *data;
190 u8 *tx_buf;
191 u8 *rx_buf;
192 unsigned int bytes_per_word;
193 unsigned long tx_remain;
194 unsigned long rx_remain;
195 unsigned long xfer_remain;
196 struct pinctrl *pinctrl;
197 struct pinctrl_state *pins_idle_high;
198 struct pinctrl_state *pins_idle_low;
199 dma_addr_t tx_dma;
200 dma_addr_t rx_dma;
201 bool using_dma;
202 };
203
204 #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
205
meson_spicc_oen_enable(struct meson_spicc_device * spicc)206 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
207 {
208 u32 conf;
209
210 if (!spicc->data->has_oen) {
211 /* Try to get pinctrl states for idle high/low */
212 spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl,
213 "idle-high");
214 if (IS_ERR(spicc->pins_idle_high)) {
215 dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n");
216 spicc->pins_idle_high = NULL;
217 }
218 spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl,
219 "idle-low");
220 if (IS_ERR(spicc->pins_idle_low)) {
221 dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n");
222 spicc->pins_idle_low = NULL;
223 }
224 return;
225 }
226
227 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
228 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
229
230 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
231 }
232
meson_spicc_dma_map(struct meson_spicc_device * spicc,struct spi_transfer * t)233 static int meson_spicc_dma_map(struct meson_spicc_device *spicc,
234 struct spi_transfer *t)
235 {
236 struct device *dev = spicc->host->dev.parent;
237
238 if (!(t->tx_buf && t->rx_buf))
239 return -EINVAL;
240
241 t->tx_dma = dma_map_single(dev, (void *)t->tx_buf, t->len, DMA_TO_DEVICE);
242 if (dma_mapping_error(dev, t->tx_dma))
243 return -ENOMEM;
244
245 t->rx_dma = dma_map_single(dev, t->rx_buf, t->len, DMA_FROM_DEVICE);
246 if (dma_mapping_error(dev, t->rx_dma))
247 return -ENOMEM;
248
249 spicc->tx_dma = t->tx_dma;
250 spicc->rx_dma = t->rx_dma;
251
252 return 0;
253 }
254
meson_spicc_dma_unmap(struct meson_spicc_device * spicc,struct spi_transfer * t)255 static void meson_spicc_dma_unmap(struct meson_spicc_device *spicc,
256 struct spi_transfer *t)
257 {
258 struct device *dev = spicc->host->dev.parent;
259
260 if (t->tx_dma)
261 dma_unmap_single(dev, t->tx_dma, t->len, DMA_TO_DEVICE);
262 if (t->rx_dma)
263 dma_unmap_single(dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
264 }
265
266 /*
267 * According to the remain words length, calculate a suitable spi burst length
268 * and a dma burst length for current spi burst
269 */
meson_spicc_calc_dma_len(struct meson_spicc_device * spicc,u32 len,u32 * dma_burst_len)270 static u32 meson_spicc_calc_dma_len(struct meson_spicc_device *spicc,
271 u32 len, u32 *dma_burst_len)
272 {
273 u32 i;
274
275 if (len <= spicc->data->fifo_size) {
276 *dma_burst_len = len;
277 return len;
278 }
279
280 *dma_burst_len = DMA_BURST_LEN_DEFAULT;
281
282 if (len == (SPI_BURST_LEN_MAX + 1))
283 return SPI_BURST_LEN_MAX - DMA_BURST_LEN_DEFAULT;
284
285 if (len >= SPI_BURST_LEN_MAX)
286 return SPI_BURST_LEN_MAX;
287
288 for (i = DMA_BURST_LEN_DEFAULT; i > 1; i--)
289 if ((len % i) == 0) {
290 *dma_burst_len = i;
291 return len;
292 }
293
294 i = len % DMA_BURST_LEN_DEFAULT;
295 len -= i;
296
297 if (i == 1)
298 len -= DMA_BURST_LEN_DEFAULT;
299
300 return len;
301 }
302
meson_spicc_setup_dma(struct meson_spicc_device * spicc)303 static void meson_spicc_setup_dma(struct meson_spicc_device *spicc)
304 {
305 unsigned int len;
306 unsigned int dma_burst_len, dma_burst_count;
307 unsigned int count_en = 0;
308 unsigned int txfifo_thres = 0;
309 unsigned int read_req = 0;
310 unsigned int rxfifo_thres = 31;
311 unsigned int write_req = 0;
312 unsigned int ld_ctr1 = 0;
313
314 writel_relaxed(spicc->tx_dma, spicc->base + SPICC_DRADDR);
315 writel_relaxed(spicc->rx_dma, spicc->base + SPICC_DWADDR);
316
317 /* Set the max burst length to support a transmission with length of
318 * no more than 1024 bytes(128 words), which must use the CS management
319 * because of some strict timing requirements
320 */
321 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, SPICC_BURSTLENGTH_MASK,
322 spicc->base + SPICC_CONREG);
323
324 len = meson_spicc_calc_dma_len(spicc, spicc->xfer_remain,
325 &dma_burst_len);
326 spicc->xfer_remain -= len;
327 dma_burst_count = DIV_ROUND_UP(len, dma_burst_len);
328 dma_burst_len--;
329
330 if (spicc->tx_dma) {
331 spicc->tx_dma += len;
332 count_en |= DMA_READ_COUNTER_EN;
333 txfifo_thres = spicc->data->fifo_size - dma_burst_len;
334 read_req = dma_burst_len;
335 ld_ctr1 |= FIELD_PREP(DMA_READ_COUNTER, dma_burst_count);
336 }
337
338 if (spicc->rx_dma) {
339 spicc->rx_dma += len;
340 count_en |= DMA_WRITE_COUNTER_EN;
341 rxfifo_thres = dma_burst_len;
342 write_req = dma_burst_len;
343 ld_ctr1 |= FIELD_PREP(DMA_WRITE_COUNTER, dma_burst_count);
344 }
345
346 writel_relaxed(count_en, spicc->base + SPICC_LD_CNTL0);
347 writel_relaxed(ld_ctr1, spicc->base + SPICC_LD_CNTL1);
348 writel_relaxed(SPICC_DMA_ENABLE
349 | SPICC_DMA_URGENT
350 | FIELD_PREP(SPICC_TXFIFO_THRESHOLD_MASK, txfifo_thres)
351 | FIELD_PREP(SPICC_READ_BURST_MASK, read_req)
352 | FIELD_PREP(SPICC_RXFIFO_THRESHOLD_MASK, rxfifo_thres)
353 | FIELD_PREP(SPICC_WRITE_BURST_MASK, write_req),
354 spicc->base + SPICC_DMAREG);
355 }
356
meson_spicc_dma_irq(struct meson_spicc_device * spicc)357 static irqreturn_t meson_spicc_dma_irq(struct meson_spicc_device *spicc)
358 {
359 if (readl_relaxed(spicc->base + SPICC_DMAREG) & SPICC_DMA_ENABLE)
360 return IRQ_HANDLED;
361
362 if (spicc->xfer_remain) {
363 meson_spicc_setup_dma(spicc);
364 } else {
365 writel_bits_relaxed(SPICC_SMC, 0, spicc->base + SPICC_CONREG);
366 writel_relaxed(0, spicc->base + SPICC_INTREG);
367 writel_relaxed(0, spicc->base + SPICC_DMAREG);
368 meson_spicc_dma_unmap(spicc, spicc->xfer);
369 complete(&spicc->done);
370 }
371
372 return IRQ_HANDLED;
373 }
374
meson_spicc_txfull(struct meson_spicc_device * spicc)375 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
376 {
377 return !!FIELD_GET(SPICC_TF,
378 readl_relaxed(spicc->base + SPICC_STATREG));
379 }
380
meson_spicc_rxready(struct meson_spicc_device * spicc)381 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
382 {
383 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
384 readl_relaxed(spicc->base + SPICC_STATREG));
385 }
386
meson_spicc_pull_data(struct meson_spicc_device * spicc)387 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
388 {
389 unsigned int bytes = spicc->bytes_per_word;
390 unsigned int byte_shift = 0;
391 u32 data = 0;
392 u8 byte;
393
394 while (bytes--) {
395 byte = *spicc->tx_buf++;
396 data |= (byte & 0xff) << byte_shift;
397 byte_shift += 8;
398 }
399
400 spicc->tx_remain--;
401 return data;
402 }
403
meson_spicc_push_data(struct meson_spicc_device * spicc,u32 data)404 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
405 u32 data)
406 {
407 unsigned int bytes = spicc->bytes_per_word;
408 unsigned int byte_shift = 0;
409 u8 byte;
410
411 while (bytes--) {
412 byte = (data >> byte_shift) & 0xff;
413 *spicc->rx_buf++ = byte;
414 byte_shift += 8;
415 }
416
417 spicc->rx_remain--;
418 }
419
meson_spicc_rx(struct meson_spicc_device * spicc)420 static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
421 {
422 /* Empty RX FIFO */
423 while (spicc->rx_remain &&
424 meson_spicc_rxready(spicc))
425 meson_spicc_push_data(spicc,
426 readl_relaxed(spicc->base + SPICC_RXDATA));
427 }
428
meson_spicc_tx(struct meson_spicc_device * spicc)429 static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
430 {
431 /* Fill Up TX FIFO */
432 while (spicc->tx_remain &&
433 !meson_spicc_txfull(spicc))
434 writel_relaxed(meson_spicc_pull_data(spicc),
435 spicc->base + SPICC_TXDATA);
436 }
437
meson_spicc_setup_burst(struct meson_spicc_device * spicc)438 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
439 {
440
441 unsigned int burst_len = min_t(unsigned int,
442 spicc->xfer_remain /
443 spicc->bytes_per_word,
444 spicc->data->fifo_size);
445 /* Setup Xfer variables */
446 spicc->tx_remain = burst_len;
447 spicc->rx_remain = burst_len;
448 spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
449
450 /* Setup burst length */
451 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
452 FIELD_PREP(SPICC_BURSTLENGTH_MASK,
453 burst_len - 1),
454 spicc->base + SPICC_CONREG);
455
456 /* Fill TX FIFO */
457 meson_spicc_tx(spicc);
458 }
459
meson_spicc_irq(int irq,void * data)460 static irqreturn_t meson_spicc_irq(int irq, void *data)
461 {
462 struct meson_spicc_device *spicc = (void *) data;
463
464 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
465
466 if (spicc->using_dma)
467 return meson_spicc_dma_irq(spicc);
468
469 /* Empty RX FIFO */
470 meson_spicc_rx(spicc);
471
472 if (!spicc->xfer_remain) {
473 /* Disable all IRQs */
474 writel(0, spicc->base + SPICC_INTREG);
475
476 complete(&spicc->done);
477
478 return IRQ_HANDLED;
479 }
480
481 /* Setup burst */
482 meson_spicc_setup_burst(spicc);
483
484 /* Start burst */
485 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
486
487 return IRQ_HANDLED;
488 }
489
meson_spicc_auto_io_delay(struct meson_spicc_device * spicc)490 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
491 {
492 u32 div, hz;
493 u32 mi_delay, cap_delay;
494 u32 conf;
495
496 if (spicc->data->has_enhance_clk_div) {
497 div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
498 readl_relaxed(spicc->base + SPICC_ENH_CTL0));
499 div++;
500 div <<= 1;
501 } else {
502 div = FIELD_GET(SPICC_DATARATE_MASK,
503 readl_relaxed(spicc->base + SPICC_CONREG));
504 div += 2;
505 div = 1 << div;
506 }
507
508 mi_delay = SPICC_MI_NO_DELAY;
509 cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
510 hz = clk_get_rate(spicc->clk);
511
512 if (hz >= 100000000)
513 cap_delay = SPICC_CAP_DELAY_1_CYCLE;
514 else if (hz >= 80000000)
515 cap_delay = SPICC_CAP_NO_DELAY;
516 else if (hz >= 40000000)
517 cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
518 else if (div >= 16)
519 mi_delay = SPICC_MI_DELAY_3_CYCLE;
520 else if (div >= 8)
521 mi_delay = SPICC_MI_DELAY_2_CYCLE;
522 else if (div >= 6)
523 mi_delay = SPICC_MI_DELAY_1_CYCLE;
524
525 conf = readl_relaxed(spicc->base + SPICC_TESTREG);
526 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
527 | SPICC_MI_CAP_DELAY_MASK);
528 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
529 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
530 writel_relaxed(conf, spicc->base + SPICC_TESTREG);
531 }
532
meson_spicc_setup_xfer(struct meson_spicc_device * spicc,struct spi_transfer * xfer)533 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
534 struct spi_transfer *xfer)
535 {
536 u32 conf, conf_orig;
537
538 /* Read original configuration */
539 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
540
541 /* Setup word width */
542 conf &= ~SPICC_BITLENGTH_MASK;
543 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
544 (spicc->bytes_per_word << 3) - 1);
545
546 /* Ignore if unchanged */
547 if (conf != conf_orig)
548 writel_relaxed(conf, spicc->base + SPICC_CONREG);
549
550 clk_set_rate(spicc->clk, xfer->speed_hz);
551
552 meson_spicc_auto_io_delay(spicc);
553
554 writel_relaxed(0, spicc->base + SPICC_DMAREG);
555 }
556
meson_spicc_reset_fifo(struct meson_spicc_device * spicc)557 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
558 {
559 if (spicc->data->has_oen)
560 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
561 SPICC_ENH_MAIN_CLK_AO,
562 spicc->base + SPICC_ENH_CTL0);
563
564 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
565 spicc->base + SPICC_TESTREG);
566
567 while (meson_spicc_rxready(spicc))
568 readl_relaxed(spicc->base + SPICC_RXDATA);
569
570 if (spicc->data->has_oen)
571 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
572 spicc->base + SPICC_ENH_CTL0);
573 }
574
meson_spicc_transfer_one(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * xfer)575 static int meson_spicc_transfer_one(struct spi_controller *host,
576 struct spi_device *spi,
577 struct spi_transfer *xfer)
578 {
579 struct meson_spicc_device *spicc = spi_controller_get_devdata(host);
580 uint64_t timeout;
581
582 /* Store current transfer */
583 spicc->xfer = xfer;
584
585 /* Setup transfer parameters */
586 spicc->tx_buf = (u8 *)xfer->tx_buf;
587 spicc->rx_buf = (u8 *)xfer->rx_buf;
588 spicc->xfer_remain = xfer->len;
589
590 /* Pre-calculate word size */
591 spicc->bytes_per_word =
592 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
593
594 if (xfer->len % spicc->bytes_per_word)
595 return -EINVAL;
596
597 /* Setup transfer parameters */
598 meson_spicc_setup_xfer(spicc, xfer);
599
600 meson_spicc_reset_fifo(spicc);
601
602 /* Setup wait for completion */
603 reinit_completion(&spicc->done);
604
605 /* For each byte we wait for 8 cycles of the SPI clock */
606 timeout = 8LL * MSEC_PER_SEC * xfer->len;
607 do_div(timeout, xfer->speed_hz);
608
609 /* Add 10us delay between each fifo bursts */
610 timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;
611
612 /* Increase it twice and add 200 ms tolerance */
613 timeout += timeout + 200;
614
615 if (xfer->bits_per_word == 64) {
616 int ret;
617
618 /* dma_burst_len 1 can't trigger a dma burst */
619 if (xfer->len < 16)
620 return -EINVAL;
621
622 ret = meson_spicc_dma_map(spicc, xfer);
623 if (ret) {
624 meson_spicc_dma_unmap(spicc, xfer);
625 dev_err(host->dev.parent, "dma map failed\n");
626 return ret;
627 }
628
629 spicc->using_dma = true;
630 spicc->xfer_remain = DIV_ROUND_UP(xfer->len, spicc->bytes_per_word);
631 meson_spicc_setup_dma(spicc);
632 writel_relaxed(SPICC_TE_EN, spicc->base + SPICC_INTREG);
633 writel_bits_relaxed(SPICC_SMC, SPICC_SMC, spicc->base + SPICC_CONREG);
634 } else {
635 spicc->using_dma = false;
636 /* Setup burst */
637 meson_spicc_setup_burst(spicc);
638
639 /* Start burst */
640 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
641
642 /* Enable interrupts */
643 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
644 }
645
646 if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))
647 return -ETIMEDOUT;
648
649 return 0;
650 }
651
meson_spicc_prepare_message(struct spi_controller * host,struct spi_message * message)652 static int meson_spicc_prepare_message(struct spi_controller *host,
653 struct spi_message *message)
654 {
655 struct meson_spicc_device *spicc = spi_controller_get_devdata(host);
656 struct spi_device *spi = message->spi;
657 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
658
659 /* Store current message */
660 spicc->message = message;
661
662 /* Enable Master */
663 conf |= SPICC_ENABLE;
664 conf |= SPICC_MODE_MASTER;
665
666 /* SMC = 0 */
667
668 /* Setup transfer mode */
669 if (spi->mode & SPI_CPOL)
670 conf |= SPICC_POL;
671 else
672 conf &= ~SPICC_POL;
673
674 if (!spicc->data->has_oen) {
675 if (spi->mode & SPI_CPOL) {
676 if (spicc->pins_idle_high)
677 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high);
678 } else {
679 if (spicc->pins_idle_low)
680 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low);
681 }
682 }
683
684 if (spi->mode & SPI_CPHA)
685 conf |= SPICC_PHA;
686 else
687 conf &= ~SPICC_PHA;
688
689 /* SSCTL = 0 */
690
691 if (spi->mode & SPI_CS_HIGH)
692 conf |= SPICC_SSPOL;
693 else
694 conf &= ~SPICC_SSPOL;
695
696 if (spi->mode & SPI_READY)
697 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
698 else
699 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
700
701 /* Select CS */
702 conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0));
703
704 /* Default 8bit word */
705 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
706
707 writel_relaxed(conf, spicc->base + SPICC_CONREG);
708
709 /* Setup no wait cycles by default */
710 writel_relaxed(0, spicc->base + SPICC_PERIODREG);
711
712 writel_bits_relaxed(SPICC_LBC_W1,
713 spi->mode & SPI_LOOP ? SPICC_LBC_W1 : 0,
714 spicc->base + SPICC_TESTREG);
715
716 return 0;
717 }
718
meson_spicc_unprepare_transfer(struct spi_controller * host)719 static int meson_spicc_unprepare_transfer(struct spi_controller *host)
720 {
721 struct meson_spicc_device *spicc = spi_controller_get_devdata(host);
722 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
723
724 /* Disable all IRQs */
725 writel(0, spicc->base + SPICC_INTREG);
726
727 device_reset_optional(&spicc->pdev->dev);
728
729 /* Set default configuration, keeping datarate field */
730 writel_relaxed(conf, spicc->base + SPICC_CONREG);
731
732 if (!spicc->data->has_oen)
733 pinctrl_select_default_state(&spicc->pdev->dev);
734
735 return 0;
736 }
737
meson_spicc_setup(struct spi_device * spi)738 static int meson_spicc_setup(struct spi_device *spi)
739 {
740 if (!spi->controller_state)
741 spi->controller_state = spi_controller_get_devdata(spi->controller);
742
743 /* DMA works at 64 bits, the rest works on PIO */
744 if (spi->bits_per_word != 8 &&
745 spi->bits_per_word != 16 &&
746 spi->bits_per_word != 24 &&
747 spi->bits_per_word != 32 &&
748 spi->bits_per_word != 64)
749 return -EINVAL;
750
751 return 0;
752 }
753
meson_spicc_cleanup(struct spi_device * spi)754 static void meson_spicc_cleanup(struct spi_device *spi)
755 {
756 spi->controller_state = NULL;
757 }
758
759 /*
760 * The Clock Mux
761 * x-----------------x x------------x x------\
762 * |---| pow2 fixed div |---| pow2 div |----| |
763 * | x-----------------x x------------x | |
764 * src ---| | mux |-- out
765 * | x-----------------x x------------x | |
766 * |---| enh fixed div |---| enh div |0---| |
767 * x-----------------x x------------x x------/
768 *
769 * Clk path for GX series:
770 * src -> pow2 fixed div -> pow2 div -> out
771 *
772 * Clk path for AXG series:
773 * src -> pow2 fixed div -> pow2 div -> mux -> out
774 * src -> enh fixed div -> enh div -> mux -> out
775 *
776 * Clk path for G12A series:
777 * pclk -> pow2 fixed div -> pow2 div -> mux -> out
778 * pclk -> enh fixed div -> enh div -> mux -> out
779 *
780 * The pow2 divider is tied to the controller HW state, and the
781 * divider is only valid when the controller is initialized.
782 *
783 * A set of clock ops is added to make sure we don't read/set this
784 * clock rate while the controller is in an unknown state.
785 */
786
meson_spicc_pow2_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)787 static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
788 unsigned long parent_rate)
789 {
790 struct clk_divider *divider = to_clk_divider(hw);
791 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
792
793 if (!spicc->host->cur_msg)
794 return 0;
795
796 return clk_divider_ops.recalc_rate(hw, parent_rate);
797 }
798
meson_spicc_pow2_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)799 static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
800 struct clk_rate_request *req)
801 {
802 struct clk_divider *divider = to_clk_divider(hw);
803 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
804
805 if (!spicc->host->cur_msg)
806 return -EINVAL;
807
808 return clk_divider_ops.determine_rate(hw, req);
809 }
810
meson_spicc_pow2_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)811 static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
812 unsigned long parent_rate)
813 {
814 struct clk_divider *divider = to_clk_divider(hw);
815 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
816
817 if (!spicc->host->cur_msg)
818 return -EINVAL;
819
820 return clk_divider_ops.set_rate(hw, rate, parent_rate);
821 }
822
823 static const struct clk_ops meson_spicc_pow2_clk_ops = {
824 .recalc_rate = meson_spicc_pow2_recalc_rate,
825 .determine_rate = meson_spicc_pow2_determine_rate,
826 .set_rate = meson_spicc_pow2_set_rate,
827 };
828
meson_spicc_pow2_clk_init(struct meson_spicc_device * spicc)829 static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
830 {
831 struct device *dev = &spicc->pdev->dev;
832 struct clk_fixed_factor *pow2_fixed_div;
833 struct clk_init_data init;
834 struct clk *clk;
835 struct clk_parent_data parent_data[2];
836 char name[64];
837
838 memset(&init, 0, sizeof(init));
839 memset(&parent_data, 0, sizeof(parent_data));
840
841 init.parent_data = parent_data;
842
843 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
844
845 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
846 if (!pow2_fixed_div)
847 return -ENOMEM;
848
849 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
850 init.name = name;
851 init.ops = &clk_fixed_factor_ops;
852 if (spicc->data->has_pclk) {
853 init.flags = CLK_SET_RATE_PARENT;
854 parent_data[0].hw = __clk_get_hw(spicc->pclk);
855 } else {
856 init.flags = 0;
857 parent_data[0].hw = __clk_get_hw(spicc->core);
858 }
859 init.num_parents = 1;
860
861 pow2_fixed_div->mult = 1;
862 pow2_fixed_div->div = 4;
863 pow2_fixed_div->hw.init = &init;
864
865 clk = devm_clk_register(dev, &pow2_fixed_div->hw);
866 if (WARN_ON(IS_ERR(clk)))
867 return PTR_ERR(clk);
868
869 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
870 init.name = name;
871 init.ops = &meson_spicc_pow2_clk_ops;
872 /*
873 * Set NOCACHE here to make sure we read the actual HW value
874 * since we reset the HW after each transfer.
875 */
876 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
877 parent_data[0].hw = &pow2_fixed_div->hw;
878 init.num_parents = 1;
879
880 spicc->pow2_div.shift = 16;
881 spicc->pow2_div.width = 3;
882 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO;
883 spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
884 spicc->pow2_div.hw.init = &init;
885
886 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
887 if (WARN_ON(IS_ERR(spicc->clk)))
888 return PTR_ERR(spicc->clk);
889
890 return 0;
891 }
892
meson_spicc_enh_clk_init(struct meson_spicc_device * spicc)893 static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
894 {
895 struct device *dev = &spicc->pdev->dev;
896 struct clk_fixed_factor *enh_fixed_div;
897 struct clk_divider *enh_div;
898 struct clk_mux *mux;
899 struct clk_init_data init;
900 struct clk *clk;
901 struct clk_parent_data parent_data[2];
902 char name[64];
903
904 memset(&init, 0, sizeof(init));
905 memset(&parent_data, 0, sizeof(parent_data));
906
907 init.parent_data = parent_data;
908
909 /* algorithm for enh div: rate = freq / 2 / (N + 1) */
910
911 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
912 if (!enh_fixed_div)
913 return -ENOMEM;
914
915 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
916 init.name = name;
917 init.ops = &clk_fixed_factor_ops;
918 if (spicc->data->has_pclk) {
919 init.flags = CLK_SET_RATE_PARENT;
920 parent_data[0].hw = __clk_get_hw(spicc->pclk);
921 } else {
922 init.flags = 0;
923 parent_data[0].hw = __clk_get_hw(spicc->core);
924 }
925 init.num_parents = 1;
926
927 enh_fixed_div->mult = 1;
928 enh_fixed_div->div = 2;
929 enh_fixed_div->hw.init = &init;
930
931 clk = devm_clk_register(dev, &enh_fixed_div->hw);
932 if (WARN_ON(IS_ERR(clk)))
933 return PTR_ERR(clk);
934
935 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
936 if (!enh_div)
937 return -ENOMEM;
938
939 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
940 init.name = name;
941 init.ops = &clk_divider_ops;
942 init.flags = CLK_SET_RATE_PARENT;
943 parent_data[0].hw = &enh_fixed_div->hw;
944 init.num_parents = 1;
945
946 enh_div->shift = 16;
947 enh_div->width = 8;
948 enh_div->reg = spicc->base + SPICC_ENH_CTL0;
949 enh_div->hw.init = &init;
950
951 clk = devm_clk_register(dev, &enh_div->hw);
952 if (WARN_ON(IS_ERR(clk)))
953 return PTR_ERR(clk);
954
955 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
956 if (!mux)
957 return -ENOMEM;
958
959 snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
960 init.name = name;
961 init.ops = &clk_mux_ops;
962 parent_data[0].hw = &spicc->pow2_div.hw;
963 parent_data[1].hw = &enh_div->hw;
964 init.num_parents = 2;
965 init.flags = CLK_SET_RATE_PARENT;
966
967 mux->mask = 0x1;
968 mux->shift = 24;
969 mux->reg = spicc->base + SPICC_ENH_CTL0;
970 mux->hw.init = &init;
971
972 spicc->clk = devm_clk_register(dev, &mux->hw);
973 if (WARN_ON(IS_ERR(spicc->clk)))
974 return PTR_ERR(spicc->clk);
975
976 return 0;
977 }
978
meson_spicc_probe(struct platform_device * pdev)979 static int meson_spicc_probe(struct platform_device *pdev)
980 {
981 struct spi_controller *host;
982 struct meson_spicc_device *spicc;
983 int ret, irq;
984
985 host = spi_alloc_host(&pdev->dev, sizeof(*spicc));
986 if (!host) {
987 dev_err(&pdev->dev, "host allocation failed\n");
988 return -ENOMEM;
989 }
990 spicc = spi_controller_get_devdata(host);
991 spicc->host = host;
992
993 spicc->data = of_device_get_match_data(&pdev->dev);
994 if (!spicc->data) {
995 dev_err(&pdev->dev, "failed to get match data\n");
996 ret = -EINVAL;
997 goto out_host;
998 }
999
1000 spicc->pdev = pdev;
1001 platform_set_drvdata(pdev, spicc);
1002
1003 init_completion(&spicc->done);
1004
1005 spicc->base = devm_platform_ioremap_resource(pdev, 0);
1006 if (IS_ERR(spicc->base)) {
1007 dev_err(&pdev->dev, "io resource mapping failed\n");
1008 ret = PTR_ERR(spicc->base);
1009 goto out_host;
1010 }
1011
1012 /* Set master mode and enable controller */
1013 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
1014 spicc->base + SPICC_CONREG);
1015
1016 /* Disable all IRQs */
1017 writel_relaxed(0, spicc->base + SPICC_INTREG);
1018
1019 irq = platform_get_irq(pdev, 0);
1020 if (irq < 0) {
1021 ret = irq;
1022 goto out_host;
1023 }
1024
1025 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
1026 0, NULL, spicc);
1027 if (ret) {
1028 dev_err(&pdev->dev, "irq request failed\n");
1029 goto out_host;
1030 }
1031
1032 spicc->core = devm_clk_get_enabled(&pdev->dev, "core");
1033 if (IS_ERR(spicc->core)) {
1034 dev_err(&pdev->dev, "core clock request failed\n");
1035 ret = PTR_ERR(spicc->core);
1036 goto out_host;
1037 }
1038
1039 if (spicc->data->has_pclk) {
1040 spicc->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
1041 if (IS_ERR(spicc->pclk)) {
1042 dev_err(&pdev->dev, "pclk clock request failed\n");
1043 ret = PTR_ERR(spicc->pclk);
1044 goto out_host;
1045 }
1046 }
1047
1048 spicc->pinctrl = devm_pinctrl_get(&pdev->dev);
1049 if (IS_ERR(spicc->pinctrl)) {
1050 ret = PTR_ERR(spicc->pinctrl);
1051 goto out_host;
1052 }
1053
1054 device_reset_optional(&pdev->dev);
1055
1056 host->num_chipselect = 4;
1057 host->dev.of_node = pdev->dev.of_node;
1058 host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LOOP;
1059 host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX);
1060 host->min_speed_hz = spicc->data->min_speed_hz;
1061 host->max_speed_hz = spicc->data->max_speed_hz;
1062 host->setup = meson_spicc_setup;
1063 host->cleanup = meson_spicc_cleanup;
1064 host->prepare_message = meson_spicc_prepare_message;
1065 host->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
1066 host->transfer_one = meson_spicc_transfer_one;
1067 host->use_gpio_descriptors = true;
1068
1069 meson_spicc_oen_enable(spicc);
1070
1071 ret = meson_spicc_pow2_clk_init(spicc);
1072 if (ret) {
1073 dev_err(&pdev->dev, "pow2 clock registration failed\n");
1074 goto out_host;
1075 }
1076
1077 if (spicc->data->has_enhance_clk_div) {
1078 ret = meson_spicc_enh_clk_init(spicc);
1079 if (ret) {
1080 dev_err(&pdev->dev, "clock registration failed\n");
1081 goto out_host;
1082 }
1083 }
1084
1085 ret = devm_spi_register_controller(&pdev->dev, host);
1086 if (ret) {
1087 dev_err(&pdev->dev, "spi registration failed\n");
1088 goto out_host;
1089 }
1090
1091 return 0;
1092
1093 out_host:
1094 spi_controller_put(host);
1095
1096 return ret;
1097 }
1098
meson_spicc_remove(struct platform_device * pdev)1099 static void meson_spicc_remove(struct platform_device *pdev)
1100 {
1101 struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
1102
1103 /* Disable SPI */
1104 writel(0, spicc->base + SPICC_CONREG);
1105
1106 spi_controller_put(spicc->host);
1107 }
1108
1109 static const struct meson_spicc_data meson_spicc_gx_data = {
1110 .max_speed_hz = 30000000,
1111 .min_speed_hz = 325000,
1112 .fifo_size = 16,
1113 };
1114
1115 static const struct meson_spicc_data meson_spicc_axg_data = {
1116 .max_speed_hz = 80000000,
1117 .min_speed_hz = 325000,
1118 .fifo_size = 16,
1119 .has_oen = true,
1120 .has_enhance_clk_div = true,
1121 };
1122
1123 static const struct meson_spicc_data meson_spicc_g12a_data = {
1124 .max_speed_hz = 166666666,
1125 .min_speed_hz = 50000,
1126 .fifo_size = 15,
1127 .has_oen = true,
1128 .has_enhance_clk_div = true,
1129 .has_pclk = true,
1130 };
1131
1132 static const struct of_device_id meson_spicc_of_match[] = {
1133 {
1134 .compatible = "amlogic,meson-gx-spicc",
1135 .data = &meson_spicc_gx_data,
1136 },
1137 {
1138 .compatible = "amlogic,meson-axg-spicc",
1139 .data = &meson_spicc_axg_data,
1140 },
1141 {
1142 .compatible = "amlogic,meson-g12a-spicc",
1143 .data = &meson_spicc_g12a_data,
1144 },
1145 { /* sentinel */ }
1146 };
1147 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
1148
1149 static struct platform_driver meson_spicc_driver = {
1150 .probe = meson_spicc_probe,
1151 .remove = meson_spicc_remove,
1152 .driver = {
1153 .name = "meson-spicc",
1154 .of_match_table = of_match_ptr(meson_spicc_of_match),
1155 },
1156 };
1157
1158 module_platform_driver(meson_spicc_driver);
1159
1160 MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
1161 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
1162 MODULE_LICENSE("GPL");
1163