1 /*
2 * Copyright 2025 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include "amdgpu.h"
27 #include "soc15_common.h"
28 #include "soc_v1_0.h"
29 #include "gc/gc_12_1_0_offset.h"
30 #include "gc/gc_12_1_0_sh_mask.h"
31 #include "gc/gc_11_0_0_default.h"
32 #include "v12_structs.h"
33 #include "mes_v12_api_def.h"
34 #include "gfx_v12_1_pkt.h"
35 #include "sdma_v7_1_0_pkt_open.h"
36
37 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin");
38 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin");
39 MODULE_FIRMWARE("amdgpu/gc_12_1_0_uni_mes.bin");
40
41 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block);
42 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id);
43 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block);
44 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
45 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
46 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id);
47
48 #define MES_EOP_SIZE 2048
49 #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */
50 #define MES12_HUNG_HQD_INFO_OFFSET 4
51
52 #define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000
53 #define XCC_MID_MASK 0x41000000
54
mes_v12_1_ring_set_wptr(struct amdgpu_ring * ring)55 static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring)
56 {
57 struct amdgpu_device *adev = ring->adev;
58
59 if (ring->use_doorbell) {
60 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
61 ring->wptr);
62 WDOORBELL64(ring->doorbell_index, ring->wptr);
63 } else {
64 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__);
65 }
66 }
67
mes_v12_1_ring_get_rptr(struct amdgpu_ring * ring)68 static u64 mes_v12_1_ring_get_rptr(struct amdgpu_ring *ring)
69 {
70 return *ring->rptr_cpu_addr;
71 }
72
mes_v12_1_ring_get_wptr(struct amdgpu_ring * ring)73 static u64 mes_v12_1_ring_get_wptr(struct amdgpu_ring *ring)
74 {
75 struct amdgpu_device *adev = ring->adev;
76 u64 wptr;
77
78 if (ring->use_doorbell) {
79 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
80 } else {
81 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__);
82 wptr = 0;
83
84 }
85 return wptr;
86 }
87
88 static const struct amdgpu_ring_funcs mes_v12_1_ring_funcs = {
89 .type = AMDGPU_RING_TYPE_MES,
90 .align_mask = 1,
91 .nop = 0,
92 .support_64bit_ptrs = true,
93 .get_rptr = mes_v12_1_ring_get_rptr,
94 .get_wptr = mes_v12_1_ring_get_wptr,
95 .set_wptr = mes_v12_1_ring_set_wptr,
96 .insert_nop = amdgpu_ring_insert_nop,
97 };
98
99 static const char *mes_v12_1_opcodes[] = {
100 "SET_HW_RSRC",
101 "SET_SCHEDULING_CONFIG",
102 "ADD_QUEUE",
103 "REMOVE_QUEUE",
104 "PERFORM_YIELD",
105 "SET_GANG_PRIORITY_LEVEL",
106 "SUSPEND",
107 "RESUME",
108 "RESET",
109 "SET_LOG_BUFFER",
110 "CHANGE_GANG_PRORITY",
111 "QUERY_SCHEDULER_STATUS",
112 "unused",
113 "SET_DEBUG_VMID",
114 "MISC",
115 "UPDATE_ROOT_PAGE_TABLE",
116 "AMD_LOG",
117 "SET_SE_MODE",
118 "SET_GANG_SUBMIT",
119 "SET_HW_RSRC_1",
120 "INVALIDATE_TLBS",
121 };
122
123 static const char *mes_v12_1_misc_opcodes[] = {
124 "WRITE_REG",
125 "INV_GART",
126 "QUERY_STATUS",
127 "READ_REG",
128 "WAIT_REG_MEM",
129 "SET_SHADER_DEBUGGER",
130 "NOTIFY_WORK_ON_UNMAPPED_QUEUE",
131 "NOTIFY_TO_UNMAP_PROCESSES",
132 };
133
mes_v12_1_get_op_string(union MESAPI__MISC * x_pkt)134 static const char *mes_v12_1_get_op_string(union MESAPI__MISC *x_pkt)
135 {
136 const char *op_str = NULL;
137
138 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_1_opcodes))
139 op_str = mes_v12_1_opcodes[x_pkt->header.opcode];
140
141 return op_str;
142 }
143
mes_v12_1_get_misc_op_string(union MESAPI__MISC * x_pkt)144 static const char *mes_v12_1_get_misc_op_string(union MESAPI__MISC *x_pkt)
145 {
146 const char *op_str = NULL;
147
148 if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
149 (x_pkt->opcode < ARRAY_SIZE(mes_v12_1_misc_opcodes)))
150 op_str = mes_v12_1_misc_opcodes[x_pkt->opcode];
151
152 return op_str;
153 }
154
mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,int xcc_id,int pipe,void * pkt,int size,int api_status_off)155 static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
156 int xcc_id, int pipe, void *pkt,
157 int size, int api_status_off)
158 {
159 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
160 signed long timeout = 2100000; /* 2100 ms */
161 struct amdgpu_device *adev = mes->adev;
162 struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)];
163 spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)];
164 struct MES_API_STATUS *api_status;
165 union MESAPI__MISC *x_pkt = pkt;
166 const char *op_str, *misc_op_str;
167 unsigned long flags;
168 u64 status_gpu_addr;
169 u32 seq, status_offset;
170 u64 *status_ptr;
171 signed long r;
172 int ret;
173
174 if (x_pkt->header.opcode >= MES_SCH_API_MAX)
175 return -EINVAL;
176
177 if (amdgpu_emu_mode) {
178 timeout *= 1000;
179 } else if (amdgpu_sriov_vf(adev)) {
180 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
181 timeout = 15 * 600 * 1000;
182 }
183
184 ret = amdgpu_wb_get(adev, &status_offset);
185 if (ret)
186 return ret;
187
188 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
189 status_ptr = (u64 *)&adev->wb.wb[status_offset];
190 *status_ptr = 0;
191
192 spin_lock_irqsave(ring_lock, flags);
193 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
194 if (r)
195 goto error_unlock_free;
196
197 seq = ++ring->fence_drv.sync_seq;
198 r = amdgpu_fence_wait_polling(ring,
199 seq - ring->fence_drv.num_fences_mask,
200 timeout);
201 if (r < 1)
202 goto error_undo;
203
204 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
205 api_status->api_completion_fence_addr = status_gpu_addr;
206 api_status->api_completion_fence_value = 1;
207
208 amdgpu_ring_write_multiple(ring, pkt, size / 4);
209
210 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
211 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
212 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
213 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
214 mes_status_pkt.api_status.api_completion_fence_addr =
215 ring->fence_drv.gpu_addr;
216 mes_status_pkt.api_status.api_completion_fence_value = seq;
217
218 amdgpu_ring_write_multiple(ring, &mes_status_pkt,
219 sizeof(mes_status_pkt) / 4);
220
221 amdgpu_ring_commit(ring);
222 spin_unlock_irqrestore(ring_lock, flags);
223
224 op_str = mes_v12_1_get_op_string(x_pkt);
225 misc_op_str = mes_v12_1_get_misc_op_string(x_pkt);
226
227 if (misc_op_str)
228 dev_dbg(adev->dev, "MES(%d, %d) msg=%s (%s) was emitted\n",
229 xcc_id, pipe, op_str, misc_op_str);
230 else if (op_str)
231 dev_dbg(adev->dev, "MES(%d, %d) msg=%s was emitted\n",
232 xcc_id, pipe, op_str);
233 else
234 dev_dbg(adev->dev, "MES(%d, %d) msg=%d was emitted\n",
235 xcc_id, pipe, x_pkt->header.opcode);
236
237 r = amdgpu_fence_wait_polling(ring, seq, timeout);
238 if (r < 1 || !lower_32_bits(*status_ptr)) {
239 if (misc_op_str)
240 dev_err(adev->dev,
241 "MES(%d, %d) failed to respond to msg=%s (%s)\n",
242 xcc_id, pipe, op_str, misc_op_str);
243 else if (op_str)
244 dev_err(adev->dev,
245 "MES(%d, %d) failed to respond to msg=%s\n",
246 xcc_id, pipe, op_str);
247 else
248 dev_err(adev->dev,
249 "MES(%d, %d) failed to respond to msg=%d\n",
250 xcc_id, pipe, x_pkt->header.opcode);
251
252 while (halt_if_hws_hang)
253 schedule();
254
255 r = -ETIMEDOUT;
256 goto error_wb_free;
257 }
258
259 amdgpu_wb_free(adev, status_offset);
260 return 0;
261
262 error_undo:
263 dev_err(adev->dev, "MES(%d, %d) ring buffer is full.\n", xcc_id, pipe);
264 amdgpu_ring_undo(ring);
265
266 error_unlock_free:
267 spin_unlock_irqrestore(ring_lock, flags);
268
269 error_wb_free:
270 amdgpu_wb_free(adev, status_offset);
271 return r;
272 }
273
convert_to_mes_queue_type(int queue_type)274 static int convert_to_mes_queue_type(int queue_type)
275 {
276 if (queue_type == AMDGPU_RING_TYPE_GFX)
277 return MES_QUEUE_TYPE_GFX;
278 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
279 return MES_QUEUE_TYPE_COMPUTE;
280 else if (queue_type == AMDGPU_RING_TYPE_SDMA)
281 return MES_QUEUE_TYPE_SDMA;
282 else if (queue_type == AMDGPU_RING_TYPE_MES)
283 return MES_QUEUE_TYPE_SCHQ;
284 else
285 WARN(1, "Invalid queue type %d\n", queue_type);
286 return MES_QUEUE_TYPE_GFX;
287 }
288
mes_v12_1_add_hw_queue(struct amdgpu_mes * mes,struct mes_add_queue_input * input)289 static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes,
290 struct mes_add_queue_input *input)
291 {
292 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
293 int xcc_id = input->xcc_id;
294 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
295
296 if (mes->enable_coop_mode)
297 xcc_id = mes->master_xcc_ids[inst];
298
299 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
300
301 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
302 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
303 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
304
305 mes_add_queue_pkt.process_id = input->process_id;
306 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
307 mes_add_queue_pkt.process_va_start = input->process_va_start;
308 mes_add_queue_pkt.process_va_end = input->process_va_end;
309 mes_add_queue_pkt.process_quantum = input->process_quantum;
310 mes_add_queue_pkt.process_context_addr = input->process_context_addr;
311 mes_add_queue_pkt.gang_quantum = input->gang_quantum;
312 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
313 mes_add_queue_pkt.inprocess_gang_priority =
314 input->inprocess_gang_priority;
315 mes_add_queue_pkt.gang_global_priority_level =
316 input->gang_global_priority_level;
317 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
318 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
319
320 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
321
322 mes_add_queue_pkt.queue_type =
323 convert_to_mes_queue_type(input->queue_type);
324 mes_add_queue_pkt.paging = input->paging;
325 mes_add_queue_pkt.vm_context_cntl = input->vm_cntx_cntl;
326 mes_add_queue_pkt.gws_base = input->gws_base;
327 mes_add_queue_pkt.gws_size = input->gws_size;
328 mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
329 mes_add_queue_pkt.tma_addr = input->tma_addr;
330 mes_add_queue_pkt.trap_en = input->trap_en;
331 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
332 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
333
334 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
335 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
336 mes_add_queue_pkt.gds_size = input->queue_size;
337
338 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
339 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
340 mes_add_queue_pkt.gds_size = input->queue_size;
341
342 mes_add_queue_pkt.full_sh_mem_config_data = input->sh_mem_config_data;
343
344 return mes_v12_1_submit_pkt_and_poll_completion(mes,
345 xcc_id, AMDGPU_MES_SCHED_PIPE,
346 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
347 offsetof(union MESAPI__ADD_QUEUE, api_status));
348 }
349
mes_v12_1_remove_hw_queue(struct amdgpu_mes * mes,struct mes_remove_queue_input * input)350 static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes,
351 struct mes_remove_queue_input *input)
352 {
353 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
354 int xcc_id = input->xcc_id;
355 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
356
357 if (mes->enable_coop_mode)
358 xcc_id = mes->master_xcc_ids[inst];
359
360 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
361
362 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
363 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
364 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
365
366 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
367 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
368 mes_remove_queue_pkt.queue_type =
369 convert_to_mes_queue_type(input->queue_type);
370
371 return mes_v12_1_submit_pkt_and_poll_completion(mes,
372 xcc_id, AMDGPU_MES_SCHED_PIPE,
373 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
374 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
375 }
376
mes_v12_1_reset_hw_queue(struct amdgpu_mes * mes,struct mes_reset_queue_input * input)377 static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes,
378 struct mes_reset_queue_input *input)
379 {
380 union MESAPI__RESET mes_reset_queue_pkt;
381 int pipe;
382
383 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
384
385 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
386 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
387 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
388
389 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
390 /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */
391 /*mes_reset_queue_pkt.reset_queue_only = 1;*/
392
393 if (mes->adev->enable_uni_mes)
394 pipe = AMDGPU_MES_KIQ_PIPE;
395 else
396 pipe = AMDGPU_MES_SCHED_PIPE;
397
398 return mes_v12_1_submit_pkt_and_poll_completion(mes,
399 input->xcc_id, pipe,
400 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
401 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
402 }
403
mes_v12_1_map_legacy_queue(struct amdgpu_mes * mes,struct mes_map_legacy_queue_input * input)404 static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes,
405 struct mes_map_legacy_queue_input *input)
406 {
407 union MESAPI__ADD_QUEUE mes_add_queue_pkt;
408 int pipe;
409
410 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
411
412 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
413 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
414 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
415
416 mes_add_queue_pkt.pipe_id = input->pipe_id;
417 mes_add_queue_pkt.queue_id = input->queue_id;
418 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
419 mes_add_queue_pkt.mqd_addr = input->mqd_addr;
420 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
421 mes_add_queue_pkt.queue_type =
422 convert_to_mes_queue_type(input->queue_type);
423 mes_add_queue_pkt.map_legacy_kq = 1;
424
425 if (mes->adev->enable_uni_mes) {
426 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */
427 if (input->queue_type == AMDGPU_RING_TYPE_MES)
428 pipe = AMDGPU_MES_KIQ_PIPE;
429 else
430 pipe = AMDGPU_MES_SCHED_PIPE;
431 } else {
432 pipe = AMDGPU_MES_SCHED_PIPE;
433 }
434
435 return mes_v12_1_submit_pkt_and_poll_completion(mes,
436 input->xcc_id, pipe,
437 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
438 offsetof(union MESAPI__ADD_QUEUE, api_status));
439 }
440
mes_v12_1_unmap_legacy_queue(struct amdgpu_mes * mes,struct mes_unmap_legacy_queue_input * input)441 static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes,
442 struct mes_unmap_legacy_queue_input *input)
443 {
444 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
445 int pipe;
446
447 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
448
449 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
450 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
451 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
452
453 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
454 mes_remove_queue_pkt.gang_context_addr = 0;
455
456 mes_remove_queue_pkt.pipe_id = input->pipe_id;
457 mes_remove_queue_pkt.queue_id = input->queue_id;
458
459 if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
460 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
461 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
462 mes_remove_queue_pkt.tf_data =
463 lower_32_bits(input->trail_fence_data);
464 } else {
465 mes_remove_queue_pkt.unmap_legacy_queue = 1;
466 mes_remove_queue_pkt.queue_type =
467 convert_to_mes_queue_type(input->queue_type);
468 }
469
470 if (mes->adev->enable_uni_mes) {
471 /* Keep scheduler queue on KIQ pipe; map all other kernel queues on sched pipe. */
472 if (input->queue_type == AMDGPU_RING_TYPE_MES)
473 pipe = AMDGPU_MES_KIQ_PIPE;
474 else
475 pipe = AMDGPU_MES_SCHED_PIPE;
476 } else {
477 pipe = AMDGPU_MES_SCHED_PIPE;
478 }
479
480 return mes_v12_1_submit_pkt_and_poll_completion(mes,
481 input->xcc_id, pipe,
482 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
483 offsetof(union MESAPI__REMOVE_QUEUE, api_status));
484 }
485
mes_v12_1_suspend_gang(struct amdgpu_mes * mes,struct mes_suspend_gang_input * input)486 static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes,
487 struct mes_suspend_gang_input *input)
488 {
489 union MESAPI__SUSPEND mes_suspend_gang_pkt;
490
491 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt));
492
493 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
494 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND;
495 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
496
497 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs;
498 mes_suspend_gang_pkt.suspend_all_sdma_gangs = input->suspend_all_sdma_gangs;
499 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr;
500 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr;
501 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value;
502 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset;
503
504 /* Suspend gang is handled by master MES */
505 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE,
506 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt),
507 offsetof(union MESAPI__SUSPEND, api_status));
508 }
509
mes_v12_1_resume_gang(struct amdgpu_mes * mes,struct mes_resume_gang_input * input)510 static int mes_v12_1_resume_gang(struct amdgpu_mes *mes,
511 struct mes_resume_gang_input *input)
512 {
513 union MESAPI__RESUME mes_resume_gang_pkt;
514
515 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt));
516
517 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER;
518 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME;
519 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
520
521 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs;
522 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr;
523 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset;
524
525 /* Resume gang is handled by master MES */
526 return mes_v12_1_submit_pkt_and_poll_completion(mes, input->xcc_id, AMDGPU_MES_SCHED_PIPE,
527 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt),
528 offsetof(union MESAPI__RESUME, api_status));
529 }
530
mes_v12_1_query_sched_status(struct amdgpu_mes * mes,int pipe,int xcc_id)531 static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes,
532 int pipe, int xcc_id)
533 {
534 union MESAPI__QUERY_MES_STATUS mes_status_pkt;
535
536 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
537
538 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
539 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
540 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
541
542 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
543 &mes_status_pkt, sizeof(mes_status_pkt),
544 offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
545 }
mes_v12_1_get_xcc_from_reg(uint32_t reg_offset)546 static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset)
547 {
548 return ((reg_offset >> 16) & 0x7);
549 }
550
mes_v12_1_get_rrmt(uint32_t reg,uint32_t xcc_id,struct RRMT_OPTION * rrmt_opt,uint32_t * out_reg)551 static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id,
552 struct RRMT_OPTION *rrmt_opt,
553 uint32_t *out_reg)
554 {
555 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
556
557 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) {
558 rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg);
559 rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ?
560 MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD;
561 } else {
562 rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID;
563 if (soc_v1_0_mid1_reg_range(reg))
564 rrmt_opt->mid_die_id = 1;
565 }
566
567 *out_reg = soc_v1_0_normalize_reg_offset(reg);
568 }
569
mes_v12_1_misc_op(struct amdgpu_mes * mes,struct mes_misc_op_input * input)570 static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
571 struct mes_misc_op_input *input)
572 {
573 struct amdgpu_device *adev = mes->adev;
574 union MESAPI__MISC misc_pkt;
575 int pipe;
576
577 if (mes->adev->enable_uni_mes)
578 pipe = AMDGPU_MES_KIQ_PIPE;
579 else
580 pipe = AMDGPU_MES_SCHED_PIPE;
581
582 memset(&misc_pkt, 0, sizeof(misc_pkt));
583
584 misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
585 misc_pkt.header.opcode = MES_SCH_API_MISC;
586 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
587
588 switch (input->op) {
589 case MES_MISC_OP_READ_REG:
590 misc_pkt.opcode = MESAPI_MISC__READ_REG;
591 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
592 mes_v12_1_get_rrmt(input->read_reg.reg_offset,
593 GET_INST(GC, input->xcc_id),
594 &misc_pkt.read_reg.rrmt_opt,
595 &misc_pkt.read_reg.reg_offset);
596 break;
597 case MES_MISC_OP_WRITE_REG:
598 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
599 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
600 mes_v12_1_get_rrmt(input->write_reg.reg_offset,
601 GET_INST(GC, input->xcc_id),
602 &misc_pkt.write_reg.rrmt_opt,
603 &misc_pkt.write_reg.reg_offset);
604 break;
605 case MES_MISC_OP_WRM_REG_WAIT:
606 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
607 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
608 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
609 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
610 misc_pkt.wait_reg_mem.reg_offset2 = 0;
611 mes_v12_1_get_rrmt(input->wrm_reg.reg0,
612 GET_INST(GC, input->xcc_id),
613 &misc_pkt.wait_reg_mem.rrmt_opt1,
614 &misc_pkt.wait_reg_mem.reg_offset1);
615 break;
616 case MES_MISC_OP_WRM_REG_WR_WAIT:
617 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
618 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
619 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
620 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
621 mes_v12_1_get_rrmt(input->wrm_reg.reg0,
622 GET_INST(GC, input->xcc_id),
623 &misc_pkt.wait_reg_mem.rrmt_opt1,
624 &misc_pkt.wait_reg_mem.reg_offset1);
625 mes_v12_1_get_rrmt(input->wrm_reg.reg1,
626 GET_INST(GC, input->xcc_id),
627 &misc_pkt.wait_reg_mem.rrmt_opt2,
628 &misc_pkt.wait_reg_mem.reg_offset2);
629 break;
630 case MES_MISC_OP_SET_SHADER_DEBUGGER:
631 pipe = AMDGPU_MES_SCHED_PIPE;
632 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
633 misc_pkt.set_shader_debugger.process_context_addr =
634 input->set_shader_debugger.process_context_addr;
635 misc_pkt.set_shader_debugger.flags.u32all =
636 input->set_shader_debugger.flags.u32all;
637 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
638 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
639 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
640 input->set_shader_debugger.tcp_watch_cntl,
641 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
642 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
643 break;
644 case MES_MISC_OP_CHANGE_CONFIG:
645 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG;
646 misc_pkt.change_config.opcode =
647 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS;
648 misc_pkt.change_config.option.bits.limit_single_process =
649 input->change_config.option.limit_single_process;
650 break;
651 default:
652 DRM_ERROR("unsupported misc op (%d) \n", input->op);
653 return -EINVAL;
654 }
655
656 return mes_v12_1_submit_pkt_and_poll_completion(mes,
657 input->xcc_id, pipe,
658 &misc_pkt, sizeof(misc_pkt),
659 offsetof(union MESAPI__MISC, api_status));
660 }
661
mes_v12_1_set_hw_resources_1(struct amdgpu_mes * mes,int pipe,int xcc_id)662 static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes,
663 int pipe, int xcc_id)
664 {
665 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
666 int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe);
667
668 memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
669
670 mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
671 mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
672 mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
673 mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
674
675 /* From version 0x74 above, pipe1 support use shared command buffer
676 to distribute some tasks on individual XCCs*/
677 if (mes->enable_coop_mode &&
678 ((pipe == AMDGPU_MES_SCHED_PIPE) ||
679 ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) {
680 master_xcc_id = mes->master_xcc_ids[inst];
681 mes_set_hw_res_1_pkt.mes_coop_mode = 1;
682 mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr =
683 mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe];
684 }
685
686 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
687 &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
688 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
689 }
690
mes_v12_1_set_hw_resources(struct amdgpu_mes * mes,int pipe,int xcc_id)691 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes,
692 int pipe, int xcc_id)
693 {
694 int i, status;
695 struct amdgpu_device *adev = mes->adev;
696 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
697
698 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
699
700 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
701 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
702 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
703
704 if (pipe == AMDGPU_MES_SCHED_PIPE) {
705 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
706 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
707 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
708 mes_set_hw_res_pkt.paging_vmid = 0;
709
710 for (i = 0; i < MAX_COMPUTE_PIPES; i++)
711 mes_set_hw_res_pkt.compute_hqd_mask[i] =
712 mes->compute_hqd_mask[i];
713
714 for (i = 0; i < MAX_GFX_PIPES; i++)
715 mes_set_hw_res_pkt.gfx_hqd_mask[i] =
716 mes->gfx_hqd_mask[i];
717
718 for (i = 0; i < MAX_SDMA_PIPES; i++)
719 mes_set_hw_res_pkt.sdma_hqd_mask[i] =
720 mes->sdma_hqd_mask[i];
721
722 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
723 mes_set_hw_res_pkt.aggregated_doorbells[i] =
724 mes->aggregated_doorbells[i];
725 }
726
727 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =
728 mes->sch_ctx_gpu_addr[pipe];
729 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
730 mes->query_status_fence_gpu_addr[pipe];
731
732 for (i = 0; i < 5; i++) {
733 mes_set_hw_res_pkt.gc_base[i] =
734 adev->reg_offset[GC_HWIP][0][i];
735 mes_set_hw_res_pkt.mmhub_base[i] =
736 adev->reg_offset[MMHUB_HWIP][0][i];
737 mes_set_hw_res_pkt.osssys_base[i] =
738 adev->reg_offset[OSSSYS_HWIP][0][i];
739 }
740
741 mes_set_hw_res_pkt.disable_reset = 1;
742 mes_set_hw_res_pkt.disable_mes_log = 1;
743 mes_set_hw_res_pkt.use_different_vmid_compute = 1;
744 mes_set_hw_res_pkt.enable_reg_active_poll = 1;
745 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
746
747 /*
748 * Keep oversubscribe timer for sdma . When we have unmapped doorbell
749 * handling support, other queue will not use the oversubscribe timer.
750 * handling mode - 0: disabled; 1: basic version; 2: basic+ version
751 */
752 mes_set_hw_res_pkt.oversubscription_timer = 50;
753 mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
754
755 if (amdgpu_mes_log_enable) {
756 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
757 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
758 mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE;
759 }
760
761 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE)
762 mes_set_hw_res_pkt.limit_single_process = 1;
763
764 status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
765 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
766 offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
767
768 /* get MES scheduler versions */
769 mutex_lock(&adev->srbm_mutex);
770 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));
771
772 if (pipe == AMDGPU_MES_SCHED_PIPE)
773 adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
774 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
775 adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
776
777 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
778 mutex_unlock(&adev->srbm_mutex);
779
780 return status;
781 }
782
mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes * mes,int xcc_id)783 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes,
784 int xcc_id)
785 {
786 struct amdgpu_device *adev = mes->adev;
787 uint32_t data;
788
789 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1);
790 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
791 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
792 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
793 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
794 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
795 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
796 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data);
797
798 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2);
799 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
800 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
801 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
802 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
803 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
804 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
805 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data);
806
807 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3);
808 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
809 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
810 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
811 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
812 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
813 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
814 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data);
815
816 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4);
817 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
818 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
819 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
820 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
821 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
822 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
823 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data);
824
825 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5);
826 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
827 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
828 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
829 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
830 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
831 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
832 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data);
833
834 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
835 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data);
836 }
837
838
mes_v12_1_enable_unmapped_doorbell_handling(struct amdgpu_mes * mes,bool enable,int xcc_id)839 static void mes_v12_1_enable_unmapped_doorbell_handling(
840 struct amdgpu_mes *mes, bool enable, int xcc_id)
841 {
842 struct amdgpu_device *adev = mes->adev;
843 uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL);
844
845 /*
846 * The default PROC_LSB settng is 0xc which means doorbell
847 * addr[16:12] gives the doorbell page number. For kfd, each
848 * process will use 2 pages of doorbell, we need to change the
849 * setting to 0xd
850 */
851 data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;
852 data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;
853
854 data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;
855
856 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data);
857 }
858
859 #if 0
860 static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes,
861 struct mes_reset_legacy_queue_input *input)
862 {
863 union MESAPI__RESET mes_reset_queue_pkt;
864 int pipe;
865
866 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
867
868 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
869 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
870 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
871
872 mes_reset_queue_pkt.queue_type =
873 convert_to_mes_queue_type(input->queue_type);
874
875 if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) {
876 mes_reset_queue_pkt.reset_legacy_gfx = 1;
877 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;
878 mes_reset_queue_pkt.queue_id_lp = input->queue_id;
879 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;
880 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;
881 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;
882 mes_reset_queue_pkt.vmid_id_lp = input->vmid;
883 } else {
884 mes_reset_queue_pkt.reset_queue_only = 1;
885 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
886 }
887
888 if (mes->adev->enable_uni_mes)
889 pipe = AMDGPU_MES_KIQ_PIPE;
890 else
891 pipe = AMDGPU_MES_SCHED_PIPE;
892
893 return mes_v12_1_submit_pkt_and_poll_completion(mes,
894 input->xcc_id, pipe,
895 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
896 offsetof(union MESAPI__RESET, api_status));
897 }
898 #endif
899
mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes * mes,struct mes_detect_and_reset_queue_input * input)900 static int mes_v12_1_detect_and_reset_hung_queues(struct amdgpu_mes *mes,
901 struct mes_detect_and_reset_queue_input *input)
902 {
903 union MESAPI__RESET mes_reset_queue_pkt;
904
905 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
906
907 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
908 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
909 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
910
911 mes_reset_queue_pkt.queue_type =
912 convert_to_mes_queue_type(input->queue_type);
913 mes_reset_queue_pkt.doorbell_offset_addr =
914 mes->hung_queue_db_array_gpu_addr[0];
915
916 if (input->detect_only)
917 mes_reset_queue_pkt.hang_detect_only = 1;
918 else
919 mes_reset_queue_pkt.hang_detect_then_reset = 1;
920
921 return mes_v12_1_submit_pkt_and_poll_completion(mes,
922 input->xcc_id, AMDGPU_MES_SCHED_PIPE,
923 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
924 offsetof(union MESAPI__RESET, api_status));
925 }
926
mes_v12_inv_tlb_convert_hub_id(uint8_t id)927 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id)
928 {
929 /*
930 * MES doesn't support invalidate gc_hub on slave xcc individually
931 * master xcc will invalidate all gc_hub for the partition
932 */
933 if (AMDGPU_IS_GFXHUB(id))
934 return 0;
935 else if (AMDGPU_IS_MMHUB0(id))
936 return 1;
937 else if (AMDGPU_IS_MMHUB1(id))
938 return 2;
939 return -EINVAL;
940
941 }
942
mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes * mes,struct mes_inv_tlbs_pasid_input * input)943 static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes,
944 struct mes_inv_tlbs_pasid_input *input)
945 {
946 union MESAPI__INV_TLBS mes_inv_tlbs;
947 int xcc_id = input->xcc_id;
948 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
949 int ret;
950
951 if (mes->enable_coop_mode)
952 xcc_id = mes->master_xcc_ids[inst];
953
954 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs));
955
956 mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER;
957 mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS;
958 mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
959
960 mes_inv_tlbs.invalidate_tlbs.inv_sel = 0;
961 mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type;
962 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid;
963
964 /*convert amdgpu_mes_hub_id to mes expected hub_id */
965 ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id);
966 if (ret < 0)
967 return -EINVAL;
968 mes_inv_tlbs.invalidate_tlbs.hub_id = ret;
969 return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE,
970 &mes_inv_tlbs, sizeof(mes_inv_tlbs),
971 offsetof(union MESAPI__INV_TLBS, api_status));
972
973 }
974
975 static const struct amdgpu_mes_funcs mes_v12_1_funcs = {
976 .add_hw_queue = mes_v12_1_add_hw_queue,
977 .remove_hw_queue = mes_v12_1_remove_hw_queue,
978 .map_legacy_queue = mes_v12_1_map_legacy_queue,
979 .unmap_legacy_queue = mes_v12_1_unmap_legacy_queue,
980 .suspend_gang = mes_v12_1_suspend_gang,
981 .resume_gang = mes_v12_1_resume_gang,
982 .misc_op = mes_v12_1_misc_op,
983 .reset_hw_queue = mes_v12_1_reset_hw_queue,
984 .detect_and_reset_hung_queues = mes_v12_1_detect_and_reset_hung_queues,
985 .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid,
986 };
987
mes_v12_1_allocate_ucode_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id)988 static int mes_v12_1_allocate_ucode_buffer(struct amdgpu_device *adev,
989 enum amdgpu_mes_pipe pipe,
990 int xcc_id)
991 {
992 int r, inst = MES_PIPE_INST(xcc_id, pipe);
993 const struct mes_firmware_header_v1_0 *mes_hdr;
994 const __le32 *fw_data;
995 unsigned fw_size;
996
997 mes_hdr = (const struct mes_firmware_header_v1_0 *)
998 adev->mes.fw[pipe]->data;
999
1000 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1001 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1002 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1003
1004 r = amdgpu_bo_create_reserved(adev, fw_size,
1005 PAGE_SIZE,
1006 AMDGPU_GEM_DOMAIN_VRAM,
1007 &adev->mes.ucode_fw_obj[inst],
1008 &adev->mes.ucode_fw_gpu_addr[inst],
1009 (void **)&adev->mes.ucode_fw_ptr[inst]);
1010 if (r) {
1011 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
1012 return r;
1013 }
1014
1015 memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size);
1016
1017 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]);
1018 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]);
1019
1020 return 0;
1021 }
1022
mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id)1023 static int mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device *adev,
1024 enum amdgpu_mes_pipe pipe,
1025 int xcc_id)
1026 {
1027 int r, inst = MES_PIPE_INST(xcc_id, pipe);
1028 const struct mes_firmware_header_v1_0 *mes_hdr;
1029 const __le32 *fw_data;
1030 unsigned fw_size;
1031
1032 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1033 adev->mes.fw[pipe]->data;
1034
1035 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1036 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1037 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1038
1039 r = amdgpu_bo_create_reserved(adev, fw_size,
1040 64 * 1024,
1041 AMDGPU_GEM_DOMAIN_VRAM,
1042 &adev->mes.data_fw_obj[inst],
1043 &adev->mes.data_fw_gpu_addr[inst],
1044 (void **)&adev->mes.data_fw_ptr[inst]);
1045 if (r) {
1046 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
1047 return r;
1048 }
1049
1050 memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size);
1051
1052 amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]);
1053 amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]);
1054
1055 return 0;
1056 }
1057
mes_v12_1_free_ucode_buffers(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id)1058 static void mes_v12_1_free_ucode_buffers(struct amdgpu_device *adev,
1059 enum amdgpu_mes_pipe pipe,
1060 int xcc_id)
1061 {
1062 int inst = MES_PIPE_INST(xcc_id, pipe);
1063
1064 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst],
1065 &adev->mes.data_fw_gpu_addr[inst],
1066 (void **)&adev->mes.data_fw_ptr[inst]);
1067
1068 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst],
1069 &adev->mes.ucode_fw_gpu_addr[inst],
1070 (void **)&adev->mes.ucode_fw_ptr[inst]);
1071 }
1072
mes_v12_1_enable(struct amdgpu_device * adev,bool enable,int xcc_id)1073 static void mes_v12_1_enable(struct amdgpu_device *adev,
1074 bool enable, int xcc_id)
1075 {
1076 uint64_t ucode_addr;
1077 uint32_t pipe, data = 0;
1078
1079 if (enable) {
1080 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);
1081 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
1082 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
1083 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);
1084
1085 mutex_lock(&adev->srbm_mutex);
1086 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1087 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0,
1088 GET_INST(GC, xcc_id));
1089
1090 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1091 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
1092 regCP_MES_PRGRM_CNTR_START,
1093 lower_32_bits(ucode_addr));
1094 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
1095 regCP_MES_PRGRM_CNTR_START_HI,
1096 upper_32_bits(ucode_addr));
1097 }
1098 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1099 mutex_unlock(&adev->srbm_mutex);
1100
1101 /* unhalt MES and activate pipe0 */
1102 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
1103 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
1104 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);
1105
1106 if (amdgpu_emu_mode)
1107 msleep(500);
1108 else if (adev->enable_uni_mes)
1109 udelay(500);
1110 else
1111 udelay(50);
1112 } else {
1113 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);
1114 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
1115 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
1116 data = REG_SET_FIELD(data, CP_MES_CNTL,
1117 MES_INVALIDATE_ICACHE, 1);
1118 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
1119 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
1120 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
1121 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data);
1122 }
1123 }
1124
mes_v12_1_set_ucode_start_addr(struct amdgpu_device * adev,int xcc_id)1125 static void mes_v12_1_set_ucode_start_addr(struct amdgpu_device *adev,
1126 int xcc_id)
1127 {
1128 uint64_t ucode_addr;
1129 int pipe;
1130
1131 mes_v12_1_enable(adev, false, xcc_id);
1132
1133 mutex_lock(&adev->srbm_mutex);
1134 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1135 /* me=3, queue=0 */
1136 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));
1137
1138 /* set ucode start address */
1139 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
1140 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START,
1141 lower_32_bits(ucode_addr));
1142 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI,
1143 upper_32_bits(ucode_addr));
1144
1145 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1146 }
1147 mutex_unlock(&adev->srbm_mutex);
1148 }
1149
1150 /* This function is for backdoor MES firmware */
mes_v12_1_load_microcode(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,bool prime_icache,int xcc_id)1151 static int mes_v12_1_load_microcode(struct amdgpu_device *adev,
1152 enum amdgpu_mes_pipe pipe,
1153 bool prime_icache, int xcc_id)
1154 {
1155 int r, inst = MES_PIPE_INST(xcc_id, pipe);
1156 uint32_t data;
1157
1158 mes_v12_1_enable(adev, false, xcc_id);
1159
1160 if (!adev->mes.fw[pipe])
1161 return -EINVAL;
1162
1163 r = mes_v12_1_allocate_ucode_buffer(adev, pipe, xcc_id);
1164 if (r)
1165 return r;
1166
1167 r = mes_v12_1_allocate_ucode_data_buffer(adev, pipe, xcc_id);
1168 if (r) {
1169 mes_v12_1_free_ucode_buffers(adev, pipe, xcc_id);
1170 return r;
1171 }
1172
1173 mutex_lock(&adev->srbm_mutex);
1174 /* me=3, pipe=0, queue=0 */
1175 soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));
1176
1177 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0);
1178
1179 /* set ucode fimrware address */
1180 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO,
1181 lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst]));
1182 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI,
1183 upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst]));
1184
1185 /* set ucode instruction cache boundary to 2M-1 */
1186 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF);
1187
1188 /* set ucode data firmware address */
1189 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO,
1190 lower_32_bits(adev->mes.data_fw_gpu_addr[inst]));
1191 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI,
1192 upper_32_bits(adev->mes.data_fw_gpu_addr[inst]));
1193
1194 /* Set data cache boundary CP_MES_MDBOUND_LO */
1195 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF);
1196
1197 if (prime_icache) {
1198 /* invalidate ICACHE */
1199 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);
1200 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
1201 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1202 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data);
1203
1204 /* prime the ICACHE. */
1205 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);
1206 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
1207 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data);
1208 }
1209
1210 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1211 mutex_unlock(&adev->srbm_mutex);
1212
1213 return 0;
1214 }
1215
mes_v12_1_allocate_eop_buf(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id)1216 static int mes_v12_1_allocate_eop_buf(struct amdgpu_device *adev,
1217 enum amdgpu_mes_pipe pipe,
1218 int xcc_id)
1219 {
1220 int r, inst = MES_PIPE_INST(xcc_id, pipe);
1221 u32 *eop;
1222
1223 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
1224 AMDGPU_GEM_DOMAIN_GTT,
1225 &adev->mes.eop_gpu_obj[inst],
1226 &adev->mes.eop_gpu_addr[inst],
1227 (void **)&eop);
1228 if (r) {
1229 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
1230 return r;
1231 }
1232
1233 memset(eop, 0,
1234 adev->mes.eop_gpu_obj[inst]->tbo.base.size);
1235
1236 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]);
1237 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]);
1238
1239 return 0;
1240 }
1241
mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id)1242 static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev,
1243 enum amdgpu_mes_pipe pipe,
1244 int xcc_id)
1245 {
1246 int r, inst = MES_PIPE_INST(xcc_id, pipe);
1247
1248 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1249 AMDGPU_GEM_DOMAIN_VRAM,
1250 &adev->mes.shared_cmd_buf_obj[inst],
1251 &adev->mes.shared_cmd_buf_gpu_addr[inst],
1252 NULL);
1253 if (r) {
1254 dev_err(adev->dev,
1255 "(%d) failed to create shared cmd buf bo\n", r);
1256 return r;
1257 }
1258
1259 return 0;
1260 }
1261
mes_v12_1_mqd_init(struct amdgpu_ring * ring)1262 static int mes_v12_1_mqd_init(struct amdgpu_ring *ring)
1263 {
1264 struct v12_1_mes_mqd *mqd = ring->mqd_ptr;
1265 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1266 uint32_t tmp;
1267
1268 mqd->header = 0xC0310800;
1269 mqd->compute_pipelinestat_enable = 0x00000001;
1270 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1271 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1272 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1273 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1274 mqd->compute_misc_reserved = 0x00000007;
1275
1276 eop_base_addr = ring->eop_gpu_addr >> 8;
1277
1278 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1279 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
1280 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1281 (order_base_2(MES_EOP_SIZE / 4) - 1));
1282
1283 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
1284 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1285 mqd->cp_hqd_eop_control = tmp;
1286
1287 /* disable the queue if it's active */
1288 ring->wptr = 0;
1289 mqd->cp_hqd_pq_rptr = 0;
1290 mqd->cp_hqd_pq_wptr_lo = 0;
1291 mqd->cp_hqd_pq_wptr_hi = 0;
1292
1293 /* set the pointer to the MQD */
1294 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1295 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1296
1297 /* set MQD vmid to 0 */
1298 tmp = regCP_MQD_CONTROL_DEFAULT;
1299 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1300 mqd->cp_mqd_control = tmp;
1301
1302 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1303 hqd_gpu_addr = ring->gpu_addr >> 8;
1304 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
1305 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1306
1307 /* set the wb address whether it's enabled or not */
1308 wb_gpu_addr = ring->rptr_gpu_addr;
1309 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1310 mqd->cp_hqd_pq_rptr_report_addr_hi =
1311 upper_32_bits(wb_gpu_addr) & 0xffff;
1312
1313 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1314 wb_gpu_addr = ring->wptr_gpu_addr;
1315 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
1316 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1317
1318 /* set up the HQD, this is similar to CP_RB0_CNTL */
1319 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
1320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1321 (order_base_2(ring->ring_size / 4) - 1));
1322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1323 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1324 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
1325 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
1326 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1327 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1328 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
1329 mqd->cp_hqd_pq_control = tmp;
1330
1331 /* enable doorbell */
1332 tmp = 0;
1333 if (ring->use_doorbell) {
1334 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1335 DOORBELL_OFFSET, ring->doorbell_index);
1336 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1337 DOORBELL_EN, 1);
1338 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1339 DOORBELL_SOURCE, 0);
1340 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1341 DOORBELL_HIT, 0);
1342 } else {
1343 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1344 DOORBELL_EN, 0);
1345 }
1346 mqd->cp_hqd_pq_doorbell_control = tmp;
1347
1348 mqd->cp_hqd_vmid = 0;
1349 /* activate the queue */
1350 mqd->cp_hqd_active = 1;
1351
1352 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1353 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1354 PRELOAD_SIZE, 0x63);
1355 mqd->cp_hqd_persistent_state = tmp;
1356
1357 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT;
1358 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1359 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1360
1361 /*
1362 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped
1363 * doorbell handling. This is a reserved CP internal register can
1364 * not be accesss by others
1365 */
1366 mqd->cp_hqd_gfx_control = BIT(15);
1367
1368 return 0;
1369 }
1370
mes_v12_1_queue_init_register(struct amdgpu_ring * ring,int xcc_id)1371 static void mes_v12_1_queue_init_register(struct amdgpu_ring *ring,
1372 int xcc_id)
1373 {
1374 struct v12_1_mes_mqd *mqd = ring->mqd_ptr;
1375 struct amdgpu_device *adev = ring->adev;
1376 uint32_t data = 0;
1377
1378 mutex_lock(&adev->srbm_mutex);
1379 soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id));
1380
1381 /* set CP_HQD_VMID.VMID = 0. */
1382 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID);
1383 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1384 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data);
1385
1386 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1387 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
1388 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1389 DOORBELL_EN, 0);
1390 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data);
1391
1392 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1393 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1394 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1395
1396 /* set CP_MQD_CONTROL.VMID=0 */
1397 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
1398 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1399 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0);
1400
1401 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1402 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1403 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1404
1405 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1406 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,
1407 mqd->cp_hqd_pq_rptr_report_addr_lo);
1408 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1409 mqd->cp_hqd_pq_rptr_report_addr_hi);
1410
1411 /* set CP_HQD_PQ_CONTROL */
1412 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1413
1414 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1415 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,
1416 mqd->cp_hqd_pq_wptr_poll_addr_lo);
1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1418 mqd->cp_hqd_pq_wptr_poll_addr_hi);
1419
1420 /* set CP_HQD_PQ_DOORBELL_CONTROL */
1421 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1422 mqd->cp_hqd_pq_doorbell_control);
1423
1424 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1425 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1426
1427 /* set CP_HQD_ACTIVE.ACTIVE=1 */
1428 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1429
1430 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1431 mutex_unlock(&adev->srbm_mutex);
1432 }
1433
mes_v12_1_kiq_enable_queue(struct amdgpu_device * adev,int xcc_id)1434 static int mes_v12_1_kiq_enable_queue(struct amdgpu_device *adev, int xcc_id)
1435 {
1436 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
1437 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring;
1438 int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
1439
1440 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1441 return -EINVAL;
1442
1443 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1444 if (r) {
1445 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1446 return r;
1447 }
1448
1449 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]);
1450
1451 r = amdgpu_ring_test_ring(kiq_ring);
1452 if (r) {
1453 DRM_ERROR("kfq enable failed\n");
1454 kiq_ring->sched.ready = false;
1455 }
1456 return r;
1457 }
1458
mes_v12_1_queue_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id)1459 static int mes_v12_1_queue_init(struct amdgpu_device *adev,
1460 enum amdgpu_mes_pipe pipe,
1461 int xcc_id)
1462 {
1463 struct amdgpu_ring *ring;
1464 int r;
1465
1466 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1467 ring = &adev->gfx.kiq[xcc_id].ring;
1468 else
1469 ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)];
1470
1471 if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &&
1472 (amdgpu_in_reset(adev) || adev->in_suspend)) {
1473 *(ring->wptr_cpu_addr) = 0;
1474 *(ring->rptr_cpu_addr) = 0;
1475 amdgpu_ring_clear_ring(ring);
1476 }
1477
1478 r = mes_v12_1_mqd_init(ring);
1479 if (r)
1480 return r;
1481
1482 if (pipe == AMDGPU_MES_SCHED_PIPE) {
1483 if (adev->enable_uni_mes)
1484 r = amdgpu_mes_map_legacy_queue(adev, ring, xcc_id);
1485 else
1486 r = mes_v12_1_kiq_enable_queue(adev, xcc_id);
1487 if (r)
1488 return r;
1489 } else {
1490 mes_v12_1_queue_init_register(ring, xcc_id);
1491 }
1492
1493 return 0;
1494 }
1495
mes_v12_1_ring_init(struct amdgpu_device * adev,int xcc_id,int pipe)1496 static int mes_v12_1_ring_init(struct amdgpu_device *adev,
1497 int xcc_id, int pipe)
1498 {
1499 struct amdgpu_ring *ring;
1500 int inst = MES_PIPE_INST(xcc_id, pipe);
1501
1502 ring = &adev->mes.ring[inst];
1503
1504 ring->funcs = &mes_v12_1_ring_funcs;
1505
1506 ring->me = 3;
1507 ring->pipe = pipe;
1508 ring->queue = 0;
1509 ring->xcc_id = xcc_id;
1510 ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
1511
1512 ring->ring_obj = NULL;
1513 ring->use_doorbell = true;
1514 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst];
1515 ring->no_scheduler = true;
1516 snprintf(ring->name, sizeof(ring->name), "mes_%hhu.%hhu.%hhu.%hhu",
1517 (unsigned char)xcc_id, (unsigned char)ring->me,
1518 (unsigned char)ring->pipe, (unsigned char)ring->queue);
1519
1520 if (pipe == AMDGPU_MES_SCHED_PIPE)
1521 ring->doorbell_index =
1522 (adev->doorbell_index.mes_ring0 +
1523 xcc_id * adev->doorbell_index.xcc_doorbell_range)
1524 << 1;
1525 else
1526 ring->doorbell_index =
1527 (adev->doorbell_index.mes_ring1 +
1528 xcc_id * adev->doorbell_index.xcc_doorbell_range)
1529 << 1;
1530
1531 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1532 AMDGPU_RING_PRIO_DEFAULT, NULL);
1533 }
1534
mes_v12_1_kiq_ring_init(struct amdgpu_device * adev,int xcc_id)1535 static int mes_v12_1_kiq_ring_init(struct amdgpu_device *adev, int xcc_id)
1536 {
1537 struct amdgpu_ring *ring;
1538 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE);
1539
1540 spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock);
1541
1542 ring = &adev->gfx.kiq[xcc_id].ring;
1543
1544 ring->me = 3;
1545 ring->pipe = 1;
1546 ring->queue = 0;
1547 ring->xcc_id = xcc_id;
1548 ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
1549
1550 ring->adev = NULL;
1551 ring->ring_obj = NULL;
1552 ring->use_doorbell = true;
1553 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst];
1554 ring->no_scheduler = true;
1555 ring->doorbell_index =
1556 (adev->doorbell_index.mes_ring1 +
1557 xcc_id * adev->doorbell_index.xcc_doorbell_range)
1558 << 1;
1559
1560 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%hhu.%hhu.%hhu.%hhu",
1561 (unsigned char)xcc_id, (unsigned char)ring->me,
1562 (unsigned char)ring->pipe, (unsigned char)ring->queue);
1563
1564 return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1565 AMDGPU_RING_PRIO_DEFAULT, NULL);
1566 }
1567
mes_v12_1_mqd_sw_init(struct amdgpu_device * adev,enum amdgpu_mes_pipe pipe,int xcc_id)1568 static int mes_v12_1_mqd_sw_init(struct amdgpu_device *adev,
1569 enum amdgpu_mes_pipe pipe,
1570 int xcc_id)
1571 {
1572 int r, mqd_size = sizeof(struct v12_1_mes_mqd);
1573 struct amdgpu_ring *ring;
1574 int inst = MES_PIPE_INST(xcc_id, pipe);
1575
1576 if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1577 ring = &adev->gfx.kiq[xcc_id].ring;
1578 else
1579 ring = &adev->mes.ring[inst];
1580
1581 if (ring->mqd_obj)
1582 return 0;
1583
1584 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1585 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1586 &ring->mqd_gpu_addr, &ring->mqd_ptr);
1587 if (r) {
1588 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1589 return r;
1590 }
1591
1592 memset(ring->mqd_ptr, 0, mqd_size);
1593
1594 /* prepare MQD backup */
1595 adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL);
1596 if (!adev->mes.mqd_backup[inst])
1597 dev_warn(adev->dev,
1598 "no memory to create MQD backup for ring %s\n",
1599 ring->name);
1600
1601 return 0;
1602 }
1603
mes_v12_1_sw_init(struct amdgpu_ip_block * ip_block)1604 static int mes_v12_1_sw_init(struct amdgpu_ip_block *ip_block)
1605 {
1606 struct amdgpu_device *adev = ip_block->adev;
1607 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1608
1609 adev->mes.funcs = &mes_v12_1_funcs;
1610 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init;
1611 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini;
1612 adev->mes.enable_legacy_queue_map = true;
1613
1614 adev->mes.event_log_size =
1615 adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE;
1616
1617 r = amdgpu_mes_init(adev);
1618 if (r)
1619 return r;
1620
1621 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1622 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1623 r = mes_v12_1_allocate_eop_buf(adev, pipe, xcc_id);
1624 if (r)
1625 return r;
1626
1627 r = mes_v12_1_mqd_sw_init(adev, pipe, xcc_id);
1628 if (r)
1629 return r;
1630
1631 if (!adev->enable_uni_mes && pipe ==
1632 AMDGPU_MES_KIQ_PIPE)
1633 r = mes_v12_1_kiq_ring_init(adev, xcc_id);
1634 else
1635 r = mes_v12_1_ring_init(adev, xcc_id, pipe);
1636 if (r)
1637 return r;
1638
1639 if (adev->enable_uni_mes && num_xcc > 1) {
1640 r = mes_v12_1_allocate_shared_cmd_buf(adev,
1641 pipe, xcc_id);
1642 if (r)
1643 return r;
1644 }
1645 }
1646 }
1647
1648 return 0;
1649 }
1650
mes_v12_1_sw_fini(struct amdgpu_ip_block * ip_block)1651 static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block)
1652 {
1653 struct amdgpu_device *adev = ip_block->adev;
1654 int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1655
1656 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1657 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1658 inst = MES_PIPE_INST(xcc_id, pipe);
1659
1660 amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst],
1661 &adev->mes.shared_cmd_buf_gpu_addr[inst],
1662 NULL);
1663
1664 kfree(adev->mes.mqd_backup[inst]);
1665
1666 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst],
1667 &adev->mes.eop_gpu_addr[inst],
1668 NULL);
1669
1670 if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {
1671 amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj,
1672 &adev->mes.ring[inst].mqd_gpu_addr,
1673 &adev->mes.ring[inst].mqd_ptr);
1674 amdgpu_ring_fini(&adev->mes.ring[inst]);
1675 }
1676 }
1677 }
1678
1679 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++)
1680 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1681
1682 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1683 if (!adev->enable_uni_mes) {
1684 amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj,
1685 &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr,
1686 &adev->gfx.kiq[xcc_id].ring.mqd_ptr);
1687 amdgpu_ring_fini(&adev->gfx.kiq[xcc_id].ring);
1688 }
1689
1690 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1691 mes_v12_1_free_ucode_buffers(adev,
1692 AMDGPU_MES_KIQ_PIPE, xcc_id);
1693 mes_v12_1_free_ucode_buffers(adev,
1694 AMDGPU_MES_SCHED_PIPE, xcc_id);
1695 }
1696 }
1697
1698 amdgpu_mes_fini(adev);
1699 return 0;
1700 }
1701
mes_v12_1_kiq_dequeue_sched(struct amdgpu_device * adev,int xcc_id)1702 static void mes_v12_1_kiq_dequeue_sched(struct amdgpu_device *adev,
1703 int xcc_id)
1704 {
1705 uint32_t data;
1706 int i;
1707
1708 mutex_lock(&adev->srbm_mutex);
1709 soc_v1_0_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0,
1710 GET_INST(GC, xcc_id));
1711
1712 /* disable the queue if it's active */
1713 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1714 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1715 for (i = 0; i < adev->usec_timeout; i++) {
1716 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1717 break;
1718 udelay(1);
1719 }
1720 }
1721 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
1722 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1723 DOORBELL_EN, 0);
1724 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1725 DOORBELL_HIT, 1);
1726 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data);
1727
1728 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1729
1730 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);
1731 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);
1732 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
1733
1734 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1735 mutex_unlock(&adev->srbm_mutex);
1736
1737 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false;
1738 }
1739
mes_v12_1_kiq_setting(struct amdgpu_ring * ring,int xcc_id)1740 static void mes_v12_1_kiq_setting(struct amdgpu_ring *ring, int xcc_id)
1741 {
1742 uint32_t tmp;
1743 struct amdgpu_device *adev = ring->adev;
1744
1745 /* tell RLC which is KIQ queue */
1746 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
1747 tmp &= 0xffffff00;
1748 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1749 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1750 tmp |= 0x80;
1751 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1752 }
1753
mes_v12_1_kiq_hw_init(struct amdgpu_device * adev,uint32_t xcc_id)1754 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id)
1755 {
1756 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE);
1757 int r = 0;
1758 struct amdgpu_ip_block *ip_block;
1759
1760 if (adev->enable_uni_mes)
1761 mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id);
1762 else
1763 mes_v12_1_kiq_setting(&adev->gfx.kiq[xcc_id].ring, xcc_id);
1764
1765 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1766
1767 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE,
1768 false, xcc_id);
1769 if (r) {
1770 DRM_ERROR("failed to load MES fw, r=%d\n", r);
1771 return r;
1772 }
1773
1774 r = mes_v12_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE,
1775 true, xcc_id);
1776 if (r) {
1777 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1778 return r;
1779 }
1780
1781 mes_v12_1_set_ucode_start_addr(adev, xcc_id);
1782
1783 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1784 mes_v12_1_set_ucode_start_addr(adev, xcc_id);
1785
1786 mes_v12_1_enable(adev, true, xcc_id);
1787
1788 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES);
1789 if (unlikely(!ip_block)) {
1790 dev_err(adev->dev, "Failed to get MES handle\n");
1791 return -EINVAL;
1792 }
1793
1794 r = mes_v12_1_queue_init(adev, AMDGPU_MES_KIQ_PIPE, xcc_id);
1795 if (r)
1796 goto failure;
1797
1798 if (adev->enable_uni_mes) {
1799 r = mes_v12_1_setup_coop_mode(adev, xcc_id);
1800 if (r)
1801 goto failure;
1802
1803 r = mes_v12_1_set_hw_resources(&adev->mes,
1804 AMDGPU_MES_KIQ_PIPE, xcc_id);
1805 if (r)
1806 goto failure;
1807
1808 mes_v12_1_set_hw_resources_1(&adev->mes,
1809 AMDGPU_MES_KIQ_PIPE, xcc_id);
1810 }
1811
1812 if (adev->mes.enable_legacy_queue_map) {
1813 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id);
1814 if (r)
1815 goto failure;
1816 }
1817
1818 return r;
1819
1820 failure:
1821 mes_v12_1_hw_fini(ip_block);
1822 return r;
1823 }
1824
mes_v12_1_kiq_hw_fini(struct amdgpu_device * adev,uint32_t xcc_id)1825 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id)
1826 {
1827 int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
1828
1829 if (adev->mes.ring[inst].sched.ready) {
1830 if (adev->enable_uni_mes)
1831 amdgpu_mes_unmap_legacy_queue(adev,
1832 &adev->mes.ring[inst],
1833 RESET_QUEUES, 0, 0, xcc_id);
1834 else
1835 mes_v12_1_kiq_dequeue_sched(adev, xcc_id);
1836
1837 adev->mes.ring[inst].sched.ready = false;
1838 }
1839
1840 mes_v12_1_enable(adev, false, xcc_id);
1841
1842 return 0;
1843 }
1844
mes_v12_1_setup_coop_mode(struct amdgpu_device * adev,int xcc_id)1845 static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id)
1846 {
1847 u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1848 int r = 0;
1849
1850 if (num_xcc == 1)
1851 return r;
1852
1853 if (adev->gfx.funcs &&
1854 adev->gfx.funcs->get_xccs_per_xcp)
1855 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev);
1856 else
1857 return -EINVAL;
1858
1859 switch (adev->xcp_mgr->mode) {
1860 case AMDGPU_SPX_PARTITION_MODE:
1861 adev->mes.enable_coop_mode = 1;
1862 adev->mes.master_xcc_ids[xcc_id] = 0;
1863 break;
1864 case AMDGPU_DPX_PARTITION_MODE:
1865 adev->mes.enable_coop_mode = 1;
1866 adev->mes.master_xcc_ids[xcc_id] =
1867 (xcc_id/num_xcc_per_xcp) * (num_xcc / 2);
1868 break;
1869 case AMDGPU_QPX_PARTITION_MODE:
1870 adev->mes.enable_coop_mode = 1;
1871 adev->mes.master_xcc_ids[xcc_id] =
1872 (xcc_id/num_xcc_per_xcp) * (num_xcc / 4);
1873 break;
1874 case AMDGPU_CPX_PARTITION_MODE:
1875 adev->mes.enable_coop_mode = 0;
1876 break;
1877 default:
1878 r = -EINVAL;
1879 break;
1880 }
1881 return r;
1882 }
1883
mes_v12_1_xcc_hw_init(struct amdgpu_ip_block * ip_block,int xcc_id)1884 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id)
1885 {
1886 int r;
1887 struct amdgpu_device *adev = ip_block->adev;
1888
1889 if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready)
1890 goto out;
1891
1892 if (!adev->enable_mes_kiq) {
1893 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1894 r = mes_v12_1_load_microcode(adev,
1895 AMDGPU_MES_SCHED_PIPE, true, xcc_id);
1896 if (r) {
1897 DRM_ERROR("failed to MES fw, r=%d\n", r);
1898 return r;
1899 }
1900
1901 mes_v12_1_set_ucode_start_addr(adev, xcc_id);
1902
1903 } else if (adev->firmware.load_type ==
1904 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1905
1906 mes_v12_1_set_ucode_start_addr(adev, xcc_id);
1907 }
1908
1909 mes_v12_1_enable(adev, true, xcc_id);
1910 }
1911
1912 /* Enable the MES to handle doorbell ring on unmapped queue */
1913 mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id);
1914
1915 r = mes_v12_1_queue_init(adev, AMDGPU_MES_SCHED_PIPE, xcc_id);
1916 if (r)
1917 goto failure;
1918
1919 r = mes_v12_1_set_hw_resources(&adev->mes,
1920 AMDGPU_MES_SCHED_PIPE, xcc_id);
1921 if (r)
1922 goto failure;
1923
1924 if (adev->enable_uni_mes) {
1925 mes_v12_1_set_hw_resources_1(&adev->mes,
1926 AMDGPU_MES_SCHED_PIPE, xcc_id);
1927 }
1928 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id);
1929
1930 r = mes_v12_1_query_sched_status(&adev->mes,
1931 AMDGPU_MES_SCHED_PIPE, xcc_id);
1932 if (r) {
1933 DRM_ERROR("MES is busy\n");
1934 goto failure;
1935 }
1936
1937 amdgpu_mes_validate_fw_version(adev);
1938 out:
1939 /*
1940 * Disable KIQ ring usage from the driver once MES is enabled.
1941 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1942 * with MES enabled.
1943 */
1944 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
1945 adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true;
1946
1947 return 0;
1948
1949 failure:
1950 mes_v12_1_hw_fini(ip_block);
1951 return r;
1952 }
1953
mes_v12_1_hw_init(struct amdgpu_ip_block * ip_block)1954 static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block)
1955 {
1956 struct amdgpu_device *adev = ip_block->adev;
1957 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1958
1959 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1960 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id);
1961 if (r)
1962 return r;
1963 }
1964
1965 return 0;
1966 }
1967
mes_v12_1_hw_fini(struct amdgpu_ip_block * ip_block)1968 static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block)
1969 {
1970 return 0;
1971 }
1972
mes_v12_1_suspend(struct amdgpu_ip_block * ip_block)1973 static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block)
1974 {
1975 return mes_v12_1_hw_fini(ip_block);
1976 }
1977
mes_v12_1_resume(struct amdgpu_ip_block * ip_block)1978 static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block)
1979 {
1980 return mes_v12_1_hw_init(ip_block);
1981 }
1982
mes_v12_1_early_init(struct amdgpu_ip_block * ip_block)1983 static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block)
1984 {
1985 struct amdgpu_device *adev = ip_block->adev;
1986 int pipe, r;
1987
1988 adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE;
1989 adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET;
1990
1991 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1992 r = amdgpu_mes_init_microcode(adev, pipe);
1993 if (r)
1994 return r;
1995 }
1996
1997 return 0;
1998 }
1999
2000 static const struct amd_ip_funcs mes_v12_1_ip_funcs = {
2001 .name = "mes_v12_1",
2002 .early_init = mes_v12_1_early_init,
2003 .late_init = NULL,
2004 .sw_init = mes_v12_1_sw_init,
2005 .sw_fini = mes_v12_1_sw_fini,
2006 .hw_init = mes_v12_1_hw_init,
2007 .hw_fini = mes_v12_1_hw_fini,
2008 .suspend = mes_v12_1_suspend,
2009 .resume = mes_v12_1_resume,
2010 };
2011
2012 const struct amdgpu_ip_block_version mes_v12_1_ip_block = {
2013 .type = AMD_IP_BLOCK_TYPE_MES,
2014 .major = 12,
2015 .minor = 1,
2016 .rev = 0,
2017 .funcs = &mes_v12_1_ip_funcs,
2018 };
2019