xref: /linux/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include "amdgpu.h"
27 #include "soc15_common.h"
28 #include "soc21.h"
29 #include "gc/gc_12_0_0_offset.h"
30 #include "gc/gc_12_0_0_sh_mask.h"
31 #include "gc/gc_11_0_0_default.h"
32 #include "v12_structs.h"
33 #include "mes_v12_api_def.h"
34 
35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");
36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");
37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");
38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");
39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");
40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");
41 
42 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block);
43 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block);
44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);
45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);
46 
47 #define MES_EOP_SIZE   2048
48 
mes_v12_0_ring_set_wptr(struct amdgpu_ring * ring)49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)
50 {
51 	struct amdgpu_device *adev = ring->adev;
52 
53 	if (ring->use_doorbell) {
54 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
55 			     ring->wptr);
56 		WDOORBELL64(ring->doorbell_index, ring->wptr);
57 	} else {
58 		BUG();
59 	}
60 }
61 
mes_v12_0_ring_get_rptr(struct amdgpu_ring * ring)62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)
63 {
64 	return *ring->rptr_cpu_addr;
65 }
66 
mes_v12_0_ring_get_wptr(struct amdgpu_ring * ring)67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)
68 {
69 	u64 wptr;
70 
71 	if (ring->use_doorbell)
72 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
73 	else
74 		BUG();
75 	return wptr;
76 }
77 
78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {
79 	.type = AMDGPU_RING_TYPE_MES,
80 	.align_mask = 1,
81 	.nop = 0,
82 	.support_64bit_ptrs = true,
83 	.get_rptr = mes_v12_0_ring_get_rptr,
84 	.get_wptr = mes_v12_0_ring_get_wptr,
85 	.set_wptr = mes_v12_0_ring_set_wptr,
86 	.insert_nop = amdgpu_ring_insert_nop,
87 };
88 
89 static const char *mes_v12_0_opcodes[] = {
90 	"SET_HW_RSRC",
91 	"SET_SCHEDULING_CONFIG",
92 	"ADD_QUEUE",
93 	"REMOVE_QUEUE",
94 	"PERFORM_YIELD",
95 	"SET_GANG_PRIORITY_LEVEL",
96 	"SUSPEND",
97 	"RESUME",
98 	"RESET",
99 	"SET_LOG_BUFFER",
100 	"CHANGE_GANG_PRORITY",
101 	"QUERY_SCHEDULER_STATUS",
102 	"unused",
103 	"SET_DEBUG_VMID",
104 	"MISC",
105 	"UPDATE_ROOT_PAGE_TABLE",
106 	"AMD_LOG",
107 	"SET_SE_MODE",
108 	"SET_GANG_SUBMIT",
109 	"SET_HW_RSRC_1",
110 };
111 
112 static const char *mes_v12_0_misc_opcodes[] = {
113 	"WRITE_REG",
114 	"INV_GART",
115 	"QUERY_STATUS",
116 	"READ_REG",
117 	"WAIT_REG_MEM",
118 	"SET_SHADER_DEBUGGER",
119 	"NOTIFY_WORK_ON_UNMAPPED_QUEUE",
120 	"NOTIFY_TO_UNMAP_PROCESSES",
121 };
122 
mes_v12_0_get_op_string(union MESAPI__MISC * x_pkt)123 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)
124 {
125 	const char *op_str = NULL;
126 
127 	if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))
128 		op_str = mes_v12_0_opcodes[x_pkt->header.opcode];
129 
130 	return op_str;
131 }
132 
mes_v12_0_get_misc_op_string(union MESAPI__MISC * x_pkt)133 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
134 {
135 	const char *op_str = NULL;
136 
137 	if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
138 	    (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))
139 		op_str = mes_v12_0_misc_opcodes[x_pkt->opcode];
140 
141 	return op_str;
142 }
143 
mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes * mes,int pipe,void * pkt,int size,int api_status_off)144 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
145 					    int pipe, void *pkt, int size,
146 					    int api_status_off)
147 {
148 	union MESAPI__QUERY_MES_STATUS mes_status_pkt;
149 	signed long timeout = 2100000; /* 2100 ms */
150 	struct amdgpu_device *adev = mes->adev;
151 	struct amdgpu_ring *ring = &mes->ring[pipe];
152 	spinlock_t *ring_lock = &mes->ring_lock[pipe];
153 	struct MES_API_STATUS *api_status;
154 	union MESAPI__MISC *x_pkt = pkt;
155 	const char *op_str, *misc_op_str;
156 	unsigned long flags;
157 	u64 status_gpu_addr;
158 	u32 seq, status_offset;
159 	u64 *status_ptr;
160 	signed long r;
161 	int ret;
162 
163 	if (x_pkt->header.opcode >= MES_SCH_API_MAX)
164 		return -EINVAL;
165 
166 	if (amdgpu_emu_mode) {
167 		timeout *= 100;
168 	} else if (amdgpu_sriov_vf(adev)) {
169 		/* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
170 		timeout = 15 * 600 * 1000;
171 	}
172 
173 	ret = amdgpu_device_wb_get(adev, &status_offset);
174 	if (ret)
175 		return ret;
176 
177 	status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4);
178 	status_ptr = (u64 *)&adev->wb.wb[status_offset];
179 	*status_ptr = 0;
180 
181 	spin_lock_irqsave(ring_lock, flags);
182 	r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
183 	if (r)
184 		goto error_unlock_free;
185 
186 	seq = ++ring->fence_drv.sync_seq;
187 	r = amdgpu_fence_wait_polling(ring,
188 				      seq - ring->fence_drv.num_fences_mask,
189 				      timeout);
190 	if (r < 1)
191 		goto error_undo;
192 
193 	api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
194 	api_status->api_completion_fence_addr = status_gpu_addr;
195 	api_status->api_completion_fence_value = 1;
196 
197 	amdgpu_ring_write_multiple(ring, pkt, size / 4);
198 
199 	memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
200 	mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
201 	mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
202 	mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
203 	mes_status_pkt.api_status.api_completion_fence_addr =
204 		ring->fence_drv.gpu_addr;
205 	mes_status_pkt.api_status.api_completion_fence_value = seq;
206 
207 	amdgpu_ring_write_multiple(ring, &mes_status_pkt,
208 				   sizeof(mes_status_pkt) / 4);
209 
210 	amdgpu_ring_commit(ring);
211 	spin_unlock_irqrestore(ring_lock, flags);
212 
213 	op_str = mes_v12_0_get_op_string(x_pkt);
214 	misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);
215 
216 	if (misc_op_str)
217 		dev_dbg(adev->dev, "MES(%d) msg=%s (%s) was emitted\n",
218 			pipe, op_str, misc_op_str);
219 	else if (op_str)
220 		dev_dbg(adev->dev, "MES(%d) msg=%s was emitted\n",
221 			pipe, op_str);
222 	else
223 		dev_dbg(adev->dev, "MES(%d) msg=%d was emitted\n",
224 			pipe, x_pkt->header.opcode);
225 
226 	r = amdgpu_fence_wait_polling(ring, seq, timeout);
227 	if (r < 1 || !*status_ptr) {
228 
229 		if (misc_op_str)
230 			dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n",
231 				pipe, op_str, misc_op_str);
232 		else if (op_str)
233 			dev_err(adev->dev, "MES(%d) failed to respond to msg=%s\n",
234 				pipe, op_str);
235 		else
236 			dev_err(adev->dev, "MES(%d) failed to respond to msg=%d\n",
237 				pipe, x_pkt->header.opcode);
238 
239 		while (halt_if_hws_hang)
240 			schedule();
241 
242 		r = -ETIMEDOUT;
243 		goto error_wb_free;
244 	}
245 
246 	amdgpu_device_wb_free(adev, status_offset);
247 	return 0;
248 
249 error_undo:
250 	dev_err(adev->dev, "MES ring buffer is full.\n");
251 	amdgpu_ring_undo(ring);
252 
253 error_unlock_free:
254 	spin_unlock_irqrestore(ring_lock, flags);
255 
256 error_wb_free:
257 	amdgpu_device_wb_free(adev, status_offset);
258 	return r;
259 }
260 
convert_to_mes_queue_type(int queue_type)261 static int convert_to_mes_queue_type(int queue_type)
262 {
263 	if (queue_type == AMDGPU_RING_TYPE_GFX)
264 		return MES_QUEUE_TYPE_GFX;
265 	else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
266 		return MES_QUEUE_TYPE_COMPUTE;
267 	else if (queue_type == AMDGPU_RING_TYPE_SDMA)
268 		return MES_QUEUE_TYPE_SDMA;
269 	else if (queue_type == AMDGPU_RING_TYPE_MES)
270 		return MES_QUEUE_TYPE_SCHQ;
271 	else
272 		BUG();
273 	return -1;
274 }
275 
mes_v12_0_add_hw_queue(struct amdgpu_mes * mes,struct mes_add_queue_input * input)276 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,
277 				  struct mes_add_queue_input *input)
278 {
279 	struct amdgpu_device *adev = mes->adev;
280 	union MESAPI__ADD_QUEUE mes_add_queue_pkt;
281 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
282 	uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
283 
284 	memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
285 
286 	mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
287 	mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
288 	mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
289 
290 	mes_add_queue_pkt.process_id = input->process_id;
291 	mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
292 	mes_add_queue_pkt.process_va_start = input->process_va_start;
293 	mes_add_queue_pkt.process_va_end = input->process_va_end;
294 	mes_add_queue_pkt.process_quantum = input->process_quantum;
295 	mes_add_queue_pkt.process_context_addr = input->process_context_addr;
296 	mes_add_queue_pkt.gang_quantum = input->gang_quantum;
297 	mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
298 	mes_add_queue_pkt.inprocess_gang_priority =
299 		input->inprocess_gang_priority;
300 	mes_add_queue_pkt.gang_global_priority_level =
301 		input->gang_global_priority_level;
302 	mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
303 	mes_add_queue_pkt.mqd_addr = input->mqd_addr;
304 
305 	mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
306 
307 	mes_add_queue_pkt.queue_type =
308 		convert_to_mes_queue_type(input->queue_type);
309 	mes_add_queue_pkt.paging = input->paging;
310 	mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
311 	mes_add_queue_pkt.gws_base = input->gws_base;
312 	mes_add_queue_pkt.gws_size = input->gws_size;
313 	mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
314 	mes_add_queue_pkt.tma_addr = input->tma_addr;
315 	mes_add_queue_pkt.trap_en = input->trap_en;
316 	mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
317 	mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
318 
319 	/* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
320 	mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
321 	mes_add_queue_pkt.gds_size = input->queue_size;
322 
323 	/* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
324 	mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
325 	mes_add_queue_pkt.gds_size = input->queue_size;
326 
327 	return mes_v12_0_submit_pkt_and_poll_completion(mes,
328 			AMDGPU_MES_SCHED_PIPE,
329 			&mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
330 			offsetof(union MESAPI__ADD_QUEUE, api_status));
331 }
332 
mes_v12_0_remove_hw_queue(struct amdgpu_mes * mes,struct mes_remove_queue_input * input)333 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,
334 				     struct mes_remove_queue_input *input)
335 {
336 	union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
337 
338 	memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
339 
340 	mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
341 	mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
342 	mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
343 
344 	mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
345 	mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
346 
347 	return mes_v12_0_submit_pkt_and_poll_completion(mes,
348 			AMDGPU_MES_SCHED_PIPE,
349 			&mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
350 			offsetof(union MESAPI__REMOVE_QUEUE, api_status));
351 }
352 
mes_v12_0_reset_hw_queue(struct amdgpu_mes * mes,struct mes_reset_queue_input * input)353 static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
354 				    struct mes_reset_queue_input *input)
355 {
356 	union MESAPI__RESET mes_reset_queue_pkt;
357 	int pipe;
358 
359 	memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
360 
361 	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
362 	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
363 	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
364 
365 	mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
366 	mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr;
367 	/*mes_reset_queue_pkt.reset_queue_only = 1;*/
368 
369 	if (mes->adev->enable_uni_mes)
370 		pipe = AMDGPU_MES_KIQ_PIPE;
371 	else
372 		pipe = AMDGPU_MES_SCHED_PIPE;
373 
374 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
375 			&mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
376 			offsetof(union MESAPI__REMOVE_QUEUE, api_status));
377 }
378 
mes_v12_0_map_legacy_queue(struct amdgpu_mes * mes,struct mes_map_legacy_queue_input * input)379 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,
380 				      struct mes_map_legacy_queue_input *input)
381 {
382 	union MESAPI__ADD_QUEUE mes_add_queue_pkt;
383 	int pipe;
384 
385 	memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
386 
387 	mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
388 	mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
389 	mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
390 
391 	mes_add_queue_pkt.pipe_id = input->pipe_id;
392 	mes_add_queue_pkt.queue_id = input->queue_id;
393 	mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
394 	mes_add_queue_pkt.mqd_addr = input->mqd_addr;
395 	mes_add_queue_pkt.wptr_addr = input->wptr_addr;
396 	mes_add_queue_pkt.queue_type =
397 		convert_to_mes_queue_type(input->queue_type);
398 	mes_add_queue_pkt.map_legacy_kq = 1;
399 
400 	if (mes->adev->enable_uni_mes)
401 		pipe = AMDGPU_MES_KIQ_PIPE;
402 	else
403 		pipe = AMDGPU_MES_SCHED_PIPE;
404 
405 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
406 			&mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
407 			offsetof(union MESAPI__ADD_QUEUE, api_status));
408 }
409 
mes_v12_0_unmap_legacy_queue(struct amdgpu_mes * mes,struct mes_unmap_legacy_queue_input * input)410 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,
411 			struct mes_unmap_legacy_queue_input *input)
412 {
413 	union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
414 	int pipe;
415 
416 	memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
417 
418 	mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
419 	mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
420 	mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
421 
422 	mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
423 	mes_remove_queue_pkt.gang_context_addr = 0;
424 
425 	mes_remove_queue_pkt.pipe_id = input->pipe_id;
426 	mes_remove_queue_pkt.queue_id = input->queue_id;
427 
428 	if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
429 		mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
430 		mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
431 		mes_remove_queue_pkt.tf_data =
432 			lower_32_bits(input->trail_fence_data);
433 	} else {
434 		mes_remove_queue_pkt.unmap_legacy_queue = 1;
435 		mes_remove_queue_pkt.queue_type =
436 			convert_to_mes_queue_type(input->queue_type);
437 	}
438 
439 	if (mes->adev->enable_uni_mes)
440 		pipe = AMDGPU_MES_KIQ_PIPE;
441 	else
442 		pipe = AMDGPU_MES_SCHED_PIPE;
443 
444 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
445 			&mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
446 			offsetof(union MESAPI__REMOVE_QUEUE, api_status));
447 }
448 
mes_v12_0_suspend_gang(struct amdgpu_mes * mes,struct mes_suspend_gang_input * input)449 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,
450 				  struct mes_suspend_gang_input *input)
451 {
452 	return 0;
453 }
454 
mes_v12_0_resume_gang(struct amdgpu_mes * mes,struct mes_resume_gang_input * input)455 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,
456 				 struct mes_resume_gang_input *input)
457 {
458 	return 0;
459 }
460 
mes_v12_0_query_sched_status(struct amdgpu_mes * mes,int pipe)461 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe)
462 {
463 	union MESAPI__QUERY_MES_STATUS mes_status_pkt;
464 
465 	memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
466 
467 	mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
468 	mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
469 	mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
470 
471 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
472 			&mes_status_pkt, sizeof(mes_status_pkt),
473 			offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
474 }
475 
mes_v12_0_misc_op(struct amdgpu_mes * mes,struct mes_misc_op_input * input)476 static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
477 			     struct mes_misc_op_input *input)
478 {
479 	union MESAPI__MISC misc_pkt;
480 	int pipe;
481 
482 	if (mes->adev->enable_uni_mes)
483 		pipe = AMDGPU_MES_KIQ_PIPE;
484 	else
485 		pipe = AMDGPU_MES_SCHED_PIPE;
486 
487 	memset(&misc_pkt, 0, sizeof(misc_pkt));
488 
489 	misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
490 	misc_pkt.header.opcode = MES_SCH_API_MISC;
491 	misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
492 
493 	switch (input->op) {
494 	case MES_MISC_OP_READ_REG:
495 		misc_pkt.opcode = MESAPI_MISC__READ_REG;
496 		misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
497 		misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
498 		break;
499 	case MES_MISC_OP_WRITE_REG:
500 		misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
501 		misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
502 		misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
503 		break;
504 	case MES_MISC_OP_WRM_REG_WAIT:
505 		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
506 		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
507 		misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
508 		misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
509 		misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
510 		misc_pkt.wait_reg_mem.reg_offset2 = 0;
511 		break;
512 	case MES_MISC_OP_WRM_REG_WR_WAIT:
513 		misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
514 		misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
515 		misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
516 		misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
517 		misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
518 		misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
519 		break;
520 	case MES_MISC_OP_SET_SHADER_DEBUGGER:
521 		pipe = AMDGPU_MES_SCHED_PIPE;
522 		misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
523 		misc_pkt.set_shader_debugger.process_context_addr =
524 				input->set_shader_debugger.process_context_addr;
525 		misc_pkt.set_shader_debugger.flags.u32all =
526 				input->set_shader_debugger.flags.u32all;
527 		misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
528 				input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
529 		memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
530 				input->set_shader_debugger.tcp_watch_cntl,
531 				sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
532 		misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
533 		break;
534 	case MES_MISC_OP_CHANGE_CONFIG:
535 		misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG;
536 		misc_pkt.change_config.opcode =
537 				MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS;
538 		misc_pkt.change_config.option.bits.limit_single_process =
539 				input->change_config.option.limit_single_process;
540 		break;
541 
542 	default:
543 		DRM_ERROR("unsupported misc op (%d) \n", input->op);
544 		return -EINVAL;
545 	}
546 
547 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
548 			&misc_pkt, sizeof(misc_pkt),
549 			offsetof(union MESAPI__MISC, api_status));
550 }
551 
mes_v12_0_set_hw_resources_1(struct amdgpu_mes * mes,int pipe)552 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
553 {
554 	union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
555 
556 	memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
557 
558 	mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
559 	mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
560 	mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
561 	mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
562 
563 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
564 			&mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
565 			offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
566 }
567 
mes_v12_0_set_hw_resources(struct amdgpu_mes * mes,int pipe)568 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
569 {
570 	int i;
571 	struct amdgpu_device *adev = mes->adev;
572 	union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
573 
574 	memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
575 
576 	mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
577 	mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
578 	mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
579 
580 	if (pipe == AMDGPU_MES_SCHED_PIPE) {
581 		mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
582 		mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
583 		mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
584 		mes_set_hw_res_pkt.paging_vmid = 0;
585 
586 		for (i = 0; i < MAX_COMPUTE_PIPES; i++)
587 			mes_set_hw_res_pkt.compute_hqd_mask[i] =
588 				mes->compute_hqd_mask[i];
589 
590 		for (i = 0; i < MAX_GFX_PIPES; i++)
591 			mes_set_hw_res_pkt.gfx_hqd_mask[i] =
592 				mes->gfx_hqd_mask[i];
593 
594 		for (i = 0; i < MAX_SDMA_PIPES; i++)
595 			mes_set_hw_res_pkt.sdma_hqd_mask[i] =
596 				mes->sdma_hqd_mask[i];
597 
598 		for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
599 			mes_set_hw_res_pkt.aggregated_doorbells[i] =
600 				mes->aggregated_doorbells[i];
601 	}
602 
603 	mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr =
604 		mes->sch_ctx_gpu_addr[pipe];
605 	mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
606 		mes->query_status_fence_gpu_addr[pipe];
607 
608 	for (i = 0; i < 5; i++) {
609 		mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
610 		mes_set_hw_res_pkt.mmhub_base[i] =
611 				adev->reg_offset[MMHUB_HWIP][0][i];
612 		mes_set_hw_res_pkt.osssys_base[i] =
613 		adev->reg_offset[OSSSYS_HWIP][0][i];
614 	}
615 
616 	mes_set_hw_res_pkt.disable_reset = 1;
617 	mes_set_hw_res_pkt.disable_mes_log = 1;
618 	mes_set_hw_res_pkt.use_different_vmid_compute = 1;
619 	mes_set_hw_res_pkt.enable_reg_active_poll = 1;
620 	mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
621 
622 	/*
623 	 * Keep oversubscribe timer for sdma . When we have unmapped doorbell
624 	 * handling support, other queue will not use the oversubscribe timer.
625 	 * handling  mode - 0: disabled; 1: basic version; 2: basic+ version
626 	 */
627 	mes_set_hw_res_pkt.oversubscription_timer = 50;
628 	mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
629 
630 	if (amdgpu_mes_log_enable) {
631 		mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
632 		mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + pipe * AMDGPU_MES_LOG_BUFFER_SIZE;
633 	}
634 
635 	if (enforce_isolation)
636 		mes_set_hw_res_pkt.limit_single_process = 1;
637 
638 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
639 			&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
640 			offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
641 }
642 
mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes * mes)643 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
644 {
645 	struct amdgpu_device *adev = mes->adev;
646 	uint32_t data;
647 
648 	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
649 	data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
650 		  CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
651 		  CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
652 	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
653 		CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
654 	data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
655 	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
656 
657 	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
658 	data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
659 		  CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
660 		  CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
661 	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
662 		CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
663 	data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
664 	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
665 
666 	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
667 	data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
668 		  CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
669 		  CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
670 	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
671 		CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
672 	data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
673 	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
674 
675 	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
676 	data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
677 		  CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
678 		  CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
679 	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
680 		CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
681 	data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
682 	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
683 
684 	data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
685 	data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
686 		  CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
687 		  CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
688 	data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
689 		CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
690 	data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
691 	WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
692 
693 	data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
694 	WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
695 }
696 
697 
mes_v12_0_enable_unmapped_doorbell_handling(struct amdgpu_mes * mes,bool enable)698 static void mes_v12_0_enable_unmapped_doorbell_handling(
699 		struct amdgpu_mes *mes, bool enable)
700 {
701 	struct amdgpu_device *adev = mes->adev;
702 	uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);
703 
704 	/*
705 	 * The default PROC_LSB settng is 0xc which means doorbell
706 	 * addr[16:12] gives the doorbell page number. For kfd, each
707 	 * process will use 2 pages of doorbell, we need to change the
708 	 * setting to 0xd
709 	 */
710 	data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;
711 	data |= 0xd <<  CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;
712 
713 	data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;
714 
715 	WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data);
716 }
717 
mes_v12_0_reset_legacy_queue(struct amdgpu_mes * mes,struct mes_reset_legacy_queue_input * input)718 static int mes_v12_0_reset_legacy_queue(struct amdgpu_mes *mes,
719 					struct mes_reset_legacy_queue_input *input)
720 {
721 	union MESAPI__RESET mes_reset_queue_pkt;
722 	int pipe;
723 
724 	memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
725 
726 	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
727 	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;
728 	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
729 
730 	mes_reset_queue_pkt.queue_type =
731 		convert_to_mes_queue_type(input->queue_type);
732 
733 	if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) {
734 		mes_reset_queue_pkt.reset_legacy_gfx = 1;
735 		mes_reset_queue_pkt.pipe_id_lp = input->pipe_id;
736 		mes_reset_queue_pkt.queue_id_lp = input->queue_id;
737 		mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr;
738 		mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset;
739 		mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr;
740 		mes_reset_queue_pkt.vmid_id_lp = input->vmid;
741 	} else {
742 		mes_reset_queue_pkt.reset_queue_only = 1;
743 		mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
744 	}
745 
746 	if (mes->adev->enable_uni_mes)
747 		pipe = AMDGPU_MES_KIQ_PIPE;
748 	else
749 		pipe = AMDGPU_MES_SCHED_PIPE;
750 
751 	return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
752 			&mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),
753 			offsetof(union MESAPI__RESET, api_status));
754 }
755 
756 static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
757 	.add_hw_queue = mes_v12_0_add_hw_queue,
758 	.remove_hw_queue = mes_v12_0_remove_hw_queue,
759 	.map_legacy_queue = mes_v12_0_map_legacy_queue,
760 	.unmap_legacy_queue = mes_v12_0_unmap_legacy_queue,
761 	.suspend_gang = mes_v12_0_suspend_gang,
762 	.resume_gang = mes_v12_0_resume_gang,
763 	.misc_op = mes_v12_0_misc_op,
764 	.reset_legacy_queue = mes_v12_0_reset_legacy_queue,
765 	.reset_hw_queue = mes_v12_0_reset_hw_queue,
766 };
767 
mes_v12_0_allocate_ucode_buffer(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)768 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
769 					   enum admgpu_mes_pipe pipe)
770 {
771 	int r;
772 	const struct mes_firmware_header_v1_0 *mes_hdr;
773 	const __le32 *fw_data;
774 	unsigned fw_size;
775 
776 	mes_hdr = (const struct mes_firmware_header_v1_0 *)
777 		adev->mes.fw[pipe]->data;
778 
779 	fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
780 		   le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
781 	fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
782 
783 	r = amdgpu_bo_create_reserved(adev, fw_size,
784 				      PAGE_SIZE,
785 				      AMDGPU_GEM_DOMAIN_VRAM,
786 				      &adev->mes.ucode_fw_obj[pipe],
787 				      &adev->mes.ucode_fw_gpu_addr[pipe],
788 				      (void **)&adev->mes.ucode_fw_ptr[pipe]);
789 	if (r) {
790 		dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
791 		return r;
792 	}
793 
794 	memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
795 
796 	amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
797 	amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
798 
799 	return 0;
800 }
801 
mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)802 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
803 						enum admgpu_mes_pipe pipe)
804 {
805 	int r;
806 	const struct mes_firmware_header_v1_0 *mes_hdr;
807 	const __le32 *fw_data;
808 	unsigned fw_size;
809 
810 	mes_hdr = (const struct mes_firmware_header_v1_0 *)
811 		adev->mes.fw[pipe]->data;
812 
813 	fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
814 		   le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
815 	fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
816 
817 	r = amdgpu_bo_create_reserved(adev, fw_size,
818 				      64 * 1024,
819 				      AMDGPU_GEM_DOMAIN_VRAM,
820 				      &adev->mes.data_fw_obj[pipe],
821 				      &adev->mes.data_fw_gpu_addr[pipe],
822 				      (void **)&adev->mes.data_fw_ptr[pipe]);
823 	if (r) {
824 		dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
825 		return r;
826 	}
827 
828 	memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
829 
830 	amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
831 	amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
832 
833 	return 0;
834 }
835 
mes_v12_0_free_ucode_buffers(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)836 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,
837 					 enum admgpu_mes_pipe pipe)
838 {
839 	amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
840 			      &adev->mes.data_fw_gpu_addr[pipe],
841 			      (void **)&adev->mes.data_fw_ptr[pipe]);
842 
843 	amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
844 			      &adev->mes.ucode_fw_gpu_addr[pipe],
845 			      (void **)&adev->mes.ucode_fw_ptr[pipe]);
846 }
847 
mes_v12_0_enable(struct amdgpu_device * adev,bool enable)848 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
849 {
850 	uint64_t ucode_addr;
851 	uint32_t pipe, data = 0;
852 
853 	if (enable) {
854 		data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
855 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
856 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
857 		WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
858 
859 		mutex_lock(&adev->srbm_mutex);
860 		for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
861 			soc21_grbm_select(adev, 3, pipe, 0, 0);
862 
863 			ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
864 			WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
865 				     lower_32_bits(ucode_addr));
866 			WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
867 				     upper_32_bits(ucode_addr));
868 		}
869 		soc21_grbm_select(adev, 0, 0, 0, 0);
870 		mutex_unlock(&adev->srbm_mutex);
871 
872 		/* unhalt MES and activate pipe0 */
873 		data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
874 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
875 		WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
876 
877 		if (amdgpu_emu_mode)
878 			msleep(100);
879 		else if (adev->enable_uni_mes)
880 			udelay(500);
881 		else
882 			udelay(50);
883 	} else {
884 		data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
885 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
886 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
887 		data = REG_SET_FIELD(data, CP_MES_CNTL,
888 				     MES_INVALIDATE_ICACHE, 1);
889 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
890 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
891 		data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
892 		WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
893 	}
894 }
895 
mes_v12_0_set_ucode_start_addr(struct amdgpu_device * adev)896 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)
897 {
898 	uint64_t ucode_addr;
899 	int pipe;
900 
901 	mes_v12_0_enable(adev, false);
902 
903 	mutex_lock(&adev->srbm_mutex);
904 	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
905 		/* me=3, queue=0 */
906 		soc21_grbm_select(adev, 3, pipe, 0, 0);
907 
908 		/* set ucode start address */
909 		ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
910 		WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
911 				lower_32_bits(ucode_addr));
912 		WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
913 				upper_32_bits(ucode_addr));
914 
915 		soc21_grbm_select(adev, 0, 0, 0, 0);
916 	}
917 	mutex_unlock(&adev->srbm_mutex);
918 }
919 
920 /* This function is for backdoor MES firmware */
mes_v12_0_load_microcode(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe,bool prime_icache)921 static int mes_v12_0_load_microcode(struct amdgpu_device *adev,
922 				    enum admgpu_mes_pipe pipe, bool prime_icache)
923 {
924 	int r;
925 	uint32_t data;
926 
927 	mes_v12_0_enable(adev, false);
928 
929 	if (!adev->mes.fw[pipe])
930 		return -EINVAL;
931 
932 	r = mes_v12_0_allocate_ucode_buffer(adev, pipe);
933 	if (r)
934 		return r;
935 
936 	r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);
937 	if (r) {
938 		mes_v12_0_free_ucode_buffers(adev, pipe);
939 		return r;
940 	}
941 
942 	mutex_lock(&adev->srbm_mutex);
943 	/* me=3, pipe=0, queue=0 */
944 	soc21_grbm_select(adev, 3, pipe, 0, 0);
945 
946 	WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
947 
948 	/* set ucode fimrware address */
949 	WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
950 		     lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
951 	WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
952 		     upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
953 
954 	/* set ucode instruction cache boundary to 2M-1 */
955 	WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
956 
957 	/* set ucode data firmware address */
958 	WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
959 		     lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
960 	WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
961 		     upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
962 
963 	/* Set data cache boundary CP_MES_MDBOUND_LO */
964 	WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
965 
966 	if (prime_icache) {
967 		/* invalidate ICACHE */
968 		data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
969 		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
970 		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
971 		WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
972 
973 		/* prime the ICACHE. */
974 		data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
975 		data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
976 		WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
977 	}
978 
979 	soc21_grbm_select(adev, 0, 0, 0, 0);
980 	mutex_unlock(&adev->srbm_mutex);
981 
982 	return 0;
983 }
984 
mes_v12_0_allocate_eop_buf(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)985 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,
986 				      enum admgpu_mes_pipe pipe)
987 {
988 	int r;
989 	u32 *eop;
990 
991 	r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
992 			      AMDGPU_GEM_DOMAIN_GTT,
993 			      &adev->mes.eop_gpu_obj[pipe],
994 			      &adev->mes.eop_gpu_addr[pipe],
995 			      (void **)&eop);
996 	if (r) {
997 		dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
998 		return r;
999 	}
1000 
1001 	memset(eop, 0,
1002 	       adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
1003 
1004 	amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
1005 	amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
1006 
1007 	return 0;
1008 }
1009 
mes_v12_0_mqd_init(struct amdgpu_ring * ring)1010 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)
1011 {
1012 	struct v12_compute_mqd *mqd = ring->mqd_ptr;
1013 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1014 	uint32_t tmp;
1015 
1016 	mqd->header = 0xC0310800;
1017 	mqd->compute_pipelinestat_enable = 0x00000001;
1018 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1019 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1020 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1021 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1022 	mqd->compute_misc_reserved = 0x00000007;
1023 
1024 	eop_base_addr = ring->eop_gpu_addr >> 8;
1025 
1026 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1027 	tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
1028 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1029 			(order_base_2(MES_EOP_SIZE / 4) - 1));
1030 
1031 	mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
1032 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1033 	mqd->cp_hqd_eop_control = tmp;
1034 
1035 	/* disable the queue if it's active */
1036 	ring->wptr = 0;
1037 	mqd->cp_hqd_pq_rptr = 0;
1038 	mqd->cp_hqd_pq_wptr_lo = 0;
1039 	mqd->cp_hqd_pq_wptr_hi = 0;
1040 
1041 	/* set the pointer to the MQD */
1042 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1043 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1044 
1045 	/* set MQD vmid to 0 */
1046 	tmp = regCP_MQD_CONTROL_DEFAULT;
1047 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1048 	mqd->cp_mqd_control = tmp;
1049 
1050 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1051 	hqd_gpu_addr = ring->gpu_addr >> 8;
1052 	mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
1053 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1054 
1055 	/* set the wb address whether it's enabled or not */
1056 	wb_gpu_addr = ring->rptr_gpu_addr;
1057 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1058 	mqd->cp_hqd_pq_rptr_report_addr_hi =
1059 		upper_32_bits(wb_gpu_addr) & 0xffff;
1060 
1061 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1062 	wb_gpu_addr = ring->wptr_gpu_addr;
1063 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
1064 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1065 
1066 	/* set up the HQD, this is similar to CP_RB0_CNTL */
1067 	tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
1068 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1069 			    (order_base_2(ring->ring_size / 4) - 1));
1070 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1071 			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1072 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
1073 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
1074 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1075 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1076 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
1077 	mqd->cp_hqd_pq_control = tmp;
1078 
1079 	/* enable doorbell */
1080 	tmp = 0;
1081 	if (ring->use_doorbell) {
1082 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1083 				    DOORBELL_OFFSET, ring->doorbell_index);
1084 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1085 				    DOORBELL_EN, 1);
1086 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1087 				    DOORBELL_SOURCE, 0);
1088 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1089 				    DOORBELL_HIT, 0);
1090 	} else {
1091 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1092 				    DOORBELL_EN, 0);
1093 	}
1094 	mqd->cp_hqd_pq_doorbell_control = tmp;
1095 
1096 	mqd->cp_hqd_vmid = 0;
1097 	/* activate the queue */
1098 	mqd->cp_hqd_active = 1;
1099 
1100 	tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
1101 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
1102 			    PRELOAD_SIZE, 0x55);
1103 	mqd->cp_hqd_persistent_state = tmp;
1104 
1105 	mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
1106 	mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
1107 	mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
1108 
1109 	/*
1110 	 * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped
1111 	 * doorbell handling. This is a reserved CP internal register can
1112 	 * not be accesss by others
1113 	 */
1114 	mqd->reserved_184 = BIT(15);
1115 
1116 	return 0;
1117 }
1118 
mes_v12_0_queue_init_register(struct amdgpu_ring * ring)1119 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)
1120 {
1121 	struct v12_compute_mqd *mqd = ring->mqd_ptr;
1122 	struct amdgpu_device *adev = ring->adev;
1123 	uint32_t data = 0;
1124 
1125 	mutex_lock(&adev->srbm_mutex);
1126 	soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1127 
1128 	/* set CP_HQD_VMID.VMID = 0. */
1129 	data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
1130 	data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1131 	WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1132 
1133 	/* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1134 	data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1135 	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1136 			     DOORBELL_EN, 0);
1137 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1138 
1139 	/* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1140 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1141 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1142 
1143 	/* set CP_MQD_CONTROL.VMID=0 */
1144 	data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1145 	data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1146 	WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1147 
1148 	/* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1149 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1150 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1151 
1152 	/* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1153 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1154 		     mqd->cp_hqd_pq_rptr_report_addr_lo);
1155 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1156 		     mqd->cp_hqd_pq_rptr_report_addr_hi);
1157 
1158 	/* set CP_HQD_PQ_CONTROL */
1159 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1160 
1161 	/* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1162 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1163 		     mqd->cp_hqd_pq_wptr_poll_addr_lo);
1164 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1165 		     mqd->cp_hqd_pq_wptr_poll_addr_hi);
1166 
1167 	/* set CP_HQD_PQ_DOORBELL_CONTROL */
1168 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1169 		     mqd->cp_hqd_pq_doorbell_control);
1170 
1171 	/* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1172 	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1173 
1174 	/* set CP_HQD_ACTIVE.ACTIVE=1 */
1175 	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1176 
1177 	soc21_grbm_select(adev, 0, 0, 0, 0);
1178 	mutex_unlock(&adev->srbm_mutex);
1179 }
1180 
mes_v12_0_kiq_enable_queue(struct amdgpu_device * adev)1181 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)
1182 {
1183 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1184 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1185 	int r;
1186 
1187 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1188 		return -EINVAL;
1189 
1190 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1191 	if (r) {
1192 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1193 		return r;
1194 	}
1195 
1196 	kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
1197 
1198 	r = amdgpu_ring_test_ring(kiq_ring);
1199 	if (r) {
1200 		DRM_ERROR("kfq enable failed\n");
1201 		kiq_ring->sched.ready = false;
1202 	}
1203 	return r;
1204 }
1205 
mes_v12_0_queue_init(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)1206 static int mes_v12_0_queue_init(struct amdgpu_device *adev,
1207 				enum admgpu_mes_pipe pipe)
1208 {
1209 	struct amdgpu_ring *ring;
1210 	int r;
1211 
1212 	if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1213 		ring = &adev->gfx.kiq[0].ring;
1214 	else
1215 		ring = &adev->mes.ring[pipe];
1216 
1217 	if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) &&
1218 	    (amdgpu_in_reset(adev) || adev->in_suspend)) {
1219 		*(ring->wptr_cpu_addr) = 0;
1220 		*(ring->rptr_cpu_addr) = 0;
1221 		amdgpu_ring_clear_ring(ring);
1222 	}
1223 
1224 	r = mes_v12_0_mqd_init(ring);
1225 	if (r)
1226 		return r;
1227 
1228 	if (pipe == AMDGPU_MES_SCHED_PIPE) {
1229 		if (adev->enable_uni_mes)
1230 			r = amdgpu_mes_map_legacy_queue(adev, ring);
1231 		else
1232 			r = mes_v12_0_kiq_enable_queue(adev);
1233 		if (r)
1234 			return r;
1235 	} else {
1236 		mes_v12_0_queue_init_register(ring);
1237 	}
1238 
1239 	/* get MES scheduler/KIQ versions */
1240 	mutex_lock(&adev->srbm_mutex);
1241 	soc21_grbm_select(adev, 3, pipe, 0, 0);
1242 
1243 	if (pipe == AMDGPU_MES_SCHED_PIPE)
1244 		adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1245 	else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1246 		adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1247 
1248 	soc21_grbm_select(adev, 0, 0, 0, 0);
1249 	mutex_unlock(&adev->srbm_mutex);
1250 
1251 	return 0;
1252 }
1253 
mes_v12_0_ring_init(struct amdgpu_device * adev,int pipe)1254 static int mes_v12_0_ring_init(struct amdgpu_device *adev, int pipe)
1255 {
1256 	struct amdgpu_ring *ring;
1257 
1258 	ring = &adev->mes.ring[pipe];
1259 
1260 	ring->funcs = &mes_v12_0_ring_funcs;
1261 
1262 	ring->me = 3;
1263 	ring->pipe = pipe;
1264 	ring->queue = 0;
1265 
1266 	ring->ring_obj = NULL;
1267 	ring->use_doorbell = true;
1268 	ring->eop_gpu_addr = adev->mes.eop_gpu_addr[pipe];
1269 	ring->no_scheduler = true;
1270 	sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1271 
1272 	if (pipe == AMDGPU_MES_SCHED_PIPE)
1273 		ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1274 	else
1275 		ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1276 
1277 	return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1278 				AMDGPU_RING_PRIO_DEFAULT, NULL);
1279 }
1280 
mes_v12_0_kiq_ring_init(struct amdgpu_device * adev)1281 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)
1282 {
1283 	struct amdgpu_ring *ring;
1284 
1285 	spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1286 
1287 	ring = &adev->gfx.kiq[0].ring;
1288 
1289 	ring->me = 3;
1290 	ring->pipe = 1;
1291 	ring->queue = 0;
1292 
1293 	ring->adev = NULL;
1294 	ring->ring_obj = NULL;
1295 	ring->use_doorbell = true;
1296 	ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1297 	ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1298 	ring->no_scheduler = true;
1299 	sprintf(ring->name, "mes_kiq_%d.%d.%d",
1300 		ring->me, ring->pipe, ring->queue);
1301 
1302 	return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1303 				AMDGPU_RING_PRIO_DEFAULT, NULL);
1304 }
1305 
mes_v12_0_mqd_sw_init(struct amdgpu_device * adev,enum admgpu_mes_pipe pipe)1306 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,
1307 				 enum admgpu_mes_pipe pipe)
1308 {
1309 	int r, mqd_size = sizeof(struct v12_compute_mqd);
1310 	struct amdgpu_ring *ring;
1311 
1312 	if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1313 		ring = &adev->gfx.kiq[0].ring;
1314 	else
1315 		ring = &adev->mes.ring[pipe];
1316 
1317 	if (ring->mqd_obj)
1318 		return 0;
1319 
1320 	r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1321 				    AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1322 				    &ring->mqd_gpu_addr, &ring->mqd_ptr);
1323 	if (r) {
1324 		dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1325 		return r;
1326 	}
1327 
1328 	memset(ring->mqd_ptr, 0, mqd_size);
1329 
1330 	/* prepare MQD backup */
1331 	adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1332 	if (!adev->mes.mqd_backup[pipe])
1333 		dev_warn(adev->dev,
1334 			 "no memory to create MQD backup for ring %s\n",
1335 			 ring->name);
1336 
1337 	return 0;
1338 }
1339 
mes_v12_0_sw_init(struct amdgpu_ip_block * ip_block)1340 static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
1341 {
1342 	struct amdgpu_device *adev = ip_block->adev;
1343 	int pipe, r;
1344 
1345 	adev->mes.funcs = &mes_v12_0_funcs;
1346 	adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
1347 	adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
1348 	adev->mes.enable_legacy_queue_map = true;
1349 
1350 	adev->mes.event_log_size = adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE) : AMDGPU_MES_LOG_BUFFER_SIZE;
1351 
1352 	r = amdgpu_mes_init(adev);
1353 	if (r)
1354 		return r;
1355 
1356 	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1357 		r = mes_v12_0_allocate_eop_buf(adev, pipe);
1358 		if (r)
1359 			return r;
1360 
1361 		r = mes_v12_0_mqd_sw_init(adev, pipe);
1362 		if (r)
1363 			return r;
1364 
1365 		if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE)
1366 			r = mes_v12_0_kiq_ring_init(adev);
1367 		else
1368 			r = mes_v12_0_ring_init(adev, pipe);
1369 		if (r)
1370 			return r;
1371 	}
1372 
1373 	return 0;
1374 }
1375 
mes_v12_0_sw_fini(struct amdgpu_ip_block * ip_block)1376 static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
1377 {
1378 	struct amdgpu_device *adev = ip_block->adev;
1379 	int pipe;
1380 
1381 	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1382 		kfree(adev->mes.mqd_backup[pipe]);
1383 
1384 		amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1385 				      &adev->mes.eop_gpu_addr[pipe],
1386 				      NULL);
1387 		amdgpu_ucode_release(&adev->mes.fw[pipe]);
1388 
1389 		if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) {
1390 			amdgpu_bo_free_kernel(&adev->mes.ring[pipe].mqd_obj,
1391 					      &adev->mes.ring[pipe].mqd_gpu_addr,
1392 					      &adev->mes.ring[pipe].mqd_ptr);
1393 			amdgpu_ring_fini(&adev->mes.ring[pipe]);
1394 		}
1395 	}
1396 
1397 	if (!adev->enable_uni_mes) {
1398 		amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1399 				      &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1400 				      &adev->gfx.kiq[0].ring.mqd_ptr);
1401 		amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1402 	}
1403 
1404 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1405 		mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1406 		mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1407 	}
1408 
1409 	amdgpu_mes_fini(adev);
1410 	return 0;
1411 }
1412 
mes_v12_0_kiq_dequeue_sched(struct amdgpu_device * adev)1413 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)
1414 {
1415 	uint32_t data;
1416 	int i;
1417 
1418 	mutex_lock(&adev->srbm_mutex);
1419 	soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
1420 
1421 	/* disable the queue if it's active */
1422 	if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1423 		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1424 		for (i = 0; i < adev->usec_timeout; i++) {
1425 			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1426 				break;
1427 			udelay(1);
1428 		}
1429 	}
1430 	data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1431 	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1432 				DOORBELL_EN, 0);
1433 	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1434 				DOORBELL_HIT, 1);
1435 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1436 
1437 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1438 
1439 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1440 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1441 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1442 
1443 	soc21_grbm_select(adev, 0, 0, 0, 0);
1444 	mutex_unlock(&adev->srbm_mutex);
1445 
1446 	adev->mes.ring[0].sched.ready = false;
1447 }
1448 
mes_v12_0_kiq_setting(struct amdgpu_ring * ring)1449 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)
1450 {
1451 	uint32_t tmp;
1452 	struct amdgpu_device *adev = ring->adev;
1453 
1454 	/* tell RLC which is KIQ queue */
1455 	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1456 	tmp &= 0xffffff00;
1457 	tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1458 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1459 	tmp |= 0x80;
1460 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1461 }
1462 
mes_v12_0_kiq_hw_init(struct amdgpu_device * adev)1463 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
1464 {
1465 	int r = 0;
1466 	struct amdgpu_ip_block *ip_block;
1467 
1468 	if (adev->enable_uni_mes)
1469 		mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]);
1470 	else
1471 		mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring);
1472 
1473 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1474 
1475 		r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1476 		if (r) {
1477 			DRM_ERROR("failed to load MES fw, r=%d\n", r);
1478 			return r;
1479 		}
1480 
1481 		r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1482 		if (r) {
1483 			DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1484 			return r;
1485 		}
1486 
1487 		mes_v12_0_set_ucode_start_addr(adev);
1488 
1489 	} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1490 		mes_v12_0_set_ucode_start_addr(adev);
1491 
1492 	mes_v12_0_enable(adev, true);
1493 
1494 	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES);
1495 	if (unlikely(!ip_block)) {
1496 		dev_err(adev->dev, "Failed to get MES handle\n");
1497 		return -EINVAL;
1498 	}
1499 
1500 	r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1501 	if (r)
1502 		goto failure;
1503 
1504 	if (adev->enable_uni_mes) {
1505 		r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1506 		if (r)
1507 			goto failure;
1508 
1509 		mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);
1510 	}
1511 
1512 	if (adev->mes.enable_legacy_queue_map) {
1513 		r = mes_v12_0_hw_init(ip_block);
1514 		if (r)
1515 			goto failure;
1516 	}
1517 
1518 	return r;
1519 
1520 failure:
1521 	mes_v12_0_hw_fini(ip_block);
1522 	return r;
1523 }
1524 
mes_v12_0_kiq_hw_fini(struct amdgpu_device * adev)1525 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)
1526 {
1527 	if (adev->mes.ring[0].sched.ready) {
1528 		if (adev->enable_uni_mes)
1529 			amdgpu_mes_unmap_legacy_queue(adev,
1530 				      &adev->mes.ring[AMDGPU_MES_SCHED_PIPE],
1531 				      RESET_QUEUES, 0, 0);
1532 		else
1533 			mes_v12_0_kiq_dequeue_sched(adev);
1534 
1535 		adev->mes.ring[0].sched.ready = false;
1536 	}
1537 
1538 	mes_v12_0_enable(adev, false);
1539 
1540 	return 0;
1541 }
1542 
mes_v12_0_hw_init(struct amdgpu_ip_block * ip_block)1543 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
1544 {
1545 	int r;
1546 	struct amdgpu_device *adev = ip_block->adev;
1547 
1548 	if (adev->mes.ring[0].sched.ready)
1549 		goto out;
1550 
1551 	if (!adev->enable_mes_kiq) {
1552 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1553 			r = mes_v12_0_load_microcode(adev,
1554 					     AMDGPU_MES_SCHED_PIPE, true);
1555 			if (r) {
1556 				DRM_ERROR("failed to MES fw, r=%d\n", r);
1557 				return r;
1558 			}
1559 
1560 			mes_v12_0_set_ucode_start_addr(adev);
1561 
1562 		} else if (adev->firmware.load_type ==
1563 			   AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1564 
1565 			mes_v12_0_set_ucode_start_addr(adev);
1566 		}
1567 
1568 		mes_v12_0_enable(adev, true);
1569 	}
1570 
1571 	/* Enable the MES to handle doorbell ring on unmapped queue */
1572 	mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true);
1573 
1574 	r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1575 	if (r)
1576 		goto failure;
1577 
1578 	r = mes_v12_0_set_hw_resources(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1579 	if (r)
1580 		goto failure;
1581 
1582 	if (adev->enable_uni_mes)
1583 		mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1584 
1585 	mes_v12_0_init_aggregated_doorbell(&adev->mes);
1586 
1587 	r = mes_v12_0_query_sched_status(&adev->mes, AMDGPU_MES_SCHED_PIPE);
1588 	if (r) {
1589 		DRM_ERROR("MES is busy\n");
1590 		goto failure;
1591 	}
1592 
1593 out:
1594 	/*
1595 	 * Disable KIQ ring usage from the driver once MES is enabled.
1596 	 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1597 	 * with MES enabled.
1598 	 */
1599 	adev->gfx.kiq[0].ring.sched.ready = false;
1600 	adev->mes.ring[0].sched.ready = true;
1601 
1602 	return 0;
1603 
1604 failure:
1605 	mes_v12_0_hw_fini(ip_block);
1606 	return r;
1607 }
1608 
mes_v12_0_hw_fini(struct amdgpu_ip_block * ip_block)1609 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
1610 {
1611 	return 0;
1612 }
1613 
mes_v12_0_suspend(struct amdgpu_ip_block * ip_block)1614 static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block)
1615 {
1616 	int r;
1617 
1618 	r = amdgpu_mes_suspend(ip_block->adev);
1619 	if (r)
1620 		return r;
1621 
1622 	return mes_v12_0_hw_fini(ip_block);
1623 }
1624 
mes_v12_0_resume(struct amdgpu_ip_block * ip_block)1625 static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block)
1626 {
1627 	int r;
1628 
1629 	r = mes_v12_0_hw_init(ip_block);
1630 	if (r)
1631 		return r;
1632 
1633 	return amdgpu_mes_resume(ip_block->adev);
1634 }
1635 
mes_v12_0_early_init(struct amdgpu_ip_block * ip_block)1636 static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block)
1637 {
1638 	struct amdgpu_device *adev = ip_block->adev;
1639 	int pipe, r;
1640 
1641 	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1642 		r = amdgpu_mes_init_microcode(adev, pipe);
1643 		if (r)
1644 			return r;
1645 	}
1646 
1647 	return 0;
1648 }
1649 
mes_v12_0_late_init(struct amdgpu_ip_block * ip_block)1650 static int mes_v12_0_late_init(struct amdgpu_ip_block *ip_block)
1651 {
1652 	struct amdgpu_device *adev = ip_block->adev;
1653 
1654 	/* it's only intended for use in mes_self_test case, not for s0ix and reset */
1655 	if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend)
1656 		amdgpu_mes_self_test(adev);
1657 
1658 	return 0;
1659 }
1660 
1661 static const struct amd_ip_funcs mes_v12_0_ip_funcs = {
1662 	.name = "mes_v12_0",
1663 	.early_init = mes_v12_0_early_init,
1664 	.late_init = mes_v12_0_late_init,
1665 	.sw_init = mes_v12_0_sw_init,
1666 	.sw_fini = mes_v12_0_sw_fini,
1667 	.hw_init = mes_v12_0_hw_init,
1668 	.hw_fini = mes_v12_0_hw_fini,
1669 	.suspend = mes_v12_0_suspend,
1670 	.resume = mes_v12_0_resume,
1671 };
1672 
1673 const struct amdgpu_ip_block_version mes_v12_0_ip_block = {
1674 	.type = AMD_IP_BLOCK_TYPE_MES,
1675 	.major = 12,
1676 	.minor = 0,
1677 	.rev = 0,
1678 	.funcs = &mes_v12_0_ip_funcs,
1679 };
1680