1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); 63 64 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 65 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 66 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 67 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 68 69 #define MES_EOP_SIZE 2048 70 #define GFX_MES_DRAM_SIZE 0x80000 71 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 72 73 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 74 #define MES11_HUNG_HQD_INFO_OFFSET 4 75 76 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 77 { 78 struct amdgpu_device *adev = ring->adev; 79 80 if (ring->use_doorbell) { 81 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 82 ring->wptr); 83 WDOORBELL64(ring->doorbell_index, ring->wptr); 84 } else { 85 BUG(); 86 } 87 } 88 89 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 90 { 91 return *ring->rptr_cpu_addr; 92 } 93 94 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 95 { 96 u64 wptr; 97 98 if (ring->use_doorbell) 99 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 100 else 101 BUG(); 102 return wptr; 103 } 104 105 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 106 .type = AMDGPU_RING_TYPE_MES, 107 .align_mask = 1, 108 .nop = 0, 109 .support_64bit_ptrs = true, 110 .get_rptr = mes_v11_0_ring_get_rptr, 111 .get_wptr = mes_v11_0_ring_get_wptr, 112 .set_wptr = mes_v11_0_ring_set_wptr, 113 .insert_nop = amdgpu_ring_insert_nop, 114 }; 115 116 static const char *mes_v11_0_opcodes[] = { 117 "SET_HW_RSRC", 118 "SET_SCHEDULING_CONFIG", 119 "ADD_QUEUE", 120 "REMOVE_QUEUE", 121 "PERFORM_YIELD", 122 "SET_GANG_PRIORITY_LEVEL", 123 "SUSPEND", 124 "RESUME", 125 "RESET", 126 "SET_LOG_BUFFER", 127 "CHANGE_GANG_PRORITY", 128 "QUERY_SCHEDULER_STATUS", 129 "PROGRAM_GDS", 130 "SET_DEBUG_VMID", 131 "MISC", 132 "UPDATE_ROOT_PAGE_TABLE", 133 "AMD_LOG", 134 "unused", 135 "unused", 136 "SET_HW_RSRC_1", 137 }; 138 139 static const char *mes_v11_0_misc_opcodes[] = { 140 "WRITE_REG", 141 "INV_GART", 142 "QUERY_STATUS", 143 "READ_REG", 144 "WAIT_REG_MEM", 145 "SET_SHADER_DEBUGGER", 146 }; 147 148 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 149 { 150 const char *op_str = NULL; 151 152 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 153 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 154 155 return op_str; 156 } 157 158 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 159 { 160 const char *op_str = NULL; 161 162 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 163 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 164 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 165 166 return op_str; 167 } 168 169 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 170 void *pkt, int size, 171 int api_status_off) 172 { 173 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 174 signed long timeout = 2100000; /* 2100 ms */ 175 struct amdgpu_device *adev = mes->adev; 176 struct amdgpu_ring *ring = &mes->ring[0]; 177 struct MES_API_STATUS *api_status; 178 union MESAPI__MISC *x_pkt = pkt; 179 const char *op_str, *misc_op_str; 180 unsigned long flags; 181 u64 status_gpu_addr; 182 u32 seq, status_offset; 183 u64 *status_ptr; 184 signed long r; 185 int ret; 186 187 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 188 return -EINVAL; 189 190 if (amdgpu_emu_mode) { 191 timeout *= 100; 192 } else if (amdgpu_sriov_vf(adev)) { 193 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 194 timeout = 15 * 600 * 1000; 195 } 196 197 ret = amdgpu_device_wb_get(adev, &status_offset); 198 if (ret) 199 return ret; 200 201 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 202 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 203 *status_ptr = 0; 204 205 spin_lock_irqsave(&mes->ring_lock[0], flags); 206 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 207 if (r) 208 goto error_unlock_free; 209 210 seq = ++ring->fence_drv.sync_seq; 211 r = amdgpu_fence_wait_polling(ring, 212 seq - ring->fence_drv.num_fences_mask, 213 timeout); 214 if (r < 1) 215 goto error_undo; 216 217 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 218 api_status->api_completion_fence_addr = status_gpu_addr; 219 api_status->api_completion_fence_value = 1; 220 221 amdgpu_ring_write_multiple(ring, pkt, size / 4); 222 223 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 224 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 225 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 226 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 227 mes_status_pkt.api_status.api_completion_fence_addr = 228 ring->fence_drv.gpu_addr; 229 mes_status_pkt.api_status.api_completion_fence_value = seq; 230 231 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 232 sizeof(mes_status_pkt) / 4); 233 234 amdgpu_ring_commit(ring); 235 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 236 237 op_str = mes_v11_0_get_op_string(x_pkt); 238 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 239 240 if (misc_op_str) 241 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 242 misc_op_str); 243 else if (op_str) 244 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 245 else 246 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 247 x_pkt->header.opcode); 248 249 r = amdgpu_fence_wait_polling(ring, seq, timeout); 250 if (r < 1 || !*status_ptr) { 251 252 if (misc_op_str) 253 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 254 op_str, misc_op_str); 255 else if (op_str) 256 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 257 op_str); 258 else 259 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 260 x_pkt->header.opcode); 261 262 while (halt_if_hws_hang) 263 schedule(); 264 265 r = -ETIMEDOUT; 266 goto error_wb_free; 267 } 268 269 amdgpu_device_wb_free(adev, status_offset); 270 return 0; 271 272 error_undo: 273 dev_err(adev->dev, "MES ring buffer is full.\n"); 274 amdgpu_ring_undo(ring); 275 276 error_unlock_free: 277 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 278 279 error_wb_free: 280 amdgpu_device_wb_free(adev, status_offset); 281 return r; 282 } 283 284 static int convert_to_mes_queue_type(int queue_type) 285 { 286 if (queue_type == AMDGPU_RING_TYPE_GFX) 287 return MES_QUEUE_TYPE_GFX; 288 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 289 return MES_QUEUE_TYPE_COMPUTE; 290 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 291 return MES_QUEUE_TYPE_SDMA; 292 else 293 BUG(); 294 return -1; 295 } 296 297 static int convert_to_mes_priority_level(int priority_level) 298 { 299 switch (priority_level) { 300 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 301 return AMD_PRIORITY_LEVEL_LOW; 302 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 303 default: 304 return AMD_PRIORITY_LEVEL_NORMAL; 305 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 306 return AMD_PRIORITY_LEVEL_MEDIUM; 307 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 308 return AMD_PRIORITY_LEVEL_HIGH; 309 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 310 return AMD_PRIORITY_LEVEL_REALTIME; 311 } 312 } 313 314 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 315 struct mes_add_queue_input *input) 316 { 317 struct amdgpu_device *adev = mes->adev; 318 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 319 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 320 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 321 322 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 323 324 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 325 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 326 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 327 328 mes_add_queue_pkt.process_id = input->process_id; 329 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 330 mes_add_queue_pkt.process_va_start = input->process_va_start; 331 mes_add_queue_pkt.process_va_end = input->process_va_end; 332 mes_add_queue_pkt.process_quantum = input->process_quantum; 333 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 334 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 335 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 336 mes_add_queue_pkt.inprocess_gang_priority = 337 convert_to_mes_priority_level(input->inprocess_gang_priority); 338 mes_add_queue_pkt.gang_global_priority_level = 339 convert_to_mes_priority_level(input->gang_global_priority_level); 340 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 341 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 342 343 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 344 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 345 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 346 else 347 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 348 349 mes_add_queue_pkt.queue_type = 350 convert_to_mes_queue_type(input->queue_type); 351 mes_add_queue_pkt.paging = input->paging; 352 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 353 mes_add_queue_pkt.gws_base = input->gws_base; 354 mes_add_queue_pkt.gws_size = input->gws_size; 355 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 356 mes_add_queue_pkt.tma_addr = input->tma_addr; 357 mes_add_queue_pkt.trap_en = input->trap_en; 358 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 359 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 360 361 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 362 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 363 mes_add_queue_pkt.gds_size = input->queue_size; 364 365 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 366 367 return mes_v11_0_submit_pkt_and_poll_completion(mes, 368 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 369 offsetof(union MESAPI__ADD_QUEUE, api_status)); 370 } 371 372 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 373 struct mes_remove_queue_input *input) 374 { 375 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 376 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 377 378 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 379 380 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 381 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 382 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 383 384 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 385 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 386 387 if (mes_rev >= 0x60) 388 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 389 390 return mes_v11_0_submit_pkt_and_poll_completion(mes, 391 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 392 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 393 } 394 395 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 396 uint32_t me_id, uint32_t pipe_id, 397 uint32_t queue_id, uint32_t vmid) 398 { 399 struct amdgpu_device *adev = mes->adev; 400 uint32_t value, reg; 401 int i, r = 0; 402 403 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 404 405 if (queue_type == AMDGPU_RING_TYPE_GFX) { 406 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 407 me_id, pipe_id, queue_id, vmid); 408 409 mutex_lock(&adev->gfx.reset_sem_mutex); 410 gfx_v11_0_request_gfx_index_mutex(adev, true); 411 /* all se allow writes */ 412 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 413 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 414 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 415 if (pipe_id == 0) 416 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 417 else 418 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 419 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 420 gfx_v11_0_request_gfx_index_mutex(adev, false); 421 mutex_unlock(&adev->gfx.reset_sem_mutex); 422 423 mutex_lock(&adev->srbm_mutex); 424 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 425 /* wait till dequeue take effects */ 426 for (i = 0; i < adev->usec_timeout; i++) { 427 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 428 break; 429 udelay(1); 430 } 431 if (i >= adev->usec_timeout) { 432 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 433 r = -ETIMEDOUT; 434 } 435 436 soc21_grbm_select(adev, 0, 0, 0, 0); 437 mutex_unlock(&adev->srbm_mutex); 438 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 439 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 440 me_id, pipe_id, queue_id); 441 mutex_lock(&adev->srbm_mutex); 442 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 443 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 444 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 445 446 /* wait till dequeue take effects */ 447 for (i = 0; i < adev->usec_timeout; i++) { 448 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 449 break; 450 udelay(1); 451 } 452 if (i >= adev->usec_timeout) { 453 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 454 r = -ETIMEDOUT; 455 } 456 soc21_grbm_select(adev, 0, 0, 0, 0); 457 mutex_unlock(&adev->srbm_mutex); 458 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 459 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 460 me_id, pipe_id, queue_id); 461 switch (me_id) { 462 case 1: 463 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 464 break; 465 case 0: 466 default: 467 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 468 break; 469 } 470 471 value = 1 << queue_id; 472 WREG32(reg, value); 473 /* wait for queue reset done */ 474 for (i = 0; i < adev->usec_timeout; i++) { 475 if (!(RREG32(reg) & value)) 476 break; 477 udelay(1); 478 } 479 if (i >= adev->usec_timeout) { 480 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 481 r = -ETIMEDOUT; 482 } 483 } 484 485 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 486 return r; 487 } 488 489 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 490 struct mes_map_legacy_queue_input *input) 491 { 492 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 493 494 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 495 496 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 497 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 498 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 499 500 mes_add_queue_pkt.pipe_id = input->pipe_id; 501 mes_add_queue_pkt.queue_id = input->queue_id; 502 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 503 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 504 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 505 mes_add_queue_pkt.queue_type = 506 convert_to_mes_queue_type(input->queue_type); 507 mes_add_queue_pkt.map_legacy_kq = 1; 508 509 return mes_v11_0_submit_pkt_and_poll_completion(mes, 510 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 511 offsetof(union MESAPI__ADD_QUEUE, api_status)); 512 } 513 514 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 515 struct mes_unmap_legacy_queue_input *input) 516 { 517 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 518 519 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 520 521 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 522 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 523 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 524 525 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 526 mes_remove_queue_pkt.gang_context_addr = 0; 527 528 mes_remove_queue_pkt.pipe_id = input->pipe_id; 529 mes_remove_queue_pkt.queue_id = input->queue_id; 530 531 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 532 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 533 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 534 mes_remove_queue_pkt.tf_data = 535 lower_32_bits(input->trail_fence_data); 536 } else { 537 mes_remove_queue_pkt.unmap_legacy_queue = 1; 538 mes_remove_queue_pkt.queue_type = 539 convert_to_mes_queue_type(input->queue_type); 540 } 541 542 return mes_v11_0_submit_pkt_and_poll_completion(mes, 543 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 544 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 545 } 546 547 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 548 struct mes_suspend_gang_input *input) 549 { 550 union MESAPI__SUSPEND mes_suspend_gang_pkt; 551 552 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 553 554 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 555 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 556 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 557 558 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 559 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 560 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 561 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 562 563 return mes_v11_0_submit_pkt_and_poll_completion(mes, 564 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 565 offsetof(union MESAPI__SUSPEND, api_status)); 566 } 567 568 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 569 struct mes_resume_gang_input *input) 570 { 571 union MESAPI__RESUME mes_resume_gang_pkt; 572 573 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 574 575 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 576 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 577 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 578 579 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 580 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 581 582 return mes_v11_0_submit_pkt_and_poll_completion(mes, 583 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 584 offsetof(union MESAPI__RESUME, api_status)); 585 } 586 587 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 588 { 589 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 590 591 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 592 593 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 594 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 595 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 596 597 return mes_v11_0_submit_pkt_and_poll_completion(mes, 598 &mes_status_pkt, sizeof(mes_status_pkt), 599 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 600 } 601 602 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 603 struct mes_misc_op_input *input) 604 { 605 union MESAPI__MISC misc_pkt; 606 607 memset(&misc_pkt, 0, sizeof(misc_pkt)); 608 609 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 610 misc_pkt.header.opcode = MES_SCH_API_MISC; 611 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 612 613 switch (input->op) { 614 case MES_MISC_OP_READ_REG: 615 misc_pkt.opcode = MESAPI_MISC__READ_REG; 616 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 617 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 618 break; 619 case MES_MISC_OP_WRITE_REG: 620 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 621 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 622 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 623 break; 624 case MES_MISC_OP_WRM_REG_WAIT: 625 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 626 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 627 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 628 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 629 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 630 misc_pkt.wait_reg_mem.reg_offset2 = 0; 631 break; 632 case MES_MISC_OP_WRM_REG_WR_WAIT: 633 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 634 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 635 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 636 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 637 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 638 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 639 break; 640 case MES_MISC_OP_SET_SHADER_DEBUGGER: 641 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 642 misc_pkt.set_shader_debugger.process_context_addr = 643 input->set_shader_debugger.process_context_addr; 644 misc_pkt.set_shader_debugger.flags.u32all = 645 input->set_shader_debugger.flags.u32all; 646 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 647 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 648 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 649 input->set_shader_debugger.tcp_watch_cntl, 650 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 651 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 652 break; 653 case MES_MISC_OP_CHANGE_CONFIG: 654 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 655 dev_warn_once(mes->adev->dev, 656 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 657 return 0; 658 } 659 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 660 misc_pkt.change_config.opcode = 661 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 662 misc_pkt.change_config.option.bits.limit_single_process = 663 input->change_config.option.limit_single_process; 664 break; 665 666 default: 667 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 668 return -EINVAL; 669 } 670 671 return mes_v11_0_submit_pkt_and_poll_completion(mes, 672 &misc_pkt, sizeof(misc_pkt), 673 offsetof(union MESAPI__MISC, api_status)); 674 } 675 676 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 677 { 678 int i; 679 struct amdgpu_device *adev = mes->adev; 680 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 681 682 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 683 684 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 685 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 686 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 687 688 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 689 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 690 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 691 mes_set_hw_res_pkt.paging_vmid = 0; 692 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 693 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 694 mes->query_status_fence_gpu_addr[0]; 695 696 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 697 mes_set_hw_res_pkt.compute_hqd_mask[i] = 698 mes->compute_hqd_mask[i]; 699 700 for (i = 0; i < MAX_GFX_PIPES; i++) 701 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 702 mes->gfx_hqd_mask[i]; 703 704 for (i = 0; i < MAX_SDMA_PIPES; i++) 705 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 706 707 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 708 mes_set_hw_res_pkt.aggregated_doorbells[i] = 709 mes->aggregated_doorbells[i]; 710 711 for (i = 0; i < 5; i++) { 712 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 713 mes_set_hw_res_pkt.mmhub_base[i] = 714 adev->reg_offset[MMHUB_HWIP][0][i]; 715 mes_set_hw_res_pkt.osssys_base[i] = 716 adev->reg_offset[OSSSYS_HWIP][0][i]; 717 } 718 719 mes_set_hw_res_pkt.disable_reset = 1; 720 mes_set_hw_res_pkt.disable_mes_log = 1; 721 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 722 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 723 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 724 mes_set_hw_res_pkt.oversubscription_timer = 50; 725 726 if (amdgpu_mes_log_enable) { 727 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 728 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 729 mes->event_log_gpu_addr; 730 } 731 732 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 733 mes_set_hw_res_pkt.limit_single_process = 1; 734 735 return mes_v11_0_submit_pkt_and_poll_completion(mes, 736 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 737 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 738 } 739 740 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 741 { 742 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 743 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 744 745 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 746 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 747 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 748 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 749 750 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 751 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 752 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 753 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 754 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 755 } 756 757 return mes_v11_0_submit_pkt_and_poll_completion(mes, 758 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 759 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 760 } 761 762 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 763 struct mes_reset_queue_input *input) 764 { 765 union MESAPI__RESET mes_reset_queue_pkt; 766 767 if (input->use_mmio) 768 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, 769 input->me_id, input->pipe_id, 770 input->queue_id, input->vmid); 771 772 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 773 774 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 775 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 776 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 777 778 mes_reset_queue_pkt.queue_type = 779 convert_to_mes_queue_type(input->queue_type); 780 781 if (input->legacy_gfx) { 782 mes_reset_queue_pkt.reset_legacy_gfx = 1; 783 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 784 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 785 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 786 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 787 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 788 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 789 } else { 790 mes_reset_queue_pkt.reset_queue_only = 1; 791 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 792 } 793 794 return mes_v11_0_submit_pkt_and_poll_completion(mes, 795 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 796 offsetof(union MESAPI__RESET, api_status)); 797 } 798 799 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 800 struct mes_detect_and_reset_queue_input *input) 801 { 802 union MESAPI__RESET mes_reset_queue_pkt; 803 804 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 805 806 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 807 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 808 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 809 810 mes_reset_queue_pkt.queue_type = 811 convert_to_mes_queue_type(input->queue_type); 812 mes_reset_queue_pkt.doorbell_offset_addr = 813 mes->hung_queue_db_array_gpu_addr[0]; 814 815 if (input->detect_only) 816 mes_reset_queue_pkt.hang_detect_only = 1; 817 else 818 mes_reset_queue_pkt.hang_detect_then_reset = 1; 819 820 return mes_v11_0_submit_pkt_and_poll_completion(mes, 821 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 822 offsetof(union MESAPI__RESET, api_status)); 823 } 824 825 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 826 .add_hw_queue = mes_v11_0_add_hw_queue, 827 .remove_hw_queue = mes_v11_0_remove_hw_queue, 828 .map_legacy_queue = mes_v11_0_map_legacy_queue, 829 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 830 .suspend_gang = mes_v11_0_suspend_gang, 831 .resume_gang = mes_v11_0_resume_gang, 832 .misc_op = mes_v11_0_misc_op, 833 .reset_hw_queue = mes_v11_0_reset_hw_queue, 834 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 835 }; 836 837 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 838 enum amdgpu_mes_pipe pipe) 839 { 840 int r; 841 const struct mes_firmware_header_v1_0 *mes_hdr; 842 const __le32 *fw_data; 843 unsigned fw_size; 844 845 mes_hdr = (const struct mes_firmware_header_v1_0 *) 846 adev->mes.fw[pipe]->data; 847 848 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 849 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 850 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 851 852 r = amdgpu_bo_create_reserved(adev, fw_size, 853 PAGE_SIZE, 854 AMDGPU_GEM_DOMAIN_VRAM | 855 AMDGPU_GEM_DOMAIN_GTT, 856 &adev->mes.ucode_fw_obj[pipe], 857 &adev->mes.ucode_fw_gpu_addr[pipe], 858 (void **)&adev->mes.ucode_fw_ptr[pipe]); 859 if (r) { 860 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 861 return r; 862 } 863 864 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 865 866 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 867 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 868 869 return 0; 870 } 871 872 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 873 enum amdgpu_mes_pipe pipe) 874 { 875 int r; 876 const struct mes_firmware_header_v1_0 *mes_hdr; 877 const __le32 *fw_data; 878 unsigned fw_size; 879 880 mes_hdr = (const struct mes_firmware_header_v1_0 *) 881 adev->mes.fw[pipe]->data; 882 883 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 884 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 885 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 886 887 if (fw_size > GFX_MES_DRAM_SIZE) { 888 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 889 pipe, fw_size, GFX_MES_DRAM_SIZE); 890 return -EINVAL; 891 } 892 893 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 894 64 * 1024, 895 AMDGPU_GEM_DOMAIN_VRAM | 896 AMDGPU_GEM_DOMAIN_GTT, 897 &adev->mes.data_fw_obj[pipe], 898 &adev->mes.data_fw_gpu_addr[pipe], 899 (void **)&adev->mes.data_fw_ptr[pipe]); 900 if (r) { 901 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 902 return r; 903 } 904 905 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 906 907 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 908 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 909 910 return 0; 911 } 912 913 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 914 enum amdgpu_mes_pipe pipe) 915 { 916 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 917 &adev->mes.data_fw_gpu_addr[pipe], 918 (void **)&adev->mes.data_fw_ptr[pipe]); 919 920 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 921 &adev->mes.ucode_fw_gpu_addr[pipe], 922 (void **)&adev->mes.ucode_fw_ptr[pipe]); 923 } 924 925 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 926 { 927 int pipe; 928 929 /* return early if we have already fetched these */ 930 if (adev->mes.sched_version && adev->mes.kiq_version) 931 return; 932 933 /* get MES scheduler/KIQ versions */ 934 mutex_lock(&adev->srbm_mutex); 935 936 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 937 soc21_grbm_select(adev, 3, pipe, 0, 0); 938 939 if (pipe == AMDGPU_MES_SCHED_PIPE) 940 adev->mes.sched_version = 941 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 942 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 943 adev->mes.kiq_version = 944 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 945 } 946 947 soc21_grbm_select(adev, 0, 0, 0, 0); 948 mutex_unlock(&adev->srbm_mutex); 949 } 950 951 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 952 { 953 uint64_t ucode_addr; 954 uint32_t pipe, data = 0; 955 956 if (enable) { 957 if (amdgpu_mes_log_enable) { 958 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 959 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 960 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 961 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 962 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 963 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 964 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 965 } 966 967 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 968 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 969 data = REG_SET_FIELD(data, CP_MES_CNTL, 970 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 971 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 972 973 mutex_lock(&adev->srbm_mutex); 974 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 975 if (!adev->enable_mes_kiq && 976 pipe == AMDGPU_MES_KIQ_PIPE) 977 continue; 978 979 soc21_grbm_select(adev, 3, pipe, 0, 0); 980 981 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 982 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 983 lower_32_bits(ucode_addr)); 984 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 985 upper_32_bits(ucode_addr)); 986 } 987 soc21_grbm_select(adev, 0, 0, 0, 0); 988 mutex_unlock(&adev->srbm_mutex); 989 990 /* unhalt MES and activate pipe0 */ 991 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 992 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 993 adev->enable_mes_kiq ? 1 : 0); 994 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 995 996 if (amdgpu_emu_mode) 997 msleep(100); 998 else 999 udelay(500); 1000 } else { 1001 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1002 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1003 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1004 data = REG_SET_FIELD(data, CP_MES_CNTL, 1005 MES_INVALIDATE_ICACHE, 1); 1006 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1007 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1008 adev->enable_mes_kiq ? 1 : 0); 1009 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1010 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1011 } 1012 } 1013 1014 /* This function is for backdoor MES firmware */ 1015 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1016 enum amdgpu_mes_pipe pipe, bool prime_icache) 1017 { 1018 int r; 1019 uint32_t data; 1020 uint64_t ucode_addr; 1021 1022 mes_v11_0_enable(adev, false); 1023 1024 if (!adev->mes.fw[pipe]) 1025 return -EINVAL; 1026 1027 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1028 if (r) 1029 return r; 1030 1031 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1032 if (r) { 1033 mes_v11_0_free_ucode_buffers(adev, pipe); 1034 return r; 1035 } 1036 1037 mutex_lock(&adev->srbm_mutex); 1038 /* me=3, pipe=0, queue=0 */ 1039 soc21_grbm_select(adev, 3, pipe, 0, 0); 1040 1041 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1042 1043 /* set ucode start address */ 1044 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1045 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1046 lower_32_bits(ucode_addr)); 1047 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1048 upper_32_bits(ucode_addr)); 1049 1050 /* set ucode fimrware address */ 1051 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1052 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1053 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1054 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1055 1056 /* set ucode instruction cache boundary to 2M-1 */ 1057 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1058 1059 /* set ucode data firmware address */ 1060 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1061 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1062 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1063 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1064 1065 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1066 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1067 1068 if (prime_icache) { 1069 /* invalidate ICACHE */ 1070 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1071 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1072 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1073 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1074 1075 /* prime the ICACHE. */ 1076 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1077 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1078 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1079 } 1080 1081 soc21_grbm_select(adev, 0, 0, 0, 0); 1082 mutex_unlock(&adev->srbm_mutex); 1083 1084 return 0; 1085 } 1086 1087 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1088 enum amdgpu_mes_pipe pipe) 1089 { 1090 int r; 1091 u32 *eop; 1092 1093 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1094 AMDGPU_GEM_DOMAIN_GTT, 1095 &adev->mes.eop_gpu_obj[pipe], 1096 &adev->mes.eop_gpu_addr[pipe], 1097 (void **)&eop); 1098 if (r) { 1099 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1100 return r; 1101 } 1102 1103 memset(eop, 0, 1104 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1105 1106 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1107 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1108 1109 return 0; 1110 } 1111 1112 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1113 { 1114 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1115 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1116 uint32_t tmp; 1117 1118 memset(mqd, 0, sizeof(*mqd)); 1119 1120 mqd->header = 0xC0310800; 1121 mqd->compute_pipelinestat_enable = 0x00000001; 1122 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1123 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1124 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1125 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1126 mqd->compute_misc_reserved = 0x00000007; 1127 1128 eop_base_addr = ring->eop_gpu_addr >> 8; 1129 1130 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1131 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1132 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1133 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1134 1135 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1136 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1137 mqd->cp_hqd_eop_control = tmp; 1138 1139 /* disable the queue if it's active */ 1140 ring->wptr = 0; 1141 mqd->cp_hqd_pq_rptr = 0; 1142 mqd->cp_hqd_pq_wptr_lo = 0; 1143 mqd->cp_hqd_pq_wptr_hi = 0; 1144 1145 /* set the pointer to the MQD */ 1146 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1147 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1148 1149 /* set MQD vmid to 0 */ 1150 tmp = regCP_MQD_CONTROL_DEFAULT; 1151 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1152 mqd->cp_mqd_control = tmp; 1153 1154 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1155 hqd_gpu_addr = ring->gpu_addr >> 8; 1156 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1157 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1158 1159 /* set the wb address whether it's enabled or not */ 1160 wb_gpu_addr = ring->rptr_gpu_addr; 1161 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1162 mqd->cp_hqd_pq_rptr_report_addr_hi = 1163 upper_32_bits(wb_gpu_addr) & 0xffff; 1164 1165 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1166 wb_gpu_addr = ring->wptr_gpu_addr; 1167 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1168 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1169 1170 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1171 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1172 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1173 (order_base_2(ring->ring_size / 4) - 1)); 1174 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1175 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1176 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1177 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1178 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1179 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1180 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1181 mqd->cp_hqd_pq_control = tmp; 1182 1183 /* enable doorbell */ 1184 tmp = 0; 1185 if (ring->use_doorbell) { 1186 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1187 DOORBELL_OFFSET, ring->doorbell_index); 1188 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1189 DOORBELL_EN, 1); 1190 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1191 DOORBELL_SOURCE, 0); 1192 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1193 DOORBELL_HIT, 0); 1194 } else 1195 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1196 DOORBELL_EN, 0); 1197 mqd->cp_hqd_pq_doorbell_control = tmp; 1198 1199 mqd->cp_hqd_vmid = 0; 1200 /* activate the queue */ 1201 mqd->cp_hqd_active = 1; 1202 1203 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1204 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1205 PRELOAD_SIZE, 0x55); 1206 mqd->cp_hqd_persistent_state = tmp; 1207 1208 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1209 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1210 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1211 1212 amdgpu_device_flush_hdp(ring->adev, NULL); 1213 return 0; 1214 } 1215 1216 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1217 { 1218 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1219 struct amdgpu_device *adev = ring->adev; 1220 uint32_t data = 0; 1221 1222 mutex_lock(&adev->srbm_mutex); 1223 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1224 1225 /* set CP_HQD_VMID.VMID = 0. */ 1226 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1227 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1228 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1229 1230 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1231 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1232 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1233 DOORBELL_EN, 0); 1234 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1235 1236 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1237 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1238 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1239 1240 /* set CP_MQD_CONTROL.VMID=0 */ 1241 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1242 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1243 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1244 1245 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1246 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1247 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1248 1249 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1250 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1251 mqd->cp_hqd_pq_rptr_report_addr_lo); 1252 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1253 mqd->cp_hqd_pq_rptr_report_addr_hi); 1254 1255 /* set CP_HQD_PQ_CONTROL */ 1256 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1257 1258 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1259 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1260 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1261 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1262 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1263 1264 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1265 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1266 mqd->cp_hqd_pq_doorbell_control); 1267 1268 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1269 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1270 1271 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1272 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1273 1274 soc21_grbm_select(adev, 0, 0, 0, 0); 1275 mutex_unlock(&adev->srbm_mutex); 1276 } 1277 1278 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1279 { 1280 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1281 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1282 int r; 1283 1284 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1285 return -EINVAL; 1286 1287 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1288 if (r) { 1289 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1290 return r; 1291 } 1292 1293 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1294 1295 return amdgpu_ring_test_helper(kiq_ring); 1296 } 1297 1298 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1299 enum amdgpu_mes_pipe pipe) 1300 { 1301 struct amdgpu_ring *ring; 1302 int r; 1303 1304 if (pipe == AMDGPU_MES_KIQ_PIPE) 1305 ring = &adev->gfx.kiq[0].ring; 1306 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1307 ring = &adev->mes.ring[0]; 1308 else 1309 BUG(); 1310 1311 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1312 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1313 *(ring->wptr_cpu_addr) = 0; 1314 *(ring->rptr_cpu_addr) = 0; 1315 amdgpu_ring_clear_ring(ring); 1316 } 1317 1318 r = mes_v11_0_mqd_init(ring); 1319 if (r) 1320 return r; 1321 1322 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1323 r = mes_v11_0_kiq_enable_queue(adev); 1324 if (r) 1325 return r; 1326 } else { 1327 mes_v11_0_queue_init_register(ring); 1328 } 1329 1330 return 0; 1331 } 1332 1333 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1334 { 1335 struct amdgpu_ring *ring; 1336 1337 ring = &adev->mes.ring[0]; 1338 1339 ring->funcs = &mes_v11_0_ring_funcs; 1340 1341 ring->me = 3; 1342 ring->pipe = 0; 1343 ring->queue = 0; 1344 1345 ring->ring_obj = NULL; 1346 ring->use_doorbell = true; 1347 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1348 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1349 ring->no_scheduler = true; 1350 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1351 1352 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1353 AMDGPU_RING_PRIO_DEFAULT, NULL); 1354 } 1355 1356 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1357 { 1358 struct amdgpu_ring *ring; 1359 1360 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1361 1362 ring = &adev->gfx.kiq[0].ring; 1363 1364 ring->me = 3; 1365 ring->pipe = 1; 1366 ring->queue = 0; 1367 1368 ring->adev = NULL; 1369 ring->ring_obj = NULL; 1370 ring->use_doorbell = true; 1371 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1372 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1373 ring->no_scheduler = true; 1374 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1375 ring->me, ring->pipe, ring->queue); 1376 1377 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1378 AMDGPU_RING_PRIO_DEFAULT, NULL); 1379 } 1380 1381 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1382 enum amdgpu_mes_pipe pipe) 1383 { 1384 int r, mqd_size = sizeof(struct v11_compute_mqd); 1385 struct amdgpu_ring *ring; 1386 1387 if (pipe == AMDGPU_MES_KIQ_PIPE) 1388 ring = &adev->gfx.kiq[0].ring; 1389 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1390 ring = &adev->mes.ring[0]; 1391 else 1392 BUG(); 1393 1394 if (ring->mqd_obj) 1395 return 0; 1396 1397 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1398 AMDGPU_GEM_DOMAIN_VRAM | 1399 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1400 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1401 if (r) { 1402 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1403 return r; 1404 } 1405 1406 memset(ring->mqd_ptr, 0, mqd_size); 1407 1408 /* prepare MQD backup */ 1409 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1410 if (!adev->mes.mqd_backup[pipe]) { 1411 dev_warn(adev->dev, 1412 "no memory to create MQD backup for ring %s\n", 1413 ring->name); 1414 return -ENOMEM; 1415 } 1416 1417 return 0; 1418 } 1419 1420 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1421 { 1422 struct amdgpu_device *adev = ip_block->adev; 1423 int pipe, r, bo_size; 1424 1425 adev->mes.funcs = &mes_v11_0_funcs; 1426 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1427 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1428 1429 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1430 1431 r = amdgpu_mes_init(adev); 1432 if (r) 1433 return r; 1434 1435 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1436 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1437 continue; 1438 1439 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1440 if (r) 1441 return r; 1442 1443 r = mes_v11_0_mqd_sw_init(adev, pipe); 1444 if (r) 1445 return r; 1446 } 1447 1448 if (adev->enable_mes_kiq) { 1449 r = mes_v11_0_kiq_ring_init(adev); 1450 if (r) 1451 return r; 1452 } 1453 1454 r = mes_v11_0_ring_init(adev); 1455 if (r) 1456 return r; 1457 1458 bo_size = AMDGPU_GPU_PAGE_SIZE; 1459 if (amdgpu_sriov_is_mes_info_enable(adev)) 1460 bo_size += MES11_HW_RESOURCE_1_SIZE; 1461 1462 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1463 r = amdgpu_bo_create_kernel(adev, 1464 bo_size, 1465 PAGE_SIZE, 1466 AMDGPU_GEM_DOMAIN_VRAM, 1467 &adev->mes.resource_1[0], 1468 &adev->mes.resource_1_gpu_addr[0], 1469 &adev->mes.resource_1_addr[0]); 1470 if (r) { 1471 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1472 return r; 1473 } 1474 1475 return 0; 1476 } 1477 1478 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1479 { 1480 struct amdgpu_device *adev = ip_block->adev; 1481 int pipe; 1482 1483 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1484 &adev->mes.resource_1_addr[0]); 1485 1486 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1487 kfree(adev->mes.mqd_backup[pipe]); 1488 1489 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1490 &adev->mes.eop_gpu_addr[pipe], 1491 NULL); 1492 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1493 } 1494 1495 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1496 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1497 &adev->gfx.kiq[0].ring.mqd_ptr); 1498 1499 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1500 &adev->mes.ring[0].mqd_gpu_addr, 1501 &adev->mes.ring[0].mqd_ptr); 1502 1503 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1504 amdgpu_ring_fini(&adev->mes.ring[0]); 1505 1506 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1507 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1508 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1509 } 1510 1511 amdgpu_mes_fini(adev); 1512 return 0; 1513 } 1514 1515 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1516 { 1517 uint32_t data; 1518 int i; 1519 struct amdgpu_device *adev = ring->adev; 1520 1521 mutex_lock(&adev->srbm_mutex); 1522 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1523 1524 /* disable the queue if it's active */ 1525 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1526 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1527 for (i = 0; i < adev->usec_timeout; i++) { 1528 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1529 break; 1530 udelay(1); 1531 } 1532 } 1533 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1534 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1535 DOORBELL_EN, 0); 1536 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1537 DOORBELL_HIT, 1); 1538 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1539 1540 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1541 1542 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1543 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1544 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1545 1546 soc21_grbm_select(adev, 0, 0, 0, 0); 1547 mutex_unlock(&adev->srbm_mutex); 1548 } 1549 1550 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1551 { 1552 uint32_t tmp; 1553 struct amdgpu_device *adev = ring->adev; 1554 1555 /* tell RLC which is KIQ queue */ 1556 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1557 tmp &= 0xffffff00; 1558 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1559 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1560 } 1561 1562 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1563 { 1564 uint32_t tmp; 1565 1566 /* tell RLC which is KIQ dequeue */ 1567 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1568 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1569 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1570 } 1571 1572 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1573 { 1574 int r = 0; 1575 struct amdgpu_ip_block *ip_block; 1576 1577 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1578 1579 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1580 if (r) { 1581 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1582 return r; 1583 } 1584 1585 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1586 if (r) { 1587 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1588 return r; 1589 } 1590 1591 } 1592 1593 mes_v11_0_enable(adev, true); 1594 1595 mes_v11_0_get_fw_version(adev); 1596 1597 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1598 1599 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1600 if (unlikely(!ip_block)) { 1601 dev_err(adev->dev, "Failed to get MES handle\n"); 1602 return -EINVAL; 1603 } 1604 1605 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1606 if (r) 1607 goto failure; 1608 1609 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1610 adev->mes.enable_legacy_queue_map = true; 1611 else 1612 adev->mes.enable_legacy_queue_map = false; 1613 1614 if (adev->mes.enable_legacy_queue_map) { 1615 r = mes_v11_0_hw_init(ip_block); 1616 if (r) 1617 goto failure; 1618 } 1619 1620 return r; 1621 1622 failure: 1623 mes_v11_0_hw_fini(ip_block); 1624 return r; 1625 } 1626 1627 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1628 { 1629 if (adev->mes.ring[0].sched.ready) { 1630 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1631 adev->mes.ring[0].sched.ready = false; 1632 } 1633 1634 if (amdgpu_sriov_vf(adev)) { 1635 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1636 mes_v11_0_kiq_clear(adev); 1637 } 1638 1639 mes_v11_0_enable(adev, false); 1640 1641 return 0; 1642 } 1643 1644 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1645 { 1646 int r; 1647 struct amdgpu_device *adev = ip_block->adev; 1648 1649 if (adev->mes.ring[0].sched.ready) 1650 goto out; 1651 1652 if (!adev->enable_mes_kiq) { 1653 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1654 r = mes_v11_0_load_microcode(adev, 1655 AMDGPU_MES_SCHED_PIPE, true); 1656 if (r) { 1657 DRM_ERROR("failed to MES fw, r=%d\n", r); 1658 return r; 1659 } 1660 } 1661 1662 mes_v11_0_enable(adev, true); 1663 } 1664 1665 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1666 if (r) 1667 goto failure; 1668 1669 r = mes_v11_0_set_hw_resources(&adev->mes); 1670 if (r) 1671 goto failure; 1672 1673 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 1674 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1675 if (r) { 1676 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 1677 goto failure; 1678 } 1679 } 1680 1681 r = mes_v11_0_query_sched_status(&adev->mes); 1682 if (r) { 1683 DRM_ERROR("MES is busy\n"); 1684 goto failure; 1685 } 1686 1687 r = amdgpu_mes_update_enforce_isolation(adev); 1688 if (r) 1689 goto failure; 1690 1691 amdgpu_mes_validate_fw_version(adev); 1692 out: 1693 /* 1694 * Disable KIQ ring usage from the driver once MES is enabled. 1695 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1696 * with MES enabled. 1697 */ 1698 adev->gfx.kiq[0].ring.sched.ready = false; 1699 adev->mes.ring[0].sched.ready = true; 1700 1701 return 0; 1702 1703 failure: 1704 mes_v11_0_hw_fini(ip_block); 1705 return r; 1706 } 1707 1708 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 1709 { 1710 return 0; 1711 } 1712 1713 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 1714 { 1715 return mes_v11_0_hw_fini(ip_block); 1716 } 1717 1718 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 1719 { 1720 return mes_v11_0_hw_init(ip_block); 1721 } 1722 1723 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 1724 { 1725 struct amdgpu_device *adev = ip_block->adev; 1726 int pipe, r; 1727 1728 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1729 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 1730 1731 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1732 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1733 continue; 1734 r = amdgpu_mes_init_microcode(adev, pipe); 1735 if (r) 1736 return r; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1743 .name = "mes_v11_0", 1744 .early_init = mes_v11_0_early_init, 1745 .late_init = NULL, 1746 .sw_init = mes_v11_0_sw_init, 1747 .sw_fini = mes_v11_0_sw_fini, 1748 .hw_init = mes_v11_0_hw_init, 1749 .hw_fini = mes_v11_0_hw_fini, 1750 .suspend = mes_v11_0_suspend, 1751 .resume = mes_v11_0_resume, 1752 }; 1753 1754 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1755 .type = AMD_IP_BLOCK_TYPE_MES, 1756 .major = 11, 1757 .minor = 0, 1758 .rev = 0, 1759 .funcs = &mes_v11_0_ip_funcs, 1760 }; 1761