1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Huacai Chen <chenhuacai@loongson.cn> 4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/bug.h> 9 #include <linux/compiler.h> 10 #include <linux/context_tracking.h> 11 #include <linux/entry-common.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/kexec.h> 15 #include <linux/module.h> 16 #include <linux/export.h> 17 #include <linux/extable.h> 18 #include <linux/mm.h> 19 #include <linux/sched/mm.h> 20 #include <linux/sched/debug.h> 21 #include <linux/smp.h> 22 #include <linux/spinlock.h> 23 #include <linux/kallsyms.h> 24 #include <linux/memblock.h> 25 #include <linux/interrupt.h> 26 #include <linux/ptrace.h> 27 #include <linux/kgdb.h> 28 #include <linux/kdebug.h> 29 #include <linux/notifier.h> 30 #include <linux/irq.h> 31 #include <linux/perf_event.h> 32 33 #include <asm/addrspace.h> 34 #include <asm/bootinfo.h> 35 #include <asm/branch.h> 36 #include <asm/break.h> 37 #include <asm/cpu.h> 38 #include <asm/exception.h> 39 #include <asm/fpu.h> 40 #include <asm/lbt.h> 41 #include <asm/inst.h> 42 #include <asm/kgdb.h> 43 #include <asm/loongarch.h> 44 #include <asm/mmu_context.h> 45 #include <asm/pgtable.h> 46 #include <asm/ptrace.h> 47 #include <asm/sections.h> 48 #include <asm/siginfo.h> 49 #include <asm/stacktrace.h> 50 #include <asm/tlb.h> 51 #include <asm/types.h> 52 #include <asm/unwind.h> 53 #include <asm/uprobes.h> 54 55 #include "access-helper.h" 56 57 void *exception_table[EXCCODE_INT_START] = { 58 [0 ... EXCCODE_INT_START - 1] = handle_reserved, 59 60 [EXCCODE_TLBI] = handle_tlb_load, 61 [EXCCODE_TLBL] = handle_tlb_load, 62 [EXCCODE_TLBS] = handle_tlb_store, 63 [EXCCODE_TLBM] = handle_tlb_modify, 64 [EXCCODE_TLBNR] = handle_tlb_protect, 65 [EXCCODE_TLBNX] = handle_tlb_protect, 66 [EXCCODE_TLBPE] = handle_tlb_protect, 67 [EXCCODE_ADE] = handle_ade, 68 [EXCCODE_ALE] = handle_ale, 69 [EXCCODE_BCE] = handle_bce, 70 [EXCCODE_SYS] = handle_sys, 71 [EXCCODE_BP] = handle_bp, 72 [EXCCODE_INE] = handle_ri, 73 [EXCCODE_IPE] = handle_ri, 74 [EXCCODE_FPDIS] = handle_fpu, 75 [EXCCODE_LSXDIS] = handle_lsx, 76 [EXCCODE_LASXDIS] = handle_lasx, 77 [EXCCODE_FPE] = handle_fpe, 78 [EXCCODE_WATCH] = handle_watch, 79 [EXCCODE_BTDIS] = handle_lbt, 80 }; 81 EXPORT_SYMBOL_GPL(exception_table); 82 83 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 84 const char *loglvl, bool user) 85 { 86 unsigned long addr; 87 struct unwind_state state; 88 struct pt_regs *pregs = (struct pt_regs *)regs; 89 90 if (!task) 91 task = current; 92 93 printk("%sCall Trace:", loglvl); 94 for (unwind_start(&state, task, pregs); 95 !unwind_done(&state); unwind_next_frame(&state)) { 96 addr = unwind_get_return_address(&state); 97 print_ip_sym(loglvl, addr); 98 } 99 printk("%s\n", loglvl); 100 } 101 102 static void show_stacktrace(struct task_struct *task, 103 const struct pt_regs *regs, const char *loglvl, bool user) 104 { 105 int i; 106 const int field = 2 * sizeof(unsigned long); 107 unsigned long stackdata; 108 unsigned long *sp = (unsigned long *)regs->regs[3]; 109 110 if (!task) 111 task = current; 112 113 if (!try_get_task_stack(task)) 114 return; 115 116 printk("%sStack :", loglvl); 117 i = 0; 118 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 119 if (i && ((i % (64 / field)) == 0)) { 120 pr_cont("\n"); 121 printk("%s ", loglvl); 122 } 123 if (i > 39) { 124 pr_cont(" ..."); 125 break; 126 } 127 128 if (__get_addr(&stackdata, sp++, user)) { 129 pr_cont(" (Bad stack address)"); 130 break; 131 } 132 133 pr_cont(" %0*lx", field, stackdata); 134 i++; 135 } 136 pr_cont("\n"); 137 show_backtrace(task, regs, loglvl, user); 138 139 put_task_stack(task); 140 } 141 142 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 143 { 144 struct pt_regs regs; 145 146 regs.csr_crmd = 0; 147 if (sp) { 148 regs.csr_era = 0; 149 regs.regs[1] = 0; 150 regs.regs[3] = (unsigned long)sp; 151 } else { 152 if (!task || task == current) 153 prepare_frametrace(®s); 154 else { 155 regs.csr_era = task->thread.reg01; 156 regs.regs[1] = 0; 157 regs.regs[3] = task->thread.reg03; 158 regs.regs[22] = task->thread.reg22; 159 } 160 } 161 162 show_stacktrace(task, ®s, loglvl, false); 163 } 164 165 static void show_code(unsigned int *pc, bool user) 166 { 167 long i; 168 unsigned int insn; 169 170 printk("Code:"); 171 172 for(i = -3 ; i < 6 ; i++) { 173 if (__get_inst(&insn, pc + i, user)) { 174 pr_cont(" (Bad address in era)\n"); 175 break; 176 } 177 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 178 } 179 pr_cont("\n"); 180 } 181 182 static void print_bool_fragment(const char *key, unsigned long val, bool first) 183 { 184 /* e.g. "+PG", "-DA" */ 185 pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key); 186 } 187 188 static void print_plv_fragment(const char *key, int val) 189 { 190 /* e.g. "PLV0", "PPLV3" */ 191 pr_cont("%s%d", key, val); 192 } 193 194 static void print_memory_type_fragment(const char *key, unsigned long val) 195 { 196 const char *humanized_type; 197 198 switch (val) { 199 case 0: 200 humanized_type = "SUC"; 201 break; 202 case 1: 203 humanized_type = "CC"; 204 break; 205 case 2: 206 humanized_type = "WUC"; 207 break; 208 default: 209 pr_cont(" %s=Reserved(%lu)", key, val); 210 return; 211 } 212 213 /* e.g. " DATM=WUC" */ 214 pr_cont(" %s=%s", key, humanized_type); 215 } 216 217 static void print_intr_fragment(const char *key, unsigned long val) 218 { 219 /* e.g. "LIE=0-1,3,5-7" */ 220 pr_cont("%s=%*pbl", key, EXCCODE_INT_NUM, &val); 221 } 222 223 static void print_crmd(unsigned long x) 224 { 225 printk(" CRMD: %08lx (", x); 226 print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x)); 227 print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false); 228 print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false); 229 print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false); 230 print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x)); 231 print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x)); 232 print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), false); 233 pr_cont(")\n"); 234 } 235 236 static void print_prmd(unsigned long x) 237 { 238 printk(" PRMD: %08lx (", x); 239 print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x)); 240 print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false); 241 print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), false); 242 pr_cont(")\n"); 243 } 244 245 static void print_euen(unsigned long x) 246 { 247 printk(" EUEN: %08lx (", x); 248 print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), true); 249 print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false); 250 print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false); 251 print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), false); 252 pr_cont(")\n"); 253 } 254 255 static void print_ecfg(unsigned long x) 256 { 257 printk(" ECFG: %08lx (", x); 258 print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x)); 259 pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x)); 260 } 261 262 static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode) 263 { 264 /* 265 * LoongArch users and developers are probably more familiar with 266 * those names found in the ISA manual, so we are going to print out 267 * the latter. This will require some mapping. 268 */ 269 switch (ecode) { 270 case EXCCODE_RSV: return "INT"; 271 case EXCCODE_TLBL: return "PIL"; 272 case EXCCODE_TLBS: return "PIS"; 273 case EXCCODE_TLBI: return "PIF"; 274 case EXCCODE_TLBM: return "PME"; 275 case EXCCODE_TLBNR: return "PNR"; 276 case EXCCODE_TLBNX: return "PNX"; 277 case EXCCODE_TLBPE: return "PPI"; 278 case EXCCODE_ADE: 279 switch (esubcode) { 280 case EXSUBCODE_ADEF: return "ADEF"; 281 case EXSUBCODE_ADEM: return "ADEM"; 282 } 283 break; 284 case EXCCODE_ALE: return "ALE"; 285 case EXCCODE_BCE: return "BCE"; 286 case EXCCODE_SYS: return "SYS"; 287 case EXCCODE_BP: return "BRK"; 288 case EXCCODE_INE: return "INE"; 289 case EXCCODE_IPE: return "IPE"; 290 case EXCCODE_FPDIS: return "FPD"; 291 case EXCCODE_LSXDIS: return "SXD"; 292 case EXCCODE_LASXDIS: return "ASXD"; 293 case EXCCODE_FPE: 294 switch (esubcode) { 295 case EXCSUBCODE_FPE: return "FPE"; 296 case EXCSUBCODE_VFPE: return "VFPE"; 297 } 298 break; 299 case EXCCODE_WATCH: 300 switch (esubcode) { 301 case EXCSUBCODE_WPEF: return "WPEF"; 302 case EXCSUBCODE_WPEM: return "WPEM"; 303 } 304 break; 305 case EXCCODE_BTDIS: return "BTD"; 306 case EXCCODE_BTE: return "BTE"; 307 case EXCCODE_GSPR: return "GSPR"; 308 case EXCCODE_HVC: return "HVC"; 309 case EXCCODE_GCM: 310 switch (esubcode) { 311 case EXCSUBCODE_GCSC: return "GCSC"; 312 case EXCSUBCODE_GCHC: return "GCHC"; 313 } 314 break; 315 /* 316 * The manual did not mention the EXCCODE_SE case, but print out it 317 * nevertheless. 318 */ 319 case EXCCODE_SE: return "SE"; 320 } 321 322 return "???"; 323 } 324 325 static void print_estat(unsigned long x) 326 { 327 unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x); 328 unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x); 329 330 printk("ESTAT: %08lx [%s] (", x, humanize_exc_name(ecode, esubcode)); 331 print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x)); 332 pr_cont(" ECode=%d EsubCode=%d)\n", (int) ecode, (int) esubcode); 333 } 334 335 static void __show_regs(const struct pt_regs *regs) 336 { 337 const int field = 2 * sizeof(unsigned long); 338 unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat); 339 340 show_regs_print_info(KERN_DEFAULT); 341 342 /* Print saved GPRs except $zero (substituting with PC/ERA) */ 343 #define GPR_FIELD(x) field, regs->regs[x] 344 printk("pc %0*lx ra %0*lx tp %0*lx sp %0*lx\n", 345 field, regs->csr_era, GPR_FIELD(1), GPR_FIELD(2), GPR_FIELD(3)); 346 printk("a0 %0*lx a1 %0*lx a2 %0*lx a3 %0*lx\n", 347 GPR_FIELD(4), GPR_FIELD(5), GPR_FIELD(6), GPR_FIELD(7)); 348 printk("a4 %0*lx a5 %0*lx a6 %0*lx a7 %0*lx\n", 349 GPR_FIELD(8), GPR_FIELD(9), GPR_FIELD(10), GPR_FIELD(11)); 350 printk("t0 %0*lx t1 %0*lx t2 %0*lx t3 %0*lx\n", 351 GPR_FIELD(12), GPR_FIELD(13), GPR_FIELD(14), GPR_FIELD(15)); 352 printk("t4 %0*lx t5 %0*lx t6 %0*lx t7 %0*lx\n", 353 GPR_FIELD(16), GPR_FIELD(17), GPR_FIELD(18), GPR_FIELD(19)); 354 printk("t8 %0*lx u0 %0*lx s9 %0*lx s0 %0*lx\n", 355 GPR_FIELD(20), GPR_FIELD(21), GPR_FIELD(22), GPR_FIELD(23)); 356 printk("s1 %0*lx s2 %0*lx s3 %0*lx s4 %0*lx\n", 357 GPR_FIELD(24), GPR_FIELD(25), GPR_FIELD(26), GPR_FIELD(27)); 358 printk("s5 %0*lx s6 %0*lx s7 %0*lx s8 %0*lx\n", 359 GPR_FIELD(28), GPR_FIELD(29), GPR_FIELD(30), GPR_FIELD(31)); 360 361 /* The slot for $zero is reused as the syscall restart flag */ 362 if (regs->regs[0]) 363 printk("syscall restart flag: %0*lx\n", GPR_FIELD(0)); 364 365 if (user_mode(regs)) { 366 printk(" ra: %0*lx\n", GPR_FIELD(1)); 367 printk(" ERA: %0*lx\n", field, regs->csr_era); 368 } else { 369 printk(" ra: %0*lx %pS\n", GPR_FIELD(1), (void *) regs->regs[1]); 370 printk(" ERA: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era); 371 } 372 #undef GPR_FIELD 373 374 /* Print saved important CSRs */ 375 print_crmd(regs->csr_crmd); 376 print_prmd(regs->csr_prmd); 377 print_euen(regs->csr_euen); 378 print_ecfg(regs->csr_ecfg); 379 print_estat(regs->csr_estat); 380 381 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE) 382 printk(" BADV: %0*lx\n", field, regs->csr_badvaddr); 383 384 printk(" PRID: %08x (%s, %s)\n", read_cpucfg(LOONGARCH_CPUCFG0), 385 cpu_family_string(), cpu_full_name_string()); 386 } 387 388 void show_regs(struct pt_regs *regs) 389 { 390 __show_regs((struct pt_regs *)regs); 391 dump_stack(); 392 } 393 394 void show_registers(struct pt_regs *regs) 395 { 396 __show_regs(regs); 397 print_modules(); 398 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 399 current->comm, current->pid, current_thread_info(), current); 400 401 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs)); 402 show_code((void *)regs->csr_era, user_mode(regs)); 403 printk("\n"); 404 } 405 406 static DEFINE_RAW_SPINLOCK(die_lock); 407 408 void die(const char *str, struct pt_regs *regs) 409 { 410 int ret; 411 static int die_counter; 412 413 oops_enter(); 414 415 ret = notify_die(DIE_OOPS, str, regs, 0, 416 current->thread.trap_nr, SIGSEGV); 417 418 console_verbose(); 419 raw_spin_lock_irq(&die_lock); 420 bust_spinlocks(1); 421 422 printk("%s[#%d]:\n", str, ++die_counter); 423 show_registers(regs); 424 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 425 raw_spin_unlock_irq(&die_lock); 426 427 oops_exit(); 428 429 if (ret == NOTIFY_STOP) 430 return; 431 432 if (regs && kexec_should_crash(current)) 433 crash_kexec(regs); 434 435 if (in_interrupt()) 436 panic("Fatal exception in interrupt"); 437 438 if (panic_on_oops) 439 panic("Fatal exception"); 440 441 make_task_dead(SIGSEGV); 442 } 443 444 static inline void setup_vint_size(unsigned int size) 445 { 446 unsigned int vs; 447 448 vs = ilog2(size/4); 449 450 if (vs == 0 || vs > 7) 451 panic("vint_size %d Not support yet", vs); 452 453 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG); 454 } 455 456 /* 457 * Send SIGFPE according to FCSR Cause bits, which must have already 458 * been masked against Enable bits. This is impotant as Inexact can 459 * happen together with Overflow or Underflow, and `ptrace' can set 460 * any bits. 461 */ 462 static void force_fcsr_sig(unsigned long fcsr, 463 void __user *fault_addr, struct task_struct *tsk) 464 { 465 int si_code = FPE_FLTUNK; 466 467 if (fcsr & FPU_CSR_INV_X) 468 si_code = FPE_FLTINV; 469 else if (fcsr & FPU_CSR_DIV_X) 470 si_code = FPE_FLTDIV; 471 else if (fcsr & FPU_CSR_OVF_X) 472 si_code = FPE_FLTOVF; 473 else if (fcsr & FPU_CSR_UDF_X) 474 si_code = FPE_FLTUND; 475 else if (fcsr & FPU_CSR_INE_X) 476 si_code = FPE_FLTRES; 477 478 force_sig_fault(SIGFPE, si_code, fault_addr); 479 } 480 481 static int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr) 482 { 483 int si_code; 484 485 switch (sig) { 486 case 0: 487 return 0; 488 489 case SIGFPE: 490 force_fcsr_sig(fcsr, fault_addr, current); 491 return 1; 492 493 case SIGBUS: 494 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 495 return 1; 496 497 case SIGSEGV: 498 mmap_read_lock(current->mm); 499 if (vma_lookup(current->mm, (unsigned long)fault_addr)) 500 si_code = SEGV_ACCERR; 501 else 502 si_code = SEGV_MAPERR; 503 mmap_read_unlock(current->mm); 504 force_sig_fault(SIGSEGV, si_code, fault_addr); 505 return 1; 506 507 default: 508 force_sig(sig); 509 return 1; 510 } 511 } 512 513 /* 514 * Delayed fp exceptions when doing a lazy ctx switch 515 */ 516 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr) 517 { 518 int sig; 519 void __user *fault_addr; 520 irqentry_state_t state = irqentry_enter(regs); 521 522 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 523 SIGFPE) == NOTIFY_STOP) 524 goto out; 525 526 /* Clear FCSR.Cause before enabling interrupts */ 527 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr)); 528 local_irq_enable(); 529 530 die_if_kernel("FP exception in kernel code", regs); 531 532 sig = SIGFPE; 533 fault_addr = (void __user *) regs->csr_era; 534 535 /* Send a signal if required. */ 536 process_fpemu_return(sig, fault_addr, fcsr); 537 538 out: 539 local_irq_disable(); 540 irqentry_exit(regs, state); 541 } 542 543 asmlinkage void noinstr do_ade(struct pt_regs *regs) 544 { 545 irqentry_state_t state = irqentry_enter(regs); 546 unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, regs->csr_estat); 547 548 if ((esubcode == EXSUBCODE_ADEM) && fixup_exception(regs)) 549 goto out; 550 551 die_if_kernel("Kernel ade access", regs); 552 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr); 553 554 out: 555 irqentry_exit(regs, state); 556 } 557 558 /* sysctl hooks */ 559 int unaligned_enabled __read_mostly = 1; /* Enabled by default */ 560 int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */ 561 562 asmlinkage void noinstr do_ale(struct pt_regs *regs) 563 { 564 irqentry_state_t state = irqentry_enter(regs); 565 566 #ifndef CONFIG_ARCH_STRICT_ALIGN 567 die_if_kernel("Kernel ale access", regs); 568 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 569 #else 570 bool pie = regs_irqs_disabled(regs); 571 unsigned int *pc; 572 573 if (!pie) 574 local_irq_enable(); 575 576 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr); 577 578 /* 579 * Did we catch a fault trying to load an instruction? 580 */ 581 if (regs->csr_badvaddr == regs->csr_era) 582 goto sigbus; 583 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) 584 goto sigbus; 585 if (!unaligned_enabled) 586 goto sigbus; 587 if (!no_unaligned_warning) 588 show_registers(regs); 589 590 pc = (unsigned int *)exception_era(regs); 591 592 emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc); 593 594 goto out; 595 596 sigbus: 597 die_if_kernel("Kernel ale access", regs); 598 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 599 out: 600 if (!pie) 601 local_irq_disable(); 602 #endif 603 irqentry_exit(regs, state); 604 } 605 606 #ifdef CONFIG_GENERIC_BUG 607 int is_valid_bugaddr(unsigned long addr) 608 { 609 return 1; 610 } 611 #endif /* CONFIG_GENERIC_BUG */ 612 613 static void bug_handler(struct pt_regs *regs) 614 { 615 if (user_mode(regs)) { 616 force_sig(SIGTRAP); 617 return; 618 } 619 620 switch (report_bug(regs->csr_era, regs)) { 621 case BUG_TRAP_TYPE_BUG: 622 die("Oops - BUG", regs); 623 break; 624 625 case BUG_TRAP_TYPE_WARN: 626 /* Skip the BUG instruction and continue */ 627 regs->csr_era += LOONGARCH_INSN_SIZE; 628 break; 629 630 default: 631 if (!fixup_exception(regs)) 632 die("Oops - BUG", regs); 633 } 634 } 635 636 asmlinkage void noinstr do_bce(struct pt_regs *regs) 637 { 638 bool user = user_mode(regs); 639 bool pie = regs_irqs_disabled(regs); 640 unsigned long era = exception_era(regs); 641 unsigned long badv = 0, lower = 0, upper = ULONG_MAX; 642 union loongarch_instruction insn; 643 irqentry_state_t state = irqentry_enter(regs); 644 645 if (!pie) 646 local_irq_enable(); 647 648 current->thread.trap_nr = read_csr_excode(); 649 650 die_if_kernel("Bounds check error in kernel code", regs); 651 652 /* 653 * Pull out the address that failed bounds checking, and the lower / 654 * upper bound, by minimally looking at the faulting instruction word 655 * and reading from the correct register. 656 */ 657 if (__get_inst(&insn.word, (u32 *)era, user)) 658 goto bad_era; 659 660 switch (insn.reg3_format.opcode) { 661 case asrtle_op: 662 if (insn.reg3_format.rd != 0) 663 break; /* not asrtle */ 664 badv = regs->regs[insn.reg3_format.rj]; 665 upper = regs->regs[insn.reg3_format.rk]; 666 break; 667 668 case asrtgt_op: 669 if (insn.reg3_format.rd != 0) 670 break; /* not asrtgt */ 671 badv = regs->regs[insn.reg3_format.rj]; 672 lower = regs->regs[insn.reg3_format.rk]; 673 break; 674 675 case ldleb_op: 676 case ldleh_op: 677 case ldlew_op: 678 case ldled_op: 679 case stleb_op: 680 case stleh_op: 681 case stlew_op: 682 case stled_op: 683 case fldles_op: 684 case fldled_op: 685 case fstles_op: 686 case fstled_op: 687 badv = regs->regs[insn.reg3_format.rj]; 688 upper = regs->regs[insn.reg3_format.rk]; 689 break; 690 691 case ldgtb_op: 692 case ldgth_op: 693 case ldgtw_op: 694 case ldgtd_op: 695 case stgtb_op: 696 case stgth_op: 697 case stgtw_op: 698 case stgtd_op: 699 case fldgts_op: 700 case fldgtd_op: 701 case fstgts_op: 702 case fstgtd_op: 703 badv = regs->regs[insn.reg3_format.rj]; 704 lower = regs->regs[insn.reg3_format.rk]; 705 break; 706 } 707 708 force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper); 709 710 out: 711 if (!pie) 712 local_irq_disable(); 713 714 irqentry_exit(regs, state); 715 return; 716 717 bad_era: 718 /* 719 * Cannot pull out the instruction word, hence cannot provide more 720 * info than a regular SIGSEGV in this case. 721 */ 722 force_sig(SIGSEGV); 723 goto out; 724 } 725 726 asmlinkage void noinstr do_bp(struct pt_regs *regs) 727 { 728 bool user = user_mode(regs); 729 bool pie = regs_irqs_disabled(regs); 730 unsigned int opcode, bcode; 731 unsigned long era = exception_era(regs); 732 irqentry_state_t state = irqentry_enter(regs); 733 734 if (!pie) 735 local_irq_enable(); 736 737 if (__get_inst(&opcode, (u32 *)era, user)) 738 goto out_sigsegv; 739 740 bcode = (opcode & 0x7fff); 741 742 /* 743 * notify the kprobe handlers, if instruction is likely to 744 * pertain to them. 745 */ 746 switch (bcode) { 747 case BRK_KDB: 748 if (kgdb_breakpoint_handler(regs)) 749 goto out; 750 else 751 break; 752 case BRK_KPROBE_BP: 753 if (kprobe_breakpoint_handler(regs)) 754 goto out; 755 else 756 break; 757 case BRK_KPROBE_SSTEPBP: 758 if (kprobe_singlestep_handler(regs)) 759 goto out; 760 else 761 break; 762 case BRK_UPROBE_BP: 763 if (uprobe_breakpoint_handler(regs)) 764 goto out; 765 else 766 break; 767 case BRK_UPROBE_XOLBP: 768 if (uprobe_singlestep_handler(regs)) 769 goto out; 770 else 771 break; 772 default: 773 current->thread.trap_nr = read_csr_excode(); 774 if (notify_die(DIE_TRAP, "Break", regs, bcode, 775 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 776 goto out; 777 else 778 break; 779 } 780 781 switch (bcode) { 782 case BRK_BUG: 783 bug_handler(regs); 784 break; 785 case BRK_DIVZERO: 786 die_if_kernel("Break instruction in kernel code", regs); 787 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era); 788 break; 789 case BRK_OVERFLOW: 790 die_if_kernel("Break instruction in kernel code", regs); 791 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era); 792 break; 793 default: 794 die_if_kernel("Break instruction in kernel code", regs); 795 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era); 796 break; 797 } 798 799 out: 800 if (!pie) 801 local_irq_disable(); 802 803 irqentry_exit(regs, state); 804 return; 805 806 out_sigsegv: 807 force_sig(SIGSEGV); 808 goto out; 809 } 810 811 asmlinkage void noinstr do_watch(struct pt_regs *regs) 812 { 813 irqentry_state_t state = irqentry_enter(regs); 814 815 #ifndef CONFIG_HAVE_HW_BREAKPOINT 816 pr_warn("Hardware watch point handler not implemented!\n"); 817 #else 818 if (kgdb_breakpoint_handler(regs)) 819 goto out; 820 821 if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) { 822 int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1); 823 unsigned long pc = instruction_pointer(regs); 824 union loongarch_instruction *ip = (union loongarch_instruction *)pc; 825 826 if (llbit) { 827 /* 828 * When the ll-sc combo is encountered, it is regarded as an single 829 * instruction. So don't clear llbit and reset CSR.FWPS.Skip until 830 * the llsc execution is completed. 831 */ 832 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 833 csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL); 834 goto out; 835 } 836 837 if (pc == current->thread.single_step) { 838 /* 839 * Certain insns are occasionally not skipped when CSR.FWPS.Skip is 840 * set, such as fld.d/fst.d. So singlestep needs to compare whether 841 * the csr_era is equal to the value of singlestep which last time set. 842 */ 843 if (!is_self_loop_ins(ip, regs)) { 844 /* 845 * Check if the given instruction the target pc is equal to the 846 * current pc, If yes, then we should not set the CSR.FWPS.SKIP 847 * bit to break the original instruction stream. 848 */ 849 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 850 goto out; 851 } 852 } 853 } else { 854 breakpoint_handler(regs); 855 watchpoint_handler(regs); 856 } 857 858 force_sig(SIGTRAP); 859 out: 860 #endif 861 irqentry_exit(regs, state); 862 } 863 864 asmlinkage void noinstr do_ri(struct pt_regs *regs) 865 { 866 int status = SIGILL; 867 unsigned int __maybe_unused opcode; 868 unsigned int __user *era = (unsigned int __user *)exception_era(regs); 869 irqentry_state_t state = irqentry_enter(regs); 870 871 local_irq_enable(); 872 current->thread.trap_nr = read_csr_excode(); 873 874 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 875 SIGILL) == NOTIFY_STOP) 876 goto out; 877 878 die_if_kernel("Reserved instruction in kernel code", regs); 879 880 if (unlikely(get_user(opcode, era) < 0)) { 881 status = SIGSEGV; 882 current->thread.error_code = 1; 883 } 884 885 force_sig(status); 886 887 out: 888 local_irq_disable(); 889 irqentry_exit(regs, state); 890 } 891 892 static void init_restore_fp(void) 893 { 894 if (!used_math()) { 895 /* First time FP context user. */ 896 init_fpu(); 897 } else { 898 /* This task has formerly used the FP context */ 899 if (!is_fpu_owner()) 900 own_fpu_inatomic(1); 901 } 902 903 BUG_ON(!is_fp_enabled()); 904 } 905 906 static void init_restore_lsx(void) 907 { 908 enable_lsx(); 909 910 if (!thread_lsx_context_live()) { 911 /* First time LSX context user */ 912 init_restore_fp(); 913 init_lsx_upper(); 914 set_thread_flag(TIF_LSX_CTX_LIVE); 915 } else { 916 if (!is_simd_owner()) { 917 if (is_fpu_owner()) { 918 restore_lsx_upper(current); 919 } else { 920 __own_fpu(); 921 restore_lsx(current); 922 } 923 } 924 } 925 926 set_thread_flag(TIF_USEDSIMD); 927 928 BUG_ON(!is_fp_enabled()); 929 BUG_ON(!is_lsx_enabled()); 930 } 931 932 static void init_restore_lasx(void) 933 { 934 enable_lasx(); 935 936 if (!thread_lasx_context_live()) { 937 /* First time LASX context user */ 938 init_restore_lsx(); 939 init_lasx_upper(); 940 set_thread_flag(TIF_LASX_CTX_LIVE); 941 } else { 942 if (is_fpu_owner() || is_simd_owner()) { 943 init_restore_lsx(); 944 restore_lasx_upper(current); 945 } else { 946 __own_fpu(); 947 enable_lsx(); 948 restore_lasx(current); 949 } 950 } 951 952 set_thread_flag(TIF_USEDSIMD); 953 954 BUG_ON(!is_fp_enabled()); 955 BUG_ON(!is_lsx_enabled()); 956 BUG_ON(!is_lasx_enabled()); 957 } 958 959 asmlinkage void noinstr do_fpu(struct pt_regs *regs) 960 { 961 irqentry_state_t state = irqentry_enter(regs); 962 963 local_irq_enable(); 964 die_if_kernel("do_fpu invoked from kernel context!", regs); 965 BUG_ON(is_lsx_enabled()); 966 BUG_ON(is_lasx_enabled()); 967 968 preempt_disable(); 969 init_restore_fp(); 970 preempt_enable(); 971 972 local_irq_disable(); 973 irqentry_exit(regs, state); 974 } 975 976 asmlinkage void noinstr do_lsx(struct pt_regs *regs) 977 { 978 irqentry_state_t state = irqentry_enter(regs); 979 980 local_irq_enable(); 981 if (!cpu_has_lsx) { 982 force_sig(SIGILL); 983 goto out; 984 } 985 986 die_if_kernel("do_lsx invoked from kernel context!", regs); 987 BUG_ON(is_lasx_enabled()); 988 989 preempt_disable(); 990 init_restore_lsx(); 991 preempt_enable(); 992 993 out: 994 local_irq_disable(); 995 irqentry_exit(regs, state); 996 } 997 998 asmlinkage void noinstr do_lasx(struct pt_regs *regs) 999 { 1000 irqentry_state_t state = irqentry_enter(regs); 1001 1002 local_irq_enable(); 1003 if (!cpu_has_lasx) { 1004 force_sig(SIGILL); 1005 goto out; 1006 } 1007 1008 die_if_kernel("do_lasx invoked from kernel context!", regs); 1009 1010 preempt_disable(); 1011 init_restore_lasx(); 1012 preempt_enable(); 1013 1014 out: 1015 local_irq_disable(); 1016 irqentry_exit(regs, state); 1017 } 1018 1019 static void init_restore_lbt(void) 1020 { 1021 if (!thread_lbt_context_live()) { 1022 /* First time LBT context user */ 1023 init_lbt(); 1024 set_thread_flag(TIF_LBT_CTX_LIVE); 1025 } else { 1026 if (!is_lbt_owner()) 1027 own_lbt_inatomic(1); 1028 } 1029 1030 BUG_ON(!is_lbt_enabled()); 1031 } 1032 1033 asmlinkage void noinstr do_lbt(struct pt_regs *regs) 1034 { 1035 bool pie = regs_irqs_disabled(regs); 1036 irqentry_state_t state = irqentry_enter(regs); 1037 1038 /* 1039 * BTD (Binary Translation Disable exception) can be triggered 1040 * during FP save/restore if TM (Top Mode) is on, which may 1041 * cause irq_enable during 'switch_to'. To avoid this situation 1042 * (including the user using 'MOVGR2GCSR' to turn on TM, which 1043 * will not trigger the BTE), we need to check PRMD first. 1044 */ 1045 if (!pie) 1046 local_irq_enable(); 1047 1048 if (!cpu_has_lbt) { 1049 force_sig(SIGILL); 1050 goto out; 1051 } 1052 BUG_ON(is_lbt_enabled()); 1053 1054 preempt_disable(); 1055 init_restore_lbt(); 1056 preempt_enable(); 1057 1058 out: 1059 if (!pie) 1060 local_irq_disable(); 1061 1062 irqentry_exit(regs, state); 1063 } 1064 1065 asmlinkage void noinstr do_reserved(struct pt_regs *regs) 1066 { 1067 irqentry_state_t state = irqentry_enter(regs); 1068 1069 local_irq_enable(); 1070 /* 1071 * Game over - no way to handle this if it ever occurs. Most probably 1072 * caused by a fatal error after another hardware/software error. 1073 */ 1074 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n", 1075 read_csr_excode(), current->pid, current->comm); 1076 die_if_kernel("do_reserved exception", regs); 1077 force_sig(SIGUNUSED); 1078 1079 local_irq_disable(); 1080 1081 irqentry_exit(regs, state); 1082 } 1083 1084 asmlinkage void cache_parity_error(void) 1085 { 1086 u32 merrctl = csr_read32(LOONGARCH_CSR_MERRCTL); 1087 unsigned long merrera = csr_read(LOONGARCH_CSR_MERRERA); 1088 1089 /* For the moment, report the problem and hang. */ 1090 pr_err("Cache error exception:\n"); 1091 pr_err("csr_merrctl == %08x\n", merrctl); 1092 pr_err("csr_merrera == %016lx\n", merrera); 1093 panic("Can't handle the cache error!"); 1094 } 1095 1096 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs) 1097 { 1098 struct pt_regs *old_regs; 1099 1100 irq_enter_rcu(); 1101 old_regs = set_irq_regs(regs); 1102 handle_arch_irq(regs); 1103 set_irq_regs(old_regs); 1104 irq_exit_rcu(); 1105 } 1106 1107 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) 1108 { 1109 register int cpu; 1110 register unsigned long stack; 1111 irqentry_state_t state = irqentry_enter(regs); 1112 1113 cpu = smp_processor_id(); 1114 1115 if (on_irq_stack(cpu, sp)) 1116 handle_loongarch_irq(regs); 1117 else { 1118 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START; 1119 1120 /* Save task's sp on IRQ stack for unwinding */ 1121 *(unsigned long *)stack = sp; 1122 1123 __asm__ __volatile__( 1124 "move $s0, $sp \n" /* Preserve sp */ 1125 "move $sp, %[stk] \n" /* Switch stack */ 1126 "move $a0, %[regs] \n" 1127 "bl handle_loongarch_irq \n" 1128 "move $sp, $s0 \n" /* Restore sp */ 1129 : /* No outputs */ 1130 : [stk] "r" (stack), [regs] "r" (regs) 1131 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0", 1132 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", 1133 "memory"); 1134 } 1135 1136 irqentry_exit(regs, state); 1137 } 1138 1139 unsigned long eentry; 1140 unsigned long tlbrentry; 1141 1142 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K); 1143 1144 static void configure_exception_vector(void) 1145 { 1146 eentry = (unsigned long)exception_handlers; 1147 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 1148 1149 csr_write(eentry, LOONGARCH_CSR_EENTRY); 1150 csr_write(__pa(eentry), LOONGARCH_CSR_MERRENTRY); 1151 csr_write(__pa(tlbrentry), LOONGARCH_CSR_TLBRENTRY); 1152 } 1153 1154 void per_cpu_trap_init(int cpu) 1155 { 1156 unsigned int i; 1157 1158 setup_vint_size(VECSIZE); 1159 1160 configure_exception_vector(); 1161 1162 if (!cpu_data[cpu].asid_cache) 1163 cpu_data[cpu].asid_cache = asid_first_version(cpu); 1164 1165 mmgrab(&init_mm); 1166 current->active_mm = &init_mm; 1167 BUG_ON(current->mm); 1168 enter_lazy_tlb(&init_mm, current); 1169 1170 /* Initialise exception handlers */ 1171 if (cpu == 0) 1172 for (i = 0; i < 64; i++) 1173 set_handler(i * VECSIZE, handle_reserved, VECSIZE); 1174 1175 tlb_init(cpu); 1176 cpu_cache_init(); 1177 } 1178 1179 /* Install CPU exception handler */ 1180 void set_handler(unsigned long offset, void *addr, unsigned long size) 1181 { 1182 memcpy((void *)(eentry + offset), addr, size); 1183 local_flush_icache_range(eentry + offset, eentry + offset + size); 1184 } 1185 1186 static const char panic_null_cerr[] = 1187 "Trying to set NULL cache error exception handler\n"; 1188 1189 /* 1190 * Install uncached CPU exception handler. 1191 * This is suitable only for the cache error exception which is the only 1192 * exception handler that is being run uncached. 1193 */ 1194 void set_merr_handler(unsigned long offset, void *addr, unsigned long size) 1195 { 1196 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry)); 1197 1198 if (!addr) 1199 panic(panic_null_cerr); 1200 1201 memcpy((void *)(uncached_eentry + offset), addr, size); 1202 } 1203 1204 void __init trap_init(void) 1205 { 1206 long i; 1207 1208 /* Set interrupt vector handler */ 1209 for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++) 1210 set_handler(i * VECSIZE, handle_vint, VECSIZE); 1211 1212 /* Set exception vector handler */ 1213 for (i = EXCCODE_ADE; i <= EXCCODE_BTDIS; i++) 1214 set_handler(i * VECSIZE, exception_table[i], VECSIZE); 1215 1216 cache_error_setup(); 1217 1218 local_flush_icache_range(eentry, eentry + 0x400); 1219 } 1220