1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/debugfs.h> 30 #include <linux/firmware.h> 31 #include <linux/module.h> 32 #include <linux/pci.h> 33 #include <linux/seq_file.h> 34 #include <linux/slab.h> 35 36 #include <drm/drm_device.h> 37 #include <drm/drm_file.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_vblank.h> 41 #include <drm/radeon_drm.h> 42 43 #include "atom.h" 44 #include "r100_reg_safe.h" 45 #include "r100d.h" 46 #include "radeon.h" 47 #include "radeon_asic.h" 48 #include "radeon_reg.h" 49 #include "rn50_reg_safe.h" 50 #include "rs100d.h" 51 #include "rv200d.h" 52 #include "rv250d.h" 53 54 /* Firmware Names */ 55 #define FIRMWARE_R100 "radeon/R100_cp.bin" 56 #define FIRMWARE_R200 "radeon/R200_cp.bin" 57 #define FIRMWARE_R300 "radeon/R300_cp.bin" 58 #define FIRMWARE_R420 "radeon/R420_cp.bin" 59 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 60 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 61 #define FIRMWARE_R520 "radeon/R520_cp.bin" 62 63 MODULE_FIRMWARE(FIRMWARE_R100); 64 MODULE_FIRMWARE(FIRMWARE_R200); 65 MODULE_FIRMWARE(FIRMWARE_R300); 66 MODULE_FIRMWARE(FIRMWARE_R420); 67 MODULE_FIRMWARE(FIRMWARE_RS690); 68 MODULE_FIRMWARE(FIRMWARE_RS600); 69 MODULE_FIRMWARE(FIRMWARE_R520); 70 71 #include "r100_track.h" 72 73 /* This files gather functions specifics to: 74 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 75 * and others in some cases. 76 */ 77 78 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 79 { 80 if (crtc == 0) { 81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 82 return true; 83 else 84 return false; 85 } else { 86 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 87 return true; 88 else 89 return false; 90 } 91 } 92 93 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 94 { 95 u32 vline1, vline2; 96 97 if (crtc == 0) { 98 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 99 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 100 } else { 101 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 102 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 103 } 104 if (vline1 != vline2) 105 return true; 106 else 107 return false; 108 } 109 110 /** 111 * r100_wait_for_vblank - vblank wait asic callback. 112 * 113 * @rdev: radeon_device pointer 114 * @crtc: crtc to wait for vblank on 115 * 116 * Wait for vblank on the requested crtc (r1xx-r4xx). 117 */ 118 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 119 { 120 unsigned i = 0; 121 122 if (crtc >= rdev->num_crtc) 123 return; 124 125 if (crtc == 0) { 126 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 127 return; 128 } else { 129 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 130 return; 131 } 132 133 /* depending on when we hit vblank, we may be close to active; if so, 134 * wait for another frame. 135 */ 136 while (r100_is_in_vblank(rdev, crtc)) { 137 if (i++ % 100 == 0) { 138 if (!r100_is_counter_moving(rdev, crtc)) 139 break; 140 } 141 } 142 143 while (!r100_is_in_vblank(rdev, crtc)) { 144 if (i++ % 100 == 0) { 145 if (!r100_is_counter_moving(rdev, crtc)) 146 break; 147 } 148 } 149 } 150 151 /** 152 * r100_page_flip - pageflip callback. 153 * 154 * @rdev: radeon_device pointer 155 * @crtc_id: crtc to cleanup pageflip on 156 * @crtc_base: new address of the crtc (GPU MC address) 157 * @async: asynchronous flip 158 * 159 * Does the actual pageflip (r1xx-r4xx). 160 * During vblank we take the crtc lock and wait for the update_pending 161 * bit to go high, when it does, we release the lock, and allow the 162 * double buffered update to take place. 163 */ 164 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) 165 { 166 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 167 uint32_t crtc_pitch, pitch_pixels; 168 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; 169 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 170 int i; 171 172 /* Lock the graphics update lock */ 173 /* update the scanout addresses */ 174 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 175 176 /* update pitch */ 177 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; 178 crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8, 179 fb->format->cpp[0] * 8 * 8); 180 crtc_pitch |= crtc_pitch << 16; 181 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 182 183 /* Wait for update_pending to go high. */ 184 for (i = 0; i < rdev->usec_timeout; i++) { 185 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 186 break; 187 udelay(1); 188 } 189 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 190 191 /* Unlock the lock, so double-buffering can take place inside vblank */ 192 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 193 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 194 195 } 196 197 /** 198 * r100_page_flip_pending - check if page flip is still pending 199 * 200 * @rdev: radeon_device pointer 201 * @crtc_id: crtc to check 202 * 203 * Check if the last pagefilp is still pending (r1xx-r4xx). 204 * Returns the current update pending status. 205 */ 206 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id) 207 { 208 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 209 210 /* Return current update_pending status: */ 211 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & 212 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET); 213 } 214 215 /** 216 * r100_pm_get_dynpm_state - look up dynpm power state callback. 217 * 218 * @rdev: radeon_device pointer 219 * 220 * Look up the optimal power state based on the 221 * current state of the GPU (r1xx-r5xx). 222 * Used for dynpm only. 223 */ 224 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 225 { 226 int i; 227 rdev->pm.dynpm_can_upclock = true; 228 rdev->pm.dynpm_can_downclock = true; 229 230 switch (rdev->pm.dynpm_planned_action) { 231 case DYNPM_ACTION_MINIMUM: 232 rdev->pm.requested_power_state_index = 0; 233 rdev->pm.dynpm_can_downclock = false; 234 break; 235 case DYNPM_ACTION_DOWNCLOCK: 236 if (rdev->pm.current_power_state_index == 0) { 237 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 238 rdev->pm.dynpm_can_downclock = false; 239 } else { 240 if (rdev->pm.active_crtc_count > 1) { 241 for (i = 0; i < rdev->pm.num_power_states; i++) { 242 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 243 continue; 244 else if (i >= rdev->pm.current_power_state_index) { 245 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 246 break; 247 } else { 248 rdev->pm.requested_power_state_index = i; 249 break; 250 } 251 } 252 } else 253 rdev->pm.requested_power_state_index = 254 rdev->pm.current_power_state_index - 1; 255 } 256 /* don't use the power state if crtcs are active and no display flag is set */ 257 if ((rdev->pm.active_crtc_count > 0) && 258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 259 RADEON_PM_MODE_NO_DISPLAY)) { 260 rdev->pm.requested_power_state_index++; 261 } 262 break; 263 case DYNPM_ACTION_UPCLOCK: 264 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 265 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 266 rdev->pm.dynpm_can_upclock = false; 267 } else { 268 if (rdev->pm.active_crtc_count > 1) { 269 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 270 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 271 continue; 272 else if (i <= rdev->pm.current_power_state_index) { 273 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 274 break; 275 } else { 276 rdev->pm.requested_power_state_index = i; 277 break; 278 } 279 } 280 } else 281 rdev->pm.requested_power_state_index = 282 rdev->pm.current_power_state_index + 1; 283 } 284 break; 285 case DYNPM_ACTION_DEFAULT: 286 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 287 rdev->pm.dynpm_can_upclock = false; 288 break; 289 case DYNPM_ACTION_NONE: 290 default: 291 DRM_ERROR("Requested mode for not defined action\n"); 292 return; 293 } 294 /* only one clock mode per power state */ 295 rdev->pm.requested_clock_mode_index = 0; 296 297 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 298 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 299 clock_info[rdev->pm.requested_clock_mode_index].sclk, 300 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 301 clock_info[rdev->pm.requested_clock_mode_index].mclk, 302 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 303 pcie_lanes); 304 } 305 306 /** 307 * r100_pm_init_profile - Initialize power profiles callback. 308 * 309 * @rdev: radeon_device pointer 310 * 311 * Initialize the power states used in profile mode 312 * (r1xx-r3xx). 313 * Used for profile mode only. 314 */ 315 void r100_pm_init_profile(struct radeon_device *rdev) 316 { 317 /* default */ 318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 321 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 322 /* low sh */ 323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 326 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 327 /* mid sh */ 328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 331 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 332 /* high sh */ 333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 336 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 337 /* low mh */ 338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 341 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 342 /* mid mh */ 343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 346 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 347 /* high mh */ 348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 351 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 352 } 353 354 /** 355 * r100_pm_misc - set additional pm hw parameters callback. 356 * 357 * @rdev: radeon_device pointer 358 * 359 * Set non-clock parameters associated with a power state 360 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 361 */ 362 void r100_pm_misc(struct radeon_device *rdev) 363 { 364 int requested_index = rdev->pm.requested_power_state_index; 365 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 366 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 367 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 368 369 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 370 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 371 tmp = RREG32(voltage->gpio.reg); 372 if (voltage->active_high) 373 tmp |= voltage->gpio.mask; 374 else 375 tmp &= ~(voltage->gpio.mask); 376 WREG32(voltage->gpio.reg, tmp); 377 if (voltage->delay) 378 udelay(voltage->delay); 379 } else { 380 tmp = RREG32(voltage->gpio.reg); 381 if (voltage->active_high) 382 tmp &= ~voltage->gpio.mask; 383 else 384 tmp |= voltage->gpio.mask; 385 WREG32(voltage->gpio.reg, tmp); 386 if (voltage->delay) 387 udelay(voltage->delay); 388 } 389 } 390 391 sclk_cntl = RREG32_PLL(SCLK_CNTL); 392 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 393 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 394 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 395 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 396 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 397 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 398 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 399 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 400 else 401 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 402 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 403 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 404 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 405 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 406 } else 407 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 408 409 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 410 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 411 if (voltage->delay) { 412 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 413 switch (voltage->delay) { 414 case 33: 415 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 416 break; 417 case 66: 418 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 419 break; 420 case 99: 421 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 422 break; 423 case 132: 424 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 425 break; 426 } 427 } else 428 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 429 } else 430 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 431 432 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 433 sclk_cntl &= ~FORCE_HDP; 434 else 435 sclk_cntl |= FORCE_HDP; 436 437 WREG32_PLL(SCLK_CNTL, sclk_cntl); 438 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 439 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 440 441 /* set pcie lanes */ 442 if ((rdev->flags & RADEON_IS_PCIE) && 443 !(rdev->flags & RADEON_IS_IGP) && 444 rdev->asic->pm.set_pcie_lanes && 445 (ps->pcie_lanes != 446 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 447 radeon_set_pcie_lanes(rdev, 448 ps->pcie_lanes); 449 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 450 } 451 } 452 453 /** 454 * r100_pm_prepare - pre-power state change callback. 455 * 456 * @rdev: radeon_device pointer 457 * 458 * Prepare for a power state change (r1xx-r4xx). 459 */ 460 void r100_pm_prepare(struct radeon_device *rdev) 461 { 462 struct drm_device *ddev = rdev_to_drm(rdev); 463 struct drm_crtc *crtc; 464 struct radeon_crtc *radeon_crtc; 465 u32 tmp; 466 467 /* disable any active CRTCs */ 468 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 469 radeon_crtc = to_radeon_crtc(crtc); 470 if (radeon_crtc->enabled) { 471 if (radeon_crtc->crtc_id) { 472 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 473 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 474 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 475 } else { 476 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 477 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 478 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 479 } 480 } 481 } 482 } 483 484 /** 485 * r100_pm_finish - post-power state change callback. 486 * 487 * @rdev: radeon_device pointer 488 * 489 * Clean up after a power state change (r1xx-r4xx). 490 */ 491 void r100_pm_finish(struct radeon_device *rdev) 492 { 493 struct drm_device *ddev = rdev_to_drm(rdev); 494 struct drm_crtc *crtc; 495 struct radeon_crtc *radeon_crtc; 496 u32 tmp; 497 498 /* enable any active CRTCs */ 499 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 500 radeon_crtc = to_radeon_crtc(crtc); 501 if (radeon_crtc->enabled) { 502 if (radeon_crtc->crtc_id) { 503 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 504 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 505 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 506 } else { 507 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 508 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 509 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 510 } 511 } 512 } 513 } 514 515 /** 516 * r100_gui_idle - gui idle callback. 517 * 518 * @rdev: radeon_device pointer 519 * 520 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 521 * Returns true if idle, false if not. 522 */ 523 bool r100_gui_idle(struct radeon_device *rdev) 524 { 525 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 526 return false; 527 else 528 return true; 529 } 530 531 /* hpd for digital panel detect/disconnect */ 532 /** 533 * r100_hpd_sense - hpd sense callback. 534 * 535 * @rdev: radeon_device pointer 536 * @hpd: hpd (hotplug detect) pin 537 * 538 * Checks if a digital monitor is connected (r1xx-r4xx). 539 * Returns true if connected, false if not connected. 540 */ 541 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 542 { 543 bool connected = false; 544 545 switch (hpd) { 546 case RADEON_HPD_1: 547 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 548 connected = true; 549 break; 550 case RADEON_HPD_2: 551 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 552 connected = true; 553 break; 554 default: 555 break; 556 } 557 return connected; 558 } 559 560 /** 561 * r100_hpd_set_polarity - hpd set polarity callback. 562 * 563 * @rdev: radeon_device pointer 564 * @hpd: hpd (hotplug detect) pin 565 * 566 * Set the polarity of the hpd pin (r1xx-r4xx). 567 */ 568 void r100_hpd_set_polarity(struct radeon_device *rdev, 569 enum radeon_hpd_id hpd) 570 { 571 u32 tmp; 572 bool connected = r100_hpd_sense(rdev, hpd); 573 574 switch (hpd) { 575 case RADEON_HPD_1: 576 tmp = RREG32(RADEON_FP_GEN_CNTL); 577 if (connected) 578 tmp &= ~RADEON_FP_DETECT_INT_POL; 579 else 580 tmp |= RADEON_FP_DETECT_INT_POL; 581 WREG32(RADEON_FP_GEN_CNTL, tmp); 582 break; 583 case RADEON_HPD_2: 584 tmp = RREG32(RADEON_FP2_GEN_CNTL); 585 if (connected) 586 tmp &= ~RADEON_FP2_DETECT_INT_POL; 587 else 588 tmp |= RADEON_FP2_DETECT_INT_POL; 589 WREG32(RADEON_FP2_GEN_CNTL, tmp); 590 break; 591 default: 592 break; 593 } 594 } 595 596 /** 597 * r100_hpd_init - hpd setup callback. 598 * 599 * @rdev: radeon_device pointer 600 * 601 * Setup the hpd pins used by the card (r1xx-r4xx). 602 * Set the polarity, and enable the hpd interrupts. 603 */ 604 void r100_hpd_init(struct radeon_device *rdev) 605 { 606 struct drm_device *dev = rdev_to_drm(rdev); 607 struct drm_connector *connector; 608 unsigned enable = 0; 609 610 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 611 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 612 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 613 enable |= 1 << radeon_connector->hpd.hpd; 614 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 615 } 616 radeon_irq_kms_enable_hpd(rdev, enable); 617 } 618 619 /** 620 * r100_hpd_fini - hpd tear down callback. 621 * 622 * @rdev: radeon_device pointer 623 * 624 * Tear down the hpd pins used by the card (r1xx-r4xx). 625 * Disable the hpd interrupts. 626 */ 627 void r100_hpd_fini(struct radeon_device *rdev) 628 { 629 struct drm_device *dev = rdev_to_drm(rdev); 630 struct drm_connector *connector; 631 unsigned disable = 0; 632 633 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 634 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 635 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 636 disable |= 1 << radeon_connector->hpd.hpd; 637 } 638 radeon_irq_kms_disable_hpd(rdev, disable); 639 } 640 641 /* 642 * PCI GART 643 */ 644 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 645 { 646 /* TODO: can we do somethings here ? */ 647 /* It seems hw only cache one entry so we should discard this 648 * entry otherwise if first GPU GART read hit this entry it 649 * could end up in wrong address. */ 650 } 651 652 int r100_pci_gart_init(struct radeon_device *rdev) 653 { 654 int r; 655 656 if (rdev->gart.ptr) { 657 WARN(1, "R100 PCI GART already initialized\n"); 658 return 0; 659 } 660 /* Initialize common gart structure */ 661 r = radeon_gart_init(rdev); 662 if (r) 663 return r; 664 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 665 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 666 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; 667 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 668 return radeon_gart_table_ram_alloc(rdev); 669 } 670 671 int r100_pci_gart_enable(struct radeon_device *rdev) 672 { 673 uint32_t tmp; 674 675 /* discard memory request outside of configured range */ 676 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 677 WREG32(RADEON_AIC_CNTL, tmp); 678 /* set address range for PCI address translate */ 679 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 680 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 681 /* set PCI GART page-table base address */ 682 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 683 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 684 WREG32(RADEON_AIC_CNTL, tmp); 685 r100_pci_gart_tlb_flush(rdev); 686 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 687 (unsigned)(rdev->mc.gtt_size >> 20), 688 (unsigned long long)rdev->gart.table_addr); 689 rdev->gart.ready = true; 690 return 0; 691 } 692 693 void r100_pci_gart_disable(struct radeon_device *rdev) 694 { 695 uint32_t tmp; 696 697 /* discard memory request outside of configured range */ 698 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 699 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 700 WREG32(RADEON_AIC_LO_ADDR, 0); 701 WREG32(RADEON_AIC_HI_ADDR, 0); 702 } 703 704 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags) 705 { 706 return addr; 707 } 708 709 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 710 uint64_t entry) 711 { 712 u32 *gtt = rdev->gart.ptr; 713 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 714 } 715 716 void r100_pci_gart_fini(struct radeon_device *rdev) 717 { 718 radeon_gart_fini(rdev); 719 r100_pci_gart_disable(rdev); 720 radeon_gart_table_ram_free(rdev); 721 } 722 723 int r100_irq_set(struct radeon_device *rdev) 724 { 725 uint32_t tmp = 0; 726 727 if (!rdev->irq.installed) { 728 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 729 WREG32(R_000040_GEN_INT_CNTL, 0); 730 return -EINVAL; 731 } 732 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 733 tmp |= RADEON_SW_INT_ENABLE; 734 } 735 if (rdev->irq.crtc_vblank_int[0] || 736 atomic_read(&rdev->irq.pflip[0])) { 737 tmp |= RADEON_CRTC_VBLANK_MASK; 738 } 739 if (rdev->irq.crtc_vblank_int[1] || 740 atomic_read(&rdev->irq.pflip[1])) { 741 tmp |= RADEON_CRTC2_VBLANK_MASK; 742 } 743 if (rdev->irq.hpd[0]) { 744 tmp |= RADEON_FP_DETECT_MASK; 745 } 746 if (rdev->irq.hpd[1]) { 747 tmp |= RADEON_FP2_DETECT_MASK; 748 } 749 WREG32(RADEON_GEN_INT_CNTL, tmp); 750 751 /* read back to post the write */ 752 RREG32(RADEON_GEN_INT_CNTL); 753 754 return 0; 755 } 756 757 void r100_irq_disable(struct radeon_device *rdev) 758 { 759 u32 tmp; 760 761 WREG32(R_000040_GEN_INT_CNTL, 0); 762 /* Wait and acknowledge irq */ 763 mdelay(1); 764 tmp = RREG32(R_000044_GEN_INT_STATUS); 765 WREG32(R_000044_GEN_INT_STATUS, tmp); 766 } 767 768 static uint32_t r100_irq_ack(struct radeon_device *rdev) 769 { 770 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 771 uint32_t irq_mask = RADEON_SW_INT_TEST | 772 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 773 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 774 775 if (irqs) { 776 WREG32(RADEON_GEN_INT_STATUS, irqs); 777 } 778 return irqs & irq_mask; 779 } 780 781 int r100_irq_process(struct radeon_device *rdev) 782 { 783 uint32_t status, msi_rearm; 784 bool queue_hotplug = false; 785 786 status = r100_irq_ack(rdev); 787 if (!status) { 788 return IRQ_NONE; 789 } 790 if (rdev->shutdown) { 791 return IRQ_NONE; 792 } 793 while (status) { 794 /* SW interrupt */ 795 if (status & RADEON_SW_INT_TEST) { 796 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 797 } 798 /* Vertical blank interrupts */ 799 if (status & RADEON_CRTC_VBLANK_STAT) { 800 if (rdev->irq.crtc_vblank_int[0]) { 801 drm_handle_vblank(rdev_to_drm(rdev), 0); 802 rdev->pm.vblank_sync = true; 803 wake_up(&rdev->irq.vblank_queue); 804 } 805 if (atomic_read(&rdev->irq.pflip[0])) 806 radeon_crtc_handle_vblank(rdev, 0); 807 } 808 if (status & RADEON_CRTC2_VBLANK_STAT) { 809 if (rdev->irq.crtc_vblank_int[1]) { 810 drm_handle_vblank(rdev_to_drm(rdev), 1); 811 rdev->pm.vblank_sync = true; 812 wake_up(&rdev->irq.vblank_queue); 813 } 814 if (atomic_read(&rdev->irq.pflip[1])) 815 radeon_crtc_handle_vblank(rdev, 1); 816 } 817 if (status & RADEON_FP_DETECT_STAT) { 818 queue_hotplug = true; 819 DRM_DEBUG("HPD1\n"); 820 } 821 if (status & RADEON_FP2_DETECT_STAT) { 822 queue_hotplug = true; 823 DRM_DEBUG("HPD2\n"); 824 } 825 status = r100_irq_ack(rdev); 826 } 827 if (queue_hotplug) 828 schedule_delayed_work(&rdev->hotplug_work, 0); 829 if (rdev->msi_enabled) { 830 switch (rdev->family) { 831 case CHIP_RS400: 832 case CHIP_RS480: 833 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 834 WREG32(RADEON_AIC_CNTL, msi_rearm); 835 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 836 break; 837 default: 838 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 839 break; 840 } 841 } 842 return IRQ_HANDLED; 843 } 844 845 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 846 { 847 if (crtc == 0) 848 return RREG32(RADEON_CRTC_CRNT_FRAME); 849 else 850 return RREG32(RADEON_CRTC2_CRNT_FRAME); 851 } 852 853 /** 854 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer 855 * @rdev: radeon device structure 856 * @ring: ring buffer struct for emitting packets 857 */ 858 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring) 859 { 860 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 862 RADEON_HDP_READ_BUFFER_INVALIDATE); 863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 865 } 866 867 /* Who ever call radeon_fence_emit should call ring_lock and ask 868 * for enough space (today caller are ib schedule and buffer move) */ 869 void r100_fence_ring_emit(struct radeon_device *rdev, 870 struct radeon_fence *fence) 871 { 872 struct radeon_ring *ring = &rdev->ring[fence->ring]; 873 874 /* We have to make sure that caches are flushed before 875 * CPU might read something from VRAM. */ 876 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 877 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 878 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 879 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 880 /* Wait until IDLE & CLEAN */ 881 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 882 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 883 r100_ring_hdp_flush(rdev, ring); 884 /* Emit fence sequence & fire IRQ */ 885 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 886 radeon_ring_write(ring, fence->seq); 887 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 888 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 889 } 890 891 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 892 struct radeon_ring *ring, 893 struct radeon_semaphore *semaphore, 894 bool emit_wait) 895 { 896 /* Unused on older asics, since we don't have semaphores or multiple rings */ 897 BUG(); 898 return false; 899 } 900 901 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 902 uint64_t src_offset, 903 uint64_t dst_offset, 904 unsigned num_gpu_pages, 905 struct dma_resv *resv) 906 { 907 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 908 struct radeon_fence *fence; 909 uint64_t cur_src_offset, cur_dst_offset; 910 uint32_t cur_pages; 911 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 912 uint32_t pitch; 913 uint32_t stride_pixels; 914 unsigned ndw; 915 int num_loops; 916 int r = 0; 917 918 /* radeon limited to 16k stride */ 919 stride_bytes &= 0x3fff; 920 /* radeon pitch is /64 */ 921 pitch = stride_bytes / 64; 922 stride_pixels = stride_bytes / 4; 923 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 924 925 /* Ask for enough room for blit + flush + fence */ 926 ndw = 64 + (10 * num_loops); 927 r = radeon_ring_lock(rdev, ring, ndw); 928 if (r) { 929 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 930 return ERR_PTR(-EINVAL); 931 } 932 while (num_gpu_pages > 0) { 933 cur_pages = num_gpu_pages; 934 if (cur_pages > 8191) { 935 cur_pages = 8191; 936 } 937 num_gpu_pages -= cur_pages; 938 cur_src_offset = src_offset + 939 (uint64_t)num_gpu_pages * RADEON_GPU_PAGE_SIZE; 940 cur_dst_offset = dst_offset + 941 (uint64_t)num_gpu_pages * RADEON_GPU_PAGE_SIZE; 942 943 /* pages are in Y direction - height 944 page width in X direction - width */ 945 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 946 radeon_ring_write(ring, 947 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 948 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 949 RADEON_GMC_SRC_CLIPPING | 950 RADEON_GMC_DST_CLIPPING | 951 RADEON_GMC_BRUSH_NONE | 952 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 953 RADEON_GMC_SRC_DATATYPE_COLOR | 954 RADEON_ROP3_S | 955 RADEON_DP_SRC_SOURCE_MEMORY | 956 RADEON_GMC_CLR_CMP_CNTL_DIS | 957 RADEON_GMC_WR_MSK_DIS); 958 radeon_ring_write(ring, (pitch << 22) | (cur_src_offset >> 10)); 959 radeon_ring_write(ring, (pitch << 22) | (cur_dst_offset >> 10)); 960 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 961 radeon_ring_write(ring, 0); 962 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 963 radeon_ring_write(ring, 0); 964 radeon_ring_write(ring, 0); 965 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 966 } 967 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 968 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 969 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 970 radeon_ring_write(ring, 971 RADEON_WAIT_2D_IDLECLEAN | 972 RADEON_WAIT_HOST_IDLECLEAN | 973 RADEON_WAIT_DMA_GUI_IDLE); 974 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 975 if (r) { 976 radeon_ring_unlock_undo(rdev, ring); 977 return ERR_PTR(r); 978 } 979 radeon_ring_unlock_commit(rdev, ring, false); 980 return fence; 981 } 982 983 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 984 { 985 unsigned i; 986 u32 tmp; 987 988 for (i = 0; i < rdev->usec_timeout; i++) { 989 tmp = RREG32(R_000E40_RBBM_STATUS); 990 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 991 return 0; 992 } 993 udelay(1); 994 } 995 return -1; 996 } 997 998 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 999 { 1000 int r; 1001 1002 r = radeon_ring_lock(rdev, ring, 2); 1003 if (r) { 1004 return; 1005 } 1006 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 1007 radeon_ring_write(ring, 1008 RADEON_ISYNC_ANY2D_IDLE3D | 1009 RADEON_ISYNC_ANY3D_IDLE2D | 1010 RADEON_ISYNC_WAIT_IDLEGUI | 1011 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 1012 radeon_ring_unlock_commit(rdev, ring, false); 1013 } 1014 1015 1016 /* Load the microcode for the CP */ 1017 static int r100_cp_init_microcode(struct radeon_device *rdev) 1018 { 1019 const char *fw_name = NULL; 1020 int err; 1021 1022 DRM_DEBUG_KMS("\n"); 1023 1024 switch (rdev->family) { 1025 case CHIP_R100: 1026 case CHIP_RV100: 1027 case CHIP_RV200: 1028 case CHIP_RS100: 1029 case CHIP_RS200: 1030 DRM_INFO("Loading R100 Microcode\n"); 1031 fw_name = FIRMWARE_R100; 1032 break; 1033 1034 case CHIP_R200: 1035 case CHIP_RV250: 1036 case CHIP_RV280: 1037 case CHIP_RS300: 1038 DRM_INFO("Loading R200 Microcode\n"); 1039 fw_name = FIRMWARE_R200; 1040 break; 1041 1042 case CHIP_R300: 1043 case CHIP_R350: 1044 case CHIP_RV350: 1045 case CHIP_RV380: 1046 case CHIP_RS400: 1047 case CHIP_RS480: 1048 DRM_INFO("Loading R300 Microcode\n"); 1049 fw_name = FIRMWARE_R300; 1050 break; 1051 1052 case CHIP_R420: 1053 case CHIP_R423: 1054 case CHIP_RV410: 1055 DRM_INFO("Loading R400 Microcode\n"); 1056 fw_name = FIRMWARE_R420; 1057 break; 1058 1059 case CHIP_RS690: 1060 case CHIP_RS740: 1061 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1062 fw_name = FIRMWARE_RS690; 1063 break; 1064 1065 case CHIP_RS600: 1066 DRM_INFO("Loading RS600 Microcode\n"); 1067 fw_name = FIRMWARE_RS600; 1068 break; 1069 1070 case CHIP_RV515: 1071 case CHIP_R520: 1072 case CHIP_RV530: 1073 case CHIP_R580: 1074 case CHIP_RV560: 1075 case CHIP_RV570: 1076 DRM_INFO("Loading R500 Microcode\n"); 1077 fw_name = FIRMWARE_R520; 1078 break; 1079 1080 default: 1081 DRM_ERROR("Unsupported Radeon family %u\n", rdev->family); 1082 return -EINVAL; 1083 } 1084 1085 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); 1086 if (err) { 1087 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name); 1088 } else if (rdev->me_fw->size % 8) { 1089 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1090 rdev->me_fw->size, fw_name); 1091 err = -EINVAL; 1092 release_firmware(rdev->me_fw); 1093 rdev->me_fw = NULL; 1094 } 1095 return err; 1096 } 1097 1098 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 1099 struct radeon_ring *ring) 1100 { 1101 u32 rptr; 1102 1103 if (rdev->wb.enabled) 1104 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 1105 else 1106 rptr = RREG32(RADEON_CP_RB_RPTR); 1107 1108 return rptr; 1109 } 1110 1111 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 1112 struct radeon_ring *ring) 1113 { 1114 return RREG32(RADEON_CP_RB_WPTR); 1115 } 1116 1117 void r100_gfx_set_wptr(struct radeon_device *rdev, 1118 struct radeon_ring *ring) 1119 { 1120 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1121 (void)RREG32(RADEON_CP_RB_WPTR); 1122 } 1123 1124 static void r100_cp_load_microcode(struct radeon_device *rdev) 1125 { 1126 const __be32 *fw_data; 1127 int i, size; 1128 1129 if (r100_gui_wait_for_idle(rdev)) { 1130 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1131 } 1132 1133 if (rdev->me_fw) { 1134 size = rdev->me_fw->size / 4; 1135 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 1136 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1137 for (i = 0; i < size; i += 2) { 1138 WREG32(RADEON_CP_ME_RAM_DATAH, 1139 be32_to_cpup(&fw_data[i])); 1140 WREG32(RADEON_CP_ME_RAM_DATAL, 1141 be32_to_cpup(&fw_data[i + 1])); 1142 } 1143 } 1144 } 1145 1146 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1147 { 1148 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1149 unsigned rb_bufsz; 1150 unsigned rb_blksz; 1151 unsigned max_fetch; 1152 unsigned pre_write_timer; 1153 unsigned pre_write_limit; 1154 unsigned indirect2_start; 1155 unsigned indirect1_start; 1156 uint32_t tmp; 1157 int r; 1158 1159 r100_debugfs_cp_init(rdev); 1160 if (!rdev->me_fw) { 1161 r = r100_cp_init_microcode(rdev); 1162 if (r) { 1163 DRM_ERROR("Failed to load firmware!\n"); 1164 return r; 1165 } 1166 } 1167 1168 /* Align ring size */ 1169 rb_bufsz = order_base_2(ring_size / 8); 1170 ring_size = (1 << (rb_bufsz + 1)) * 4; 1171 r100_cp_load_microcode(rdev); 1172 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1173 RADEON_CP_PACKET2); 1174 if (r) { 1175 return r; 1176 } 1177 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1178 * the rptr copy in system ram */ 1179 rb_blksz = 9; 1180 /* cp will read 128bytes at a time (4 dwords) */ 1181 max_fetch = 1; 1182 ring->align_mask = 16 - 1; 1183 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1184 pre_write_timer = 64; 1185 /* Force CP_RB_WPTR write if written more than one time before the 1186 * delay expire 1187 */ 1188 pre_write_limit = 0; 1189 /* Setup the cp cache like this (cache size is 96 dwords) : 1190 * RING 0 to 15 1191 * INDIRECT1 16 to 79 1192 * INDIRECT2 80 to 95 1193 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1194 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1195 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1196 * Idea being that most of the gpu cmd will be through indirect1 buffer 1197 * so it gets the bigger cache. 1198 */ 1199 indirect2_start = 80; 1200 indirect1_start = 16; 1201 /* cp setup */ 1202 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1203 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1204 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1205 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1206 #ifdef __BIG_ENDIAN 1207 tmp |= RADEON_BUF_SWAP_32BIT; 1208 #endif 1209 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1210 1211 /* Set ring address */ 1212 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1213 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1214 /* Force read & write ptr to 0 */ 1215 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1216 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1217 ring->wptr = 0; 1218 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1219 1220 /* set the wb address whether it's enabled or not */ 1221 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1222 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1223 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1224 1225 if (rdev->wb.enabled) 1226 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1227 else { 1228 tmp |= RADEON_RB_NO_UPDATE; 1229 WREG32(R_000770_SCRATCH_UMSK, 0); 1230 } 1231 1232 WREG32(RADEON_CP_RB_CNTL, tmp); 1233 udelay(10); 1234 /* Set cp mode to bus mastering & enable cp*/ 1235 WREG32(RADEON_CP_CSQ_MODE, 1236 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1237 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1238 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1239 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1240 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1241 1242 /* at this point everything should be setup correctly to enable master */ 1243 pci_set_master(rdev->pdev); 1244 1245 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1246 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1247 if (r) { 1248 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1249 return r; 1250 } 1251 ring->ready = true; 1252 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1253 1254 if (!ring->rptr_save_reg /* not resuming from suspend */ 1255 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1256 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1257 if (r) { 1258 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1259 ring->rptr_save_reg = 0; 1260 } 1261 } 1262 return 0; 1263 } 1264 1265 void r100_cp_fini(struct radeon_device *rdev) 1266 { 1267 if (r100_cp_wait_for_idle(rdev)) { 1268 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1269 } 1270 /* Disable ring */ 1271 r100_cp_disable(rdev); 1272 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1273 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1274 DRM_INFO("radeon: cp finalized\n"); 1275 } 1276 1277 void r100_cp_disable(struct radeon_device *rdev) 1278 { 1279 /* Disable ring */ 1280 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1281 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1282 WREG32(RADEON_CP_CSQ_MODE, 0); 1283 WREG32(RADEON_CP_CSQ_CNTL, 0); 1284 WREG32(R_000770_SCRATCH_UMSK, 0); 1285 if (r100_gui_wait_for_idle(rdev)) { 1286 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); 1287 } 1288 } 1289 1290 /* 1291 * CS functions 1292 */ 1293 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1294 struct radeon_cs_packet *pkt, 1295 unsigned idx, 1296 unsigned reg) 1297 { 1298 int r; 1299 u32 tile_flags = 0; 1300 u32 tmp; 1301 struct radeon_bo_list *reloc; 1302 u32 value; 1303 1304 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1305 if (r) { 1306 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1307 idx, reg); 1308 radeon_cs_dump_packet(p, pkt); 1309 return r; 1310 } 1311 1312 value = radeon_get_ib_value(p, idx); 1313 tmp = value & 0x003fffff; 1314 tmp += (((u32)reloc->gpu_offset) >> 10); 1315 1316 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1317 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1318 tile_flags |= RADEON_DST_TILE_MACRO; 1319 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1320 if (reg == RADEON_SRC_PITCH_OFFSET) { 1321 dev_warn_once(p->dev, "Cannot src blit from microtiled surface\n"); 1322 radeon_cs_dump_packet(p, pkt); 1323 return -EINVAL; 1324 } 1325 tile_flags |= RADEON_DST_TILE_MICRO; 1326 } 1327 1328 tmp |= tile_flags; 1329 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1330 } else 1331 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1332 return 0; 1333 } 1334 1335 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1336 struct radeon_cs_packet *pkt, 1337 int idx) 1338 { 1339 unsigned c, i; 1340 struct radeon_bo_list *reloc; 1341 struct r100_cs_track *track; 1342 int r = 0; 1343 volatile uint32_t *ib; 1344 u32 idx_value; 1345 1346 ib = p->ib.ptr; 1347 track = (struct r100_cs_track *)p->track; 1348 c = radeon_get_ib_value(p, idx++) & 0x1F; 1349 if (c > 16) { 1350 dev_warn_once(p->dev, "Only 16 vertex buffers are allowed %d\n", 1351 pkt->opcode); 1352 radeon_cs_dump_packet(p, pkt); 1353 return -EINVAL; 1354 } 1355 track->num_arrays = c; 1356 for (i = 0; i < (c - 1); i += 2, idx += 3) { 1357 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1358 if (r) { 1359 dev_warn_once(p->dev, "No reloc for packet3 %d\n", 1360 pkt->opcode); 1361 radeon_cs_dump_packet(p, pkt); 1362 return r; 1363 } 1364 idx_value = radeon_get_ib_value(p, idx); 1365 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1366 1367 track->arrays[i + 0].esize = idx_value >> 8; 1368 track->arrays[i + 0].robj = reloc->robj; 1369 track->arrays[i + 0].esize &= 0x7F; 1370 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1371 if (r) { 1372 dev_warn_once(p->dev, "No reloc for packet3 %d\n", 1373 pkt->opcode); 1374 radeon_cs_dump_packet(p, pkt); 1375 return r; 1376 } 1377 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); 1378 track->arrays[i + 1].robj = reloc->robj; 1379 track->arrays[i + 1].esize = idx_value >> 24; 1380 track->arrays[i + 1].esize &= 0x7F; 1381 } 1382 if (c & 1) { 1383 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1384 if (r) { 1385 dev_warn_once(p->dev, "No reloc for packet3 %d\n", 1386 pkt->opcode); 1387 radeon_cs_dump_packet(p, pkt); 1388 return r; 1389 } 1390 idx_value = radeon_get_ib_value(p, idx); 1391 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); 1392 track->arrays[i + 0].robj = reloc->robj; 1393 track->arrays[i + 0].esize = idx_value >> 8; 1394 track->arrays[i + 0].esize &= 0x7F; 1395 } 1396 return r; 1397 } 1398 1399 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1400 struct radeon_cs_packet *pkt, 1401 const unsigned *auth, unsigned n, 1402 radeon_packet0_check_t check) 1403 { 1404 unsigned reg; 1405 unsigned i, j, m; 1406 unsigned idx; 1407 int r; 1408 1409 idx = pkt->idx + 1; 1410 reg = pkt->reg; 1411 /* Check that register fall into register range 1412 * determined by the number of entry (n) in the 1413 * safe register bitmap. 1414 */ 1415 if (pkt->one_reg_wr) { 1416 if ((reg >> 7) > n) { 1417 return -EINVAL; 1418 } 1419 } else { 1420 if (((reg + (pkt->count << 2)) >> 7) > n) { 1421 return -EINVAL; 1422 } 1423 } 1424 for (i = 0; i <= pkt->count; i++, idx++) { 1425 j = (reg >> 7); 1426 m = 1 << ((reg >> 2) & 31); 1427 if (auth[j] & m) { 1428 r = check(p, pkt, idx, reg); 1429 if (r) { 1430 return r; 1431 } 1432 } 1433 if (pkt->one_reg_wr) { 1434 if (!(auth[j] & m)) { 1435 break; 1436 } 1437 } else { 1438 reg += 4; 1439 } 1440 } 1441 return 0; 1442 } 1443 1444 /** 1445 * r100_cs_packet_parse_vline() - parse userspace VLINE packet 1446 * @p: parser structure holding parsing context. 1447 * 1448 * Userspace sends a special sequence for VLINE waits. 1449 * PACKET0 - VLINE_START_END + value 1450 * PACKET0 - WAIT_UNTIL +_value 1451 * RELOC (P3) - crtc_id in reloc. 1452 * 1453 * This function parses this and relocates the VLINE START END 1454 * and WAIT UNTIL packets to the correct crtc. 1455 * It also detects a switched off crtc and nulls out the 1456 * wait in that case. 1457 */ 1458 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1459 { 1460 struct drm_crtc *crtc; 1461 struct radeon_crtc *radeon_crtc; 1462 struct radeon_cs_packet p3reloc, waitreloc; 1463 int crtc_id; 1464 int r; 1465 uint32_t header, h_idx, reg; 1466 volatile uint32_t *ib; 1467 1468 ib = p->ib.ptr; 1469 1470 /* parse the wait until */ 1471 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); 1472 if (r) 1473 return r; 1474 1475 /* check its a wait until and only 1 count */ 1476 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1477 waitreloc.count != 0) { 1478 dev_warn_once(p->dev, "vline wait had illegal wait until segment\n"); 1479 return -EINVAL; 1480 } 1481 1482 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1483 dev_warn_once(p->dev, "vline wait had illegal wait until\n"); 1484 return -EINVAL; 1485 } 1486 1487 /* jump over the NOP */ 1488 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1489 if (r) 1490 return r; 1491 1492 h_idx = p->idx - 2; 1493 p->idx += waitreloc.count + 2; 1494 p->idx += p3reloc.count + 2; 1495 1496 header = radeon_get_ib_value(p, h_idx); 1497 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1498 reg = R100_CP_PACKET0_GET_REG(header); 1499 crtc = drm_crtc_find(rdev_to_drm(p->rdev), p->filp, crtc_id); 1500 if (!crtc) { 1501 dev_warn_once(p->dev, "cannot find crtc %d\n", crtc_id); 1502 return -ENOENT; 1503 } 1504 radeon_crtc = to_radeon_crtc(crtc); 1505 crtc_id = radeon_crtc->crtc_id; 1506 1507 if (!crtc->enabled) { 1508 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1509 ib[h_idx + 2] = PACKET2(0); 1510 ib[h_idx + 3] = PACKET2(0); 1511 } else if (crtc_id == 1) { 1512 switch (reg) { 1513 case AVIVO_D1MODE_VLINE_START_END: 1514 header &= ~R300_CP_PACKET0_REG_MASK; 1515 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1516 break; 1517 case RADEON_CRTC_GUI_TRIG_VLINE: 1518 header &= ~R300_CP_PACKET0_REG_MASK; 1519 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1520 break; 1521 default: 1522 dev_warn_once(p->dev, "unknown crtc reloc\n"); 1523 return -EINVAL; 1524 } 1525 ib[h_idx] = header; 1526 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int r100_get_vtx_size(uint32_t vtx_fmt) 1533 { 1534 int vtx_size; 1535 vtx_size = 2; 1536 /* ordered according to bits in spec */ 1537 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1538 vtx_size++; 1539 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1540 vtx_size += 3; 1541 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1542 vtx_size++; 1543 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1544 vtx_size++; 1545 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1546 vtx_size += 3; 1547 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1548 vtx_size++; 1549 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1550 vtx_size++; 1551 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1552 vtx_size += 2; 1553 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1554 vtx_size += 2; 1555 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1556 vtx_size++; 1557 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1558 vtx_size += 2; 1559 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1560 vtx_size++; 1561 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1562 vtx_size += 2; 1563 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1564 vtx_size++; 1565 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1566 vtx_size++; 1567 /* blend weight */ 1568 if (vtx_fmt & (0x7 << 15)) 1569 vtx_size += (vtx_fmt >> 15) & 0x7; 1570 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1571 vtx_size += 3; 1572 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1573 vtx_size += 2; 1574 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1575 vtx_size++; 1576 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1577 vtx_size++; 1578 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1579 vtx_size++; 1580 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1581 vtx_size++; 1582 return vtx_size; 1583 } 1584 1585 static int r100_packet0_check(struct radeon_cs_parser *p, 1586 struct radeon_cs_packet *pkt, 1587 unsigned idx, unsigned reg) 1588 { 1589 struct radeon_bo_list *reloc; 1590 struct r100_cs_track *track; 1591 volatile uint32_t *ib; 1592 uint32_t tmp; 1593 int r; 1594 int i, face; 1595 u32 tile_flags = 0; 1596 u32 idx_value; 1597 1598 ib = p->ib.ptr; 1599 track = (struct r100_cs_track *)p->track; 1600 1601 idx_value = radeon_get_ib_value(p, idx); 1602 1603 switch (reg) { 1604 case RADEON_CRTC_GUI_TRIG_VLINE: 1605 r = r100_cs_packet_parse_vline(p); 1606 if (r) { 1607 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1608 idx, reg); 1609 radeon_cs_dump_packet(p, pkt); 1610 return r; 1611 } 1612 break; 1613 /* FIXME: only allow PACKET3 blit? easier to check for out of 1614 * range access */ 1615 case RADEON_DST_PITCH_OFFSET: 1616 case RADEON_SRC_PITCH_OFFSET: 1617 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1618 if (r) 1619 return r; 1620 break; 1621 case RADEON_RB3D_DEPTHOFFSET: 1622 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1623 if (r) { 1624 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1625 idx, reg); 1626 radeon_cs_dump_packet(p, pkt); 1627 return r; 1628 } 1629 track->zb.robj = reloc->robj; 1630 track->zb.offset = idx_value; 1631 track->zb_dirty = true; 1632 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1633 break; 1634 case RADEON_RB3D_COLOROFFSET: 1635 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1636 if (r) { 1637 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1638 idx, reg); 1639 radeon_cs_dump_packet(p, pkt); 1640 return r; 1641 } 1642 track->cb[0].robj = reloc->robj; 1643 track->cb[0].offset = idx_value; 1644 track->cb_dirty = true; 1645 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1646 break; 1647 case RADEON_PP_TXOFFSET_0: 1648 case RADEON_PP_TXOFFSET_1: 1649 case RADEON_PP_TXOFFSET_2: 1650 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1651 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1652 if (r) { 1653 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1654 idx, reg); 1655 radeon_cs_dump_packet(p, pkt); 1656 return r; 1657 } 1658 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1659 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1660 tile_flags |= RADEON_TXO_MACRO_TILE; 1661 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1662 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1663 1664 tmp = idx_value & ~(0x7 << 2); 1665 tmp |= tile_flags; 1666 ib[idx] = tmp + ((u32)reloc->gpu_offset); 1667 } else 1668 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1669 track->textures[i].robj = reloc->robj; 1670 track->tex_dirty = true; 1671 break; 1672 case RADEON_PP_CUBIC_OFFSET_T0_0: 1673 case RADEON_PP_CUBIC_OFFSET_T0_1: 1674 case RADEON_PP_CUBIC_OFFSET_T0_2: 1675 case RADEON_PP_CUBIC_OFFSET_T0_3: 1676 case RADEON_PP_CUBIC_OFFSET_T0_4: 1677 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1678 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1679 if (r) { 1680 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1681 idx, reg); 1682 radeon_cs_dump_packet(p, pkt); 1683 return r; 1684 } 1685 track->textures[0].cube_info[i].offset = idx_value; 1686 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1687 track->textures[0].cube_info[i].robj = reloc->robj; 1688 track->tex_dirty = true; 1689 break; 1690 case RADEON_PP_CUBIC_OFFSET_T1_0: 1691 case RADEON_PP_CUBIC_OFFSET_T1_1: 1692 case RADEON_PP_CUBIC_OFFSET_T1_2: 1693 case RADEON_PP_CUBIC_OFFSET_T1_3: 1694 case RADEON_PP_CUBIC_OFFSET_T1_4: 1695 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1696 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1697 if (r) { 1698 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1699 idx, reg); 1700 radeon_cs_dump_packet(p, pkt); 1701 return r; 1702 } 1703 track->textures[1].cube_info[i].offset = idx_value; 1704 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1705 track->textures[1].cube_info[i].robj = reloc->robj; 1706 track->tex_dirty = true; 1707 break; 1708 case RADEON_PP_CUBIC_OFFSET_T2_0: 1709 case RADEON_PP_CUBIC_OFFSET_T2_1: 1710 case RADEON_PP_CUBIC_OFFSET_T2_2: 1711 case RADEON_PP_CUBIC_OFFSET_T2_3: 1712 case RADEON_PP_CUBIC_OFFSET_T2_4: 1713 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1714 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1715 if (r) { 1716 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1717 idx, reg); 1718 radeon_cs_dump_packet(p, pkt); 1719 return r; 1720 } 1721 track->textures[2].cube_info[i].offset = idx_value; 1722 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1723 track->textures[2].cube_info[i].robj = reloc->robj; 1724 track->tex_dirty = true; 1725 break; 1726 case RADEON_RE_WIDTH_HEIGHT: 1727 track->maxy = ((idx_value >> 16) & 0x7FF); 1728 track->cb_dirty = true; 1729 track->zb_dirty = true; 1730 break; 1731 case RADEON_RB3D_COLORPITCH: 1732 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1733 if (r) { 1734 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1735 idx, reg); 1736 radeon_cs_dump_packet(p, pkt); 1737 return r; 1738 } 1739 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1740 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1741 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1742 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1743 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1744 1745 tmp = idx_value & ~(0x7 << 16); 1746 tmp |= tile_flags; 1747 ib[idx] = tmp; 1748 } else 1749 ib[idx] = idx_value; 1750 1751 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1752 track->cb_dirty = true; 1753 break; 1754 case RADEON_RB3D_DEPTHPITCH: 1755 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1756 track->zb_dirty = true; 1757 break; 1758 case RADEON_RB3D_CNTL: 1759 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1760 case 7: 1761 case 8: 1762 case 9: 1763 case 11: 1764 case 12: 1765 track->cb[0].cpp = 1; 1766 break; 1767 case 3: 1768 case 4: 1769 case 15: 1770 track->cb[0].cpp = 2; 1771 break; 1772 case 6: 1773 track->cb[0].cpp = 4; 1774 break; 1775 default: 1776 dev_warn_once(p->dev, "Invalid color buffer format (%d) !\n", 1777 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1778 return -EINVAL; 1779 } 1780 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1781 track->cb_dirty = true; 1782 track->zb_dirty = true; 1783 break; 1784 case RADEON_RB3D_ZSTENCILCNTL: 1785 switch (idx_value & 0xf) { 1786 case 0: 1787 track->zb.cpp = 2; 1788 break; 1789 case 2: 1790 case 3: 1791 case 4: 1792 case 5: 1793 case 9: 1794 case 11: 1795 track->zb.cpp = 4; 1796 break; 1797 default: 1798 break; 1799 } 1800 track->zb_dirty = true; 1801 break; 1802 case RADEON_RB3D_ZPASS_ADDR: 1803 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1804 if (r) { 1805 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1806 idx, reg); 1807 radeon_cs_dump_packet(p, pkt); 1808 return r; 1809 } 1810 ib[idx] = idx_value + ((u32)reloc->gpu_offset); 1811 break; 1812 case RADEON_PP_CNTL: 1813 { 1814 uint32_t temp = idx_value >> 4; 1815 for (i = 0; i < track->num_texture; i++) 1816 track->textures[i].enabled = !!(temp & (1 << i)); 1817 track->tex_dirty = true; 1818 } 1819 break; 1820 case RADEON_SE_VF_CNTL: 1821 track->vap_vf_cntl = idx_value; 1822 break; 1823 case RADEON_SE_VTX_FMT: 1824 track->vtx_size = r100_get_vtx_size(idx_value); 1825 break; 1826 case RADEON_PP_TEX_SIZE_0: 1827 case RADEON_PP_TEX_SIZE_1: 1828 case RADEON_PP_TEX_SIZE_2: 1829 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1830 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1831 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1832 track->tex_dirty = true; 1833 break; 1834 case RADEON_PP_TEX_PITCH_0: 1835 case RADEON_PP_TEX_PITCH_1: 1836 case RADEON_PP_TEX_PITCH_2: 1837 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1838 track->textures[i].pitch = idx_value + 32; 1839 track->tex_dirty = true; 1840 break; 1841 case RADEON_PP_TXFILTER_0: 1842 case RADEON_PP_TXFILTER_1: 1843 case RADEON_PP_TXFILTER_2: 1844 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1845 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1846 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1847 tmp = (idx_value >> 23) & 0x7; 1848 if (tmp == 2 || tmp == 6) 1849 track->textures[i].roundup_w = false; 1850 tmp = (idx_value >> 27) & 0x7; 1851 if (tmp == 2 || tmp == 6) 1852 track->textures[i].roundup_h = false; 1853 track->tex_dirty = true; 1854 break; 1855 case RADEON_PP_TXFORMAT_0: 1856 case RADEON_PP_TXFORMAT_1: 1857 case RADEON_PP_TXFORMAT_2: 1858 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1859 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1860 track->textures[i].use_pitch = true; 1861 } else { 1862 track->textures[i].use_pitch = false; 1863 track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT); 1864 track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT); 1865 } 1866 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1867 track->textures[i].tex_coord_type = 2; 1868 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1869 case RADEON_TXFORMAT_I8: 1870 case RADEON_TXFORMAT_RGB332: 1871 case RADEON_TXFORMAT_Y8: 1872 track->textures[i].cpp = 1; 1873 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1874 break; 1875 case RADEON_TXFORMAT_AI88: 1876 case RADEON_TXFORMAT_ARGB1555: 1877 case RADEON_TXFORMAT_RGB565: 1878 case RADEON_TXFORMAT_ARGB4444: 1879 case RADEON_TXFORMAT_VYUY422: 1880 case RADEON_TXFORMAT_YVYU422: 1881 case RADEON_TXFORMAT_SHADOW16: 1882 case RADEON_TXFORMAT_LDUDV655: 1883 case RADEON_TXFORMAT_DUDV88: 1884 track->textures[i].cpp = 2; 1885 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1886 break; 1887 case RADEON_TXFORMAT_ARGB8888: 1888 case RADEON_TXFORMAT_RGBA8888: 1889 case RADEON_TXFORMAT_SHADOW32: 1890 case RADEON_TXFORMAT_LDUDUV8888: 1891 track->textures[i].cpp = 4; 1892 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1893 break; 1894 case RADEON_TXFORMAT_DXT1: 1895 track->textures[i].cpp = 1; 1896 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1897 break; 1898 case RADEON_TXFORMAT_DXT23: 1899 case RADEON_TXFORMAT_DXT45: 1900 track->textures[i].cpp = 1; 1901 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1902 break; 1903 } 1904 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1905 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1906 track->tex_dirty = true; 1907 break; 1908 case RADEON_PP_CUBIC_FACES_0: 1909 case RADEON_PP_CUBIC_FACES_1: 1910 case RADEON_PP_CUBIC_FACES_2: 1911 tmp = idx_value; 1912 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1913 for (face = 0; face < 4; face++) { 1914 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1915 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1916 } 1917 track->tex_dirty = true; 1918 break; 1919 default: 1920 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); 1921 return -EINVAL; 1922 } 1923 return 0; 1924 } 1925 1926 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1927 struct radeon_cs_packet *pkt, 1928 struct radeon_bo *robj) 1929 { 1930 unsigned idx; 1931 u32 value; 1932 idx = pkt->idx + 1; 1933 value = radeon_get_ib_value(p, idx + 2); 1934 if ((value + 1) > radeon_bo_size(robj)) { 1935 dev_warn_once(p->dev, "[drm] Buffer too small for PACKET3 INDX_BUFFER " 1936 "(need %u have %lu) !\n", 1937 value + 1, 1938 radeon_bo_size(robj)); 1939 return -EINVAL; 1940 } 1941 return 0; 1942 } 1943 1944 static int r100_packet3_check(struct radeon_cs_parser *p, 1945 struct radeon_cs_packet *pkt) 1946 { 1947 struct radeon_bo_list *reloc; 1948 struct r100_cs_track *track; 1949 unsigned idx; 1950 volatile uint32_t *ib; 1951 int r; 1952 1953 ib = p->ib.ptr; 1954 idx = pkt->idx + 1; 1955 track = (struct r100_cs_track *)p->track; 1956 switch (pkt->opcode) { 1957 case PACKET3_3D_LOAD_VBPNTR: 1958 r = r100_packet3_load_vbpntr(p, pkt, idx); 1959 if (r) 1960 return r; 1961 break; 1962 case PACKET3_INDX_BUFFER: 1963 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1964 if (r) { 1965 dev_warn_once(p->dev, "No reloc for packet3 %d\n", pkt->opcode); 1966 radeon_cs_dump_packet(p, pkt); 1967 return r; 1968 } 1969 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); 1970 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1971 if (r) { 1972 return r; 1973 } 1974 break; 1975 case 0x23: 1976 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1977 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1978 if (r) { 1979 dev_warn_once(p->dev, "No reloc for packet3 %d\n", pkt->opcode); 1980 radeon_cs_dump_packet(p, pkt); 1981 return r; 1982 } 1983 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); 1984 track->num_arrays = 1; 1985 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1986 1987 track->arrays[0].robj = reloc->robj; 1988 track->arrays[0].esize = track->vtx_size; 1989 1990 track->max_indx = radeon_get_ib_value(p, idx+1); 1991 1992 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1993 track->immd_dwords = pkt->count - 1; 1994 r = r100_cs_track_check(p->rdev, track); 1995 if (r) 1996 return r; 1997 break; 1998 case PACKET3_3D_DRAW_IMMD: 1999 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 2000 dev_warn_once(p->dev, "PRIM_WALK must be 3 for IMMD draw\n"); 2001 return -EINVAL; 2002 } 2003 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 2004 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2005 track->immd_dwords = pkt->count - 1; 2006 r = r100_cs_track_check(p->rdev, track); 2007 if (r) 2008 return r; 2009 break; 2010 /* triggers drawing using in-packet vertex data */ 2011 case PACKET3_3D_DRAW_IMMD_2: 2012 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 2013 dev_warn_once(p->dev, "PRIM_WALK must be 3 for IMMD draw\n"); 2014 return -EINVAL; 2015 } 2016 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2017 track->immd_dwords = pkt->count; 2018 r = r100_cs_track_check(p->rdev, track); 2019 if (r) 2020 return r; 2021 break; 2022 /* triggers drawing using in-packet vertex data */ 2023 case PACKET3_3D_DRAW_VBUF_2: 2024 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2025 r = r100_cs_track_check(p->rdev, track); 2026 if (r) 2027 return r; 2028 break; 2029 /* triggers drawing of vertex buffers setup elsewhere */ 2030 case PACKET3_3D_DRAW_INDX_2: 2031 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2032 r = r100_cs_track_check(p->rdev, track); 2033 if (r) 2034 return r; 2035 break; 2036 /* triggers drawing using indices to vertex buffer */ 2037 case PACKET3_3D_DRAW_VBUF: 2038 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2039 r = r100_cs_track_check(p->rdev, track); 2040 if (r) 2041 return r; 2042 break; 2043 /* triggers drawing of vertex buffers setup elsewhere */ 2044 case PACKET3_3D_DRAW_INDX: 2045 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2046 r = r100_cs_track_check(p->rdev, track); 2047 if (r) 2048 return r; 2049 break; 2050 /* triggers drawing using indices to vertex buffer */ 2051 case PACKET3_3D_CLEAR_HIZ: 2052 case PACKET3_3D_CLEAR_ZMASK: 2053 if (p->rdev->hyperz_filp != p->filp) 2054 return -EINVAL; 2055 break; 2056 case PACKET3_NOP: 2057 break; 2058 default: 2059 dev_warn_once(p->dev, "Packet3 opcode %x not supported\n", pkt->opcode); 2060 return -EINVAL; 2061 } 2062 return 0; 2063 } 2064 2065 int r100_cs_parse(struct radeon_cs_parser *p) 2066 { 2067 struct radeon_cs_packet pkt; 2068 struct r100_cs_track *track; 2069 int r; 2070 2071 track = kzalloc_obj(*track); 2072 if (!track) 2073 return -ENOMEM; 2074 r100_cs_track_clear(p->rdev, track); 2075 p->track = track; 2076 do { 2077 r = radeon_cs_packet_parse(p, &pkt, p->idx); 2078 if (r) { 2079 return r; 2080 } 2081 p->idx += pkt.count + 2; 2082 switch (pkt.type) { 2083 case RADEON_PACKET_TYPE0: 2084 if (p->rdev->family >= CHIP_R200) 2085 r = r100_cs_parse_packet0(p, &pkt, 2086 p->rdev->config.r100.reg_safe_bm, 2087 p->rdev->config.r100.reg_safe_bm_size, 2088 &r200_packet0_check); 2089 else 2090 r = r100_cs_parse_packet0(p, &pkt, 2091 p->rdev->config.r100.reg_safe_bm, 2092 p->rdev->config.r100.reg_safe_bm_size, 2093 &r100_packet0_check); 2094 break; 2095 case RADEON_PACKET_TYPE2: 2096 break; 2097 case RADEON_PACKET_TYPE3: 2098 r = r100_packet3_check(p, &pkt); 2099 break; 2100 default: 2101 dev_warn_once(p->dev, "Unknown packet type %d !\n", 2102 pkt.type); 2103 return -EINVAL; 2104 } 2105 if (r) 2106 return r; 2107 } while (p->idx < p->chunk_ib->length_dw); 2108 return 0; 2109 } 2110 2111 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2112 { 2113 DRM_DEBUG("pitch %d\n", t->pitch); 2114 DRM_DEBUG("use_pitch %d\n", t->use_pitch); 2115 DRM_DEBUG("width %d\n", t->width); 2116 DRM_DEBUG("width_11 %d\n", t->width_11); 2117 DRM_DEBUG("height %d\n", t->height); 2118 DRM_DEBUG("height_11 %d\n", t->height_11); 2119 DRM_DEBUG("num levels %d\n", t->num_levels); 2120 DRM_DEBUG("depth %d\n", t->txdepth); 2121 DRM_DEBUG("bpp %d\n", t->cpp); 2122 DRM_DEBUG("coordinate type %d\n", t->tex_coord_type); 2123 DRM_DEBUG("width round to power of 2 %d\n", t->roundup_w); 2124 DRM_DEBUG("height round to power of 2 %d\n", t->roundup_h); 2125 DRM_DEBUG("compress format %d\n", t->compress_format); 2126 } 2127 2128 static int r100_track_compress_size(int compress_format, int w, int h) 2129 { 2130 int block_width, block_height, block_bytes; 2131 int wblocks, hblocks; 2132 int min_wblocks; 2133 int sz; 2134 2135 block_width = 4; 2136 block_height = 4; 2137 2138 switch (compress_format) { 2139 case R100_TRACK_COMP_DXT1: 2140 block_bytes = 8; 2141 min_wblocks = 4; 2142 break; 2143 default: 2144 case R100_TRACK_COMP_DXT35: 2145 block_bytes = 16; 2146 min_wblocks = 2; 2147 break; 2148 } 2149 2150 hblocks = (h + block_height - 1) / block_height; 2151 wblocks = (w + block_width - 1) / block_width; 2152 if (wblocks < min_wblocks) 2153 wblocks = min_wblocks; 2154 sz = wblocks * hblocks * block_bytes; 2155 return sz; 2156 } 2157 2158 static int r100_cs_track_cube(struct radeon_device *rdev, 2159 struct r100_cs_track *track, unsigned idx) 2160 { 2161 unsigned face, w, h; 2162 struct radeon_bo *cube_robj; 2163 unsigned long size; 2164 unsigned compress_format = track->textures[idx].compress_format; 2165 2166 for (face = 0; face < 5; face++) { 2167 cube_robj = track->textures[idx].cube_info[face].robj; 2168 w = track->textures[idx].cube_info[face].width; 2169 h = track->textures[idx].cube_info[face].height; 2170 2171 if (compress_format) { 2172 size = r100_track_compress_size(compress_format, w, h); 2173 } else 2174 size = w * h; 2175 size *= track->textures[idx].cpp; 2176 2177 size += track->textures[idx].cube_info[face].offset; 2178 2179 if (size > radeon_bo_size(cube_robj)) { 2180 dev_warn_once(rdev->dev, 2181 "Cube texture offset greater than object size %lu %lu\n", 2182 size, radeon_bo_size(cube_robj)); 2183 r100_cs_track_texture_print(&track->textures[idx]); 2184 return -1; 2185 } 2186 } 2187 return 0; 2188 } 2189 2190 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2191 struct r100_cs_track *track) 2192 { 2193 struct radeon_bo *robj; 2194 unsigned long size; 2195 unsigned u, i, w, h, d; 2196 int ret; 2197 2198 for (u = 0; u < track->num_texture; u++) { 2199 if (!track->textures[u].enabled) 2200 continue; 2201 if (track->textures[u].lookup_disable) 2202 continue; 2203 robj = track->textures[u].robj; 2204 if (robj == NULL) { 2205 dev_warn_once(rdev->dev, "No texture bound to unit %u\n", u); 2206 return -EINVAL; 2207 } 2208 size = 0; 2209 for (i = 0; i <= track->textures[u].num_levels; i++) { 2210 if (track->textures[u].use_pitch) { 2211 if (rdev->family < CHIP_R300) 2212 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2213 else 2214 w = track->textures[u].pitch / (1 << i); 2215 } else { 2216 w = track->textures[u].width; 2217 if (rdev->family >= CHIP_RV515) 2218 w |= track->textures[u].width_11; 2219 w = w / (1 << i); 2220 if (track->textures[u].roundup_w) 2221 w = roundup_pow_of_two(w); 2222 } 2223 h = track->textures[u].height; 2224 if (rdev->family >= CHIP_RV515) 2225 h |= track->textures[u].height_11; 2226 h = h / (1 << i); 2227 if (track->textures[u].roundup_h) 2228 h = roundup_pow_of_two(h); 2229 if (track->textures[u].tex_coord_type == 1) { 2230 d = (1 << track->textures[u].txdepth) / (1 << i); 2231 if (!d) 2232 d = 1; 2233 } else { 2234 d = 1; 2235 } 2236 if (track->textures[u].compress_format) { 2237 2238 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2239 /* compressed textures are block based */ 2240 } else 2241 size += w * h * d; 2242 } 2243 size *= track->textures[u].cpp; 2244 2245 switch (track->textures[u].tex_coord_type) { 2246 case 0: 2247 case 1: 2248 break; 2249 case 2: 2250 if (track->separate_cube) { 2251 ret = r100_cs_track_cube(rdev, track, u); 2252 if (ret) 2253 return ret; 2254 } else 2255 size *= 6; 2256 break; 2257 default: 2258 dev_warn_once(rdev->dev, "Invalid texture coordinate type %u for unit " 2259 "%u\n", track->textures[u].tex_coord_type, u); 2260 return -EINVAL; 2261 } 2262 if (size > radeon_bo_size(robj)) { 2263 dev_warn_once(rdev->dev, "Texture of unit %u needs %lu bytes but is " 2264 "%lu\n", u, size, radeon_bo_size(robj)); 2265 r100_cs_track_texture_print(&track->textures[u]); 2266 return -EINVAL; 2267 } 2268 } 2269 return 0; 2270 } 2271 2272 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2273 { 2274 unsigned i; 2275 unsigned long size; 2276 unsigned prim_walk; 2277 unsigned nverts; 2278 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2279 2280 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2281 !track->blend_read_enable) 2282 num_cb = 0; 2283 2284 for (i = 0; i < num_cb; i++) { 2285 if (track->cb[i].robj == NULL) { 2286 dev_warn_once(rdev->dev, "[drm] No buffer for color buffer %d !\n", i); 2287 return -EINVAL; 2288 } 2289 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2290 size += track->cb[i].offset; 2291 if (size > radeon_bo_size(track->cb[i].robj)) { 2292 dev_warn_once(rdev->dev, "[drm] Buffer too small for color buffer %d " 2293 "(need %lu have %lu) !\n", i, size, 2294 radeon_bo_size(track->cb[i].robj)); 2295 dev_warn_once(rdev->dev, "[drm] color buffer %d (%u %u %u %u)\n", 2296 i, track->cb[i].pitch, track->cb[i].cpp, 2297 track->cb[i].offset, track->maxy); 2298 return -EINVAL; 2299 } 2300 } 2301 track->cb_dirty = false; 2302 2303 if (track->zb_dirty && track->z_enabled) { 2304 if (track->zb.robj == NULL) { 2305 dev_warn_once(rdev->dev, "[drm] No buffer for z buffer !\n"); 2306 return -EINVAL; 2307 } 2308 size = track->zb.pitch * track->zb.cpp * track->maxy; 2309 size += track->zb.offset; 2310 if (size > radeon_bo_size(track->zb.robj)) { 2311 dev_warn_once(rdev->dev, "[drm] Buffer too small for z buffer " 2312 "(need %lu have %lu) !\n", size, 2313 radeon_bo_size(track->zb.robj)); 2314 dev_warn_once(rdev->dev, "[drm] zbuffer (%u %u %u %u)\n", 2315 track->zb.pitch, track->zb.cpp, 2316 track->zb.offset, track->maxy); 2317 return -EINVAL; 2318 } 2319 } 2320 track->zb_dirty = false; 2321 2322 if (track->aa_dirty && track->aaresolve) { 2323 if (track->aa.robj == NULL) { 2324 dev_warn_once(rdev->dev, "[drm] No buffer for AA resolve buffer %d !\n", i); 2325 return -EINVAL; 2326 } 2327 /* I believe the format comes from colorbuffer0. */ 2328 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2329 size += track->aa.offset; 2330 if (size > radeon_bo_size(track->aa.robj)) { 2331 dev_warn_once(rdev->dev, "[drm] Buffer too small for AA resolve buffer %d " 2332 "(need %lu have %lu) !\n", i, size, 2333 radeon_bo_size(track->aa.robj)); 2334 dev_warn_once(rdev->dev, "[drm] AA resolve buffer %d (%u %u %u %u)\n", 2335 i, track->aa.pitch, track->cb[0].cpp, 2336 track->aa.offset, track->maxy); 2337 return -EINVAL; 2338 } 2339 } 2340 track->aa_dirty = false; 2341 2342 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2343 if (track->vap_vf_cntl & (1 << 14)) { 2344 nverts = track->vap_alt_nverts; 2345 } else { 2346 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2347 } 2348 switch (prim_walk) { 2349 case 1: 2350 for (i = 0; i < track->num_arrays; i++) { 2351 size = track->arrays[i].esize * track->max_indx * 4UL; 2352 if (track->arrays[i].robj == NULL) { 2353 dev_warn_once(rdev->dev, "(PW %u) Vertex array %u no buffer " 2354 "bound\n", prim_walk, i); 2355 return -EINVAL; 2356 } 2357 if (size > radeon_bo_size(track->arrays[i].robj)) { 2358 dev_warn_once(rdev->dev, "(PW %u) Vertex array %u " 2359 "need %lu dwords have %lu dwords\n", 2360 prim_walk, i, size >> 2, 2361 radeon_bo_size(track->arrays[i].robj) 2362 >> 2); 2363 dev_warn_once(rdev->dev, "Max indices %u\n", track->max_indx); 2364 return -EINVAL; 2365 } 2366 } 2367 break; 2368 case 2: 2369 for (i = 0; i < track->num_arrays; i++) { 2370 size = track->arrays[i].esize * (nverts - 1) * 4UL; 2371 if (track->arrays[i].robj == NULL) { 2372 dev_warn_once(rdev->dev, "(PW %u) Vertex array %u no buffer " 2373 "bound\n", prim_walk, i); 2374 return -EINVAL; 2375 } 2376 if (size > radeon_bo_size(track->arrays[i].robj)) { 2377 dev_warn_once(rdev->dev, "(PW %u) Vertex array %u " 2378 "need %lu dwords have %lu dwords\n", 2379 prim_walk, i, size >> 2, 2380 radeon_bo_size(track->arrays[i].robj) 2381 >> 2); 2382 return -EINVAL; 2383 } 2384 } 2385 break; 2386 case 3: 2387 size = track->vtx_size * nverts; 2388 if (size != track->immd_dwords) { 2389 dev_warn_once(rdev->dev, "IMMD draw %u dwors but needs %lu dwords\n", 2390 track->immd_dwords, size); 2391 dev_warn_once(rdev->dev, "VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2392 nverts, track->vtx_size); 2393 return -EINVAL; 2394 } 2395 break; 2396 default: 2397 dev_warn_once(rdev->dev, "[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2398 prim_walk); 2399 return -EINVAL; 2400 } 2401 2402 if (track->tex_dirty) { 2403 track->tex_dirty = false; 2404 return r100_cs_track_texture_check(rdev, track); 2405 } 2406 return 0; 2407 } 2408 2409 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2410 { 2411 unsigned i, face; 2412 2413 track->cb_dirty = true; 2414 track->zb_dirty = true; 2415 track->tex_dirty = true; 2416 track->aa_dirty = true; 2417 2418 if (rdev->family < CHIP_R300) { 2419 track->num_cb = 1; 2420 if (rdev->family <= CHIP_RS200) 2421 track->num_texture = 3; 2422 else 2423 track->num_texture = 6; 2424 track->maxy = 2048; 2425 track->separate_cube = true; 2426 } else { 2427 track->num_cb = 4; 2428 track->num_texture = 16; 2429 track->maxy = 4096; 2430 track->separate_cube = false; 2431 track->aaresolve = false; 2432 track->aa.robj = NULL; 2433 } 2434 2435 for (i = 0; i < track->num_cb; i++) { 2436 track->cb[i].robj = NULL; 2437 track->cb[i].pitch = 8192; 2438 track->cb[i].cpp = 16; 2439 track->cb[i].offset = 0; 2440 } 2441 track->z_enabled = true; 2442 track->zb.robj = NULL; 2443 track->zb.pitch = 8192; 2444 track->zb.cpp = 4; 2445 track->zb.offset = 0; 2446 track->vtx_size = 0x7F; 2447 track->immd_dwords = 0xFFFFFFFFUL; 2448 track->num_arrays = 11; 2449 track->max_indx = 0x00FFFFFFUL; 2450 for (i = 0; i < track->num_arrays; i++) { 2451 track->arrays[i].robj = NULL; 2452 track->arrays[i].esize = 0x7F; 2453 } 2454 for (i = 0; i < track->num_texture; i++) { 2455 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2456 track->textures[i].pitch = 16536; 2457 track->textures[i].width = 16536; 2458 track->textures[i].height = 16536; 2459 track->textures[i].width_11 = 1 << 11; 2460 track->textures[i].height_11 = 1 << 11; 2461 track->textures[i].num_levels = 12; 2462 if (rdev->family <= CHIP_RS200) { 2463 track->textures[i].tex_coord_type = 0; 2464 track->textures[i].txdepth = 0; 2465 } else { 2466 track->textures[i].txdepth = 16; 2467 track->textures[i].tex_coord_type = 1; 2468 } 2469 track->textures[i].cpp = 64; 2470 track->textures[i].robj = NULL; 2471 /* CS IB emission code makes sure texture unit are disabled */ 2472 track->textures[i].enabled = false; 2473 track->textures[i].lookup_disable = false; 2474 track->textures[i].roundup_w = true; 2475 track->textures[i].roundup_h = true; 2476 if (track->separate_cube) 2477 for (face = 0; face < 5; face++) { 2478 track->textures[i].cube_info[face].robj = NULL; 2479 track->textures[i].cube_info[face].width = 16536; 2480 track->textures[i].cube_info[face].height = 16536; 2481 track->textures[i].cube_info[face].offset = 0; 2482 } 2483 } 2484 } 2485 2486 /* 2487 * Global GPU functions 2488 */ 2489 static void r100_errata(struct radeon_device *rdev) 2490 { 2491 rdev->pll_errata = 0; 2492 2493 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2494 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2495 } 2496 2497 if (rdev->family == CHIP_RV100 || 2498 rdev->family == CHIP_RS100 || 2499 rdev->family == CHIP_RS200) { 2500 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2501 } 2502 } 2503 2504 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2505 { 2506 unsigned i; 2507 uint32_t tmp; 2508 2509 for (i = 0; i < rdev->usec_timeout; i++) { 2510 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2511 if (tmp >= n) { 2512 return 0; 2513 } 2514 udelay(1); 2515 } 2516 return -1; 2517 } 2518 2519 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2520 { 2521 unsigned i; 2522 uint32_t tmp; 2523 2524 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2525 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n"); 2526 } 2527 for (i = 0; i < rdev->usec_timeout; i++) { 2528 tmp = RREG32(RADEON_RBBM_STATUS); 2529 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2530 return 0; 2531 } 2532 udelay(1); 2533 } 2534 return -1; 2535 } 2536 2537 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2538 { 2539 unsigned i; 2540 uint32_t tmp; 2541 2542 for (i = 0; i < rdev->usec_timeout; i++) { 2543 /* read MC_STATUS */ 2544 tmp = RREG32(RADEON_MC_STATUS); 2545 if (tmp & RADEON_MC_IDLE) { 2546 return 0; 2547 } 2548 udelay(1); 2549 } 2550 return -1; 2551 } 2552 2553 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2554 { 2555 u32 rbbm_status; 2556 2557 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2558 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2559 radeon_ring_lockup_update(rdev, ring); 2560 return false; 2561 } 2562 return radeon_ring_test_lockup(rdev, ring); 2563 } 2564 2565 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2566 void r100_enable_bm(struct radeon_device *rdev) 2567 { 2568 uint32_t tmp; 2569 /* Enable bus mastering */ 2570 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2571 WREG32(RADEON_BUS_CNTL, tmp); 2572 } 2573 2574 void r100_bm_disable(struct radeon_device *rdev) 2575 { 2576 u32 tmp; 2577 2578 /* disable bus mastering */ 2579 tmp = RREG32(R_000030_BUS_CNTL); 2580 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2581 mdelay(1); 2582 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2583 mdelay(1); 2584 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2585 tmp = RREG32(RADEON_BUS_CNTL); 2586 mdelay(1); 2587 pci_clear_master(rdev->pdev); 2588 mdelay(1); 2589 } 2590 2591 int r100_asic_reset(struct radeon_device *rdev, bool hard) 2592 { 2593 struct r100_mc_save save; 2594 u32 status, tmp; 2595 int ret = 0; 2596 2597 status = RREG32(R_000E40_RBBM_STATUS); 2598 if (!G_000E40_GUI_ACTIVE(status)) { 2599 return 0; 2600 } 2601 r100_mc_stop(rdev, &save); 2602 status = RREG32(R_000E40_RBBM_STATUS); 2603 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2604 /* stop CP */ 2605 WREG32(RADEON_CP_CSQ_CNTL, 0); 2606 tmp = RREG32(RADEON_CP_RB_CNTL); 2607 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2608 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2609 WREG32(RADEON_CP_RB_WPTR, 0); 2610 WREG32(RADEON_CP_RB_CNTL, tmp); 2611 /* save PCI state */ 2612 pci_save_state(rdev->pdev); 2613 /* disable bus mastering */ 2614 r100_bm_disable(rdev); 2615 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2616 S_0000F0_SOFT_RESET_RE(1) | 2617 S_0000F0_SOFT_RESET_PP(1) | 2618 S_0000F0_SOFT_RESET_RB(1)); 2619 RREG32(R_0000F0_RBBM_SOFT_RESET); 2620 mdelay(500); 2621 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2622 mdelay(1); 2623 status = RREG32(R_000E40_RBBM_STATUS); 2624 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2625 /* reset CP */ 2626 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2627 RREG32(R_0000F0_RBBM_SOFT_RESET); 2628 mdelay(500); 2629 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2630 mdelay(1); 2631 status = RREG32(R_000E40_RBBM_STATUS); 2632 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2633 /* restore PCI & busmastering */ 2634 pci_restore_state(rdev->pdev); 2635 r100_enable_bm(rdev); 2636 /* Check if GPU is idle */ 2637 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2638 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2639 dev_err(rdev->dev, "failed to reset GPU\n"); 2640 ret = -1; 2641 } else 2642 dev_info(rdev->dev, "GPU reset succeed\n"); 2643 r100_mc_resume(rdev, &save); 2644 return ret; 2645 } 2646 2647 void r100_set_common_regs(struct radeon_device *rdev) 2648 { 2649 bool force_dac2 = false; 2650 u32 tmp; 2651 2652 /* set these so they don't interfere with anything */ 2653 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2654 WREG32(RADEON_SUBPIC_CNTL, 0); 2655 WREG32(RADEON_VIPH_CONTROL, 0); 2656 WREG32(RADEON_I2C_CNTL_1, 0); 2657 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2658 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2659 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2660 2661 /* always set up dac2 on rn50 and some rv100 as lots 2662 * of servers seem to wire it up to a VGA port but 2663 * don't report it in the bios connector 2664 * table. 2665 */ 2666 switch (rdev->pdev->device) { 2667 /* RN50 */ 2668 case 0x515e: 2669 case 0x5969: 2670 force_dac2 = true; 2671 break; 2672 /* RV100*/ 2673 case 0x5159: 2674 case 0x515a: 2675 /* DELL triple head servers */ 2676 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2677 ((rdev->pdev->subsystem_device == 0x016c) || 2678 (rdev->pdev->subsystem_device == 0x016d) || 2679 (rdev->pdev->subsystem_device == 0x016e) || 2680 (rdev->pdev->subsystem_device == 0x016f) || 2681 (rdev->pdev->subsystem_device == 0x0170) || 2682 (rdev->pdev->subsystem_device == 0x017d) || 2683 (rdev->pdev->subsystem_device == 0x017e) || 2684 (rdev->pdev->subsystem_device == 0x0183) || 2685 (rdev->pdev->subsystem_device == 0x018a) || 2686 (rdev->pdev->subsystem_device == 0x019a))) 2687 force_dac2 = true; 2688 break; 2689 } 2690 2691 if (force_dac2) { 2692 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2693 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2694 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2695 2696 /* For CRT on DAC2, don't turn it on if BIOS didn't 2697 enable it, even it's detected. 2698 */ 2699 2700 /* force it to crtc0 */ 2701 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2702 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2703 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2704 2705 /* set up the TV DAC */ 2706 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2707 RADEON_TV_DAC_STD_MASK | 2708 RADEON_TV_DAC_RDACPD | 2709 RADEON_TV_DAC_GDACPD | 2710 RADEON_TV_DAC_BDACPD | 2711 RADEON_TV_DAC_BGADJ_MASK | 2712 RADEON_TV_DAC_DACADJ_MASK); 2713 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2714 RADEON_TV_DAC_NHOLD | 2715 RADEON_TV_DAC_STD_PS2 | 2716 (0x58 << 16)); 2717 2718 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2719 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2720 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2721 } 2722 2723 /* switch PM block to ACPI mode */ 2724 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2725 tmp &= ~RADEON_PM_MODE_SEL; 2726 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2727 2728 } 2729 2730 /* 2731 * VRAM info 2732 */ 2733 static void r100_vram_get_type(struct radeon_device *rdev) 2734 { 2735 uint32_t tmp; 2736 2737 rdev->mc.vram_is_ddr = false; 2738 if (rdev->flags & RADEON_IS_IGP) 2739 rdev->mc.vram_is_ddr = true; 2740 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2741 rdev->mc.vram_is_ddr = true; 2742 if ((rdev->family == CHIP_RV100) || 2743 (rdev->family == CHIP_RS100) || 2744 (rdev->family == CHIP_RS200)) { 2745 tmp = RREG32(RADEON_MEM_CNTL); 2746 if (tmp & RV100_HALF_MODE) { 2747 rdev->mc.vram_width = 32; 2748 } else { 2749 rdev->mc.vram_width = 64; 2750 } 2751 if (rdev->flags & RADEON_SINGLE_CRTC) { 2752 rdev->mc.vram_width /= 4; 2753 rdev->mc.vram_is_ddr = true; 2754 } 2755 } else if (rdev->family <= CHIP_RV280) { 2756 tmp = RREG32(RADEON_MEM_CNTL); 2757 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2758 rdev->mc.vram_width = 128; 2759 } else { 2760 rdev->mc.vram_width = 64; 2761 } 2762 } else { 2763 /* newer IGPs */ 2764 rdev->mc.vram_width = 128; 2765 } 2766 } 2767 2768 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2769 { 2770 u32 aper_size; 2771 u8 byte; 2772 2773 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2774 2775 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2776 * that is has the 2nd generation multifunction PCI interface 2777 */ 2778 if (rdev->family == CHIP_RV280 || 2779 rdev->family >= CHIP_RV350) { 2780 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2781 ~RADEON_HDP_APER_CNTL); 2782 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2783 return aper_size * 2; 2784 } 2785 2786 /* Older cards have all sorts of funny issues to deal with. First 2787 * check if it's a multifunction card by reading the PCI config 2788 * header type... Limit those to one aperture size 2789 */ 2790 pci_read_config_byte(rdev->pdev, 0xe, &byte); 2791 if (byte & 0x80) { 2792 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2793 DRM_INFO("Limiting VRAM to one aperture\n"); 2794 return aper_size; 2795 } 2796 2797 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2798 * have set it up. We don't write this as it's broken on some ASICs but 2799 * we expect the BIOS to have done the right thing (might be too optimistic...) 2800 */ 2801 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2802 return aper_size * 2; 2803 return aper_size; 2804 } 2805 2806 void r100_vram_init_sizes(struct radeon_device *rdev) 2807 { 2808 u64 config_aper_size; 2809 2810 /* work out accessible VRAM */ 2811 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2812 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2813 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2814 /* FIXME we don't use the second aperture yet when we could use it */ 2815 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2816 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2817 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2818 if (rdev->flags & RADEON_IS_IGP) { 2819 uint32_t tom; 2820 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2821 tom = RREG32(RADEON_NB_TOM); 2822 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2823 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2824 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2825 } else { 2826 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2827 /* Some production boards of m6 will report 0 2828 * if it's 8 MB 2829 */ 2830 if (rdev->mc.real_vram_size == 0) { 2831 rdev->mc.real_vram_size = 8192 * 1024; 2832 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2833 } 2834 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2835 * Novell bug 204882 + along with lots of ubuntu ones 2836 */ 2837 if (rdev->mc.aper_size > config_aper_size) 2838 config_aper_size = rdev->mc.aper_size; 2839 2840 if (config_aper_size > rdev->mc.real_vram_size) 2841 rdev->mc.mc_vram_size = config_aper_size; 2842 else 2843 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2844 } 2845 } 2846 2847 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2848 { 2849 uint32_t temp; 2850 2851 temp = RREG32(RADEON_CONFIG_CNTL); 2852 if (!state) { 2853 temp &= ~RADEON_CFG_VGA_RAM_EN; 2854 temp |= RADEON_CFG_VGA_IO_DIS; 2855 } else { 2856 temp &= ~RADEON_CFG_VGA_IO_DIS; 2857 } 2858 WREG32(RADEON_CONFIG_CNTL, temp); 2859 } 2860 2861 static void r100_mc_init(struct radeon_device *rdev) 2862 { 2863 u64 base; 2864 2865 r100_vram_get_type(rdev); 2866 r100_vram_init_sizes(rdev); 2867 base = rdev->mc.aper_base; 2868 if (rdev->flags & RADEON_IS_IGP) 2869 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2870 radeon_vram_location(rdev, &rdev->mc, base); 2871 rdev->mc.gtt_base_align = 0; 2872 if (!(rdev->flags & RADEON_IS_AGP)) 2873 radeon_gtt_location(rdev, &rdev->mc); 2874 radeon_update_bandwidth_info(rdev); 2875 } 2876 2877 2878 /* 2879 * Indirect registers accessor 2880 */ 2881 void r100_pll_errata_after_index(struct radeon_device *rdev) 2882 { 2883 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2884 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2885 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2886 } 2887 } 2888 2889 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2890 { 2891 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2892 * or the chip could hang on a subsequent access 2893 */ 2894 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2895 mdelay(5); 2896 } 2897 2898 /* This function is required to workaround a hardware bug in some (all?) 2899 * revisions of the R300. This workaround should be called after every 2900 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2901 * may not be correct. 2902 */ 2903 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2904 uint32_t save, tmp; 2905 2906 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2907 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2908 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2909 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2910 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2911 } 2912 } 2913 2914 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2915 { 2916 unsigned long flags; 2917 uint32_t data; 2918 2919 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2920 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2921 r100_pll_errata_after_index(rdev); 2922 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2923 r100_pll_errata_after_data(rdev); 2924 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2925 return data; 2926 } 2927 2928 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2929 { 2930 unsigned long flags; 2931 2932 spin_lock_irqsave(&rdev->pll_idx_lock, flags); 2933 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2934 r100_pll_errata_after_index(rdev); 2935 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2936 r100_pll_errata_after_data(rdev); 2937 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); 2938 } 2939 2940 static void r100_set_safe_registers(struct radeon_device *rdev) 2941 { 2942 if (ASIC_IS_RN50(rdev)) { 2943 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2944 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2945 } else if (rdev->family < CHIP_R200) { 2946 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2947 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2948 } else { 2949 r200_set_safe_registers(rdev); 2950 } 2951 } 2952 2953 /* 2954 * Debugfs info 2955 */ 2956 #if defined(CONFIG_DEBUG_FS) 2957 static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused) 2958 { 2959 struct radeon_device *rdev = m->private; 2960 uint32_t reg, value; 2961 unsigned i; 2962 2963 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2964 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2965 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2966 for (i = 0; i < 64; i++) { 2967 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2968 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2969 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2970 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2971 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2972 } 2973 return 0; 2974 } 2975 2976 static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused) 2977 { 2978 struct radeon_device *rdev = m->private; 2979 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2980 uint32_t rdp, wdp; 2981 unsigned count, i, j; 2982 2983 radeon_ring_free_size(rdev, ring); 2984 rdp = RREG32(RADEON_CP_RB_RPTR); 2985 wdp = RREG32(RADEON_CP_RB_WPTR); 2986 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 2987 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2988 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2989 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2990 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 2991 seq_printf(m, "%u dwords in ring\n", count); 2992 if (ring->ready) { 2993 for (j = 0; j <= count; j++) { 2994 i = (rdp + j) & ring->ptr_mask; 2995 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 2996 } 2997 } 2998 return 0; 2999 } 3000 3001 3002 static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused) 3003 { 3004 struct radeon_device *rdev = m->private; 3005 uint32_t csq_stat, csq2_stat, tmp; 3006 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 3007 unsigned i; 3008 3009 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 3010 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 3011 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 3012 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 3013 r_rptr = (csq_stat >> 0) & 0x3ff; 3014 r_wptr = (csq_stat >> 10) & 0x3ff; 3015 ib1_rptr = (csq_stat >> 20) & 0x3ff; 3016 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 3017 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 3018 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 3019 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 3020 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 3021 seq_printf(m, "Ring rptr %u\n", r_rptr); 3022 seq_printf(m, "Ring wptr %u\n", r_wptr); 3023 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 3024 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 3025 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 3026 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3027 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3028 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3029 seq_printf(m, "Ring fifo:\n"); 3030 for (i = 0; i < 256; i++) { 3031 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3032 tmp = RREG32(RADEON_CP_CSQ_DATA); 3033 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3034 } 3035 seq_printf(m, "Indirect1 fifo:\n"); 3036 for (i = 256; i <= 512; i++) { 3037 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3038 tmp = RREG32(RADEON_CP_CSQ_DATA); 3039 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3040 } 3041 seq_printf(m, "Indirect2 fifo:\n"); 3042 for (i = 640; i < ib1_wptr; i++) { 3043 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3044 tmp = RREG32(RADEON_CP_CSQ_DATA); 3045 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3046 } 3047 return 0; 3048 } 3049 3050 static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused) 3051 { 3052 struct radeon_device *rdev = m->private; 3053 uint32_t tmp; 3054 3055 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3056 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3057 tmp = RREG32(RADEON_MC_FB_LOCATION); 3058 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3059 tmp = RREG32(RADEON_BUS_CNTL); 3060 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3061 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3062 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3063 tmp = RREG32(RADEON_AGP_BASE); 3064 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3065 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3066 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3067 tmp = RREG32(0x01D0); 3068 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3069 tmp = RREG32(RADEON_AIC_LO_ADDR); 3070 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3071 tmp = RREG32(RADEON_AIC_HI_ADDR); 3072 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3073 tmp = RREG32(0x01E4); 3074 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3075 return 0; 3076 } 3077 3078 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info); 3079 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info); 3080 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo); 3081 DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info); 3082 3083 #endif 3084 3085 void r100_debugfs_rbbm_init(struct radeon_device *rdev) 3086 { 3087 #if defined(CONFIG_DEBUG_FS) 3088 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; 3089 3090 debugfs_create_file("r100_rbbm_info", 0444, root, rdev, 3091 &r100_debugfs_rbbm_info_fops); 3092 #endif 3093 } 3094 3095 void r100_debugfs_cp_init(struct radeon_device *rdev) 3096 { 3097 #if defined(CONFIG_DEBUG_FS) 3098 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; 3099 3100 debugfs_create_file("r100_cp_ring_info", 0444, root, rdev, 3101 &r100_debugfs_cp_ring_info_fops); 3102 debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev, 3103 &r100_debugfs_cp_csq_fifo_fops); 3104 #endif 3105 } 3106 3107 void r100_debugfs_mc_info_init(struct radeon_device *rdev) 3108 { 3109 #if defined(CONFIG_DEBUG_FS) 3110 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; 3111 3112 debugfs_create_file("r100_mc_info", 0444, root, rdev, 3113 &r100_debugfs_mc_info_fops); 3114 #endif 3115 } 3116 3117 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3118 uint32_t tiling_flags, uint32_t pitch, 3119 uint32_t offset, uint32_t obj_size) 3120 { 3121 int surf_index = reg * 16; 3122 int flags = 0; 3123 3124 if (rdev->family <= CHIP_RS200) { 3125 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3126 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3127 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3128 if (tiling_flags & RADEON_TILING_MACRO) 3129 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3130 /* setting pitch to 0 disables tiling */ 3131 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3132 == 0) 3133 pitch = 0; 3134 } else if (rdev->family <= CHIP_RV280) { 3135 if (tiling_flags & (RADEON_TILING_MACRO)) 3136 flags |= R200_SURF_TILE_COLOR_MACRO; 3137 if (tiling_flags & RADEON_TILING_MICRO) 3138 flags |= R200_SURF_TILE_COLOR_MICRO; 3139 } else { 3140 if (tiling_flags & RADEON_TILING_MACRO) 3141 flags |= R300_SURF_TILE_MACRO; 3142 if (tiling_flags & RADEON_TILING_MICRO) 3143 flags |= R300_SURF_TILE_MICRO; 3144 } 3145 3146 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3147 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3148 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3149 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3150 3151 /* r100/r200 divide by 16 */ 3152 if (rdev->family < CHIP_R300) 3153 flags |= pitch / 16; 3154 else 3155 flags |= pitch / 8; 3156 3157 3158 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3159 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3160 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3161 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3162 return 0; 3163 } 3164 3165 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3166 { 3167 int surf_index = reg * 16; 3168 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3169 } 3170 3171 void r100_bandwidth_update(struct radeon_device *rdev) 3172 { 3173 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3174 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3175 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; 3176 fixed20_12 crit_point_ff = {0}; 3177 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3178 fixed20_12 memtcas_ff[8] = { 3179 dfixed_init(1), 3180 dfixed_init(2), 3181 dfixed_init(3), 3182 dfixed_init(0), 3183 dfixed_init_half(1), 3184 dfixed_init_half(2), 3185 dfixed_init(0), 3186 }; 3187 fixed20_12 memtcas_rs480_ff[8] = { 3188 dfixed_init(0), 3189 dfixed_init(1), 3190 dfixed_init(2), 3191 dfixed_init(3), 3192 dfixed_init(0), 3193 dfixed_init_half(1), 3194 dfixed_init_half(2), 3195 dfixed_init_half(3), 3196 }; 3197 fixed20_12 memtcas2_ff[8] = { 3198 dfixed_init(0), 3199 dfixed_init(1), 3200 dfixed_init(2), 3201 dfixed_init(3), 3202 dfixed_init(4), 3203 dfixed_init(5), 3204 dfixed_init(6), 3205 dfixed_init(7), 3206 }; 3207 fixed20_12 memtrbs[8] = { 3208 dfixed_init(1), 3209 dfixed_init_half(1), 3210 dfixed_init(2), 3211 dfixed_init_half(2), 3212 dfixed_init(3), 3213 dfixed_init_half(3), 3214 dfixed_init(4), 3215 dfixed_init_half(4) 3216 }; 3217 fixed20_12 memtrbs_r4xx[8] = { 3218 dfixed_init(4), 3219 dfixed_init(5), 3220 dfixed_init(6), 3221 dfixed_init(7), 3222 dfixed_init(8), 3223 dfixed_init(9), 3224 dfixed_init(10), 3225 dfixed_init(11) 3226 }; 3227 fixed20_12 min_mem_eff; 3228 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3229 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3230 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0}, 3231 disp_drain_rate2, read_return_rate; 3232 fixed20_12 time_disp1_drop_priority; 3233 int c; 3234 int cur_size = 16; /* in octawords */ 3235 int critical_point = 0, critical_point2; 3236 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3237 int stop_req, max_stop_req; 3238 struct drm_display_mode *mode1 = NULL; 3239 struct drm_display_mode *mode2 = NULL; 3240 uint32_t pixel_bytes1 = 0; 3241 uint32_t pixel_bytes2 = 0; 3242 3243 /* Guess line buffer size to be 8192 pixels */ 3244 u32 lb_size = 8192; 3245 3246 if (!rdev->mode_info.mode_config_initialized) 3247 return; 3248 3249 radeon_update_display_priority(rdev); 3250 3251 if (rdev->mode_info.crtcs[0]->base.enabled) { 3252 const struct drm_framebuffer *fb = 3253 rdev->mode_info.crtcs[0]->base.primary->fb; 3254 3255 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3256 pixel_bytes1 = fb->format->cpp[0]; 3257 } 3258 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3259 if (rdev->mode_info.crtcs[1]->base.enabled) { 3260 const struct drm_framebuffer *fb = 3261 rdev->mode_info.crtcs[1]->base.primary->fb; 3262 3263 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3264 pixel_bytes2 = fb->format->cpp[0]; 3265 } 3266 } 3267 3268 min_mem_eff.full = dfixed_const_8(0); 3269 /* get modes */ 3270 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3271 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3272 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3273 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3274 /* check crtc enables */ 3275 if (mode2) 3276 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3277 if (mode1) 3278 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3279 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3280 } 3281 3282 /* 3283 * determine is there is enough bw for current mode 3284 */ 3285 sclk_ff = rdev->pm.sclk; 3286 mclk_ff = rdev->pm.mclk; 3287 3288 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3289 temp_ff.full = dfixed_const(temp); 3290 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3291 3292 pix_clk.full = 0; 3293 pix_clk2.full = 0; 3294 peak_disp_bw.full = 0; 3295 if (mode1) { 3296 temp_ff.full = dfixed_const(1000); 3297 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3298 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3299 temp_ff.full = dfixed_const(pixel_bytes1); 3300 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3301 } 3302 if (mode2) { 3303 temp_ff.full = dfixed_const(1000); 3304 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3305 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3306 temp_ff.full = dfixed_const(pixel_bytes2); 3307 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3308 } 3309 3310 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3311 if (peak_disp_bw.full >= mem_bw.full) { 3312 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3313 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3314 } 3315 3316 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3317 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3318 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3319 mem_trcd = ((temp >> 2) & 0x3) + 1; 3320 mem_trp = ((temp & 0x3)) + 1; 3321 mem_tras = ((temp & 0x70) >> 4) + 1; 3322 } else if (rdev->family == CHIP_R300 || 3323 rdev->family == CHIP_R350) { /* r300, r350 */ 3324 mem_trcd = (temp & 0x7) + 1; 3325 mem_trp = ((temp >> 8) & 0x7) + 1; 3326 mem_tras = ((temp >> 11) & 0xf) + 4; 3327 } else if (rdev->family == CHIP_RV350 || 3328 rdev->family == CHIP_RV380) { 3329 /* rv3x0 */ 3330 mem_trcd = (temp & 0x7) + 3; 3331 mem_trp = ((temp >> 8) & 0x7) + 3; 3332 mem_tras = ((temp >> 11) & 0xf) + 6; 3333 } else if (rdev->family == CHIP_R420 || 3334 rdev->family == CHIP_R423 || 3335 rdev->family == CHIP_RV410) { 3336 /* r4xx */ 3337 mem_trcd = (temp & 0xf) + 3; 3338 if (mem_trcd > 15) 3339 mem_trcd = 15; 3340 mem_trp = ((temp >> 8) & 0xf) + 3; 3341 if (mem_trp > 15) 3342 mem_trp = 15; 3343 mem_tras = ((temp >> 12) & 0x1f) + 6; 3344 if (mem_tras > 31) 3345 mem_tras = 31; 3346 } else { /* RV200, R200 */ 3347 mem_trcd = (temp & 0x7) + 1; 3348 mem_trp = ((temp >> 8) & 0x7) + 1; 3349 mem_tras = ((temp >> 12) & 0xf) + 4; 3350 } 3351 /* convert to FF */ 3352 trcd_ff.full = dfixed_const(mem_trcd); 3353 trp_ff.full = dfixed_const(mem_trp); 3354 tras_ff.full = dfixed_const(mem_tras); 3355 3356 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3357 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3358 data = (temp & (7 << 20)) >> 20; 3359 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3360 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3361 tcas_ff = memtcas_rs480_ff[data]; 3362 else 3363 tcas_ff = memtcas_ff[data]; 3364 } else 3365 tcas_ff = memtcas2_ff[data]; 3366 3367 if (rdev->family == CHIP_RS400 || 3368 rdev->family == CHIP_RS480) { 3369 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3370 data = (temp >> 23) & 0x7; 3371 if (data < 5) 3372 tcas_ff.full += dfixed_const(data); 3373 } 3374 3375 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3376 /* on the R300, Tcas is included in Trbs. 3377 */ 3378 temp = RREG32(RADEON_MEM_CNTL); 3379 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3380 if (data == 1) { 3381 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3382 temp = RREG32(R300_MC_IND_INDEX); 3383 temp &= ~R300_MC_IND_ADDR_MASK; 3384 temp |= R300_MC_READ_CNTL_CD_mcind; 3385 WREG32(R300_MC_IND_INDEX, temp); 3386 temp = RREG32(R300_MC_IND_DATA); 3387 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3388 } else { 3389 temp = RREG32(R300_MC_READ_CNTL_AB); 3390 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3391 } 3392 } else { 3393 temp = RREG32(R300_MC_READ_CNTL_AB); 3394 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3395 } 3396 if (rdev->family == CHIP_RV410 || 3397 rdev->family == CHIP_R420 || 3398 rdev->family == CHIP_R423) 3399 trbs_ff = memtrbs_r4xx[data]; 3400 else 3401 trbs_ff = memtrbs[data]; 3402 tcas_ff.full += trbs_ff.full; 3403 } 3404 3405 sclk_eff_ff.full = sclk_ff.full; 3406 3407 if (rdev->flags & RADEON_IS_AGP) { 3408 fixed20_12 agpmode_ff; 3409 agpmode_ff.full = dfixed_const(radeon_agpmode); 3410 temp_ff.full = dfixed_const_666(16); 3411 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3412 } 3413 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3414 3415 if (ASIC_IS_R300(rdev)) { 3416 sclk_delay_ff.full = dfixed_const(250); 3417 } else { 3418 if ((rdev->family == CHIP_RV100) || 3419 rdev->flags & RADEON_IS_IGP) { 3420 if (rdev->mc.vram_is_ddr) 3421 sclk_delay_ff.full = dfixed_const(41); 3422 else 3423 sclk_delay_ff.full = dfixed_const(33); 3424 } else { 3425 if (rdev->mc.vram_width == 128) 3426 sclk_delay_ff.full = dfixed_const(57); 3427 else 3428 sclk_delay_ff.full = dfixed_const(41); 3429 } 3430 } 3431 3432 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3433 3434 if (rdev->mc.vram_is_ddr) { 3435 if (rdev->mc.vram_width == 32) { 3436 k1.full = dfixed_const(40); 3437 c = 3; 3438 } else { 3439 k1.full = dfixed_const(20); 3440 c = 1; 3441 } 3442 } else { 3443 k1.full = dfixed_const(40); 3444 c = 3; 3445 } 3446 3447 temp_ff.full = dfixed_const(2); 3448 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3449 temp_ff.full = dfixed_const(c); 3450 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3451 temp_ff.full = dfixed_const(4); 3452 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3453 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3454 mc_latency_mclk.full += k1.full; 3455 3456 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3457 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3458 3459 /* 3460 HW cursor time assuming worst case of full size colour cursor. 3461 */ 3462 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3463 temp_ff.full += trcd_ff.full; 3464 if (temp_ff.full < tras_ff.full) 3465 temp_ff.full = tras_ff.full; 3466 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3467 3468 temp_ff.full = dfixed_const(cur_size); 3469 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3470 /* 3471 Find the total latency for the display data. 3472 */ 3473 disp_latency_overhead.full = dfixed_const(8); 3474 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3475 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3476 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3477 3478 if (mc_latency_mclk.full > mc_latency_sclk.full) 3479 disp_latency.full = mc_latency_mclk.full; 3480 else 3481 disp_latency.full = mc_latency_sclk.full; 3482 3483 /* setup Max GRPH_STOP_REQ default value */ 3484 if (ASIC_IS_RV100(rdev)) 3485 max_stop_req = 0x5c; 3486 else 3487 max_stop_req = 0x7c; 3488 3489 if (mode1) { 3490 /* CRTC1 3491 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3492 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3493 */ 3494 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3495 3496 if (stop_req > max_stop_req) 3497 stop_req = max_stop_req; 3498 3499 /* 3500 Find the drain rate of the display buffer. 3501 */ 3502 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3503 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3504 3505 /* 3506 Find the critical point of the display buffer. 3507 */ 3508 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3509 crit_point_ff.full += dfixed_const_half(0); 3510 3511 critical_point = dfixed_trunc(crit_point_ff); 3512 3513 if (rdev->disp_priority == 2) { 3514 critical_point = 0; 3515 } 3516 3517 /* 3518 The critical point should never be above max_stop_req-4. Setting 3519 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3520 */ 3521 if (max_stop_req - critical_point < 4) 3522 critical_point = 0; 3523 3524 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3525 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3526 critical_point = 0x10; 3527 } 3528 3529 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3530 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3531 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3532 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3533 if ((rdev->family == CHIP_R350) && 3534 (stop_req > 0x15)) { 3535 stop_req -= 0x10; 3536 } 3537 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3538 temp |= RADEON_GRPH_BUFFER_SIZE; 3539 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3540 RADEON_GRPH_CRITICAL_AT_SOF | 3541 RADEON_GRPH_STOP_CNTL); 3542 /* 3543 Write the result into the register. 3544 */ 3545 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3546 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3547 3548 #if 0 3549 if ((rdev->family == CHIP_RS400) || 3550 (rdev->family == CHIP_RS480)) { 3551 /* attempt to program RS400 disp regs correctly ??? */ 3552 temp = RREG32(RS400_DISP1_REG_CNTL); 3553 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3554 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3555 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3556 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3557 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3558 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3559 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3560 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3561 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3562 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3563 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3564 } 3565 #endif 3566 3567 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3568 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3569 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3570 } 3571 3572 if (mode2) { 3573 u32 grph2_cntl; 3574 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3575 3576 if (stop_req > max_stop_req) 3577 stop_req = max_stop_req; 3578 3579 /* 3580 Find the drain rate of the display buffer. 3581 */ 3582 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3583 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3584 3585 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3586 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3587 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3588 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3589 if ((rdev->family == CHIP_R350) && 3590 (stop_req > 0x15)) { 3591 stop_req -= 0x10; 3592 } 3593 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3594 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3595 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3596 RADEON_GRPH_CRITICAL_AT_SOF | 3597 RADEON_GRPH_STOP_CNTL); 3598 3599 if ((rdev->family == CHIP_RS100) || 3600 (rdev->family == CHIP_RS200)) 3601 critical_point2 = 0; 3602 else { 3603 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3604 temp_ff.full = dfixed_const(temp); 3605 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3606 if (sclk_ff.full < temp_ff.full) 3607 temp_ff.full = sclk_ff.full; 3608 3609 read_return_rate.full = temp_ff.full; 3610 3611 if (mode1) { 3612 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3613 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3614 } else { 3615 time_disp1_drop_priority.full = 0; 3616 } 3617 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3618 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3619 crit_point_ff.full += dfixed_const_half(0); 3620 3621 critical_point2 = dfixed_trunc(crit_point_ff); 3622 3623 if (rdev->disp_priority == 2) { 3624 critical_point2 = 0; 3625 } 3626 3627 if (max_stop_req - critical_point2 < 4) 3628 critical_point2 = 0; 3629 3630 } 3631 3632 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3633 /* some R300 cards have problem with this set to 0 */ 3634 critical_point2 = 0x10; 3635 } 3636 3637 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3638 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3639 3640 if ((rdev->family == CHIP_RS400) || 3641 (rdev->family == CHIP_RS480)) { 3642 #if 0 3643 /* attempt to program RS400 disp2 regs correctly ??? */ 3644 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3645 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3646 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3647 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3648 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3649 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3650 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3651 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3652 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3653 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3654 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3655 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3656 #endif 3657 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3658 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3659 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3660 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3661 } 3662 3663 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3664 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3665 } 3666 3667 /* Save number of lines the linebuffer leads before the scanout */ 3668 if (mode1) 3669 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 3670 3671 if (mode2) 3672 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3673 } 3674 3675 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3676 { 3677 uint32_t scratch; 3678 uint32_t tmp = 0; 3679 unsigned i; 3680 int r; 3681 3682 r = radeon_scratch_get(rdev, &scratch); 3683 if (r) { 3684 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3685 return r; 3686 } 3687 WREG32(scratch, 0xCAFEDEAD); 3688 r = radeon_ring_lock(rdev, ring, 2); 3689 if (r) { 3690 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3691 radeon_scratch_free(rdev, scratch); 3692 return r; 3693 } 3694 radeon_ring_write(ring, PACKET0(scratch, 0)); 3695 radeon_ring_write(ring, 0xDEADBEEF); 3696 radeon_ring_unlock_commit(rdev, ring, false); 3697 for (i = 0; i < rdev->usec_timeout; i++) { 3698 tmp = RREG32(scratch); 3699 if (tmp == 0xDEADBEEF) { 3700 break; 3701 } 3702 udelay(1); 3703 } 3704 if (i < rdev->usec_timeout) { 3705 DRM_INFO("ring test succeeded in %d usecs\n", i); 3706 } else { 3707 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3708 scratch, tmp); 3709 r = -EINVAL; 3710 } 3711 radeon_scratch_free(rdev, scratch); 3712 return r; 3713 } 3714 3715 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3716 { 3717 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3718 3719 if (ring->rptr_save_reg) { 3720 u32 next_rptr = ring->wptr + 2 + 3; 3721 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3722 radeon_ring_write(ring, next_rptr); 3723 } 3724 3725 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3726 radeon_ring_write(ring, ib->gpu_addr); 3727 radeon_ring_write(ring, ib->length_dw); 3728 } 3729 3730 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3731 { 3732 struct radeon_ib ib; 3733 uint32_t scratch; 3734 uint32_t tmp = 0; 3735 unsigned i; 3736 int r; 3737 3738 r = radeon_scratch_get(rdev, &scratch); 3739 if (r) { 3740 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3741 return r; 3742 } 3743 WREG32(scratch, 0xCAFEDEAD); 3744 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3745 if (r) { 3746 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3747 goto free_scratch; 3748 } 3749 ib.ptr[0] = PACKET0(scratch, 0); 3750 ib.ptr[1] = 0xDEADBEEF; 3751 ib.ptr[2] = PACKET2(0); 3752 ib.ptr[3] = PACKET2(0); 3753 ib.ptr[4] = PACKET2(0); 3754 ib.ptr[5] = PACKET2(0); 3755 ib.ptr[6] = PACKET2(0); 3756 ib.ptr[7] = PACKET2(0); 3757 ib.length_dw = 8; 3758 r = radeon_ib_schedule(rdev, &ib, NULL, false); 3759 if (r) { 3760 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3761 goto free_ib; 3762 } 3763 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( 3764 RADEON_USEC_IB_TEST_TIMEOUT)); 3765 if (r < 0) { 3766 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3767 goto free_ib; 3768 } else if (r == 0) { 3769 DRM_ERROR("radeon: fence wait timed out.\n"); 3770 r = -ETIMEDOUT; 3771 goto free_ib; 3772 } 3773 r = 0; 3774 for (i = 0; i < rdev->usec_timeout; i++) { 3775 tmp = RREG32(scratch); 3776 if (tmp == 0xDEADBEEF) { 3777 break; 3778 } 3779 udelay(1); 3780 } 3781 if (i < rdev->usec_timeout) { 3782 DRM_INFO("ib test succeeded in %u usecs\n", i); 3783 } else { 3784 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3785 scratch, tmp); 3786 r = -EINVAL; 3787 } 3788 free_ib: 3789 radeon_ib_free(rdev, &ib); 3790 free_scratch: 3791 radeon_scratch_free(rdev, scratch); 3792 return r; 3793 } 3794 3795 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3796 { 3797 /* Shutdown CP we shouldn't need to do that but better be safe than 3798 * sorry 3799 */ 3800 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3801 WREG32(R_000740_CP_CSQ_CNTL, 0); 3802 3803 /* Save few CRTC registers */ 3804 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3805 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3806 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3807 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3808 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3809 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3810 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3811 } 3812 3813 /* Disable VGA aperture access */ 3814 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3815 /* Disable cursor, overlay, crtc */ 3816 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3817 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3818 S_000054_CRTC_DISPLAY_DIS(1)); 3819 WREG32(R_000050_CRTC_GEN_CNTL, 3820 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3821 S_000050_CRTC_DISP_REQ_EN_B(1)); 3822 WREG32(R_000420_OV0_SCALE_CNTL, 3823 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3824 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3825 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3826 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3827 S_000360_CUR2_LOCK(1)); 3828 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3829 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3830 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3831 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3832 WREG32(R_000360_CUR2_OFFSET, 3833 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3834 } 3835 } 3836 3837 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3838 { 3839 /* Update base address for crtc */ 3840 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3841 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3842 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3843 } 3844 /* Restore CRTC registers */ 3845 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3846 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3847 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3848 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3849 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3850 } 3851 } 3852 3853 void r100_vga_render_disable(struct radeon_device *rdev) 3854 { 3855 u32 tmp; 3856 3857 tmp = RREG8(R_0003C2_GENMO_WT); 3858 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3859 } 3860 3861 static void r100_mc_program(struct radeon_device *rdev) 3862 { 3863 struct r100_mc_save save; 3864 3865 /* Stops all mc clients */ 3866 r100_mc_stop(rdev, &save); 3867 if (rdev->flags & RADEON_IS_AGP) { 3868 WREG32(R_00014C_MC_AGP_LOCATION, 3869 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3870 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3871 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3872 if (rdev->family > CHIP_RV200) 3873 WREG32(R_00015C_AGP_BASE_2, 3874 upper_32_bits(rdev->mc.agp_base) & 0xff); 3875 } else { 3876 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3877 WREG32(R_000170_AGP_BASE, 0); 3878 if (rdev->family > CHIP_RV200) 3879 WREG32(R_00015C_AGP_BASE_2, 0); 3880 } 3881 /* Wait for mc idle */ 3882 if (r100_mc_wait_for_idle(rdev)) 3883 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3884 /* Program MC, should be a 32bits limited address space */ 3885 WREG32(R_000148_MC_FB_LOCATION, 3886 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3887 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3888 r100_mc_resume(rdev, &save); 3889 } 3890 3891 static void r100_clock_startup(struct radeon_device *rdev) 3892 { 3893 u32 tmp; 3894 3895 if (radeon_dynclks != -1 && radeon_dynclks) 3896 radeon_legacy_set_clock_gating(rdev, 1); 3897 /* We need to force on some of the block */ 3898 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3899 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3900 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3901 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3902 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3903 } 3904 3905 static int r100_startup(struct radeon_device *rdev) 3906 { 3907 int r; 3908 3909 /* set common regs */ 3910 r100_set_common_regs(rdev); 3911 /* program mc */ 3912 r100_mc_program(rdev); 3913 /* Resume clock */ 3914 r100_clock_startup(rdev); 3915 /* Initialize GART (initialize after TTM so we can allocate 3916 * memory through TTM but finalize after TTM) */ 3917 r100_enable_bm(rdev); 3918 if (rdev->flags & RADEON_IS_PCI) { 3919 r = r100_pci_gart_enable(rdev); 3920 if (r) 3921 return r; 3922 } 3923 3924 /* allocate wb buffer */ 3925 r = radeon_wb_init(rdev); 3926 if (r) 3927 return r; 3928 3929 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3930 if (r) { 3931 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3932 return r; 3933 } 3934 3935 /* Enable IRQ */ 3936 if (!rdev->irq.installed) { 3937 r = radeon_irq_kms_init(rdev); 3938 if (r) 3939 return r; 3940 } 3941 3942 r100_irq_set(rdev); 3943 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3944 /* 1M ring buffer */ 3945 r = r100_cp_init(rdev, 1024 * 1024); 3946 if (r) { 3947 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3948 return r; 3949 } 3950 3951 r = radeon_ib_pool_init(rdev); 3952 if (r) { 3953 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3954 return r; 3955 } 3956 3957 return 0; 3958 } 3959 3960 int r100_resume(struct radeon_device *rdev) 3961 { 3962 int r; 3963 3964 /* Make sur GART are not working */ 3965 if (rdev->flags & RADEON_IS_PCI) 3966 r100_pci_gart_disable(rdev); 3967 /* Resume clock before doing reset */ 3968 r100_clock_startup(rdev); 3969 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3970 if (radeon_asic_reset(rdev)) { 3971 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3972 RREG32(R_000E40_RBBM_STATUS), 3973 RREG32(R_0007C0_CP_STAT)); 3974 } 3975 /* post */ 3976 radeon_combios_asic_init(rdev_to_drm(rdev)); 3977 /* Resume clock after posting */ 3978 r100_clock_startup(rdev); 3979 /* Initialize surface registers */ 3980 radeon_surface_init(rdev); 3981 3982 rdev->accel_working = true; 3983 r = r100_startup(rdev); 3984 if (r) { 3985 rdev->accel_working = false; 3986 } 3987 return r; 3988 } 3989 3990 int r100_suspend(struct radeon_device *rdev) 3991 { 3992 radeon_pm_suspend(rdev); 3993 r100_cp_disable(rdev); 3994 radeon_wb_disable(rdev); 3995 r100_irq_disable(rdev); 3996 if (rdev->flags & RADEON_IS_PCI) 3997 r100_pci_gart_disable(rdev); 3998 return 0; 3999 } 4000 4001 void r100_fini(struct radeon_device *rdev) 4002 { 4003 radeon_pm_fini(rdev); 4004 r100_cp_fini(rdev); 4005 radeon_wb_fini(rdev); 4006 radeon_ib_pool_fini(rdev); 4007 radeon_gem_fini(rdev); 4008 if (rdev->flags & RADEON_IS_PCI) 4009 r100_pci_gart_fini(rdev); 4010 radeon_agp_fini(rdev); 4011 radeon_irq_kms_fini(rdev); 4012 radeon_fence_driver_fini(rdev); 4013 radeon_bo_fini(rdev); 4014 radeon_atombios_fini(rdev); 4015 kfree(rdev->bios); 4016 rdev->bios = NULL; 4017 } 4018 4019 /* 4020 * Due to how kexec works, it can leave the hw fully initialised when it 4021 * boots the new kernel. However doing our init sequence with the CP and 4022 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 4023 * do some quick sanity checks and restore sane values to avoid this 4024 * problem. 4025 */ 4026 void r100_restore_sanity(struct radeon_device *rdev) 4027 { 4028 u32 tmp; 4029 4030 tmp = RREG32(RADEON_CP_CSQ_CNTL); 4031 if (tmp) { 4032 WREG32(RADEON_CP_CSQ_CNTL, 0); 4033 } 4034 tmp = RREG32(RADEON_CP_RB_CNTL); 4035 if (tmp) { 4036 WREG32(RADEON_CP_RB_CNTL, 0); 4037 } 4038 tmp = RREG32(RADEON_SCRATCH_UMSK); 4039 if (tmp) { 4040 WREG32(RADEON_SCRATCH_UMSK, 0); 4041 } 4042 } 4043 4044 int r100_init(struct radeon_device *rdev) 4045 { 4046 int r; 4047 4048 /* Register debugfs file specific to this group of asics */ 4049 r100_debugfs_mc_info_init(rdev); 4050 /* Disable VGA */ 4051 r100_vga_render_disable(rdev); 4052 /* Initialize scratch registers */ 4053 radeon_scratch_init(rdev); 4054 /* Initialize surface registers */ 4055 radeon_surface_init(rdev); 4056 /* sanity check some register to avoid hangs like after kexec */ 4057 r100_restore_sanity(rdev); 4058 /* TODO: disable VGA need to use VGA request */ 4059 /* BIOS*/ 4060 if (!radeon_get_bios(rdev)) { 4061 if (ASIC_IS_AVIVO(rdev)) 4062 return -EINVAL; 4063 } 4064 if (rdev->is_atom_bios) { 4065 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4066 return -EINVAL; 4067 } else { 4068 r = radeon_combios_init(rdev); 4069 if (r) 4070 return r; 4071 } 4072 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4073 if (radeon_asic_reset(rdev)) { 4074 dev_warn(rdev->dev, 4075 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4076 RREG32(R_000E40_RBBM_STATUS), 4077 RREG32(R_0007C0_CP_STAT)); 4078 } 4079 /* check if cards are posted or not */ 4080 if (radeon_boot_test_post_card(rdev) == false) 4081 return -EINVAL; 4082 /* Set asic errata */ 4083 r100_errata(rdev); 4084 /* Initialize clocks */ 4085 radeon_get_clock_info(rdev_to_drm(rdev)); 4086 /* initialize AGP */ 4087 if (rdev->flags & RADEON_IS_AGP) { 4088 r = radeon_agp_init(rdev); 4089 if (r) { 4090 radeon_agp_disable(rdev); 4091 } 4092 } 4093 /* initialize VRAM */ 4094 r100_mc_init(rdev); 4095 /* Fence driver */ 4096 radeon_fence_driver_init(rdev); 4097 /* Memory manager */ 4098 r = radeon_bo_init(rdev); 4099 if (r) 4100 return r; 4101 if (rdev->flags & RADEON_IS_PCI) { 4102 r = r100_pci_gart_init(rdev); 4103 if (r) 4104 return r; 4105 } 4106 r100_set_safe_registers(rdev); 4107 4108 /* Initialize power management */ 4109 radeon_pm_init(rdev); 4110 4111 rdev->accel_working = true; 4112 r = r100_startup(rdev); 4113 if (r) { 4114 /* Somethings want wront with the accel init stop accel */ 4115 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4116 r100_cp_fini(rdev); 4117 radeon_wb_fini(rdev); 4118 radeon_ib_pool_fini(rdev); 4119 radeon_irq_kms_fini(rdev); 4120 if (rdev->flags & RADEON_IS_PCI) 4121 r100_pci_gart_fini(rdev); 4122 rdev->accel_working = false; 4123 } 4124 return 0; 4125 } 4126 4127 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) 4128 { 4129 unsigned long flags; 4130 uint32_t ret; 4131 4132 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4133 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4134 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4135 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4136 return ret; 4137 } 4138 4139 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) 4140 { 4141 unsigned long flags; 4142 4143 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4144 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 4145 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 4146 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4147 } 4148 4149 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4150 { 4151 if (reg < rdev->rio_mem_size) 4152 return ioread32(rdev->rio_mem + reg); 4153 else { 4154 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4155 return ioread32(rdev->rio_mem + RADEON_MM_DATA); 4156 } 4157 } 4158 4159 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4160 { 4161 if (reg < rdev->rio_mem_size) 4162 iowrite32(v, rdev->rio_mem + reg); 4163 else { 4164 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); 4165 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); 4166 } 4167 } 4168