1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 //
8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
10
11 /*
12 * Hardware interface for generic AMD ACP processor
13 */
14
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18
19 #include <asm/amd/node.h>
20
21 #include "../ops.h"
22 #include "acp.h"
23 #include "acp-dsp-offset.h"
24
25 static bool enable_fw_debug;
26 module_param(enable_fw_debug, bool, 0444);
27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug");
28
29 static struct acp_quirk_entry quirk_valve_galileo = {
30 .signed_fw_image = true,
31 .skip_iram_dram_size_mod = true,
32 .post_fw_run_delay = true,
33 };
34
35 const struct dmi_system_id acp_sof_quirk_table[] = {
36 {
37 /* Steam Deck OLED device */
38 .matches = {
39 DMI_MATCH(DMI_SYS_VENDOR, "Valve"),
40 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),
41 },
42 .driver_data = &quirk_valve_galileo,
43 },
44 {}
45 };
46 EXPORT_SYMBOL_GPL(acp_sof_quirk_table);
47
init_dma_descriptor(struct acp_dev_data * adata)48 static void init_dma_descriptor(struct acp_dev_data *adata)
49 {
50 struct snd_sof_dev *sdev = adata->dev;
51 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
52 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
53 unsigned int addr;
54 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr;
55
56 addr = desc->sram_pte_offset + sdev->debug_box.offset +
57 offsetof(struct scratch_reg_conf, dma_desc);
58
59 switch (acp_data->pci_rev) {
60 case ACP70_PCI_ID:
61 case ACP71_PCI_ID:
62 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;
63 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;
64 break;
65 default:
66 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR;
67 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR;
68 }
69 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr);
70 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT);
71 }
72
configure_dma_descriptor(struct acp_dev_data * adata,unsigned short idx,struct dma_descriptor * dscr_info)73 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
74 struct dma_descriptor *dscr_info)
75 {
76 struct snd_sof_dev *sdev = adata->dev;
77 unsigned int offset;
78
79 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +
80 offsetof(struct scratch_reg_conf, dma_desc) +
81 idx * sizeof(struct dma_descriptor);
82
83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);
84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
86 }
87
config_dma_channel(struct acp_dev_data * adata,unsigned int ch,unsigned int idx,unsigned int dscr_count)88 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
89 unsigned int idx, unsigned int dscr_count)
90 {
91 struct snd_sof_dev *sdev = adata->dev;
92 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
93 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
94 unsigned int val, status;
95 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0;
96 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0;
97 int ret;
98
99 switch (acp_data->pci_rev) {
100 case ACP70_PCI_ID:
101 case ACP71_PCI_ID:
102 acp_dma_cntl_0 = ACP70_DMA_CNTL_0;
103 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;
104 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;
105 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0;
106 acp_dma_prio_0 = ACP70_DMA_PRIO_0;
107 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0;
108 break;
109 default:
110 acp_dma_cntl_0 = ACP_DMA_CNTL_0;
111 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS;
112 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0;
113 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0;
114 acp_dma_prio_0 = ACP_DMA_PRIO_0;
115 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0;
116 }
117
118 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32),
119 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
120
121 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val,
122 val & (1 << ch), ACP_REG_POLL_INTERVAL,
123 ACP_REG_POLL_TIMEOUT_US);
124 if (ret < 0) {
125 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
126 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 +
127 ch * sizeof(u32));
128
129 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
130 return ret;
131 }
132
133 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0);
134 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count);
135 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx);
136 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0);
137 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
138
139 return ret;
140 }
141
acpbus_dma_start(struct acp_dev_data * adata,unsigned int ch,unsigned int dscr_count,struct dma_descriptor * dscr_info)142 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
143 unsigned int dscr_count, struct dma_descriptor *dscr_info)
144 {
145 struct snd_sof_dev *sdev = adata->dev;
146 int ret;
147 u16 dscr;
148
149 if (!dscr_info || !dscr_count)
150 return -EINVAL;
151
152 for (dscr = 0; dscr < dscr_count; dscr++)
153 configure_dma_descriptor(adata, dscr, dscr_info++);
154
155 ret = config_dma_channel(adata, ch, 0, dscr_count);
156 if (ret < 0)
157 dev_err(sdev->dev, "config dma ch failed:%d\n", ret);
158
159 return ret;
160 }
161
configure_and_run_dma(struct acp_dev_data * adata,unsigned int src_addr,unsigned int dest_addr,int dsp_data_size)162 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
163 unsigned int dest_addr, int dsp_data_size)
164 {
165 struct snd_sof_dev *sdev = adata->dev;
166 unsigned int desc_count, index;
167 int ret;
168
169 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0;
170 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) {
171 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE;
172 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE;
173 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE;
174 if (dsp_data_size < ACP_PAGE_SIZE)
175 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size;
176 }
177
178 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info);
179 if (ret)
180 dev_err(sdev->dev, "acpbus_dma_start failed\n");
181
182 /* Clear descriptor array */
183 for (index = 0; index < desc_count; index++)
184 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor));
185
186 return ret;
187 }
188
189 /*
190 * psp_mbox_ready- function to poll ready bit of psp mbox
191 * @adata: acp device data
192 * @ack: bool variable to check ready bit status or psp ack
193 */
194
psp_mbox_ready(struct acp_dev_data * adata,bool ack)195 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack)
196 {
197 struct snd_sof_dev *sdev = adata->dev;
198 int ret, data;
199
200 ret = read_poll_timeout(smn_read_register, data, data > 0 && data & MBOX_READY_MASK,
201 MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_114_REG);
202
203 if (!ret)
204 return 0;
205
206 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);
207
208 if (ack)
209 return -ETIMEDOUT;
210
211 return -EBUSY;
212 }
213
214 /*
215 * psp_send_cmd - function to send psp command over mbox
216 * @adata: acp device data
217 * @cmd: non zero integer value for command type
218 */
219
psp_send_cmd(struct acp_dev_data * adata,int cmd)220 static int psp_send_cmd(struct acp_dev_data *adata, int cmd)
221 {
222 struct snd_sof_dev *sdev = adata->dev;
223 int ret;
224 u32 data;
225
226 if (!cmd)
227 return -EINVAL;
228
229 /* Get a non-zero Doorbell value from PSP */
230 ret = read_poll_timeout(smn_read_register, data, data > 0, MBOX_DELAY_US,
231 ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_73_REG);
232
233 if (ret) {
234 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);
235 return ret;
236 }
237
238 /* Check if PSP is ready for new command */
239 ret = psp_mbox_ready(adata, 0);
240 if (ret)
241 return ret;
242
243 ret = amd_smn_write(0, MP0_C2PMSG_114_REG, cmd);
244 if (ret)
245 return ret;
246
247 /* Ring the Doorbell for PSP */
248 ret = amd_smn_write(0, MP0_C2PMSG_73_REG, data);
249 if (ret)
250 return ret;
251
252 /* Check MBOX ready as PSP ack */
253 ret = psp_mbox_ready(adata, 1);
254
255 return ret;
256 }
257
configure_and_run_sha_dma(struct acp_dev_data * adata,void * image_addr,unsigned int start_addr,unsigned int dest_addr,unsigned int image_length)258 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
259 unsigned int start_addr, unsigned int dest_addr,
260 unsigned int image_length)
261 {
262 struct snd_sof_dev *sdev = adata->dev;
263 unsigned int tx_count, fw_qualifier, val;
264 int ret;
265
266 if (!image_addr) {
267 dev_err(sdev->dev, "SHA DMA image address is NULL\n");
268 return -EINVAL;
269 }
270
271 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);
272 if (val & ACP_SHA_RUN) {
273 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);
274 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,
275 val, val & ACP_SHA_RESET,
276 ACP_REG_POLL_INTERVAL,
277 ACP_REG_POLL_TIMEOUT_US);
278 if (ret < 0) {
279 dev_err(sdev->dev, "SHA DMA Failed to Reset\n");
280 return ret;
281 }
282 }
283
284 if (adata->quirks && adata->quirks->signed_fw_image)
285 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);
286
287 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
288 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
289 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
290
291 /* psp_send_cmd only required for vangogh platform */
292 if (adata->pci_rev == ACP_VANGOGH_PCI_ID &&
293 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) {
294 /* Modify IRAM and DRAM size */
295 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);
296 if (ret)
297 return ret;
298 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);
299 if (ret)
300 return ret;
301 }
302 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
303
304 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
305 tx_count, tx_count == image_length,
306 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
307 if (ret < 0) {
308 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);
309 return ret;
310 }
311
312 /* psp_send_cmd only required for renoir platform*/
313 if (adata->pci_rev == ACP_RN_PCI_ID) {
314 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);
315 if (ret)
316 return ret;
317 }
318
319 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,
320 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,
321 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
322 if (ret < 0) {
323 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK);
324 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n",
325 fw_qualifier, val);
326 return ret;
327 }
328
329 return 0;
330 }
331
acp_dma_status(struct acp_dev_data * adata,unsigned char ch)332 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
333 {
334 struct snd_sof_dev *sdev = adata->dev;
335 unsigned int val;
336 unsigned int acp_dma_ch_sts;
337 int ret = 0;
338
339 switch (adata->pci_rev) {
340 case ACP70_PCI_ID:
341 case ACP71_PCI_ID:
342 acp_dma_ch_sts = ACP70_DMA_CH_STS;
343 break;
344 default:
345 acp_dma_ch_sts = ACP_DMA_CH_STS;
346 }
347 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));
348 if (val & ACP_DMA_CH_RUN) {
349 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val,
350 ACP_REG_POLL_INTERVAL,
351 ACP_DMA_COMPLETE_TIMEOUT_US);
352 if (ret < 0)
353 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);
354 }
355
356 return ret;
357 }
358
memcpy_from_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * dst,size_t bytes)359 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)
360 {
361 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
362 int i, j;
363
364 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
365 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
366 }
367
memcpy_to_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * src,size_t bytes)368 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)
369 {
370 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
371 int i, j;
372
373 for (i = 0, j = 0; i < bytes; i = i + 4, j++)
374 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
375 }
376
acp_memory_init(struct snd_sof_dev * sdev)377 static int acp_memory_init(struct snd_sof_dev *sdev)
378 {
379 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
380 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
381
382 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,
383 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
384 init_dma_descriptor(adata);
385
386 return 0;
387 }
388
amd_sof_handle_acp70_sdw_wake_event(struct acp_dev_data * adata)389 static void amd_sof_handle_acp70_sdw_wake_event(struct acp_dev_data *adata)
390 {
391 struct amd_sdw_manager *amd_manager;
392
393 if (adata->acp70_sdw0_wake_event) {
394 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev);
395 if (amd_manager)
396 pm_request_resume(amd_manager->dev);
397 adata->acp70_sdw0_wake_event = 0;
398 }
399
400 if (adata->acp70_sdw1_wake_event) {
401 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev);
402 if (amd_manager)
403 pm_request_resume(amd_manager->dev);
404 adata->acp70_sdw1_wake_event = 0;
405 }
406 }
407
amd_sof_check_and_handle_acp70_sdw_wake_irq(struct snd_sof_dev * sdev)408 static int amd_sof_check_and_handle_acp70_sdw_wake_irq(struct snd_sof_dev *sdev)
409 {
410 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
411 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
412 u32 ext_intr_stat1;
413 int irq_flag = 0;
414 bool sdw_wake_irq = false;
415
416 ext_intr_stat1 = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1);
417 if (ext_intr_stat1 & ACP70_SDW0_HOST_WAKE_STAT) {
418 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,
419 ACP70_SDW0_HOST_WAKE_STAT);
420 adata->acp70_sdw0_wake_event = true;
421 sdw_wake_irq = true;
422 }
423
424 if (ext_intr_stat1 & ACP70_SDW1_HOST_WAKE_STAT) {
425 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,
426 ACP70_SDW1_HOST_WAKE_STAT);
427 adata->acp70_sdw1_wake_event = true;
428 sdw_wake_irq = true;
429 }
430
431 if (ext_intr_stat1 & ACP70_SDW0_PME_STAT) {
432 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN, 0);
433 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW0_PME_STAT);
434 adata->acp70_sdw0_wake_event = true;
435 sdw_wake_irq = true;
436 }
437
438 if (ext_intr_stat1 & ACP70_SDW1_PME_STAT) {
439 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN, 0);
440 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW1_PME_STAT);
441 adata->acp70_sdw1_wake_event = true;
442 sdw_wake_irq = true;
443 }
444
445 if (sdw_wake_irq) {
446 amd_sof_handle_acp70_sdw_wake_event(adata);
447 irq_flag = 1;
448 }
449 return irq_flag;
450 }
451
acp_irq_thread(int irq,void * context)452 static irqreturn_t acp_irq_thread(int irq, void *context)
453 {
454 struct snd_sof_dev *sdev = context;
455 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
456 unsigned int count = ACP_HW_SEM_RETRY_COUNT;
457
458 spin_lock_irq(&sdev->ipc_lock);
459 /* Wait until acquired HW Semaphore lock or timeout */
460 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count)
461 ;
462 spin_unlock_irq(&sdev->ipc_lock);
463
464 if (!count) {
465 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
466 return IRQ_NONE;
467 }
468
469 sof_ops(sdev)->irq_thread(irq, sdev);
470 /* Unlock or Release HW Semaphore */
471 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
472
473 return IRQ_HANDLED;
474 };
475
acp_irq_handler(int irq,void * dev_id)476 static irqreturn_t acp_irq_handler(int irq, void *dev_id)
477 {
478 struct amd_sdw_manager *amd_manager;
479 struct snd_sof_dev *sdev = dev_id;
480 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
481 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
482 unsigned int base = desc->dsp_intr_base;
483 unsigned int val;
484 int irq_flag = 0, wake_irq_flag = 0;
485
486 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
487 if (val & ACP_DSP_TO_HOST_IRQ) {
488 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,
489 ACP_DSP_TO_HOST_IRQ);
490 return IRQ_WAKE_THREAD;
491 }
492
493 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat);
494 if (val & ACP_SDW0_IRQ_MASK) {
495 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev);
496 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK);
497 if (amd_manager)
498 schedule_work(&amd_manager->amd_sdw_irq_thread);
499 irq_flag = 1;
500 }
501
502 if (val & ACP_ERROR_IRQ_MASK) {
503 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK);
504 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0);
505 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */
506 if (adata->pci_rev >= ACP_RMB_PCI_ID)
507 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0);
508 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0);
509 irq_flag = 1;
510 }
511
512 if (desc->ext_intr_stat1) {
513 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1);
514 if (val & ACP_SDW1_IRQ_MASK) {
515 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev);
516 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,
517 ACP_SDW1_IRQ_MASK);
518 if (amd_manager)
519 schedule_work(&amd_manager->amd_sdw_irq_thread);
520 irq_flag = 1;
521 }
522 switch (adata->pci_rev) {
523 case ACP70_PCI_ID:
524 case ACP71_PCI_ID:
525 wake_irq_flag = amd_sof_check_and_handle_acp70_sdw_wake_irq(sdev);
526 break;
527 }
528 }
529 if (irq_flag || wake_irq_flag)
530 return IRQ_HANDLED;
531 else
532 return IRQ_NONE;
533 }
534
acp_power_on(struct snd_sof_dev * sdev)535 static int acp_power_on(struct snd_sof_dev *sdev)
536 {
537 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
538 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
539 unsigned int base = desc->pgfsm_base;
540 unsigned int val;
541 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask;
542 int ret;
543
544 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
545
546 if (val == ACP_POWERED_ON)
547 return 0;
548
549 switch (adata->pci_rev) {
550 case ACP_RN_PCI_ID:
551 case ACP_VANGOGH_PCI_ID:
552 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;
553 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;
554 break;
555 case ACP_RMB_PCI_ID:
556 case ACP63_PCI_ID:
557 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
558 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
559 break;
560 case ACP70_PCI_ID:
561 case ACP71_PCI_ID:
562 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;
563 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;
564 break;
565 default:
566 return -EINVAL;
567 }
568
569 if (val & acp_pgfsm_status_mask)
570 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
571 acp_pgfsm_cntl_mask);
572
573 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
574 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
575 if (ret < 0)
576 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
577
578 return ret;
579 }
580
acp_reset(struct snd_sof_dev * sdev)581 static int acp_reset(struct snd_sof_dev *sdev)
582 {
583 unsigned int val;
584 int ret;
585
586 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);
587
588 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
589 val & ACP_SOFT_RESET_DONE_MASK,
590 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
591 if (ret < 0) {
592 dev_err(sdev->dev, "timeout asserting reset\n");
593 return ret;
594 }
595
596 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);
597
598 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
599 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
600 if (ret < 0)
601 dev_err(sdev->dev, "timeout in releasing reset\n");
602
603 return ret;
604 }
605
acp_dsp_reset(struct snd_sof_dev * sdev)606 static int acp_dsp_reset(struct snd_sof_dev *sdev)
607 {
608 unsigned int val;
609 int ret;
610
611 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET);
612
613 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
614 val & ACP_DSP_SOFT_RESET_DONE_MASK,
615 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
616 if (ret < 0) {
617 dev_err(sdev->dev, "timeout asserting reset\n");
618 return ret;
619 }
620
621 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET);
622
623 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
624 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
625 if (ret < 0)
626 dev_err(sdev->dev, "timeout in releasing reset\n");
627
628 return ret;
629 }
630
acp_init(struct snd_sof_dev * sdev)631 static int acp_init(struct snd_sof_dev *sdev)
632 {
633 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
634 struct acp_dev_data *acp_data;
635 unsigned int sdw0_wake_en, sdw1_wake_en;
636 int ret;
637
638 /* power on */
639 acp_data = sdev->pdata->hw_pdata;
640 ret = acp_power_on(sdev);
641 if (ret) {
642 dev_err(sdev->dev, "ACP power on failed\n");
643 return ret;
644 }
645
646 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
647 /* Reset */
648 ret = acp_reset(sdev);
649 if (ret)
650 return ret;
651
652 if (desc->acp_clkmux_sel)
653 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
654
655 if (desc->ext_intr_enb)
656 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
657
658 if (desc->ext_intr_cntl)
659 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK);
660
661 switch (acp_data->pci_rev) {
662 case ACP70_PCI_ID:
663 case ACP71_PCI_ID:
664 sdw0_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN);
665 sdw1_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN);
666 if (sdw0_wake_en || sdw1_wake_en)
667 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP70_EXTERNAL_INTR_CNTL1,
668 ACP70_SDW_HOST_WAKE_MASK, ACP70_SDW_HOST_WAKE_MASK);
669
670 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1);
671 break;
672 }
673 return 0;
674 }
675
check_acp_sdw_enable_status(struct snd_sof_dev * sdev)676 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev)
677 {
678 struct acp_dev_data *acp_data;
679 u32 sdw0_en, sdw1_en;
680
681 acp_data = sdev->pdata->hw_pdata;
682 if (!acp_data->sdw)
683 return false;
684
685 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN);
686 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN);
687 acp_data->sdw_en_stat = sdw0_en || sdw1_en;
688 return acp_data->sdw_en_stat;
689 }
690
amd_sof_acp_suspend(struct snd_sof_dev * sdev,u32 target_state)691 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
692 {
693 struct acp_dev_data *acp_data;
694 int ret;
695 bool enable = false;
696
697 acp_data = sdev->pdata->hw_pdata;
698 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and
699 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will
700 * be reset to default values which will break the ClockStop Mode functionality.
701 * Add a condition check to apply DSP reset when SoundWire ClockStop mode
702 * is selected. For the rest of the scenarios, apply acp reset sequence.
703 */
704 if (check_acp_sdw_enable_status(sdev))
705 return acp_dsp_reset(sdev);
706
707 ret = acp_reset(sdev);
708 if (ret) {
709 dev_err(sdev->dev, "ACP Reset failed\n");
710 return ret;
711 }
712 switch (acp_data->pci_rev) {
713 case ACP70_PCI_ID:
714 case ACP71_PCI_ID:
715 enable = true;
716 break;
717 }
718 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);
719
720 return 0;
721 }
722 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, "SND_SOC_SOF_AMD_COMMON");
723
amd_sof_acp_resume(struct snd_sof_dev * sdev)724 int amd_sof_acp_resume(struct snd_sof_dev *sdev)
725 {
726 int ret;
727 struct acp_dev_data *acp_data;
728
729 acp_data = sdev->pdata->hw_pdata;
730 if (!acp_data->sdw_en_stat) {
731 ret = acp_init(sdev);
732 if (ret) {
733 dev_err(sdev->dev, "ACP Init failed\n");
734 return ret;
735 }
736 return acp_memory_init(sdev);
737 }
738 switch (acp_data->pci_rev) {
739 case ACP70_PCI_ID:
740 case ACP71_PCI_ID:
741 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1);
742 break;
743 }
744
745 return acp_dsp_reset(sdev);
746 }
747 EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON");
748
749 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE)
acp_sof_scan_sdw_devices(struct snd_sof_dev * sdev,u64 addr)750 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr)
751 {
752 struct acpi_device *sdw_dev;
753 struct acp_dev_data *acp_data;
754 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
755
756 if (!addr)
757 return -ENODEV;
758
759 acp_data = sdev->pdata->hw_pdata;
760 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0);
761 if (!sdw_dev)
762 return -ENODEV;
763
764 acp_data->info.handle = sdw_dev->handle;
765 acp_data->info.count = desc->sdw_max_link_count;
766
767 return amd_sdw_scan_controller(&acp_data->info);
768 }
769
amd_sof_sdw_probe(struct snd_sof_dev * sdev)770 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev)
771 {
772 struct acp_dev_data *acp_data;
773 struct sdw_amd_res sdw_res;
774 int ret;
775
776 acp_data = sdev->pdata->hw_pdata;
777
778 memset(&sdw_res, 0, sizeof(sdw_res));
779 sdw_res.addr = acp_data->addr;
780 sdw_res.reg_range = acp_data->reg_range;
781 sdw_res.handle = acp_data->info.handle;
782 sdw_res.parent = sdev->dev;
783 sdw_res.dev = sdev->dev;
784 sdw_res.acp_lock = &acp_data->acp_lock;
785 sdw_res.count = acp_data->info.count;
786 sdw_res.link_mask = acp_data->info.link_mask;
787 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR];
788 sdw_res.acp_rev = acp_data->pci_rev;
789
790 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw);
791 if (ret)
792 dev_err(sdev->dev, "SoundWire probe failed\n");
793 return ret;
794 }
795
amd_sof_sdw_exit(struct snd_sof_dev * sdev)796 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev)
797 {
798 struct acp_dev_data *acp_data;
799
800 acp_data = sdev->pdata->hw_pdata;
801 if (acp_data->sdw)
802 sdw_amd_exit(acp_data->sdw);
803 acp_data->sdw = NULL;
804
805 return 0;
806 }
807
808 #else
acp_sof_scan_sdw_devices(struct snd_sof_dev * sdev,u64 addr)809 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr)
810 {
811 return 0;
812 }
813
amd_sof_sdw_probe(struct snd_sof_dev * sdev)814 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev)
815 {
816 return 0;
817 }
818
amd_sof_sdw_exit(struct snd_sof_dev * sdev)819 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev)
820 {
821 return 0;
822 }
823 #endif
824
amd_sof_acp_probe(struct snd_sof_dev * sdev)825 int amd_sof_acp_probe(struct snd_sof_dev *sdev)
826 {
827 struct pci_dev *pci = to_pci_dev(sdev->dev);
828 struct acp_dev_data *adata;
829 const struct sof_amd_acp_desc *chip;
830 const struct dmi_system_id *dmi_id;
831 unsigned int addr;
832 int ret;
833
834 chip = get_chip_info(sdev->pdata);
835 if (!chip) {
836 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);
837 return -EIO;
838 }
839 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),
840 GFP_KERNEL);
841 if (!adata)
842 return -ENOMEM;
843
844 adata->dev = sdev;
845 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
846 PLATFORM_DEVID_NONE, NULL, 0);
847 if (IS_ERR(adata->dmic_dev)) {
848 dev_err(sdev->dev, "failed to register platform for dmic codec\n");
849 return PTR_ERR(adata->dmic_dev);
850 }
851 addr = pci_resource_start(pci, ACP_DSP_BAR);
852 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));
853 if (!sdev->bar[ACP_DSP_BAR]) {
854 dev_err(sdev->dev, "ioremap error\n");
855 ret = -ENXIO;
856 goto unregister_dev;
857 }
858
859 pci_set_master(pci);
860 adata->addr = addr;
861 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr;
862 adata->pci_rev = pci->revision;
863 mutex_init(&adata->acp_lock);
864 sdev->pdata->hw_pdata = adata;
865
866 ret = acp_init(sdev);
867 if (ret < 0)
868 goto unregister_dev;
869
870 sdev->ipc_irq = pci->irq;
871 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
872 IRQF_SHARED, "AudioDSP", sdev);
873 if (ret < 0) {
874 dev_err(sdev->dev, "failed to register IRQ %d\n",
875 sdev->ipc_irq);
876 goto unregister_dev;
877 }
878
879 /* scan SoundWire capabilities exposed by DSDT */
880 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr);
881 if (ret < 0) {
882 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n");
883 goto skip_soundwire;
884 }
885 ret = amd_sof_sdw_probe(sdev);
886 if (ret < 0) {
887 dev_err(sdev->dev, "error: SoundWire probe error\n");
888 free_irq(sdev->ipc_irq, sdev);
889 return ret;
890 }
891
892 skip_soundwire:
893 sdev->dsp_box.offset = 0;
894 sdev->dsp_box.size = BOX_SIZE_512;
895
896 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;
897 sdev->host_box.size = BOX_SIZE_512;
898
899 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;
900 sdev->debug_box.size = BOX_SIZE_1024;
901
902 dmi_id = dmi_first_match(acp_sof_quirk_table);
903 if (dmi_id) {
904 adata->quirks = dmi_id->driver_data;
905
906 if (adata->quirks->signed_fw_image) {
907 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
908 "sof-%s-code.bin",
909 chip->name);
910 if (!adata->fw_code_bin) {
911 ret = -ENOMEM;
912 goto free_ipc_irq;
913 }
914
915 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
916 "sof-%s-data.bin",
917 chip->name);
918 if (!adata->fw_data_bin) {
919 ret = -ENOMEM;
920 goto free_ipc_irq;
921 }
922 }
923 }
924
925 adata->enable_fw_debug = enable_fw_debug;
926 acp_memory_init(sdev);
927
928 acp_dsp_stream_init(sdev);
929
930 return 0;
931
932 free_ipc_irq:
933 free_irq(sdev->ipc_irq, sdev);
934 unregister_dev:
935 platform_device_unregister(adata->dmic_dev);
936 return ret;
937 }
938 EXPORT_SYMBOL_NS(amd_sof_acp_probe, "SND_SOC_SOF_AMD_COMMON");
939
amd_sof_acp_remove(struct snd_sof_dev * sdev)940 void amd_sof_acp_remove(struct snd_sof_dev *sdev)
941 {
942 struct acp_dev_data *adata = sdev->pdata->hw_pdata;
943
944 if (adata->sdw)
945 amd_sof_sdw_exit(sdev);
946
947 if (sdev->ipc_irq)
948 free_irq(sdev->ipc_irq, sdev);
949
950 if (adata->dmic_dev)
951 platform_device_unregister(adata->dmic_dev);
952
953 acp_reset(sdev);
954 }
955 EXPORT_SYMBOL_NS(amd_sof_acp_remove, "SND_SOC_SOF_AMD_COMMON");
956
957 MODULE_LICENSE("Dual BSD/GPL");
958 MODULE_DESCRIPTION("AMD ACP sof driver");
959 MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT");
960 MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI");
961