1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _AMDGPU_RAS_EEPROM_H 25 #define _AMDGPU_RAS_EEPROM_H 26 27 #include <linux/i2c.h> 28 29 #define RAS_TABLE_VER_V1 0x00010000 30 #define RAS_TABLE_VER_V2_1 0x00021000 31 32 struct amdgpu_device; 33 34 enum amdgpu_ras_gpu_health_status { 35 GPU_HEALTH_USABLE = 0, 36 GPU_RETIRED__ECC_REACH_THRESHOLD = 2, 37 }; 38 39 enum amdgpu_ras_eeprom_err_type { 40 AMDGPU_RAS_EEPROM_ERR_NA, 41 AMDGPU_RAS_EEPROM_ERR_RECOVERABLE, 42 AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE, 43 AMDGPU_RAS_EEPROM_ERR_COUNT, 44 }; 45 46 /* 47 * one UMC MCA address could map to multiply physical address (PA), 48 * such as 1:16, we use eeprom_table_record.address to store MCA 49 * address and use eeprom_table_record.retired_page to save PA. 50 * 51 * AMDGPU_RAS_EEPROM_REC_PA: one record store one PA 52 * AMDGPU_RAS_EEPROM_REC_MCA: one record store one MCA address 53 */ 54 enum amdgpu_ras_eeprom_rec_type { 55 AMDGPU_RAS_EEPROM_REC_PA, 56 AMDGPU_RAS_EEPROM_REC_MCA, 57 }; 58 59 struct amdgpu_ras_eeprom_table_header { 60 uint32_t header; 61 uint32_t version; 62 uint32_t first_rec_offset; 63 uint32_t tbl_size; 64 uint32_t checksum; 65 } __packed; 66 67 struct amdgpu_ras_eeprom_table_ras_info { 68 u8 rma_status; 69 u8 health_percent; 70 u16 ecc_page_threshold; 71 u32 padding[64 - 1]; 72 } __packed; 73 74 struct amdgpu_ras_eeprom_control { 75 struct amdgpu_ras_eeprom_table_header tbl_hdr; 76 77 struct amdgpu_ras_eeprom_table_ras_info tbl_rai; 78 79 /* Base I2C EEPPROM 19-bit memory address, 80 * where the table is located. For more information, 81 * see top of amdgpu_eeprom.c. 82 */ 83 u32 i2c_address; 84 85 /* The byte offset off of @i2c_address 86 * where the table header is found, 87 * and where the records start--always 88 * right after the header. 89 */ 90 u32 ras_header_offset; 91 u32 ras_info_offset; 92 u32 ras_record_offset; 93 94 /* Number of records in the table. 95 */ 96 u32 ras_num_recs; 97 98 /* the bad page number is ras_num_recs or 99 * ras_num_recs * umc.retire_unit 100 */ 101 u32 ras_num_bad_pages; 102 103 /* First record index to read, 0-based. 104 * Range is [0, num_recs-1]. This is 105 * an absolute index, starting right after 106 * the table header. 107 */ 108 u32 ras_fri; 109 110 /* Maximum possible number of records 111 * we could store, i.e. the maximum capacity 112 * of the table. 113 */ 114 u32 ras_max_record_count; 115 116 /* Protect table access via this mutex. 117 */ 118 struct mutex ras_tbl_mutex; 119 120 /* Record channel info which occurred bad pages 121 */ 122 u32 bad_channel_bitmap; 123 enum amdgpu_ras_eeprom_rec_type rec_type; 124 }; 125 126 /* 127 * Represents single table record. Packed to be easily serialized into byte 128 * stream. 129 */ 130 struct eeprom_table_record { 131 132 union { 133 uint64_t address; 134 uint64_t offset; 135 }; 136 137 uint64_t retired_page; 138 uint64_t ts; 139 140 enum amdgpu_ras_eeprom_err_type err_type; 141 142 union { 143 unsigned char bank; 144 unsigned char cu; 145 }; 146 147 unsigned char mem_channel; 148 unsigned char mcumc_id; 149 } __packed; 150 151 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control); 152 153 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control); 154 155 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev); 156 157 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 158 struct eeprom_table_record *records, const u32 num); 159 160 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 161 struct eeprom_table_record *records, const u32 num); 162 163 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control); 164 165 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control); 166 167 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control); 168 169 extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; 170 extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; 171 172 #endif // _AMDGPU_RAS_EEPROM_H 173