1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/sched.h>
15 #include <linux/interrupt.h>
16
17 #include <linux/pm_domain.h>
18 #include <linux/pm_runtime.h>
19
20 #include <linux/mei.h>
21
22 #include "mei_dev.h"
23 #include "client.h"
24 #include "hw-me-regs.h"
25 #include "hw-me.h"
26
27 /* mei_pci_tbl - PCI Device ID Table */
28 static const struct pci_device_id mei_me_pci_tbl[] = {
29 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
30 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
31 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
32 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
33 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
34 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
35 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
36 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
37 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
38 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
39 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
40
41 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
42 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
43 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
44 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
45 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
46 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
50
51 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
55
56 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
57 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
67 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
69
70 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
72 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
76
77 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
79
80 {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
81
82 {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
83
84 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
86 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
87
88 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
92
93 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
95 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
98
99 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
100 {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
101
102 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
103 {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
104
105 {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
106
107 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
108 {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
109
110 {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
111
112 {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
113
114 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
115 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
116 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
117 {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
118
119 {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)},
120
121 {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
122 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
123 {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
124
125 {MEI_PCI_DEVICE(MEI_DEV_ID_LNL_M, MEI_ME_PCH15_CFG)},
126
127 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_H, MEI_ME_PCH15_CFG)},
128 {MEI_PCI_DEVICE(MEI_DEV_ID_PTL_P, MEI_ME_PCH15_CFG)},
129
130 {MEI_PCI_DEVICE(MEI_DEV_ID_WCL_P, MEI_ME_PCH15_CFG)},
131
132 /* required last entry */
133 {0, }
134 };
135
136 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
137
138 #ifdef CONFIG_PM
139 static inline void mei_me_set_pm_domain(struct mei_device *dev);
140 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
141 #else
mei_me_set_pm_domain(struct mei_device * dev)142 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
mei_me_unset_pm_domain(struct mei_device * dev)143 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
144 #endif /* CONFIG_PM */
145
mei_me_read_fws(const struct mei_device * dev,int where,u32 * val)146 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
147 {
148 struct pci_dev *pdev = to_pci_dev(dev->parent);
149
150 return pci_read_config_dword(pdev, where, val);
151 }
152
153 /**
154 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
155 *
156 * @pdev: PCI device structure
157 * @cfg: per generation config
158 *
159 * Return: true if ME Interface is valid, false otherwise
160 */
mei_me_quirk_probe(struct pci_dev * pdev,const struct mei_cfg * cfg)161 static bool mei_me_quirk_probe(struct pci_dev *pdev,
162 const struct mei_cfg *cfg)
163 {
164 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
165 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
166 return false;
167 }
168
169 return true;
170 }
171
172 /**
173 * mei_me_probe - Device Initialization Routine
174 *
175 * @pdev: PCI device structure
176 * @ent: entry in kcs_pci_tbl
177 *
178 * Return: 0 on success, <0 on failure.
179 */
mei_me_probe(struct pci_dev * pdev,const struct pci_device_id * ent)180 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
181 {
182 const struct mei_cfg *cfg;
183 struct mei_device *dev;
184 struct mei_me_hw *hw;
185 unsigned int irqflags;
186 int err;
187
188 cfg = mei_me_get_cfg(ent->driver_data);
189 if (!cfg)
190 return -ENODEV;
191
192 if (!mei_me_quirk_probe(pdev, cfg))
193 return -ENODEV;
194
195 /* enable pci dev */
196 err = pcim_enable_device(pdev);
197 if (err) {
198 dev_err(&pdev->dev, "failed to enable pci device.\n");
199 goto end;
200 }
201 /* set PCI host mastering */
202 pci_set_master(pdev);
203 /* pci request regions and mapping IO device memory for mei driver */
204 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
205 if (err) {
206 dev_err(&pdev->dev, "failed to get pci regions.\n");
207 goto end;
208 }
209
210 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
211 if (err) {
212 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
213 goto end;
214 }
215
216 /* allocates and initializes the mei dev structure */
217 dev = mei_me_dev_init(&pdev->dev, cfg, false);
218 if (!dev) {
219 err = -ENOMEM;
220 goto end;
221 }
222 hw = to_me_hw(dev);
223 hw->mem_addr = pcim_iomap_table(pdev)[0];
224 hw->read_fws = mei_me_read_fws;
225
226 err = mei_register(dev, &pdev->dev);
227 if (err)
228 goto end;
229
230 pci_enable_msi(pdev);
231
232 hw->irq = pdev->irq;
233
234 /* request and enable interrupt */
235 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
236
237 err = request_threaded_irq(pdev->irq,
238 mei_me_irq_quick_handler,
239 mei_me_irq_thread_handler,
240 irqflags, KBUILD_MODNAME, dev);
241 if (err) {
242 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
243 pdev->irq);
244 goto deregister;
245 }
246
247 if (mei_start(dev)) {
248 dev_err(&pdev->dev, "init hw failure.\n");
249 err = -ENODEV;
250 goto deregister;
251 }
252
253 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
254 pm_runtime_use_autosuspend(&pdev->dev);
255
256 pci_set_drvdata(pdev, dev);
257
258 /*
259 * MEI requires to resume from runtime suspend mode
260 * in order to perform link reset flow upon system suspend.
261 */
262 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
263
264 /*
265 * ME maps runtime suspend/resume to D0i states,
266 * hence we need to go around native PCI runtime service which
267 * eventually brings the device into D3cold/hot state,
268 * but the mei device cannot wake up from D3 unlike from D0i3.
269 * To get around the PCI device native runtime pm,
270 * ME uses runtime pm domain handlers which take precedence
271 * over the driver's pm handlers.
272 */
273 mei_me_set_pm_domain(dev);
274
275 if (mei_pg_is_enabled(dev)) {
276 pm_runtime_put_noidle(&pdev->dev);
277 if (hw->d0i3_supported)
278 pm_runtime_allow(&pdev->dev);
279 }
280
281 dev_dbg(&pdev->dev, "initialization successful.\n");
282
283 return 0;
284
285 deregister:
286 mei_cancel_work(dev);
287 mei_disable_interrupts(dev);
288 free_irq(pdev->irq, dev);
289 mei_deregister(dev);
290 end:
291 dev_err(&pdev->dev, "initialization failed.\n");
292 return err;
293 }
294
295 /**
296 * mei_me_shutdown - Device Removal Routine
297 *
298 * @pdev: PCI device structure
299 *
300 * mei_me_shutdown is called from the reboot notifier
301 * it's a simplified version of remove so we go down
302 * faster.
303 */
mei_me_shutdown(struct pci_dev * pdev)304 static void mei_me_shutdown(struct pci_dev *pdev)
305 {
306 struct mei_device *dev = pci_get_drvdata(pdev);
307
308 dev_dbg(&pdev->dev, "shutdown\n");
309 mei_stop(dev);
310
311 mei_me_unset_pm_domain(dev);
312
313 mei_disable_interrupts(dev);
314 free_irq(pdev->irq, dev);
315 }
316
317 /**
318 * mei_me_remove - Device Removal Routine
319 *
320 * @pdev: PCI device structure
321 *
322 * mei_me_remove is called by the PCI subsystem to alert the driver
323 * that it should release a PCI device.
324 */
mei_me_remove(struct pci_dev * pdev)325 static void mei_me_remove(struct pci_dev *pdev)
326 {
327 struct mei_device *dev = pci_get_drvdata(pdev);
328
329 if (mei_pg_is_enabled(dev))
330 pm_runtime_get_noresume(&pdev->dev);
331
332 dev_dbg(&pdev->dev, "stop\n");
333 mei_stop(dev);
334
335 mei_me_unset_pm_domain(dev);
336
337 mei_disable_interrupts(dev);
338
339 free_irq(pdev->irq, dev);
340
341 mei_deregister(dev);
342 }
343
344 #ifdef CONFIG_PM_SLEEP
mei_me_pci_prepare(struct device * device)345 static int mei_me_pci_prepare(struct device *device)
346 {
347 pm_runtime_resume(device);
348 return 0;
349 }
350
mei_me_pci_suspend(struct device * device)351 static int mei_me_pci_suspend(struct device *device)
352 {
353 struct pci_dev *pdev = to_pci_dev(device);
354 struct mei_device *dev = pci_get_drvdata(pdev);
355
356 dev_dbg(&pdev->dev, "suspend\n");
357
358 mei_stop(dev);
359
360 mei_disable_interrupts(dev);
361
362 free_irq(pdev->irq, dev);
363 pci_disable_msi(pdev);
364
365 return 0;
366 }
367
mei_me_pci_resume(struct device * device)368 static int mei_me_pci_resume(struct device *device)
369 {
370 struct pci_dev *pdev = to_pci_dev(device);
371 struct mei_device *dev = pci_get_drvdata(pdev);
372 unsigned int irqflags;
373 int err;
374
375 pci_enable_msi(pdev);
376
377 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
378
379 /* request and enable interrupt */
380 err = request_threaded_irq(pdev->irq,
381 mei_me_irq_quick_handler,
382 mei_me_irq_thread_handler,
383 irqflags, KBUILD_MODNAME, dev);
384
385 if (err) {
386 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
387 pdev->irq);
388 return err;
389 }
390
391 err = mei_restart(dev);
392 if (err) {
393 free_irq(pdev->irq, dev);
394 return err;
395 }
396
397 /* Start timer if stopped in suspend */
398 schedule_delayed_work(&dev->timer_work, HZ);
399
400 return 0;
401 }
402
mei_me_pci_complete(struct device * device)403 static void mei_me_pci_complete(struct device *device)
404 {
405 pm_runtime_suspend(device);
406 }
407 #else /* CONFIG_PM_SLEEP */
408
409 #define mei_me_pci_prepare NULL
410 #define mei_me_pci_complete NULL
411
412 #endif /* !CONFIG_PM_SLEEP */
413
414 #ifdef CONFIG_PM
mei_me_pm_runtime_idle(struct device * device)415 static int mei_me_pm_runtime_idle(struct device *device)
416 {
417 struct mei_device *dev = dev_get_drvdata(device);
418
419 dev_dbg(device, "rpm: me: runtime_idle\n");
420
421 if (mei_write_is_idle(dev))
422 pm_runtime_autosuspend(device);
423
424 return -EBUSY;
425 }
426
mei_me_pm_runtime_suspend(struct device * device)427 static int mei_me_pm_runtime_suspend(struct device *device)
428 {
429 struct mei_device *dev = dev_get_drvdata(device);
430 int ret;
431
432 dev_dbg(device, "rpm: me: runtime suspend\n");
433
434 mutex_lock(&dev->device_lock);
435
436 if (mei_write_is_idle(dev))
437 ret = mei_me_pg_enter_sync(dev);
438 else
439 ret = -EAGAIN;
440
441 mutex_unlock(&dev->device_lock);
442
443 dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
444
445 if (ret && ret != -EAGAIN)
446 schedule_work(&dev->reset_work);
447
448 return ret;
449 }
450
mei_me_pm_runtime_resume(struct device * device)451 static int mei_me_pm_runtime_resume(struct device *device)
452 {
453 struct mei_device *dev = dev_get_drvdata(device);
454 int ret;
455
456 dev_dbg(device, "rpm: me: runtime resume\n");
457
458 mutex_lock(&dev->device_lock);
459
460 ret = mei_me_pg_exit_sync(dev);
461
462 mutex_unlock(&dev->device_lock);
463
464 dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
465
466 if (ret)
467 schedule_work(&dev->reset_work);
468
469 return ret;
470 }
471
472 /**
473 * mei_me_set_pm_domain - fill and set pm domain structure for device
474 *
475 * @dev: mei_device
476 */
mei_me_set_pm_domain(struct mei_device * dev)477 static inline void mei_me_set_pm_domain(struct mei_device *dev)
478 {
479 struct pci_dev *pdev = to_pci_dev(dev->parent);
480
481 if (pdev->dev.bus && pdev->dev.bus->pm) {
482 dev->pg_domain.ops = *pdev->dev.bus->pm;
483
484 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
485 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
486 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
487
488 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
489 }
490 }
491
492 /**
493 * mei_me_unset_pm_domain - clean pm domain structure for device
494 *
495 * @dev: mei_device
496 */
mei_me_unset_pm_domain(struct mei_device * dev)497 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
498 {
499 /* stop using pm callbacks if any */
500 dev_pm_domain_set(dev->parent, NULL);
501 }
502
503 static const struct dev_pm_ops mei_me_pm_ops = {
504 .prepare = mei_me_pci_prepare,
505 .complete = mei_me_pci_complete,
506 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
507 mei_me_pci_resume)
508 SET_RUNTIME_PM_OPS(
509 mei_me_pm_runtime_suspend,
510 mei_me_pm_runtime_resume,
511 mei_me_pm_runtime_idle)
512 };
513
514 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
515 #else
516 #define MEI_ME_PM_OPS NULL
517 #endif /* CONFIG_PM */
518 /*
519 * PCI driver structure
520 */
521 static struct pci_driver mei_me_driver = {
522 .name = KBUILD_MODNAME,
523 .id_table = mei_me_pci_tbl,
524 .probe = mei_me_probe,
525 .remove = mei_me_remove,
526 .shutdown = mei_me_shutdown,
527 .driver.pm = MEI_ME_PM_OPS,
528 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
529 };
530
531 module_pci_driver(mei_me_driver);
532
533 MODULE_AUTHOR("Intel Corporation");
534 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
535 MODULE_LICENSE("GPL v2");
536