1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/of_irq.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_vblank.h> 16 17 #include "msm_drv.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 #include "mdp5_kms.h" 21 22 static int mdp5_hw_init(struct msm_kms *kms) 23 { 24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 25 struct device *dev = &mdp5_kms->pdev->dev; 26 unsigned long flags; 27 28 pm_runtime_get_sync(dev); 29 30 /* Magic unknown register writes: 31 * 32 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 41 * 42 * Downstream fbdev driver gets these register offsets/values 43 * from DT.. not really sure what these registers are or if 44 * different values for different boards/SoC's, etc. I guess 45 * they are the golden registers. 46 * 47 * Not setting these does not seem to cause any problem. But 48 * we may be getting lucky with the bootloader initializing 49 * them for us. OTOH, if we can always count on the bootloader 50 * setting the golden registers, then perhaps we don't need to 51 * care. 52 */ 53 54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 57 58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 59 60 pm_runtime_put_sync(dev); 61 62 return 0; 63 } 64 65 /* Global/shared object state funcs */ 66 67 /* 68 * This is a helper that returns the private state currently in operation. 69 * Note that this would return the "old_state" if called in the atomic check 70 * path, and the "new_state" after the atomic swap has been done. 71 */ 72 struct mdp5_global_state * 73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) 74 { 75 return to_mdp5_global_state(mdp5_kms->glob_state.state); 76 } 77 78 /* 79 * This acquires the modeset lock set aside for global state, creates 80 * a new duplicated private object state. 81 */ 82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) 83 { 84 struct msm_drm_private *priv = s->dev->dev_private; 85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 86 struct drm_private_state *priv_state; 87 88 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); 89 if (IS_ERR(priv_state)) 90 return ERR_CAST(priv_state); 91 92 return to_mdp5_global_state(priv_state); 93 } 94 95 static struct drm_private_state * 96 mdp5_global_duplicate_state(struct drm_private_obj *obj) 97 { 98 struct mdp5_global_state *state; 99 100 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 101 if (!state) 102 return NULL; 103 104 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 105 106 return &state->base; 107 } 108 109 static void mdp5_global_destroy_state(struct drm_private_obj *obj, 110 struct drm_private_state *state) 111 { 112 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 113 114 kfree(mdp5_state); 115 } 116 117 static struct drm_private_state * 118 mdp5_global_create_state(struct drm_private_obj *obj) 119 { 120 struct drm_device *dev = obj->dev; 121 struct msm_drm_private *priv = dev->dev_private; 122 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 123 struct mdp5_global_state *mdp5_state; 124 125 mdp5_state = kzalloc_obj(*mdp5_state); 126 if (!mdp5_state) 127 return ERR_PTR(-ENOMEM); 128 129 __drm_atomic_helper_private_obj_create_state(obj, &mdp5_state->base); 130 mdp5_state->mdp5_kms = mdp5_kms; 131 132 return &mdp5_state->base; 133 } 134 135 static void mdp5_global_print_state(struct drm_printer *p, 136 const struct drm_private_state *state) 137 { 138 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 139 140 if (mdp5_state->mdp5_kms->smp) 141 mdp5_smp_dump(mdp5_state->mdp5_kms->smp, p, mdp5_state); 142 } 143 144 static const struct drm_private_state_funcs mdp5_global_state_funcs = { 145 .atomic_create_state = mdp5_global_create_state, 146 .atomic_duplicate_state = mdp5_global_duplicate_state, 147 .atomic_destroy_state = mdp5_global_destroy_state, 148 .atomic_print_state = mdp5_global_print_state, 149 }; 150 151 static void mdp5_enable_commit(struct msm_kms *kms) 152 { 153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 154 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 155 } 156 157 static void mdp5_disable_commit(struct msm_kms *kms) 158 { 159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 160 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 161 } 162 163 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 164 { 165 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 166 struct mdp5_global_state *global_state; 167 168 global_state = mdp5_get_existing_global_state(mdp5_kms); 169 170 if (mdp5_kms->smp) 171 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); 172 } 173 174 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 175 { 176 /* TODO */ 177 } 178 179 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 180 { 181 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 182 struct drm_crtc *crtc; 183 184 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) 185 mdp5_crtc_wait_for_commit_done(crtc); 186 } 187 188 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 189 { 190 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 191 struct mdp5_global_state *global_state; 192 193 global_state = mdp5_get_existing_global_state(mdp5_kms); 194 195 if (mdp5_kms->smp) 196 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 197 } 198 199 static void mdp5_destroy(struct mdp5_kms *mdp5_kms); 200 201 static void mdp5_kms_destroy(struct msm_kms *kms) 202 { 203 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 204 205 if (kms->vm) { 206 struct msm_mmu *mmu = to_msm_vm(kms->vm)->mmu; 207 208 mmu->funcs->detach(mmu); 209 drm_gpuvm_put(kms->vm); 210 } 211 212 mdp_kms_destroy(&mdp5_kms->base); 213 mdp5_destroy(mdp5_kms); 214 } 215 216 static const struct mdp_kms_funcs kms_funcs = { 217 .base = { 218 .hw_init = mdp5_hw_init, 219 .irq_preinstall = mdp5_irq_preinstall, 220 .irq_postinstall = mdp5_irq_postinstall, 221 .irq_uninstall = mdp5_irq_uninstall, 222 .irq = mdp5_irq, 223 .enable_vblank = mdp5_enable_vblank, 224 .disable_vblank = mdp5_disable_vblank, 225 .flush_commit = mdp5_flush_commit, 226 .enable_commit = mdp5_enable_commit, 227 .disable_commit = mdp5_disable_commit, 228 .prepare_commit = mdp5_prepare_commit, 229 .wait_flush = mdp5_wait_flush, 230 .complete_commit = mdp5_complete_commit, 231 .destroy = mdp5_kms_destroy, 232 }, 233 .set_irqmask = mdp5_set_irqmask, 234 }; 235 236 static int mdp5_disable(struct mdp5_kms *mdp5_kms) 237 { 238 DBG(""); 239 240 mdp5_kms->enable_count--; 241 WARN_ON(mdp5_kms->enable_count < 0); 242 243 clk_disable_unprepare(mdp5_kms->tbu_rt_clk); 244 clk_disable_unprepare(mdp5_kms->tbu_clk); 245 clk_disable_unprepare(mdp5_kms->ahb_clk); 246 clk_disable_unprepare(mdp5_kms->axi_clk); 247 clk_disable_unprepare(mdp5_kms->core_clk); 248 clk_disable_unprepare(mdp5_kms->lut_clk); 249 250 return 0; 251 } 252 253 static int mdp5_enable(struct mdp5_kms *mdp5_kms) 254 { 255 DBG(""); 256 257 mdp5_kms->enable_count++; 258 259 clk_prepare_enable(mdp5_kms->ahb_clk); 260 clk_prepare_enable(mdp5_kms->axi_clk); 261 clk_prepare_enable(mdp5_kms->core_clk); 262 clk_prepare_enable(mdp5_kms->lut_clk); 263 clk_prepare_enable(mdp5_kms->tbu_clk); 264 clk_prepare_enable(mdp5_kms->tbu_rt_clk); 265 266 return 0; 267 } 268 269 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 270 struct mdp5_interface *intf, 271 struct mdp5_ctl *ctl) 272 { 273 struct drm_device *dev = mdp5_kms->dev; 274 struct drm_encoder *encoder; 275 276 encoder = mdp5_encoder_init(dev, intf, ctl); 277 if (IS_ERR(encoder)) { 278 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); 279 return encoder; 280 } 281 282 return encoder; 283 } 284 285 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 286 { 287 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 288 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 289 int id = 0, i; 290 291 for (i = 0; i < intf_cnt; i++) { 292 if (intfs[i] == INTF_DSI) { 293 if (intf_num == i) 294 return id; 295 296 id++; 297 } 298 } 299 300 return -EINVAL; 301 } 302 303 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 304 struct mdp5_interface *intf) 305 { 306 struct drm_device *dev = mdp5_kms->dev; 307 struct msm_drm_private *priv = dev->dev_private; 308 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; 309 struct mdp5_ctl *ctl; 310 struct drm_encoder *encoder; 311 int ret = 0; 312 313 switch (intf->type) { 314 case INTF_eDP: 315 DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num); 316 break; 317 case INTF_HDMI: 318 if (!priv->kms->hdmi) 319 break; 320 321 ctl = mdp5_ctlm_request(ctlm, intf->num); 322 if (!ctl) { 323 ret = -EINVAL; 324 break; 325 } 326 327 encoder = construct_encoder(mdp5_kms, intf, ctl); 328 if (IS_ERR(encoder)) { 329 ret = PTR_ERR(encoder); 330 break; 331 } 332 333 ret = msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); 334 break; 335 case INTF_DSI: 336 { 337 const struct mdp5_cfg_hw *hw_cfg = 338 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 339 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); 340 341 if ((dsi_id >= ARRAY_SIZE(priv->kms->dsi)) || (dsi_id < 0)) { 342 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", 343 intf->num); 344 ret = -EINVAL; 345 break; 346 } 347 348 if (!priv->kms->dsi[dsi_id]) 349 break; 350 351 ctl = mdp5_ctlm_request(ctlm, intf->num); 352 if (!ctl) { 353 ret = -EINVAL; 354 break; 355 } 356 357 encoder = construct_encoder(mdp5_kms, intf, ctl); 358 if (IS_ERR(encoder)) { 359 ret = PTR_ERR(encoder); 360 break; 361 } 362 363 ret = msm_dsi_modeset_init(priv->kms->dsi[dsi_id], dev, encoder); 364 if (!ret) 365 mdp5_encoder_set_intf_mode(encoder, 366 msm_dsi_is_cmd_mode(priv->kms->dsi[dsi_id])); 367 368 break; 369 } 370 default: 371 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); 372 ret = -EINVAL; 373 break; 374 } 375 376 return ret; 377 } 378 379 static int modeset_init(struct mdp5_kms *mdp5_kms) 380 { 381 struct drm_device *dev = mdp5_kms->dev; 382 unsigned int num_crtcs; 383 int i, ret, pi = 0, ci = 0; 384 struct drm_plane *primary[MAX_BASES] = { NULL }; 385 struct drm_plane *cursor[MAX_BASES] = { NULL }; 386 struct drm_encoder *encoder; 387 unsigned int num_encoders; 388 389 /* 390 * Construct encoders and modeset initialize connector devices 391 * for each external display interface. 392 */ 393 for (i = 0; i < mdp5_kms->num_intfs; i++) { 394 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); 395 if (ret) 396 goto fail; 397 } 398 399 num_encoders = 0; 400 drm_for_each_encoder(encoder, dev) 401 num_encoders++; 402 403 /* 404 * We should ideally have less number of encoders (set up by parsing 405 * the MDP5 interfaces) than the number of layer mixers present in HW, 406 * but let's be safe here anyway 407 */ 408 num_crtcs = min(num_encoders, mdp5_kms->num_hwmixers); 409 410 /* 411 * Construct planes equaling the number of hw pipes, and CRTCs for the 412 * N encoders set up by the driver. The first N planes become primary 413 * planes for the CRTCs, with the remainder as overlay planes: 414 */ 415 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 416 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; 417 struct drm_plane *plane; 418 enum drm_plane_type type; 419 420 if (i < num_crtcs) 421 type = DRM_PLANE_TYPE_PRIMARY; 422 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) 423 type = DRM_PLANE_TYPE_CURSOR; 424 else 425 type = DRM_PLANE_TYPE_OVERLAY; 426 427 plane = mdp5_plane_init(dev, type); 428 if (IS_ERR(plane)) { 429 ret = PTR_ERR(plane); 430 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); 431 goto fail; 432 } 433 434 if (type == DRM_PLANE_TYPE_PRIMARY) 435 primary[pi++] = plane; 436 if (type == DRM_PLANE_TYPE_CURSOR) 437 cursor[ci++] = plane; 438 } 439 440 for (i = 0; i < num_crtcs; i++) { 441 struct drm_crtc *crtc; 442 443 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); 444 if (IS_ERR(crtc)) { 445 ret = PTR_ERR(crtc); 446 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); 447 goto fail; 448 } 449 } 450 451 /* 452 * Now that we know the number of crtcs we've created, set the possible 453 * crtcs for the encoders 454 */ 455 drm_for_each_encoder(encoder, dev) 456 encoder->possible_crtcs = (1 << dev->mode_config.num_crtc) - 1; 457 458 return 0; 459 460 fail: 461 return ret; 462 } 463 464 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, 465 u32 *major, u32 *minor) 466 { 467 struct device *dev = &mdp5_kms->pdev->dev; 468 u32 version; 469 470 pm_runtime_get_sync(dev); 471 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); 472 pm_runtime_put_sync(dev); 473 474 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); 475 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); 476 477 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); 478 } 479 480 static int get_clk(struct platform_device *pdev, struct clk **clkp, 481 const char *name, bool mandatory) 482 { 483 struct device *dev = &pdev->dev; 484 struct clk *clk = msm_clk_get(pdev, name); 485 if (IS_ERR(clk) && mandatory) { 486 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 487 return PTR_ERR(clk); 488 } 489 if (IS_ERR(clk)) 490 DBG("skipping %s", name); 491 else 492 *clkp = clk; 493 494 return 0; 495 } 496 497 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev); 498 499 static int mdp5_kms_init(struct drm_device *dev) 500 { 501 struct msm_drm_private *priv = dev->dev_private; 502 struct platform_device *pdev; 503 struct mdp5_kms *mdp5_kms; 504 struct mdp5_cfg *config; 505 struct msm_kms *kms = priv->kms; 506 struct drm_gpuvm *vm; 507 int i, ret; 508 509 ret = mdp5_init(to_platform_device(dev->dev), dev); 510 if (ret) 511 return ret; 512 513 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 514 515 pdev = mdp5_kms->pdev; 516 517 ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs); 518 if (ret) { 519 DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n"); 520 goto fail; 521 } 522 523 config = mdp5_cfg_get_config(mdp5_kms->cfg); 524 525 /* make sure things are off before attaching iommu (bootloader could 526 * have left things on, in which case we'll start getting faults if 527 * we don't disable): 528 */ 529 pm_runtime_get_sync(&pdev->dev); 530 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 531 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 532 !config->hw->intf.base[i]) 533 continue; 534 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 535 536 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); 537 } 538 mdelay(16); 539 540 vm = msm_kms_init_vm(mdp5_kms->dev, pdev->dev.parent); 541 if (IS_ERR(vm)) { 542 ret = PTR_ERR(vm); 543 goto fail; 544 } 545 546 kms->vm = vm; 547 548 pm_runtime_put_sync(&pdev->dev); 549 550 ret = modeset_init(mdp5_kms); 551 if (ret) { 552 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); 553 goto fail; 554 } 555 556 dev->mode_config.min_width = 0; 557 dev->mode_config.min_height = 0; 558 dev->mode_config.max_width = 0xffff; 559 dev->mode_config.max_height = 0xffff; 560 561 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ 562 dev->vblank_disable_immediate = true; 563 564 return 0; 565 fail: 566 if (kms) 567 mdp5_kms_destroy(kms); 568 569 return ret; 570 } 571 572 static void mdp5_destroy(struct mdp5_kms *mdp5_kms) 573 { 574 if (mdp5_kms->rpm_enabled) 575 pm_runtime_disable(&mdp5_kms->pdev->dev); 576 577 drm_atomic_private_obj_fini(&mdp5_kms->glob_state); 578 } 579 580 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, 581 const enum mdp5_pipe *pipes, const uint32_t *offsets, 582 uint32_t caps) 583 { 584 struct drm_device *dev = mdp5_kms->dev; 585 int i, ret; 586 587 for (i = 0; i < cnt; i++) { 588 struct mdp5_hw_pipe *hwpipe; 589 590 hwpipe = mdp5_pipe_init(dev, pipes[i], offsets[i], caps); 591 if (IS_ERR(hwpipe)) { 592 ret = PTR_ERR(hwpipe); 593 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", 594 pipe2name(pipes[i]), ret); 595 return ret; 596 } 597 hwpipe->idx = mdp5_kms->num_hwpipes; 598 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; 599 } 600 601 return 0; 602 } 603 604 static int hwpipe_init(struct mdp5_kms *mdp5_kms) 605 { 606 static const enum mdp5_pipe rgb_planes[] = { 607 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 608 }; 609 static const enum mdp5_pipe vig_planes[] = { 610 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 611 }; 612 static const enum mdp5_pipe dma_planes[] = { 613 SSPP_DMA0, SSPP_DMA1, 614 }; 615 static const enum mdp5_pipe cursor_planes[] = { 616 SSPP_CURSOR0, SSPP_CURSOR1, 617 }; 618 const struct mdp5_cfg_hw *hw_cfg; 619 int ret; 620 621 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 622 623 /* Construct RGB pipes: */ 624 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, 625 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); 626 if (ret) 627 return ret; 628 629 /* Construct video (VIG) pipes: */ 630 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, 631 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); 632 if (ret) 633 return ret; 634 635 /* Construct DMA pipes: */ 636 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, 637 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); 638 if (ret) 639 return ret; 640 641 /* Construct cursor pipes: */ 642 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, 643 cursor_planes, hw_cfg->pipe_cursor.base, 644 hw_cfg->pipe_cursor.caps); 645 if (ret) 646 return ret; 647 648 return 0; 649 } 650 651 static int hwmixer_init(struct mdp5_kms *mdp5_kms) 652 { 653 struct drm_device *dev = mdp5_kms->dev; 654 const struct mdp5_cfg_hw *hw_cfg; 655 int i, ret; 656 657 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 658 659 for (i = 0; i < hw_cfg->lm.count; i++) { 660 struct mdp5_hw_mixer *mixer; 661 662 mixer = mdp5_mixer_init(dev, &hw_cfg->lm.instances[i]); 663 if (IS_ERR(mixer)) { 664 ret = PTR_ERR(mixer); 665 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", 666 i, ret); 667 return ret; 668 } 669 670 mixer->idx = mdp5_kms->num_hwmixers; 671 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; 672 } 673 674 return 0; 675 } 676 677 static int interface_init(struct mdp5_kms *mdp5_kms) 678 { 679 struct drm_device *dev = mdp5_kms->dev; 680 const struct mdp5_cfg_hw *hw_cfg; 681 const enum mdp5_intf_type *intf_types; 682 int i; 683 684 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 685 intf_types = hw_cfg->intf.connect; 686 687 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 688 struct mdp5_interface *intf; 689 690 if (intf_types[i] == INTF_DISABLED) 691 continue; 692 693 intf = devm_kzalloc(dev->dev, sizeof(*intf), GFP_KERNEL); 694 if (!intf) { 695 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); 696 return -ENOMEM; 697 } 698 699 intf->num = i; 700 intf->type = intf_types[i]; 701 intf->mode = MDP5_INTF_MODE_NONE; 702 intf->idx = mdp5_kms->num_intfs; 703 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; 704 } 705 706 return 0; 707 } 708 709 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) 710 { 711 struct msm_drm_private *priv = dev->dev_private; 712 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 713 struct mdp5_cfg *config; 714 u32 major, minor; 715 int ret; 716 717 mdp5_kms->dev = dev; 718 719 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, 720 &mdp5_global_state_funcs); 721 722 /* we need to set a default rate before enabling. Set a safe 723 * rate first, then figure out hw revision, and then set a 724 * more optimal rate: 725 */ 726 clk_set_rate(mdp5_kms->core_clk, 200000000); 727 728 pm_runtime_enable(&pdev->dev); 729 mdp5_kms->rpm_enabled = true; 730 731 read_mdp_hw_revision(mdp5_kms, &major, &minor); 732 733 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 734 if (IS_ERR(mdp5_kms->cfg)) { 735 ret = PTR_ERR(mdp5_kms->cfg); 736 mdp5_kms->cfg = NULL; 737 goto fail; 738 } 739 740 config = mdp5_cfg_get_config(mdp5_kms->cfg); 741 mdp5_kms->caps = config->hw->mdp.caps; 742 743 /* TODO: compute core clock rate at runtime */ 744 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); 745 746 /* 747 * Some chipsets have a Shared Memory Pool (SMP), while others 748 * have dedicated latency buffering per source pipe instead; 749 * this section initializes the SMP: 750 */ 751 if (mdp5_kms->caps & MDP_CAP_SMP) { 752 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); 753 if (IS_ERR(mdp5_kms->smp)) { 754 ret = PTR_ERR(mdp5_kms->smp); 755 mdp5_kms->smp = NULL; 756 goto fail; 757 } 758 } 759 760 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 761 if (IS_ERR(mdp5_kms->ctlm)) { 762 ret = PTR_ERR(mdp5_kms->ctlm); 763 mdp5_kms->ctlm = NULL; 764 goto fail; 765 } 766 767 ret = hwpipe_init(mdp5_kms); 768 if (ret) 769 goto fail; 770 771 ret = hwmixer_init(mdp5_kms); 772 if (ret) 773 goto fail; 774 775 ret = interface_init(mdp5_kms); 776 if (ret) 777 goto fail; 778 779 return 0; 780 fail: 781 mdp5_destroy(mdp5_kms); 782 return ret; 783 } 784 785 static int mdp5_setup_interconnect(struct platform_device *pdev) 786 { 787 struct icc_path *path0 = msm_icc_get(&pdev->dev, "mdp0-mem"); 788 struct icc_path *path1 = msm_icc_get(&pdev->dev, "mdp1-mem"); 789 struct icc_path *path_rot = msm_icc_get(&pdev->dev, "rotator-mem"); 790 791 if (IS_ERR(path0)) 792 return PTR_ERR(path0); 793 794 if (!path0) { 795 /* no interconnect support is not necessarily a fatal 796 * condition, the platform may simply not have an 797 * interconnect driver yet. But warn about it in case 798 * bootloader didn't setup bus clocks high enough for 799 * scanout. 800 */ 801 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); 802 return 0; 803 } 804 805 icc_set_bw(path0, 0, MBps_to_icc(6400)); 806 807 if (!IS_ERR_OR_NULL(path1)) 808 icc_set_bw(path1, 0, MBps_to_icc(6400)); 809 if (!IS_ERR_OR_NULL(path_rot)) 810 icc_set_bw(path_rot, 0, MBps_to_icc(6400)); 811 812 return 0; 813 } 814 815 static int mdp5_dev_probe(struct platform_device *pdev) 816 { 817 struct mdp5_kms *mdp5_kms; 818 int ret, irq; 819 820 DBG(""); 821 822 if (!msm_disp_drv_should_bind(&pdev->dev, false)) 823 return -ENODEV; 824 825 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); 826 if (!mdp5_kms) 827 return -ENOMEM; 828 829 ret = mdp5_setup_interconnect(pdev); 830 if (ret) 831 return ret; 832 833 mdp5_kms->pdev = pdev; 834 835 spin_lock_init(&mdp5_kms->resource_lock); 836 837 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys"); 838 if (IS_ERR(mdp5_kms->mmio)) 839 return PTR_ERR(mdp5_kms->mmio); 840 841 /* mandatory clocks: */ 842 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); 843 if (ret) 844 return ret; 845 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); 846 if (ret) 847 return ret; 848 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); 849 if (ret) 850 return ret; 851 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); 852 if (ret) 853 return ret; 854 855 /* optional clocks: */ 856 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); 857 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); 858 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); 859 860 irq = platform_get_irq(pdev, 0); 861 if (irq < 0) 862 return dev_err_probe(&pdev->dev, irq, "failed to get irq\n"); 863 864 mdp5_kms->base.base.irq = irq; 865 866 return msm_drv_probe(&pdev->dev, mdp5_kms_init, &mdp5_kms->base.base); 867 } 868 869 static void mdp5_dev_remove(struct platform_device *pdev) 870 { 871 DBG(""); 872 component_master_del(&pdev->dev, &msm_drm_ops); 873 } 874 875 static __maybe_unused int mdp5_runtime_suspend(struct device *dev) 876 { 877 struct platform_device *pdev = to_platform_device(dev); 878 struct msm_drm_private *priv = platform_get_drvdata(pdev); 879 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 880 881 DBG(""); 882 883 return mdp5_disable(mdp5_kms); 884 } 885 886 static __maybe_unused int mdp5_runtime_resume(struct device *dev) 887 { 888 struct platform_device *pdev = to_platform_device(dev); 889 struct msm_drm_private *priv = platform_get_drvdata(pdev); 890 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 891 892 DBG(""); 893 894 return mdp5_enable(mdp5_kms); 895 } 896 897 static const struct dev_pm_ops mdp5_pm_ops = { 898 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) 899 .prepare = msm_kms_pm_prepare, 900 .complete = msm_kms_pm_complete, 901 }; 902 903 static const struct of_device_id mdp5_dt_match[] = { 904 { .compatible = "qcom,mdp5", }, 905 /* to support downstream DT files */ 906 { .compatible = "qcom,mdss_mdp", }, 907 {} 908 }; 909 MODULE_DEVICE_TABLE(of, mdp5_dt_match); 910 911 static struct platform_driver mdp5_driver = { 912 .probe = mdp5_dev_probe, 913 .remove = mdp5_dev_remove, 914 .shutdown = msm_kms_shutdown, 915 .driver = { 916 .name = "msm_mdp", 917 .of_match_table = mdp5_dt_match, 918 .pm = &mdp5_pm_ops, 919 }, 920 }; 921 922 void __init msm_mdp_register(void) 923 { 924 DBG(""); 925 platform_driver_register(&mdp5_driver); 926 } 927 928 void __exit msm_mdp_unregister(void) 929 { 930 DBG(""); 931 platform_driver_unregister(&mdp5_driver); 932 } 933