1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * drivers/net/ethernet/ibm/emac/core.h 4 * 5 * Driver for PowerPC 4xx on-chip ethernet controller. 6 * 7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 8 * <benh@kernel.crashing.org> 9 * 10 * Based on the arch/ppc version of the driver: 11 * 12 * Copyright (c) 2004, 2005 Zultys Technologies. 13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 14 * 15 * Based on original work by 16 * Armin Kuster <akuster@mvista.com> 17 * Johnnie Peters <jpeters@mvista.com> 18 * Copyright 2000, 2001 MontaVista Softare Inc. 19 */ 20 #ifndef __IBM_NEWEMAC_CORE_H 21 #define __IBM_NEWEMAC_CORE_H 22 23 #include <linux/module.h> 24 #include <linux/list.h> 25 #include <linux/kernel.h> 26 #include <linux/interrupt.h> 27 #include <linux/netdevice.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/spinlock.h> 30 #include <linux/slab.h> 31 32 #include <asm/io.h> 33 #include <asm/dcr.h> 34 35 #include "emac.h" 36 #include "phy.h" 37 #include "zmii.h" 38 #include "rgmii.h" 39 #include "mal.h" 40 #include "tah.h" 41 #include "debug.h" 42 43 #define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB 44 #define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB 45 46 /* Simple sanity check */ 47 #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256 48 #error Invalid number of buffer descriptors (greater than 256) 49 #endif 50 51 #define EMAC_MIN_MTU 46 52 53 /* Maximum L2 header length (VLAN tagged, no FCS) */ 54 #define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4) 55 56 /* RX BD size for the given MTU */ 57 static inline int emac_rx_size(int mtu) 58 { 59 return mal_rx_size(max(mtu, ETH_DATA_LEN) + EMAC_MTU_OVERHEAD); 60 } 61 62 /* Size of RX skb for the given MTU */ 63 static inline int emac_rx_skb_size(int mtu) 64 { 65 int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu)); 66 67 return SKB_DATA_ALIGN(size + NET_IP_ALIGN) + NET_SKB_PAD; 68 } 69 70 /* RX DMA sync size */ 71 static inline int emac_rx_sync_size(int mtu) 72 { 73 return SKB_DATA_ALIGN(emac_rx_size(mtu) + NET_IP_ALIGN); 74 } 75 76 /* Driver statistcs is split into two parts to make it more cache friendly: 77 * - normal statistics (packet count, etc) 78 * - error statistics 79 * 80 * When statistics is requested by ethtool, these parts are concatenated, 81 * normal one goes first. 82 * 83 * Please, keep these structures in sync with emac_stats_keys. 84 */ 85 86 /* Normal TX/RX Statistics */ 87 struct emac_stats { 88 u64 rx_packets; 89 u64 rx_bytes; 90 u64 tx_packets; 91 u64 tx_bytes; 92 u64 rx_packets_csum; 93 u64 tx_packets_csum; 94 }; 95 96 /* Error statistics */ 97 struct emac_error_stats { 98 u64 tx_undo; 99 100 /* Software RX Errors */ 101 u64 rx_dropped_stack; 102 u64 rx_dropped_oom; 103 u64 rx_dropped_error; 104 u64 rx_dropped_resize; 105 u64 rx_dropped_mtu; 106 u64 rx_stopped; 107 /* BD reported RX errors */ 108 u64 rx_bd_errors; 109 u64 rx_bd_overrun; 110 u64 rx_bd_bad_packet; 111 u64 rx_bd_runt_packet; 112 u64 rx_bd_short_event; 113 u64 rx_bd_alignment_error; 114 u64 rx_bd_bad_fcs; 115 u64 rx_bd_packet_too_long; 116 u64 rx_bd_out_of_range; 117 u64 rx_bd_in_range; 118 /* EMAC IRQ reported RX errors */ 119 u64 rx_parity; 120 u64 rx_fifo_overrun; 121 u64 rx_overrun; 122 u64 rx_bad_packet; 123 u64 rx_runt_packet; 124 u64 rx_short_event; 125 u64 rx_alignment_error; 126 u64 rx_bad_fcs; 127 u64 rx_packet_too_long; 128 u64 rx_out_of_range; 129 u64 rx_in_range; 130 131 /* Software TX Errors */ 132 u64 tx_dropped; 133 /* BD reported TX errors */ 134 u64 tx_bd_errors; 135 u64 tx_bd_bad_fcs; 136 u64 tx_bd_carrier_loss; 137 u64 tx_bd_excessive_deferral; 138 u64 tx_bd_excessive_collisions; 139 u64 tx_bd_late_collision; 140 u64 tx_bd_multple_collisions; 141 u64 tx_bd_single_collision; 142 u64 tx_bd_underrun; 143 u64 tx_bd_sqe; 144 /* EMAC IRQ reported TX errors */ 145 u64 tx_parity; 146 u64 tx_underrun; 147 u64 tx_sqe; 148 u64 tx_errors; 149 }; 150 151 #define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \ 152 sizeof(struct emac_error_stats)) \ 153 / sizeof(u64)) 154 155 struct emac_instance { 156 struct net_device *ndev; 157 struct emac_regs __iomem *emacp; 158 struct platform_device *ofdev; 159 struct device_node **blist; /* bootlist entry */ 160 161 /* MAL linkage */ 162 u32 mal_ph; 163 struct platform_device *mal_dev; 164 u32 mal_rx_chan; 165 u32 mal_tx_chan; 166 struct mal_instance *mal; 167 struct mal_commac commac; 168 169 /* PHY infos */ 170 phy_interface_t phy_mode; 171 u32 phy_map; 172 u32 phy_address; 173 u32 phy_feat_exc; 174 struct mii_phy phy; 175 struct mutex link_lock; 176 struct delayed_work link_work; 177 int link_polling; 178 179 /* GPCS PHY infos */ 180 u32 gpcs_address; 181 182 /* Shared MDIO if any */ 183 u32 mdio_ph; 184 struct platform_device *mdio_dev; 185 struct emac_instance *mdio_instance; 186 struct mutex mdio_lock; 187 188 /* ZMII infos if any */ 189 u32 zmii_ph; 190 u32 zmii_port; 191 struct platform_device *zmii_dev; 192 193 /* RGMII infos if any */ 194 u32 rgmii_ph; 195 u32 rgmii_port; 196 struct platform_device *rgmii_dev; 197 198 /* TAH infos if any */ 199 u32 tah_ph; 200 u32 tah_port; 201 struct platform_device *tah_dev; 202 203 /* IRQs */ 204 int wol_irq; 205 int emac_irq; 206 207 /* OPB bus frequency in Mhz */ 208 u32 opb_bus_freq; 209 210 /* Cell index within an ASIC (for clk mgmnt) */ 211 u32 cell_index; 212 213 /* Max supported MTU */ 214 u32 max_mtu; 215 216 /* Feature bits (from probe table) */ 217 unsigned int features; 218 219 /* Tx and Rx fifo sizes & other infos in bytes */ 220 u32 tx_fifo_size; 221 u32 tx_fifo_size_gige; 222 u32 rx_fifo_size; 223 u32 rx_fifo_size_gige; 224 u32 fifo_entry_size; 225 u32 mal_burst_size; /* move to MAL ? */ 226 227 /* IAHT and GAHT filter parameterization */ 228 u32 xaht_slots_shift; 229 u32 xaht_width_shift; 230 231 /* Descriptor management 232 */ 233 struct mal_descriptor *tx_desc; 234 int tx_cnt; 235 int tx_slot; 236 int ack_slot; 237 238 struct mal_descriptor *rx_desc; 239 int rx_slot; 240 struct sk_buff *rx_sg_skb; /* 1 */ 241 int rx_skb_size; 242 int rx_sync_size; 243 244 struct sk_buff *tx_skb[NUM_TX_BUFF]; 245 struct sk_buff *rx_skb[NUM_RX_BUFF]; 246 247 /* Stats 248 */ 249 struct emac_error_stats estats; 250 struct emac_stats stats; 251 252 /* Misc 253 */ 254 int reset_failed; 255 int stop_timeout; /* in us */ 256 int no_mcast; 257 int mcast_pending; 258 int opened; 259 struct work_struct reset_work; 260 spinlock_t lock; 261 }; 262 263 /* 264 * Features of various EMAC implementations 265 */ 266 267 /* 268 * No flow control on 40x according to the original driver 269 */ 270 #define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001 271 /* 272 * Cell is an EMAC4 273 */ 274 #define EMAC_FTR_EMAC4 0x00000002 275 /* 276 * For the 440SPe, AMCC inexplicably changed the polarity of 277 * the "operation complete" bit in the MII control register. 278 */ 279 #define EMAC_FTR_STACR_OC_INVERT 0x00000004 280 /* 281 * Set if we have a TAH. 282 */ 283 #define EMAC_FTR_HAS_TAH 0x00000008 284 /* 285 * Set if we have a ZMII. 286 */ 287 #define EMAC_FTR_HAS_ZMII 0x00000010 288 /* 289 * Set if we have a RGMII. 290 */ 291 #define EMAC_FTR_HAS_RGMII 0x00000020 292 /* 293 * Set if we have new type STACR with STAOPC 294 */ 295 #define EMAC_FTR_HAS_NEW_STACR 0x00000040 296 /* 297 * Set if we need phy clock workaround for 440gx 298 */ 299 #define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080 300 /* 301 * Set if we need phy clock workaround for 440ep or 440gr 302 */ 303 #define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100 304 /* 305 * The 405EX and 460EX contain the EMAC4SYNC core 306 */ 307 #define EMAC_FTR_EMAC4SYNC 0x00000200 308 /* 309 * Set if we need phy clock workaround for 460ex or 460gt 310 */ 311 #define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400 312 /* 313 * APM821xx requires Jumbo frame size set explicitly 314 */ 315 #define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE 0x00000800 316 /* 317 * APM821xx does not support Half Duplex mode 318 */ 319 #define EMAC_FTR_APM821XX_NO_HALF_DUPLEX 0x00001000 320 321 /* Right now, we don't quite handle the always/possible masks on the 322 * most optimal way as we don't have a way to say something like 323 * always EMAC4. Patches welcome. 324 */ 325 enum { 326 EMAC_FTRS_ALWAYS = 0, 327 328 EMAC_FTRS_POSSIBLE = 329 #ifdef CONFIG_IBM_EMAC_EMAC4 330 EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC | 331 EMAC_FTR_HAS_NEW_STACR | 332 EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX | 333 #endif 334 #ifdef CONFIG_IBM_EMAC_TAH 335 EMAC_FTR_HAS_TAH | 336 #endif 337 #ifdef CONFIG_IBM_EMAC_ZMII 338 EMAC_FTR_HAS_ZMII | 339 #endif 340 #ifdef CONFIG_IBM_EMAC_RGMII 341 EMAC_FTR_HAS_RGMII | 342 #endif 343 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL 344 EMAC_FTR_NO_FLOW_CONTROL_40x | 345 #endif 346 EMAC_FTR_460EX_PHY_CLK_FIX | 347 EMAC_FTR_440EP_PHY_CLK_FIX | 348 EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE | 349 EMAC_FTR_APM821XX_NO_HALF_DUPLEX, 350 }; 351 352 static inline int emac_has_feature(struct emac_instance *dev, 353 unsigned long feature) 354 { 355 return (EMAC_FTRS_ALWAYS & feature) || 356 (EMAC_FTRS_POSSIBLE & dev->features & feature); 357 } 358 359 /* 360 * Various instances of the EMAC core have varying 1) number of 361 * address match slots, 2) width of the registers for handling address 362 * match slots, 3) number of registers for handling address match 363 * slots and 4) base offset for those registers. 364 * 365 * These macros and inlines handle these differences based on 366 * parameters supplied by the device structure which are, in turn, 367 * initialized based on the "compatible" entry in the device tree. 368 */ 369 370 #define EMAC4_XAHT_SLOTS_SHIFT 6 371 #define EMAC4_XAHT_WIDTH_SHIFT 4 372 373 #define EMAC4SYNC_XAHT_SLOTS_SHIFT 8 374 #define EMAC4SYNC_XAHT_WIDTH_SHIFT 5 375 376 /* The largest span between slots and widths above is 3 */ 377 #define EMAC_XAHT_MAX_REGS (1 << 3) 378 379 #define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift) 380 #define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift) 381 #define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \ 382 (dev)->xaht_width_shift)) 383 384 #define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \ 385 ((EMAC_XAHT_SLOTS(dev) - 1) - \ 386 ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \ 387 (dev)->xaht_slots_shift))) 388 389 #define EMAC_XAHT_SLOT_TO_REG(dev, slot) \ 390 ((slot) >> (dev)->xaht_width_shift) 391 392 #define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \ 393 ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \ 394 ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1))) 395 396 static inline u32 __iomem *emac_xaht_base(struct emac_instance *dev) 397 { 398 struct emac_regs __iomem *p = dev->emacp; 399 int offset; 400 401 /* The first IAHT entry always is the base of the block of 402 * IAHT and GAHT registers. 403 */ 404 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) 405 offset = offsetof(struct emac_regs, u1.emac4sync.iaht1); 406 else 407 offset = offsetof(struct emac_regs, u0.emac4.iaht1); 408 409 return (u32 __iomem *)((__force ptrdiff_t)p + offset); 410 } 411 412 static inline u32 __iomem *emac_gaht_base(struct emac_instance *dev) 413 { 414 /* GAHT registers always come after an identical number of 415 * IAHT registers. 416 */ 417 return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev); 418 } 419 420 static inline u32 *emac_iaht_base(struct emac_instance *dev) 421 { 422 /* IAHT registers always come before an identical number of 423 * GAHT registers. 424 */ 425 return emac_xaht_base(dev); 426 } 427 428 /* Ethtool get_regs complex data. 429 * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH 430 * when available. 431 * 432 * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr, 433 * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers. 434 * Each register component is preceded with emac_ethtool_regs_subhdr. 435 * Order of the optional headers follows their relative bit posititions 436 * in emac_ethtool_regs_hdr.components 437 */ 438 #define EMAC_ETHTOOL_REGS_ZMII 0x00000001 439 #define EMAC_ETHTOOL_REGS_RGMII 0x00000002 440 #define EMAC_ETHTOOL_REGS_TAH 0x00000004 441 442 struct emac_ethtool_regs_hdr { 443 u32 components; 444 }; 445 446 struct emac_ethtool_regs_subhdr { 447 u32 version; 448 u32 index; 449 }; 450 451 #define EMAC_ETHTOOL_REGS_VER 3 452 #define EMAC4_ETHTOOL_REGS_VER 4 453 #define EMAC4SYNC_ETHTOOL_REGS_VER 5 454 455 #endif /* __IBM_NEWEMAC_CORE_H */ 456