1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
4 *
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
6 *
7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
9 * Based on max3107.c, by Aavamobile
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bitops.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/property.h>
21 #include <linux/regmap.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/spi/spi.h>
27 #include <linux/uaccess.h>
28
29 #define MAX310X_NAME "max310x"
30 #define MAX310X_MAJOR 204
31 #define MAX310X_MINOR 209
32 #define MAX310X_UART_NRMAX 16
33 #define MAX310X_MAX_PORTS 4 /* Maximum number of UART ports per IC. */
34
35 /* MAX310X register definitions */
36 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
37 #define MAX310X_THR_REG (0x00) /* TX FIFO */
38 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
39 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
40 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
41 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
42 #define MAX310X_REG_05 (0x05)
43 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
44 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
45 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
46 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
47 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
48 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
49 #define MAX310X_LCR_REG (0x0b) /* LCR */
50 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
51 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
52 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
53 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
54 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
55 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
56 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
57 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
58 #define MAX310X_XON1_REG (0x14) /* XON1 character */
59 #define MAX310X_XON2_REG (0x15) /* XON2 character */
60 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
61 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
62 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
63 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
64 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
65 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
66 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
67 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
68 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
69 #define MAX310X_REG_1F (0x1f)
70 #define MAX310X_EXTREG_START (0x20) /* Only relevant in SPI mode. */
71
72 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
73
74 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
75 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
76
77 /* Extended registers */
78 #define MAX310X_REVID_EXTREG (0x25) /* Revision ID
79 * (extended addressing space)
80 */
81 /* IRQ register bits */
82 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
83 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
84 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
85 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
86 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
87 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
88 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
89 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
90
91 /* LSR register bits */
92 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
93 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
94 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
95 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
96 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
97 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
98 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
99
100 /* Special character register bits */
101 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
102 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
103 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
104 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
105 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
106 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
107
108 /* Status register bits */
109 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
110 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
111 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
112 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
113 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
114 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
115
116 /* MODE1 register bits */
117 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
118 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
119 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
120 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
121 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
122 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
123 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
124 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
125
126 /* MODE2 register bits */
127 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
128 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
129 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
130 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
131 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
132 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
133 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
134 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
135
136 /* LCR register bits */
137 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
138 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
139 *
140 * Word length bits table:
141 * 00 -> 5 bit words
142 * 01 -> 6 bit words
143 * 10 -> 7 bit words
144 * 11 -> 8 bit words
145 */
146 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
147 *
148 * STOP length bit table:
149 * 0 -> 1 stop bit
150 * 1 -> 1-1.5 stop bits if
151 * word length is 5,
152 * 2 stop bits otherwise
153 */
154 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
155 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
156 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
157 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
158 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
159
160 /* IRDA register bits */
161 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
162 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
163
164 /* Flow control trigger level register masks */
165 #define MAX310X_FLOWLVL_HALT_MASK GENMASK(3, 0) /* Flow control halt level */
166 #define MAX310X_FLOWLVL_RES_MASK GENMASK(7, 4) /* Flow control resume level */
167 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
168 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
169
170 /* FIFO interrupt trigger level register masks */
171 #define MAX310X_FIFOTRIGLVL_TX_MASK GENMASK(3, 0) /* TX FIFO trigger level */
172 #define MAX310X_FIFOTRIGLVL_RX_MASK GENMASK(7, 4) /* RX FIFO trigger level */
173 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
174 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
175
176 /* Flow control register bits */
177 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
178 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
179 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
180 * are used in conjunction with
181 * XOFF2 for definition of
182 * special character
183 */
184 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
185 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
186 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
187 *
188 * SWFLOW bits 1 & 0 table:
189 * 00 -> no transmitter flow
190 * control
191 * 01 -> receiver compares
192 * XON2 and XOFF2
193 * and controls
194 * transmitter
195 * 10 -> receiver compares
196 * XON1 and XOFF1
197 * and controls
198 * transmitter
199 * 11 -> receiver compares
200 * XON1, XON2, XOFF1 and
201 * XOFF2 and controls
202 * transmitter
203 */
204 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
205 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
206 *
207 * SWFLOW bits 3 & 2 table:
208 * 00 -> no received flow
209 * control
210 * 01 -> transmitter generates
211 * XON2 and XOFF2
212 * 10 -> transmitter generates
213 * XON1 and XOFF1
214 * 11 -> transmitter generates
215 * XON1, XON2, XOFF1 and
216 * XOFF2
217 */
218
219 /* PLL configuration register masks */
220 #define MAX310X_PLLCFG_PREDIV_MASK GENMASK(5, 0) /* PLL predivision value */
221 #define MAX310X_PLLCFG_PLLFACTOR_MASK GENMASK(7, 6) /* PLL multiplication factor */
222
223 /* Baud rate generator configuration register bits */
224 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
225 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
226
227 /* Clock source register bits */
228 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
229 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
230 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
231 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
232 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
233
234 /* Global commands */
235 #define MAX310X_EXTREG_ENBL (0xce)
236 #define MAX310X_EXTREG_DSBL (0xcd)
237
238 /* Misc definitions */
239 #define MAX310X_FIFO_SIZE (128)
240 #define MAX310x_REV_MASK GENMASK(7, 3)
241 #define MAX310X_WRITE_BIT 0x80
242
243 /* Port startup definitions */
244 #define MAX310X_PORT_STARTUP_SLEEP_US 10000 /* Delay between retries */
245 #define MAX310X_PORT_STARTUP_TIMEOUT_US (20 * MAX310X_PORT_STARTUP_SLEEP_US) /* Total timeout */
246
247 /* Crystal-related definitions */
248 #define MAX310X_XTAL_SLEEP_US 10000 /* Delay between retries */
249 #define MAX310X_XTAL_TIMEOUT_US (20 * MAX310X_XTAL_SLEEP_US) /* Total timeout */
250
251 /* MAX3107 specific */
252 #define MAX3107_REV_ID (0xa0)
253
254 /* MAX3109 specific */
255 #define MAX3109_REV_ID (0xc0)
256
257 /* MAX14830 specific */
258 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
259 #define MAX14830_REV_ID (0xb0)
260
261 struct max310x_clk_config_t {
262 u8 prediv; /* Predivider */
263 u8 pll_mult; /* PLL multiplier */
264 unsigned int fref; /*
265 * Reference clock for fractional baud rate generator:
266 * PLL enabled: (freq / prediv) x pll_mult
267 * PLL disabled: freq
268 */
269 unsigned int err; /* Computed error for selected parameters */
270 };
271
272 struct max310x_if_cfg {
273 int (*extended_reg_enable)(struct device *dev, bool enable);
274 u8 rev_id_offset;
275 };
276
277 struct max310x_devtype {
278 struct {
279 unsigned short min;
280 unsigned short max;
281 } slave_addr; /* Relevant only in I2C mode. */
282 int nr;
283 char name[9];
284 u8 mode1;
285 u8 rev_id_val;
286 u8 rev_id_reg; /* Relevant only if rev_id_val is defined. */
287 u8 power_reg; /* Register address for power/sleep control. */
288 u8 power_bit; /* Bit for sleep or power-off mode (active high). */
289 };
290
291 struct max310x_one {
292 struct uart_port port;
293 struct work_struct tx_work;
294 struct work_struct md_work;
295 struct work_struct rs_work;
296 struct regmap *regmap;
297
298 u8 rx_buf[MAX310X_FIFO_SIZE];
299 };
300 #define to_max310x_port(_port) \
301 container_of(_port, struct max310x_one, port)
302
303 struct max310x_port {
304 const struct max310x_devtype *devtype;
305 const struct max310x_if_cfg *if_cfg;
306 struct regmap *regmap;
307 struct clk *clk;
308 #ifdef CONFIG_GPIOLIB
309 struct gpio_chip gpio;
310 #endif
311 struct max310x_one p[];
312 };
313
314 static struct uart_driver max310x_uart = {
315 .owner = THIS_MODULE,
316 .driver_name = MAX310X_NAME,
317 .dev_name = "ttyMAX",
318 .major = MAX310X_MAJOR,
319 .minor = MAX310X_MINOR,
320 .nr = MAX310X_UART_NRMAX,
321 };
322
323 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
324
max310x_port_read(struct uart_port * port,u8 reg)325 static u8 max310x_port_read(struct uart_port *port, u8 reg)
326 {
327 struct max310x_one *one = to_max310x_port(port);
328 unsigned int val = 0;
329
330 regmap_read(one->regmap, reg, &val);
331
332 return val;
333 }
334
max310x_port_write(struct uart_port * port,u8 reg,u8 val)335 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
336 {
337 struct max310x_one *one = to_max310x_port(port);
338
339 regmap_write(one->regmap, reg, val);
340 }
341
max310x_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)342 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
343 {
344 struct max310x_one *one = to_max310x_port(port);
345
346 regmap_update_bits(one->regmap, reg, mask, val);
347 }
348
max310x_detect(struct device * dev)349 static int max310x_detect(struct device *dev)
350 {
351 struct max310x_port *s = dev_get_drvdata(dev);
352 unsigned int val = 0;
353 int ret;
354
355 /* Check if variant supports REV ID register: */
356 if (s->devtype->rev_id_val) {
357 u8 rev_id_reg = s->devtype->rev_id_reg;
358
359 /* Check if REV ID is in extended addressing space: */
360 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) {
361 ret = s->if_cfg->extended_reg_enable(dev, true);
362 if (ret)
363 return ret;
364
365 /* Adjust REV ID extended addressing space address: */
366 if (s->if_cfg->rev_id_offset)
367 rev_id_reg -= s->if_cfg->rev_id_offset;
368 }
369
370 regmap_read(s->regmap, rev_id_reg, &val);
371
372 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) {
373 ret = s->if_cfg->extended_reg_enable(dev, false);
374 if (ret)
375 return ret;
376 }
377
378 if (((val & MAX310x_REV_MASK) != s->devtype->rev_id_val))
379 return dev_err_probe(dev, -ENODEV,
380 "%s ID 0x%02x does not match\n",
381 s->devtype->name, val);
382 } else {
383 /*
384 * For variant without REV ID register, just check default value
385 * from clocksource register to make sure everything works.
386 */
387 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
388 if (ret)
389 return ret;
390
391 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT))
392 return dev_err_probe(dev, -ENODEV,
393 "%s not present\n",
394 s->devtype->name);
395 }
396
397 return 0;
398 }
399
max310x_power(struct uart_port * port,int on)400 static void max310x_power(struct uart_port *port, int on)
401 {
402 struct max310x_port *s = dev_get_drvdata(port->dev);
403
404 max310x_port_update(port, s->devtype->power_reg, s->devtype->power_bit,
405 on ? 0 : s->devtype->power_bit);
406 if (on)
407 msleep(50);
408 }
409
410 static const struct max310x_devtype max3107_devtype = {
411 .name = "MAX3107",
412 .nr = 1,
413 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
414 .rev_id_val = MAX3107_REV_ID,
415 .rev_id_reg = MAX310X_REVID_REG,
416 .power_reg = MAX310X_MODE1_REG,
417 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT,
418 .slave_addr = {
419 .min = 0x2c,
420 .max = 0x2f,
421 },
422 };
423
424 static const struct max310x_devtype max3108_devtype = {
425 .name = "MAX3108",
426 .nr = 1,
427 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
428 .rev_id_val = 0, /* Unsupported. */
429 .rev_id_reg = 0, /* Irrelevant when rev_id_val is not defined. */
430 .power_reg = MAX310X_MODE1_REG,
431 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT,
432 .slave_addr = {
433 .min = 0x60,
434 .max = 0x6f,
435 },
436 };
437
438 static const struct max310x_devtype max3109_devtype = {
439 .name = "MAX3109",
440 .nr = 2,
441 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT,
442 .rev_id_val = MAX3109_REV_ID,
443 .rev_id_reg = MAX310X_REVID_EXTREG,
444 .power_reg = MAX310X_MODE1_REG,
445 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT,
446 .slave_addr = {
447 .min = 0x60,
448 .max = 0x6f,
449 },
450 };
451
452 static const struct max310x_devtype max14830_devtype = {
453 .name = "MAX14830",
454 .nr = 4,
455 .mode1 = MAX310X_MODE1_IRQSEL_BIT,
456 .rev_id_val = MAX14830_REV_ID,
457 .rev_id_reg = MAX310X_REVID_EXTREG,
458 .power_reg = MAX310X_BRGCFG_REG,
459 .power_bit = MAX14830_BRGCFG_CLKDIS_BIT,
460 .slave_addr = {
461 .min = 0x60,
462 .max = 0x6f,
463 },
464 };
465
max310x_reg_writeable(struct device * dev,unsigned int reg)466 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
467 {
468 switch (reg) {
469 case MAX310X_IRQSTS_REG:
470 case MAX310X_LSR_IRQSTS_REG:
471 case MAX310X_SPCHR_IRQSTS_REG:
472 case MAX310X_STS_IRQSTS_REG:
473 case MAX310X_TXFIFOLVL_REG:
474 case MAX310X_RXFIFOLVL_REG:
475 return false;
476 default:
477 return true;
478 }
479 }
480
max310x_reg_volatile(struct device * dev,unsigned int reg)481 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
482 {
483 switch (reg) {
484 case MAX310X_RHR_REG:
485 case MAX310X_IRQSTS_REG:
486 case MAX310X_LSR_IRQSTS_REG:
487 case MAX310X_SPCHR_IRQSTS_REG:
488 case MAX310X_STS_IRQSTS_REG:
489 case MAX310X_TXFIFOLVL_REG:
490 case MAX310X_RXFIFOLVL_REG:
491 case MAX310X_GPIODATA_REG:
492 case MAX310X_BRGDIVLSB_REG:
493 case MAX310X_REG_05:
494 case MAX310X_REG_1F:
495 return true;
496 default:
497 return false;
498 }
499 }
500
max310x_reg_precious(struct device * dev,unsigned int reg)501 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
502 {
503 switch (reg) {
504 case MAX310X_RHR_REG:
505 case MAX310X_IRQSTS_REG:
506 case MAX310X_SPCHR_IRQSTS_REG:
507 case MAX310X_STS_IRQSTS_REG:
508 return true;
509 default:
510 return false;
511 }
512 }
513
max310x_reg_noinc(struct device * dev,unsigned int reg)514 static bool max310x_reg_noinc(struct device *dev, unsigned int reg)
515 {
516 return reg == MAX310X_RHR_REG;
517 }
518
max310x_set_baud(struct uart_port * port,int baud)519 static int max310x_set_baud(struct uart_port *port, int baud)
520 {
521 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
522
523 /*
524 * Calculate the integer divisor first. Select a proper mode
525 * in case if the requested baud is too high for the pre-defined
526 * clocks frequency.
527 */
528 div = port->uartclk / baud;
529 if (div < 8) {
530 /* Mode x4 */
531 c = 4;
532 mode = MAX310X_BRGCFG_4XMODE_BIT;
533 } else if (div < 16) {
534 /* Mode x2 */
535 c = 8;
536 mode = MAX310X_BRGCFG_2XMODE_BIT;
537 } else {
538 c = 16;
539 }
540
541 /* Calculate the divisor in accordance with the fraction coefficient */
542 div /= c;
543 F = c*baud;
544
545 /* Calculate the baud rate fraction */
546 if (div > 0)
547 frac = (16*(port->uartclk % F)) / F;
548 else
549 div = 1;
550
551 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
552 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
553 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
554
555 /* Return the actual baud rate we just programmed */
556 return (16*port->uartclk) / (c*(16*div + frac));
557 }
558
max310x_try_cfg(unsigned int fdiv,u8 div,u8 pll_mult,struct max310x_clk_config_t * cfg)559 static void max310x_try_cfg(unsigned int fdiv, u8 div, u8 pll_mult,
560 struct max310x_clk_config_t *cfg)
561 {
562 unsigned int fmul = fdiv * pll_mult;
563 unsigned int err;
564
565 /* Use high-enough baudrate to calculate error */
566 err = fmul % (460800 * 16);
567
568 if (cfg->err > err) {
569 cfg->err = err;
570 cfg->pll_mult = pll_mult;
571 cfg->prediv = div;
572 cfg->fref = fmul;
573 }
574 }
575
max310x_pll_mult_to_id(u8 pll_mult)576 static u8 max310x_pll_mult_to_id(u8 pll_mult)
577 {
578 switch (pll_mult) {
579 case 144: return 3;
580 case 96: return 2;
581 case 48: return 1;
582 case 6:
583 default: return 0;
584 }
585 }
586
587 /*
588 * From table 7 in datasheet: PLLFactor Selector Guide
589 *
590 * +-----------+----------------+-------------------+-------------------+
591 * | PLLFactor | MULTIPLICATION | fPLLIN | fREF |
592 * | (1 & 0) | FACTOR +---------+---------+---------+---------+
593 * | | | MIN | MAX | MIN | MAX |
594 * +-----------+----------------+---------+---------+---------+---------+
595 * | 0 | 6 | 500kHz | 800kHz | 3MHz | 4.8MHz |
596 * +-----------+----------------+---------+---------+---------+---------+
597 * | 1 | 48 | 850kHz | 1.2MHz | 40.8MHz | 56MHz |
598 * +-----------+----------------+---------+---------+---------+---------+
599 * | 2 | 96 | 425kHz | 1MHz | 40.8MHz | 96MHz |
600 * +-----------+----------------+---------+---------+---------+---------+
601 * | 3 | 144 | 390kHz | 667kHz | 56MHz | 96MHz |
602 * +-----------+----------------+---------+---------+---------+---------+
603 */
max310x_set_ref_clk(struct device * dev,struct max310x_port * s,unsigned int freq,unsigned int * fref,bool xtal)604 static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
605 unsigned int freq, unsigned int *fref, bool xtal)
606 {
607 unsigned int div, fdiv, clksrc, val;
608 struct max310x_clk_config_t cfg;
609
610 cfg.err = UINT_MAX;
611 cfg.prediv = 0;
612 cfg.fref = freq;
613
614 /* First, update error without PLL */
615 max310x_try_cfg(freq, 1, 1, &cfg);
616
617 /* Try all possible PLL dividers */
618 for (div = 1; (div <= 63) && cfg.err; div++) {
619 fdiv = DIV_ROUND_CLOSEST(freq, div);
620
621 if ((fdiv >= 500000) && (fdiv <= 800000))
622 max310x_try_cfg(fdiv, div, 6, &cfg); /* PLL x6 */
623 else if ((fdiv >= 850000) && (fdiv <= 1200000))
624 max310x_try_cfg(fdiv, div, 48, &cfg); /* PLL x48 */
625
626 if ((fdiv >= 425000) && (fdiv <= 1000000))
627 max310x_try_cfg(fdiv, div, 96, &cfg); /* PLL x96 */
628
629 if ((fdiv >= 390000) && (fdiv <= 667000))
630 max310x_try_cfg(fdiv, div, 144, &cfg); /* PLL x144 */
631 }
632
633 /* Configure clock source */
634 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
635
636 /* Configure PLL */
637 if (cfg.prediv) {
638 u8 pll_id = max310x_pll_mult_to_id(cfg.pll_mult);
639
640 clksrc |= MAX310X_CLKSRC_PLL_BIT;
641 val = FIELD_PREP(MAX310X_PLLCFG_PLLFACTOR_MASK, pll_id) |
642 FIELD_PREP(MAX310X_PLLCFG_PREDIV_MASK, cfg.prediv);
643 regmap_write(s->regmap, MAX310X_PLLCFG_REG, val);
644 } else
645 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
646
647 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
648
649 /* Wait for crystal */
650 if (xtal) {
651 int ret;
652
653 ret = regmap_read_poll_timeout(s->regmap, MAX310X_STS_IRQSTS_REG,
654 val, val & MAX310X_STS_CLKREADY_BIT,
655 MAX310X_XTAL_SLEEP_US,
656 MAX310X_XTAL_TIMEOUT_US);
657 if (ret)
658 return dev_err_probe(dev, -EAGAIN,
659 "clock is not stable\n");
660 }
661
662 *fref = cfg.fref;
663
664 return 0;
665 }
666
max310x_batch_write(struct uart_port * port,u8 * txbuf,unsigned int len)667 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
668 {
669 struct max310x_one *one = to_max310x_port(port);
670
671 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len);
672 }
673
max310x_batch_read(struct uart_port * port,u8 * rxbuf,unsigned int len)674 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
675 {
676 struct max310x_one *one = to_max310x_port(port);
677
678 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len);
679 }
680
max310x_handle_rx(struct uart_port * port,unsigned int rxlen)681 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
682 {
683 struct max310x_one *one = to_max310x_port(port);
684 unsigned int sts, i;
685 u8 ch, flag;
686
687 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
688 /*
689 * We are just reading, happily ignoring any error conditions.
690 * Break condition, parity checking, framing errors -- they
691 * are all ignored. That means that we can do a batch-read.
692 *
693 * There is a small opportunity for race if the RX FIFO
694 * overruns while we're reading the buffer; the datasheets says
695 * that the LSR register applies to the "current" character.
696 * That's also the reason why we cannot do batched reads when
697 * asked to check the individual statuses.
698 */
699
700 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
701 max310x_batch_read(port, one->rx_buf, rxlen);
702
703 port->icount.rx += rxlen;
704 flag = TTY_NORMAL;
705 sts &= port->read_status_mask;
706
707 if (sts & MAX310X_LSR_RXOVR_BIT) {
708 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
709 port->icount.overrun++;
710 }
711
712 for (i = 0; i < (rxlen - 1); ++i)
713 uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
714
715 /*
716 * Handle the overrun case for the last character only, since
717 * the RxFIFO overflow happens after it is pushed to the FIFO
718 * tail.
719 */
720 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
721 one->rx_buf[rxlen-1], flag);
722
723 } else {
724 if (unlikely(rxlen >= port->fifosize)) {
725 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
726 port->icount.buf_overrun++;
727 /* Ensure sanity of RX level */
728 rxlen = port->fifosize;
729 }
730
731 while (rxlen--) {
732 ch = max310x_port_read(port, MAX310X_RHR_REG);
733 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
734
735 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
736 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
737
738 port->icount.rx++;
739 flag = TTY_NORMAL;
740
741 if (unlikely(sts)) {
742 if (sts & MAX310X_LSR_RXBRK_BIT) {
743 port->icount.brk++;
744 if (uart_handle_break(port))
745 continue;
746 } else if (sts & MAX310X_LSR_RXPAR_BIT)
747 port->icount.parity++;
748 else if (sts & MAX310X_LSR_FRERR_BIT)
749 port->icount.frame++;
750 else if (sts & MAX310X_LSR_RXOVR_BIT)
751 port->icount.overrun++;
752
753 sts &= port->read_status_mask;
754 if (sts & MAX310X_LSR_RXBRK_BIT)
755 flag = TTY_BREAK;
756 else if (sts & MAX310X_LSR_RXPAR_BIT)
757 flag = TTY_PARITY;
758 else if (sts & MAX310X_LSR_FRERR_BIT)
759 flag = TTY_FRAME;
760 else if (sts & MAX310X_LSR_RXOVR_BIT)
761 flag = TTY_OVERRUN;
762 }
763
764 if (uart_handle_sysrq_char(port, ch))
765 continue;
766
767 if (sts & port->ignore_status_mask)
768 continue;
769
770 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
771 }
772 }
773
774 tty_flip_buffer_push(&port->state->port);
775 }
776
max310x_handle_tx(struct uart_port * port)777 static void max310x_handle_tx(struct uart_port *port)
778 {
779 struct tty_port *tport = &port->state->port;
780
781 if (unlikely(port->x_char)) {
782 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
783 port->icount.tx++;
784 port->x_char = 0;
785 return;
786 }
787
788 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port))
789 return;
790
791 /*
792 * It's a circ buffer -- wrap around.
793 * We could do that in one SPI transaction, but meh.
794 */
795 while (!kfifo_is_empty(&tport->xmit_fifo)) {
796 unsigned int txlen, to_send;
797 unsigned char *tail;
798
799 /* Limit to space available in TX FIFO */
800 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
801 txlen = port->fifosize - txlen;
802 if (!txlen)
803 break;
804
805 to_send = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen);
806 max310x_batch_write(port, tail, to_send);
807 uart_xmit_advance(port, to_send);
808 }
809
810 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
811 uart_write_wakeup(port);
812 }
813
max310x_start_tx(struct uart_port * port)814 static void max310x_start_tx(struct uart_port *port)
815 {
816 struct max310x_one *one = to_max310x_port(port);
817
818 schedule_work(&one->tx_work);
819 }
820
max310x_port_irq(struct max310x_port * s,int portno)821 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
822 {
823 struct uart_port *port = &s->p[portno].port;
824 irqreturn_t res = IRQ_NONE;
825
826 do {
827 unsigned int ists, lsr, rxlen;
828
829 /* Read IRQ status & RX FIFO level */
830 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
831 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
832 if (!ists && !rxlen)
833 break;
834
835 res = IRQ_HANDLED;
836
837 if (ists & MAX310X_IRQ_CTS_BIT) {
838 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
839 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT);
840 }
841 if (rxlen)
842 max310x_handle_rx(port, rxlen);
843 if (ists & MAX310X_IRQ_TXEMPTY_BIT)
844 max310x_start_tx(port);
845 } while (1);
846
847 return res;
848 }
849
max310x_ist(int irq,void * dev_id)850 static irqreturn_t max310x_ist(int irq, void *dev_id)
851 {
852 struct max310x_port *s = (struct max310x_port *)dev_id;
853 bool handled = false;
854
855 if (s->devtype->nr > 1) {
856 bool done;
857
858 do {
859 unsigned int val = ~0;
860 unsigned long irq;
861 unsigned int port;
862
863 done = true;
864
865 WARN_ON_ONCE(regmap_read(s->regmap,
866 MAX310X_GLOBALIRQ_REG, &val));
867
868 irq = val;
869
870 for_each_clear_bit(port, &irq, s->devtype->nr) {
871 done = false;
872
873 if (max310x_port_irq(s, port) == IRQ_HANDLED)
874 handled = true;
875 }
876
877 } while (!done);
878 } else {
879 if (max310x_port_irq(s, 0) == IRQ_HANDLED)
880 handled = true;
881 }
882
883 return IRQ_RETVAL(handled);
884 }
885
max310x_tx_proc(struct work_struct * ws)886 static void max310x_tx_proc(struct work_struct *ws)
887 {
888 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
889
890 max310x_handle_tx(&one->port);
891 }
892
max310x_tx_empty(struct uart_port * port)893 static unsigned int max310x_tx_empty(struct uart_port *port)
894 {
895 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
896
897 return lvl ? 0 : TIOCSER_TEMT;
898 }
899
max310x_get_mctrl(struct uart_port * port)900 static unsigned int max310x_get_mctrl(struct uart_port *port)
901 {
902 /*
903 * DCD and DSR are not wired and CTS/RTS is handled automatically
904 * so just indicate DSR and CAR asserted
905 */
906 return TIOCM_DSR | TIOCM_CAR;
907 }
908
max310x_md_proc(struct work_struct * ws)909 static void max310x_md_proc(struct work_struct *ws)
910 {
911 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
912
913 max310x_port_update(&one->port, MAX310X_MODE2_REG,
914 MAX310X_MODE2_LOOPBACK_BIT,
915 (one->port.mctrl & TIOCM_LOOP) ?
916 MAX310X_MODE2_LOOPBACK_BIT : 0);
917 }
918
max310x_set_mctrl(struct uart_port * port,unsigned int mctrl)919 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
920 {
921 struct max310x_one *one = to_max310x_port(port);
922
923 schedule_work(&one->md_work);
924 }
925
max310x_break_ctl(struct uart_port * port,int break_state)926 static void max310x_break_ctl(struct uart_port *port, int break_state)
927 {
928 max310x_port_update(port, MAX310X_LCR_REG,
929 MAX310X_LCR_TXBREAK_BIT,
930 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
931 }
932
max310x_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)933 static void max310x_set_termios(struct uart_port *port,
934 struct ktermios *termios,
935 const struct ktermios *old)
936 {
937 unsigned int lcr = 0, flow = 0;
938 int baud;
939
940 /* Mask termios capabilities we don't support */
941 termios->c_cflag &= ~CMSPAR;
942
943 /* Word size */
944 switch (termios->c_cflag & CSIZE) {
945 case CS5:
946 break;
947 case CS6:
948 lcr = MAX310X_LCR_LENGTH0_BIT;
949 break;
950 case CS7:
951 lcr = MAX310X_LCR_LENGTH1_BIT;
952 break;
953 case CS8:
954 default:
955 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
956 break;
957 }
958
959 /* Parity */
960 if (termios->c_cflag & PARENB) {
961 lcr |= MAX310X_LCR_PARITY_BIT;
962 if (!(termios->c_cflag & PARODD))
963 lcr |= MAX310X_LCR_EVENPARITY_BIT;
964 }
965
966 /* Stop bits */
967 if (termios->c_cflag & CSTOPB)
968 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
969
970 /* Update LCR register */
971 max310x_port_write(port, MAX310X_LCR_REG, lcr);
972
973 /* Set read status mask */
974 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
975 if (termios->c_iflag & INPCK)
976 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
977 MAX310X_LSR_FRERR_BIT;
978 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
979 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
980
981 /* Set status ignore mask */
982 port->ignore_status_mask = 0;
983 if (termios->c_iflag & IGNBRK)
984 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
985 if (!(termios->c_cflag & CREAD))
986 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
987 MAX310X_LSR_RXOVR_BIT |
988 MAX310X_LSR_FRERR_BIT |
989 MAX310X_LSR_RXBRK_BIT;
990
991 /* Configure flow control */
992 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
993 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
994
995 /*
996 * Disable transmitter before enabling AutoCTS or auto transmitter
997 * flow control
998 */
999 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
1000 max310x_port_update(port, MAX310X_MODE1_REG,
1001 MAX310X_MODE1_TXDIS_BIT,
1002 MAX310X_MODE1_TXDIS_BIT);
1003 }
1004
1005 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1006
1007 if (termios->c_cflag & CRTSCTS) {
1008 /* Enable AUTORTS and AUTOCTS */
1009 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1010 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
1011 MAX310X_FLOWCTRL_AUTORTS_BIT;
1012 }
1013 if (termios->c_iflag & IXON)
1014 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
1015 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
1016 if (termios->c_iflag & IXOFF) {
1017 port->status |= UPSTAT_AUTOXOFF;
1018 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
1019 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
1020 }
1021 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
1022
1023 /*
1024 * Enable transmitter after disabling AutoCTS and auto transmitter
1025 * flow control
1026 */
1027 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
1028 max310x_port_update(port, MAX310X_MODE1_REG,
1029 MAX310X_MODE1_TXDIS_BIT,
1030 0);
1031 }
1032
1033 /* Get baud rate generator configuration */
1034 baud = uart_get_baud_rate(port, termios, old,
1035 port->uartclk / 16 / 0xffff,
1036 port->uartclk / 4);
1037
1038 /* Setup baudrate generator */
1039 baud = max310x_set_baud(port, baud);
1040
1041 /* Update timeout according to new baud rate */
1042 uart_update_timeout(port, termios->c_cflag, baud);
1043 }
1044
max310x_rs_proc(struct work_struct * ws)1045 static void max310x_rs_proc(struct work_struct *ws)
1046 {
1047 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
1048 unsigned int delay, mode1 = 0, mode2 = 0;
1049
1050 delay = (one->port.rs485.delay_rts_before_send << 4) |
1051 one->port.rs485.delay_rts_after_send;
1052 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
1053
1054 if (one->port.rs485.flags & SER_RS485_ENABLED) {
1055 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
1056
1057 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1058 mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
1059 }
1060
1061 max310x_port_update(&one->port, MAX310X_MODE1_REG,
1062 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
1063 max310x_port_update(&one->port, MAX310X_MODE2_REG,
1064 MAX310X_MODE2_ECHOSUPR_BIT, mode2);
1065 }
1066
max310x_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1067 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios,
1068 struct serial_rs485 *rs485)
1069 {
1070 struct max310x_one *one = to_max310x_port(port);
1071
1072 if ((rs485->delay_rts_before_send > 0x0f) ||
1073 (rs485->delay_rts_after_send > 0x0f))
1074 return -ERANGE;
1075
1076 port->rs485 = *rs485;
1077
1078 schedule_work(&one->rs_work);
1079
1080 return 0;
1081 }
1082
max310x_startup(struct uart_port * port)1083 static int max310x_startup(struct uart_port *port)
1084 {
1085 unsigned int val;
1086
1087 max310x_power(port, 1);
1088
1089 /* Configure MODE1 register */
1090 max310x_port_update(port, MAX310X_MODE1_REG,
1091 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1092
1093 /* Configure MODE2 register & Reset FIFOs*/
1094 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1095 max310x_port_write(port, MAX310X_MODE2_REG, val);
1096 max310x_port_update(port, MAX310X_MODE2_REG,
1097 MAX310X_MODE2_FIFORST_BIT, 0);
1098
1099 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
1100 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1101 clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1102 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1103
1104 if (port->rs485.flags & SER_RS485_ENABLED) {
1105 max310x_port_update(port, MAX310X_MODE1_REG,
1106 MAX310X_MODE1_TRNSCVCTRL_BIT,
1107 MAX310X_MODE1_TRNSCVCTRL_BIT);
1108
1109 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1110 max310x_port_update(port, MAX310X_MODE2_REG,
1111 MAX310X_MODE2_ECHOSUPR_BIT,
1112 MAX310X_MODE2_ECHOSUPR_BIT);
1113 }
1114
1115 /*
1116 * Configure flow control levels:
1117 * resume: 48
1118 * halt: 96
1119 */
1120 max310x_port_write(port, MAX310X_FLOWLVL_REG,
1121 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1122
1123 /* Clear IRQ status register */
1124 max310x_port_read(port, MAX310X_IRQSTS_REG);
1125
1126 /* Enable RX, TX, CTS change interrupts */
1127 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1128 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1129
1130 return 0;
1131 }
1132
max310x_shutdown(struct uart_port * port)1133 static void max310x_shutdown(struct uart_port *port)
1134 {
1135 /* Disable all interrupts */
1136 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1137
1138 max310x_power(port, 0);
1139 }
1140
max310x_type(struct uart_port * port)1141 static const char *max310x_type(struct uart_port *port)
1142 {
1143 struct max310x_port *s = dev_get_drvdata(port->dev);
1144
1145 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1146 }
1147
max310x_request_port(struct uart_port * port)1148 static int max310x_request_port(struct uart_port *port)
1149 {
1150 /* Do nothing */
1151 return 0;
1152 }
1153
max310x_config_port(struct uart_port * port,int flags)1154 static void max310x_config_port(struct uart_port *port, int flags)
1155 {
1156 if (flags & UART_CONFIG_TYPE)
1157 port->type = PORT_MAX310X;
1158 }
1159
max310x_verify_port(struct uart_port * port,struct serial_struct * s)1160 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1161 {
1162 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1163 return -EINVAL;
1164 if (s->irq != port->irq)
1165 return -EINVAL;
1166
1167 return 0;
1168 }
1169
max310x_null_void(struct uart_port * port)1170 static void max310x_null_void(struct uart_port *port)
1171 {
1172 /* Do nothing */
1173 }
1174
1175 static const struct uart_ops max310x_ops = {
1176 .tx_empty = max310x_tx_empty,
1177 .set_mctrl = max310x_set_mctrl,
1178 .get_mctrl = max310x_get_mctrl,
1179 .stop_tx = max310x_null_void,
1180 .start_tx = max310x_start_tx,
1181 .stop_rx = max310x_null_void,
1182 .break_ctl = max310x_break_ctl,
1183 .startup = max310x_startup,
1184 .shutdown = max310x_shutdown,
1185 .set_termios = max310x_set_termios,
1186 .type = max310x_type,
1187 .request_port = max310x_request_port,
1188 .release_port = max310x_null_void,
1189 .config_port = max310x_config_port,
1190 .verify_port = max310x_verify_port,
1191 };
1192
max310x_suspend(struct device * dev)1193 static int __maybe_unused max310x_suspend(struct device *dev)
1194 {
1195 struct max310x_port *s = dev_get_drvdata(dev);
1196 int i;
1197
1198 for (i = 0; i < s->devtype->nr; i++) {
1199 uart_suspend_port(&max310x_uart, &s->p[i].port);
1200 max310x_power(&s->p[i].port, 0);
1201 }
1202
1203 return 0;
1204 }
1205
max310x_resume(struct device * dev)1206 static int __maybe_unused max310x_resume(struct device *dev)
1207 {
1208 struct max310x_port *s = dev_get_drvdata(dev);
1209 int i;
1210
1211 for (i = 0; i < s->devtype->nr; i++) {
1212 max310x_power(&s->p[i].port, 1);
1213 uart_resume_port(&max310x_uart, &s->p[i].port);
1214 }
1215
1216 return 0;
1217 }
1218
1219 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1220
1221 #ifdef CONFIG_GPIOLIB
max310x_gpio_get(struct gpio_chip * chip,unsigned int offset)1222 static int max310x_gpio_get(struct gpio_chip *chip, unsigned int offset)
1223 {
1224 unsigned int val;
1225 struct max310x_port *s = gpiochip_get_data(chip);
1226 struct uart_port *port = &s->p[offset / 4].port;
1227
1228 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1229
1230 return !!((val >> 4) & (1 << (offset % 4)));
1231 }
1232
max310x_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1233 static int max310x_gpio_set(struct gpio_chip *chip, unsigned int offset,
1234 int value)
1235 {
1236 struct max310x_port *s = gpiochip_get_data(chip);
1237 struct uart_port *port = &s->p[offset / 4].port;
1238
1239 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1240 value ? 1 << (offset % 4) : 0);
1241
1242 return 0;
1243 }
1244
max310x_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1245 static int max310x_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1246 {
1247 struct max310x_port *s = gpiochip_get_data(chip);
1248 struct uart_port *port = &s->p[offset / 4].port;
1249 unsigned int val;
1250
1251 val = max310x_port_read(port, MAX310X_GPIOCFG_REG);
1252
1253 return val & BIT(offset % 4) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1254 }
1255
max310x_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1256 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1257 {
1258 struct max310x_port *s = gpiochip_get_data(chip);
1259 struct uart_port *port = &s->p[offset / 4].port;
1260
1261 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1262
1263 return 0;
1264 }
1265
max310x_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1266 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1267 unsigned int offset, int value)
1268 {
1269 struct max310x_port *s = gpiochip_get_data(chip);
1270 struct uart_port *port = &s->p[offset / 4].port;
1271
1272 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1273 value ? 1 << (offset % 4) : 0);
1274 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1275 1 << (offset % 4));
1276
1277 return 0;
1278 }
1279
max310x_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)1280 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1281 unsigned long config)
1282 {
1283 struct max310x_port *s = gpiochip_get_data(chip);
1284 struct uart_port *port = &s->p[offset / 4].port;
1285
1286 switch (pinconf_to_config_param(config)) {
1287 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1288 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1289 1 << ((offset % 4) + 4),
1290 1 << ((offset % 4) + 4));
1291 return 0;
1292 case PIN_CONFIG_DRIVE_PUSH_PULL:
1293 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1294 1 << ((offset % 4) + 4), 0);
1295 return 0;
1296 default:
1297 return -ENOTSUPP;
1298 }
1299 }
1300 #endif
1301
1302 static const struct serial_rs485 max310x_rs485_supported = {
1303 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX,
1304 .delay_rts_before_send = 1,
1305 .delay_rts_after_send = 1,
1306 };
1307
max310x_probe(struct device * dev,const struct max310x_devtype * devtype,const struct max310x_if_cfg * if_cfg,struct regmap * regmaps[],int irq)1308 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype,
1309 const struct max310x_if_cfg *if_cfg,
1310 struct regmap *regmaps[], int irq)
1311 {
1312 unsigned int fmin, fmax, freq;
1313 int i, ret;
1314 struct max310x_port *s;
1315 unsigned int uartclk = 0;
1316 bool xtal;
1317
1318 for (i = 0; i < devtype->nr; i++)
1319 if (IS_ERR(regmaps[i]))
1320 return PTR_ERR(regmaps[i]);
1321
1322 /* Alloc port structure */
1323 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
1324 if (!s)
1325 return -ENOMEM;
1326
1327 /* Always ask for fixed clock rate from a property. */
1328 device_property_read_u32(dev, "clock-frequency", &uartclk);
1329
1330 xtal = device_property_match_string(dev, "clock-names", "osc") < 0;
1331 if (xtal)
1332 s->clk = devm_clk_get_optional(dev, "xtal");
1333 else
1334 s->clk = devm_clk_get_optional(dev, "osc");
1335 if (IS_ERR(s->clk))
1336 return PTR_ERR(s->clk);
1337
1338 ret = clk_prepare_enable(s->clk);
1339 if (ret)
1340 return ret;
1341
1342 freq = clk_get_rate(s->clk);
1343 if (freq == 0)
1344 freq = uartclk;
1345 if (freq == 0) {
1346 ret = dev_err_probe(dev, -EINVAL, "Cannot get clock rate\n");
1347 goto out_clk;
1348 }
1349
1350 if (xtal) {
1351 fmin = 1000000;
1352 fmax = 4000000;
1353 } else {
1354 fmin = 500000;
1355 fmax = 35000000;
1356 }
1357
1358 /* Check frequency limits */
1359 if (freq < fmin || freq > fmax) {
1360 ret = -ERANGE;
1361 goto out_clk;
1362 }
1363
1364 s->regmap = regmaps[0];
1365 s->devtype = devtype;
1366 s->if_cfg = if_cfg;
1367 dev_set_drvdata(dev, s);
1368
1369 /* Check device to ensure we are talking to what we expect */
1370 ret = max310x_detect(dev);
1371 if (ret)
1372 goto out_clk;
1373
1374 for (i = 0; i < devtype->nr; i++) {
1375 unsigned int val;
1376
1377 /* Reset port */
1378 regmap_write(regmaps[i], MAX310X_MODE2_REG,
1379 MAX310X_MODE2_RST_BIT);
1380 /* Clear port reset */
1381 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0);
1382
1383 /* Wait for port startup */
1384 ret = regmap_read_poll_timeout(regmaps[i], MAX310X_BRGDIVLSB_REG,
1385 val, val == 0x01,
1386 MAX310X_PORT_STARTUP_SLEEP_US,
1387 MAX310X_PORT_STARTUP_TIMEOUT_US);
1388 if (ret) {
1389 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n");
1390 goto out_uart;
1391 }
1392
1393 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1);
1394 }
1395
1396 ret = max310x_set_ref_clk(dev, s, freq, &uartclk, xtal);
1397 if (ret < 0)
1398 goto out_uart;
1399
1400 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1401
1402 /*
1403 * Set up each port's state before registering the gpiochip,
1404 * since the gpiochip callbacks will read s->p[i].regmap as
1405 * soon as gpiolib exposes the controller.
1406 */
1407 for (i = 0; i < devtype->nr; i++) {
1408 s->p[i].port.dev = dev;
1409 s->p[i].port.irq = irq;
1410 s->p[i].port.type = PORT_MAX310X;
1411 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1412 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1413 s->p[i].port.iotype = UPIO_BUS;
1414 s->p[i].port.uartclk = uartclk;
1415 s->p[i].port.rs485_config = max310x_rs485_config;
1416 s->p[i].port.rs485_supported = max310x_rs485_supported;
1417 s->p[i].port.ops = &max310x_ops;
1418 s->p[i].regmap = regmaps[i];
1419
1420 /* Disable all interrupts */
1421 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1422 /* Clear IRQ status register */
1423 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1424 /* Initialize queue for start TX */
1425 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
1426 /* Initialize queue for changing LOOPBACK mode */
1427 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1428 /* Initialize queue for changing RS485 mode */
1429 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1430 }
1431
1432 #ifdef CONFIG_GPIOLIB
1433 /*
1434 * Register the GPIO controller before adding the UART ports so
1435 * that consumers referencing the chip's own GPIOs from device
1436 * tree (for example rs485-term-gpios = <&max310x ...>) can
1437 * resolve them at uart_add_one_port() time instead of receiving
1438 * -EPROBE_DEFER from their own provider.
1439 */
1440 s->gpio.owner = THIS_MODULE;
1441 s->gpio.parent = dev;
1442 s->gpio.label = devtype->name;
1443 s->gpio.get_direction = max310x_gpio_get_direction;
1444 s->gpio.direction_input = max310x_gpio_direction_input;
1445 s->gpio.get = max310x_gpio_get;
1446 s->gpio.direction_output= max310x_gpio_direction_output;
1447 s->gpio.set = max310x_gpio_set;
1448 s->gpio.set_config = max310x_gpio_set_config;
1449 s->gpio.base = -1;
1450 s->gpio.ngpio = devtype->nr * 4;
1451 s->gpio.can_sleep = 1;
1452 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1453 if (ret)
1454 goto out_uart;
1455 #endif
1456
1457 for (i = 0; i < devtype->nr; i++) {
1458 struct fwnode_handle *saved_fwnode = dev_fwnode(dev);
1459 struct device_node *port_np = NULL;
1460 struct device_node *child;
1461 unsigned int line;
1462
1463 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1464 if (line == MAX310X_UART_NRMAX) {
1465 ret = -ERANGE;
1466 goto out_uart;
1467 }
1468 s->p[i].port.line = line;
1469
1470 /* Locate the matching "serial@i" DT subnode, if any. */
1471 for_each_available_child_of_node(dev->of_node, child) {
1472 u32 reg;
1473
1474 if (!of_node_name_eq(child, "serial"))
1475 continue;
1476 if (of_property_read_u32(child, "reg", ®))
1477 continue;
1478 if (reg == i) {
1479 port_np = child;
1480 break;
1481 }
1482 }
1483
1484 /*
1485 * Temporarily retarget dev's fwnode to the per-port subnode
1486 * so uart_get_rs485_mode() picks up the per-port properties.
1487 * For single-port variants, fall back to the chip's own
1488 * fwnode so legacy DTs that declare rs485 properties at the
1489 * top level keep working.
1490 */
1491 if (port_np) {
1492 device_set_node(dev, of_fwnode_handle(port_np));
1493 ret = uart_get_rs485_mode(&s->p[i].port);
1494 device_set_node(dev, saved_fwnode);
1495 of_node_put(port_np);
1496 if (ret)
1497 goto out_uart;
1498 } else if (devtype->nr == 1) {
1499 ret = uart_get_rs485_mode(&s->p[i].port);
1500 if (ret)
1501 goto out_uart;
1502 }
1503
1504 /* Register port */
1505 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1506 if (ret)
1507 goto out_uart;
1508
1509 set_bit(line, max310x_lines);
1510
1511 /* Go to suspend mode */
1512 max310x_power(&s->p[i].port, 0);
1513 }
1514
1515 /* Setup interrupt */
1516 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1517 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1518 if (!ret)
1519 return 0;
1520
1521 dev_err(dev, "Unable to request IRQ %i\n", irq);
1522
1523 out_uart:
1524 for (i = 0; i < devtype->nr; i++) {
1525 if (test_and_clear_bit(s->p[i].port.line, max310x_lines))
1526 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1527 }
1528
1529 out_clk:
1530 clk_disable_unprepare(s->clk);
1531
1532 return ret;
1533 }
1534
max310x_remove(struct device * dev)1535 static void max310x_remove(struct device *dev)
1536 {
1537 struct max310x_port *s = dev_get_drvdata(dev);
1538 int i;
1539
1540 for (i = 0; i < s->devtype->nr; i++) {
1541 cancel_work_sync(&s->p[i].tx_work);
1542 cancel_work_sync(&s->p[i].md_work);
1543 cancel_work_sync(&s->p[i].rs_work);
1544
1545 if (test_and_clear_bit(s->p[i].port.line, max310x_lines))
1546 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1547
1548 max310x_power(&s->p[i].port, 0);
1549 }
1550
1551 clk_disable_unprepare(s->clk);
1552 }
1553
1554 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1555 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1556 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1557 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1558 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1559 { }
1560 };
1561 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1562
max310x_regmap_name(u8 port_id)1563 static const char *max310x_regmap_name(u8 port_id)
1564 {
1565 switch (port_id) {
1566 case 0: return "port0";
1567 case 1: return "port1";
1568 case 2: return "port2";
1569 case 3: return "port3";
1570 default:
1571 WARN_ON(true);
1572 return NULL;
1573 }
1574 }
1575
1576 #if IS_ENABLED(CONFIG_SPI_MASTER)
1577
1578 static struct regmap_config regcfg = {
1579 .reg_bits = 8,
1580 .val_bits = 8,
1581 .write_flag_mask = MAX310X_WRITE_BIT,
1582 .cache_type = REGCACHE_MAPLE,
1583 .max_register = MAX310X_REG_1F,
1584 .writeable_reg = max310x_reg_writeable,
1585 .volatile_reg = max310x_reg_volatile,
1586 .precious_reg = max310x_reg_precious,
1587 .writeable_noinc_reg = max310x_reg_noinc,
1588 .readable_noinc_reg = max310x_reg_noinc,
1589 .max_raw_read = MAX310X_FIFO_SIZE,
1590 .max_raw_write = MAX310X_FIFO_SIZE,
1591 };
1592
max310x_spi_extended_reg_enable(struct device * dev,bool enable)1593 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable)
1594 {
1595 struct max310x_port *s = dev_get_drvdata(dev);
1596
1597 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
1598 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL);
1599 }
1600
1601 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = {
1602 .extended_reg_enable = max310x_spi_extended_reg_enable,
1603 .rev_id_offset = MAX310X_EXTREG_START,
1604 };
1605
max310x_spi_probe(struct spi_device * spi)1606 static int max310x_spi_probe(struct spi_device *spi)
1607 {
1608 const struct max310x_devtype *devtype;
1609 struct regmap *regmaps[MAX310X_MAX_PORTS];
1610 unsigned int i;
1611 int ret;
1612
1613 /* Setup SPI bus */
1614 spi->bits_per_word = 8;
1615 spi->mode = spi->mode ? : SPI_MODE_0;
1616 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1617 ret = spi_setup(spi);
1618 if (ret)
1619 return ret;
1620
1621 devtype = spi_get_device_match_data(spi);
1622 if (!devtype)
1623 return dev_err_probe(&spi->dev, -ENODEV, "Failed to match device\n");
1624
1625 for (i = 0; i < devtype->nr; i++) {
1626 u8 port_mask = i * 0x20;
1627
1628 regcfg.name = max310x_regmap_name(i);
1629 regcfg.read_flag_mask = port_mask;
1630 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT;
1631 regmaps[i] = devm_regmap_init_spi(spi, ®cfg);
1632 }
1633
1634 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq);
1635 }
1636
max310x_spi_remove(struct spi_device * spi)1637 static void max310x_spi_remove(struct spi_device *spi)
1638 {
1639 max310x_remove(&spi->dev);
1640 }
1641
1642 static const struct spi_device_id max310x_id_table[] = {
1643 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1644 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1645 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1646 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1647 { }
1648 };
1649 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1650
1651 static struct spi_driver max310x_spi_driver = {
1652 .driver = {
1653 .name = MAX310X_NAME,
1654 .of_match_table = max310x_dt_ids,
1655 .pm = &max310x_pm_ops,
1656 },
1657 .probe = max310x_spi_probe,
1658 .remove = max310x_spi_remove,
1659 .id_table = max310x_id_table,
1660 };
1661 #endif
1662
1663 #if IS_ENABLED(CONFIG_I2C)
1664
max310x_i2c_extended_reg_enable(struct device * dev,bool enable)1665 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable)
1666 {
1667 return 0;
1668 }
1669
1670 static struct regmap_config regcfg_i2c = {
1671 .reg_bits = 8,
1672 .val_bits = 8,
1673 .cache_type = REGCACHE_MAPLE,
1674 .writeable_reg = max310x_reg_writeable,
1675 .volatile_reg = max310x_reg_volatile,
1676 .precious_reg = max310x_reg_precious,
1677 .max_register = MAX310X_REVID_EXTREG,
1678 .writeable_noinc_reg = max310x_reg_noinc,
1679 .readable_noinc_reg = max310x_reg_noinc,
1680 .max_raw_read = MAX310X_FIFO_SIZE,
1681 .max_raw_write = MAX310X_FIFO_SIZE,
1682 };
1683
1684 static const struct max310x_if_cfg max310x_i2c_if_cfg = {
1685 .extended_reg_enable = max310x_i2c_extended_reg_enable,
1686 .rev_id_offset = 0, /* No offset in I2C mode. */
1687 };
1688
max310x_i2c_slave_addr(unsigned short addr,unsigned int nr)1689 static unsigned short max310x_i2c_slave_addr(unsigned short addr,
1690 unsigned int nr)
1691 {
1692 /*
1693 * For MAX14830 and MAX3109, the slave address depends on what the
1694 * A0 and A1 pins are tied to.
1695 * See Table I2C Address Map of the datasheet.
1696 * Based on that table, the following formulas were determined:
1697 * UART1 - UART0 = 0x10
1698 * UART2 - UART1 = 0x20 + 0x10
1699 * UART3 - UART2 = 0x10
1700 */
1701
1702 addr -= nr * 0x10;
1703
1704 if (nr >= 2)
1705 addr -= 0x20;
1706
1707 return addr;
1708 }
1709
max310x_i2c_probe(struct i2c_client * client)1710 static int max310x_i2c_probe(struct i2c_client *client)
1711 {
1712 const struct max310x_devtype *devtype;
1713 struct i2c_client *port_client;
1714 struct regmap *regmaps[MAX310X_MAX_PORTS];
1715 unsigned int i;
1716 u8 port_addr;
1717
1718 devtype = i2c_get_match_data(client);
1719 if (!devtype)
1720 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n");
1721
1722 if (client->addr < devtype->slave_addr.min ||
1723 client->addr > devtype->slave_addr.max)
1724 return dev_err_probe(&client->dev, -EINVAL,
1725 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n",
1726 client->addr, devtype->slave_addr.min,
1727 devtype->slave_addr.max);
1728
1729 regcfg_i2c.name = max310x_regmap_name(0);
1730 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c);
1731
1732 for (i = 1; i < devtype->nr; i++) {
1733 port_addr = max310x_i2c_slave_addr(client->addr, i);
1734 port_client = devm_i2c_new_dummy_device(&client->dev,
1735 client->adapter,
1736 port_addr);
1737 if (IS_ERR(port_client))
1738 return PTR_ERR(port_client);
1739
1740 regcfg_i2c.name = max310x_regmap_name(i);
1741 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c);
1742 }
1743
1744 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg,
1745 regmaps, client->irq);
1746 }
1747
max310x_i2c_remove(struct i2c_client * client)1748 static void max310x_i2c_remove(struct i2c_client *client)
1749 {
1750 max310x_remove(&client->dev);
1751 }
1752
1753 static const struct i2c_device_id max310x_i2c_id_table[] = {
1754 { .name = "max3107", .driver_data = (kernel_ulong_t)&max3107_devtype },
1755 { .name = "max3108", .driver_data = (kernel_ulong_t)&max3108_devtype },
1756 { .name = "max3109", .driver_data = (kernel_ulong_t)&max3109_devtype },
1757 { .name = "max14830", .driver_data = (kernel_ulong_t)&max14830_devtype },
1758 { }
1759 };
1760 MODULE_DEVICE_TABLE(i2c, max310x_i2c_id_table);
1761
1762 static struct i2c_driver max310x_i2c_driver = {
1763 .driver = {
1764 .name = MAX310X_NAME,
1765 .of_match_table = max310x_dt_ids,
1766 .pm = &max310x_pm_ops,
1767 },
1768 .probe = max310x_i2c_probe,
1769 .remove = max310x_i2c_remove,
1770 .id_table = max310x_i2c_id_table,
1771 };
1772 #endif
1773
max310x_uart_init(void)1774 static int __init max310x_uart_init(void)
1775 {
1776 int ret;
1777
1778 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1779
1780 ret = uart_register_driver(&max310x_uart);
1781 if (ret)
1782 return ret;
1783
1784 #if IS_ENABLED(CONFIG_SPI_MASTER)
1785 ret = spi_register_driver(&max310x_spi_driver);
1786 if (ret)
1787 goto err_spi_register;
1788 #endif
1789
1790 #if IS_ENABLED(CONFIG_I2C)
1791 ret = i2c_add_driver(&max310x_i2c_driver);
1792 if (ret)
1793 goto err_i2c_register;
1794 #endif
1795
1796 return 0;
1797
1798 #if IS_ENABLED(CONFIG_I2C)
1799 err_i2c_register:
1800 #endif
1801 #if IS_ENABLED(CONFIG_SPI_MASTER)
1802 spi_unregister_driver(&max310x_spi_driver);
1803 err_spi_register:
1804 #endif
1805 uart_unregister_driver(&max310x_uart);
1806
1807 return ret;
1808 }
1809 module_init(max310x_uart_init);
1810
max310x_uart_exit(void)1811 static void __exit max310x_uart_exit(void)
1812 {
1813 #if IS_ENABLED(CONFIG_I2C)
1814 i2c_del_driver(&max310x_i2c_driver);
1815 #endif
1816
1817 #if IS_ENABLED(CONFIG_SPI_MASTER)
1818 spi_unregister_driver(&max310x_spi_driver);
1819 #endif
1820
1821 uart_unregister_driver(&max310x_uart);
1822 }
1823 module_exit(max310x_uart_exit);
1824
1825 MODULE_LICENSE("GPL");
1826 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1827 MODULE_DESCRIPTION("MAX310X serial driver");
1828