1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/clock/mediatek,mt7988-clk.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6#include <dt-bindings/pinctrl/mt65xx.h> 7#include <dt-bindings/reset/mediatek,mt7988-resets.h> 8 9/ { 10 compatible = "mediatek,mt7988a"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a73"; 21 reg = <0x0>; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 25 <&topckgen CLK_TOP_XTAL>; 26 clock-names = "cpu", "intermediate"; 27 operating-points-v2 = <&cluster0_opp>; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "arm,cortex-a73"; 32 reg = <0x1>; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 36 <&topckgen CLK_TOP_XTAL>; 37 clock-names = "cpu", "intermediate"; 38 operating-points-v2 = <&cluster0_opp>; 39 }; 40 41 cpu2: cpu@2 { 42 compatible = "arm,cortex-a73"; 43 reg = <0x2>; 44 device_type = "cpu"; 45 enable-method = "psci"; 46 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 47 <&topckgen CLK_TOP_XTAL>; 48 clock-names = "cpu", "intermediate"; 49 operating-points-v2 = <&cluster0_opp>; 50 }; 51 52 cpu3: cpu@3 { 53 compatible = "arm,cortex-a73"; 54 reg = <0x3>; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 58 <&topckgen CLK_TOP_XTAL>; 59 clock-names = "cpu", "intermediate"; 60 operating-points-v2 = <&cluster0_opp>; 61 }; 62 63 cluster0_opp: opp-table-0 { 64 compatible = "operating-points-v2"; 65 opp-shared; 66 67 opp-800000000 { 68 opp-hz = /bits/ 64 <800000000>; 69 opp-microvolt = <850000>; 70 }; 71 opp-1100000000 { 72 opp-hz = /bits/ 64 <1100000000>; 73 opp-microvolt = <850000>; 74 }; 75 opp-1500000000 { 76 opp-hz = /bits/ 64 <1500000000>; 77 opp-microvolt = <850000>; 78 }; 79 opp-1800000000 { 80 opp-hz = /bits/ 64 <1800000000>; 81 opp-microvolt = <900000>; 82 }; 83 }; 84 }; 85 86 oscillator-40m { 87 compatible = "fixed-clock"; 88 clock-frequency = <40000000>; 89 #clock-cells = <0>; 90 clock-output-names = "clkxtal"; 91 }; 92 93 pmu { 94 compatible = "arm,cortex-a73-pmu"; 95 interrupt-parent = <&gic>; 96 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 97 }; 98 99 psci { 100 compatible = "arm,psci-0.2"; 101 method = "smc"; 102 }; 103 104 reserved-memory { 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ 110 secmon@43000000 { 111 reg = <0 0x43000000 0 0x50000>; 112 no-map; 113 }; 114 }; 115 116 soc { 117 compatible = "simple-bus"; 118 ranges; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 122 gic: interrupt-controller@c000000 { 123 compatible = "arm,gic-v3"; 124 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 125 <0 0x0c080000 0 0x200000>, /* GICR */ 126 <0 0x0c400000 0 0x2000>, /* GICC */ 127 <0 0x0c410000 0 0x1000>, /* GICH */ 128 <0 0x0c420000 0 0x2000>; /* GICV */ 129 interrupt-parent = <&gic>; 130 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-controller; 132 #interrupt-cells = <3>; 133 }; 134 135 infracfg: clock-controller@10001000 { 136 compatible = "mediatek,mt7988-infracfg", "syscon"; 137 reg = <0 0x10001000 0 0x1000>; 138 #clock-cells = <1>; 139 #reset-cells = <1>; 140 }; 141 142 topckgen: clock-controller@1001b000 { 143 compatible = "mediatek,mt7988-topckgen", "syscon"; 144 reg = <0 0x1001b000 0 0x1000>; 145 #clock-cells = <1>; 146 }; 147 148 watchdog: watchdog@1001c000 { 149 compatible = "mediatek,mt7988-wdt"; 150 reg = <0 0x1001c000 0 0x1000>; 151 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 152 #reset-cells = <1>; 153 }; 154 155 apmixedsys: clock-controller@1001e000 { 156 compatible = "mediatek,mt7988-apmixedsys"; 157 reg = <0 0x1001e000 0 0x1000>; 158 #clock-cells = <1>; 159 }; 160 161 pio: pinctrl@1001f000 { 162 compatible = "mediatek,mt7988-pinctrl"; 163 reg = <0 0x1001f000 0 0x1000>, 164 <0 0x11c10000 0 0x1000>, 165 <0 0x11d00000 0 0x1000>, 166 <0 0x11d20000 0 0x1000>, 167 <0 0x11e00000 0 0x1000>, 168 <0 0x11f00000 0 0x1000>, 169 <0 0x1000b000 0 0x1000>; 170 reg-names = "gpio", "iocfg_tr", 171 "iocfg_br", "iocfg_rb", 172 "iocfg_lb", "iocfg_tl", "eint"; 173 gpio-controller; 174 #gpio-cells = <2>; 175 gpio-ranges = <&pio 0 0 84>; 176 interrupt-controller; 177 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-parent = <&gic>; 179 #interrupt-cells = <2>; 180 181 pcie0_pins: pcie0-pins { 182 mux { 183 function = "pcie"; 184 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", 185 "pcie_wake_n0_0"; 186 }; 187 }; 188 189 pcie1_pins: pcie1-pins { 190 mux { 191 function = "pcie"; 192 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", 193 "pcie_wake_n1_0"; 194 }; 195 }; 196 197 pcie2_pins: pcie2-pins { 198 mux { 199 function = "pcie"; 200 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", 201 "pcie_wake_n2_0"; 202 }; 203 }; 204 205 pcie3_pins: pcie3-pins { 206 mux { 207 function = "pcie"; 208 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", 209 "pcie_wake_n3_0"; 210 }; 211 }; 212 213 spi1_pins: spi1-pins { 214 mux { 215 function = "spi"; 216 groups = "spi1"; 217 }; 218 }; 219 220 uart0_pins: uart0-pins { 221 mux { 222 function = "uart"; 223 groups = "uart0"; 224 }; 225 }; 226 }; 227 228 pwm: pwm@10048000 { 229 compatible = "mediatek,mt7988-pwm"; 230 reg = <0 0x10048000 0 0x1000>; 231 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, 232 <&infracfg CLK_INFRA_66M_PWM_HCK>, 233 <&infracfg CLK_INFRA_66M_PWM_CK1>, 234 <&infracfg CLK_INFRA_66M_PWM_CK2>, 235 <&infracfg CLK_INFRA_66M_PWM_CK3>, 236 <&infracfg CLK_INFRA_66M_PWM_CK4>, 237 <&infracfg CLK_INFRA_66M_PWM_CK5>, 238 <&infracfg CLK_INFRA_66M_PWM_CK6>, 239 <&infracfg CLK_INFRA_66M_PWM_CK7>, 240 <&infracfg CLK_INFRA_66M_PWM_CK8>; 241 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 242 "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; 243 #pwm-cells = <2>; 244 status = "disabled"; 245 }; 246 247 mcusys: mcusys@100e0000 { 248 compatible = "mediatek,mt7988-mcusys", "syscon"; 249 reg = <0 0x100e0000 0 0x1000>; 250 #clock-cells = <1>; 251 }; 252 253 serial0: serial@11000000 { 254 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 255 reg = <0 0x11000000 0 0x100>; 256 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-names = "uart", "wakeup"; 258 clocks = <&topckgen CLK_TOP_UART_SEL>, 259 <&infracfg CLK_INFRA_52M_UART0_CK>; 260 clock-names = "baud", "bus"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&uart0_pins>; 263 status = "disabled"; 264 }; 265 266 serial@11000100 { 267 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 268 reg = <0 0x11000100 0 0x100>; 269 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-names = "uart", "wakeup"; 271 clocks = <&topckgen CLK_TOP_UART_SEL>, 272 <&infracfg CLK_INFRA_52M_UART1_CK>; 273 clock-names = "baud", "bus"; 274 status = "disabled"; 275 }; 276 277 serial@11000200 { 278 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 279 reg = <0 0x11000200 0 0x100>; 280 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 281 interrupt-names = "uart", "wakeup"; 282 clocks = <&topckgen CLK_TOP_UART_SEL>, 283 <&infracfg CLK_INFRA_52M_UART2_CK>; 284 clock-names = "baud", "bus"; 285 status = "disabled"; 286 }; 287 288 i2c0: i2c@11003000 { 289 compatible = "mediatek,mt7981-i2c"; 290 reg = <0 0x11003000 0 0x1000>, 291 <0 0x10217080 0 0x80>; 292 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 293 clock-div = <1>; 294 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 295 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 296 clock-names = "main", "dma"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 i2c1: i2c@11004000 { 303 compatible = "mediatek,mt7981-i2c"; 304 reg = <0 0x11004000 0 0x1000>, 305 <0 0x10217100 0 0x80>; 306 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 307 clock-div = <1>; 308 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 309 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 310 clock-names = "main", "dma"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 status = "disabled"; 314 }; 315 316 i2c2: i2c@11005000 { 317 compatible = "mediatek,mt7981-i2c"; 318 reg = <0 0x11005000 0 0x1000>, 319 <0 0x10217180 0 0x80>; 320 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 321 clock-div = <1>; 322 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 323 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 324 clock-names = "main", "dma"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 spi0: spi@11007000 { 331 compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; 332 reg = <0 0x11007000 0 0x100>; 333 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&topckgen CLK_TOP_MPLL_D2>, 335 <&topckgen CLK_TOP_SPI_SEL>, 336 <&infracfg CLK_INFRA_104M_SPI0>, 337 <&infracfg CLK_INFRA_66M_SPI0_HCK>; 338 clock-names = "parent-clk", "sel-clk", "spi-clk", 339 "hclk"; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "disabled"; 343 }; 344 345 spi1: spi@11008000 { 346 compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; 347 reg = <0 0x11008000 0 0x100>; 348 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&topckgen CLK_TOP_MPLL_D2>, 350 <&topckgen CLK_TOP_SPIM_MST_SEL>, 351 <&infracfg CLK_INFRA_104M_SPI1>, 352 <&infracfg CLK_INFRA_66M_SPI1_HCK>; 353 clock-names = "parent-clk", "sel-clk", "spi-clk", 354 "hclk"; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&spi1_pins>; 359 status = "disabled"; 360 }; 361 362 spi2: spi@11009000 { 363 compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; 364 reg = <0 0x11009000 0 0x100>; 365 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&topckgen CLK_TOP_MPLL_D2>, 367 <&topckgen CLK_TOP_SPI_SEL>, 368 <&infracfg CLK_INFRA_104M_SPI2_BCK>, 369 <&infracfg CLK_INFRA_66M_SPI2_HCK>; 370 clock-names = "parent-clk", "sel-clk", "spi-clk", 371 "hclk"; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 status = "disabled"; 375 }; 376 377 lvts: lvts@1100a000 { 378 compatible = "mediatek,mt7988-lvts-ap"; 379 #thermal-sensor-cells = <1>; 380 reg = <0 0x1100a000 0 0x1000>; 381 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; 382 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 383 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; 384 nvmem-cells = <&lvts_calibration>; 385 nvmem-cell-names = "lvts-calib-data-1"; 386 }; 387 388 usb@11190000 { 389 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 390 reg = <0 0x11190000 0 0x2e00>, 391 <0 0x11193e00 0 0x0100>; 392 reg-names = "mac", "ippc"; 393 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&infracfg CLK_INFRA_USB_SYS>, 395 <&infracfg CLK_INFRA_USB_REF>, 396 <&infracfg CLK_INFRA_66M_USB_HCK>, 397 <&infracfg CLK_INFRA_133M_USB_HCK>, 398 <&infracfg CLK_INFRA_USB_XHCI>; 399 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 400 phys = <&xphyu2port0 PHY_TYPE_USB2>, 401 <&xphyu3port0 PHY_TYPE_USB3>; 402 status = "disabled"; 403 }; 404 405 ssusb1: usb@11200000 { 406 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 407 reg = <0 0x11200000 0 0x2e00>, 408 <0 0x11203e00 0 0x0100>; 409 reg-names = "mac", "ippc"; 410 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, 412 <&infracfg CLK_INFRA_USB_CK_P1>, 413 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, 414 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, 415 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; 416 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 417 phys = <&tphyu2port0 PHY_TYPE_USB2>, 418 <&tphyu3port0 PHY_TYPE_USB3>; 419 status = "disabled"; 420 }; 421 422 mmc0: mmc@11230000 { 423 compatible = "mediatek,mt7988-mmc"; 424 reg = <0 0x11230000 0 0x1000>, 425 <0 0x11D60000 0 0x1000>; 426 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&infracfg CLK_INFRA_MSDC400>, 428 <&infracfg CLK_INFRA_MSDC2_HCK>, 429 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, 430 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; 431 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, 432 <&topckgen CLK_TOP_EMMC_400M_SEL>; 433 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, 434 <&apmixedsys CLK_APMIXED_MSDCPLL>; 435 clock-names = "source", "hclk", "axi_cg", "ahb_cg"; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 pcie2: pcie@11280000 { 442 compatible = "mediatek,mt7986-pcie", 443 "mediatek,mt8192-pcie"; 444 device_type = "pci"; 445 #address-cells = <3>; 446 #size-cells = <2>; 447 reg = <0 0x11280000 0 0x2000>; 448 reg-names = "pcie-mac"; 449 linux,pci-domain = <3>; 450 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 451 bus-range = <0x00 0xff>; 452 ranges = <0x81000000 0x00 0x20000000 0x00 453 0x20000000 0x00 0x00200000>, 454 <0x82000000 0x00 0x20200000 0x00 455 0x20200000 0x00 0x07e00000>; 456 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, 457 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, 458 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, 459 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; 460 clock-names = "pl_250m", "tl_26m", "peri_26m", 461 "top_133m"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pcie2_pins>; 464 status = "disabled"; 465 466 phys = <&xphyu3port0 PHY_TYPE_PCIE>; 467 phy-names = "pcie-phy"; 468 469 #interrupt-cells = <1>; 470 interrupt-map-mask = <0 0 0 0x7>; 471 interrupt-map = <0 0 0 1 &pcie_intc2 0>, 472 <0 0 0 2 &pcie_intc2 1>, 473 <0 0 0 3 &pcie_intc2 2>, 474 <0 0 0 4 &pcie_intc2 3>; 475 pcie_intc2: interrupt-controller { 476 #address-cells = <0>; 477 #interrupt-cells = <1>; 478 interrupt-controller; 479 }; 480 }; 481 482 pcie3: pcie@11290000 { 483 compatible = "mediatek,mt7986-pcie", 484 "mediatek,mt8192-pcie"; 485 device_type = "pci"; 486 #address-cells = <3>; 487 #size-cells = <2>; 488 reg = <0 0x11290000 0 0x2000>; 489 reg-names = "pcie-mac"; 490 linux,pci-domain = <2>; 491 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 492 bus-range = <0x00 0xff>; 493 ranges = <0x81000000 0x00 0x28000000 0x00 494 0x28000000 0x00 0x00200000>, 495 <0x82000000 0x00 0x28200000 0x00 496 0x28200000 0x00 0x07e00000>; 497 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, 498 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, 499 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, 500 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; 501 clock-names = "pl_250m", "tl_26m", "peri_26m", 502 "top_133m"; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&pcie3_pins>; 505 status = "disabled"; 506 507 #interrupt-cells = <1>; 508 interrupt-map-mask = <0 0 0 0x7>; 509 interrupt-map = <0 0 0 1 &pcie_intc3 0>, 510 <0 0 0 2 &pcie_intc3 1>, 511 <0 0 0 3 &pcie_intc3 2>, 512 <0 0 0 4 &pcie_intc3 3>; 513 pcie_intc3: interrupt-controller { 514 #address-cells = <0>; 515 #interrupt-cells = <1>; 516 interrupt-controller; 517 }; 518 }; 519 520 pcie0: pcie@11300000 { 521 compatible = "mediatek,mt7986-pcie", 522 "mediatek,mt8192-pcie"; 523 device_type = "pci"; 524 #address-cells = <3>; 525 #size-cells = <2>; 526 reg = <0 0x11300000 0 0x2000>; 527 reg-names = "pcie-mac"; 528 linux,pci-domain = <0>; 529 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 530 bus-range = <0x00 0xff>; 531 ranges = <0x81000000 0x00 0x30000000 0x00 532 0x30000000 0x00 0x00200000>, 533 <0x82000000 0x00 0x30200000 0x00 534 0x30200000 0x00 0x07e00000>; 535 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, 536 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, 537 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, 538 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; 539 clock-names = "pl_250m", "tl_26m", "peri_26m", 540 "top_133m"; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&pcie0_pins>; 543 status = "disabled"; 544 545 #interrupt-cells = <1>; 546 interrupt-map-mask = <0 0 0 0x7>; 547 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 548 <0 0 0 2 &pcie_intc0 1>, 549 <0 0 0 3 &pcie_intc0 2>, 550 <0 0 0 4 &pcie_intc0 3>; 551 pcie_intc0: interrupt-controller { 552 #address-cells = <0>; 553 #interrupt-cells = <1>; 554 interrupt-controller; 555 }; 556 }; 557 558 pcie1: pcie@11310000 { 559 compatible = "mediatek,mt7986-pcie", 560 "mediatek,mt8192-pcie"; 561 device_type = "pci"; 562 #address-cells = <3>; 563 #size-cells = <2>; 564 reg = <0 0x11310000 0 0x2000>; 565 reg-names = "pcie-mac"; 566 linux,pci-domain = <1>; 567 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 568 bus-range = <0x00 0xff>; 569 ranges = <0x81000000 0x00 0x38000000 0x00 570 0x38000000 0x00 0x00200000>, 571 <0x82000000 0x00 0x38200000 0x00 572 0x38200000 0x00 0x07e00000>; 573 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, 574 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, 575 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, 576 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; 577 clock-names = "pl_250m", "tl_26m", "peri_26m", 578 "top_133m"; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pcie1_pins>; 581 status = "disabled"; 582 583 #interrupt-cells = <1>; 584 interrupt-map-mask = <0 0 0 0x7>; 585 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 586 <0 0 0 2 &pcie_intc1 1>, 587 <0 0 0 3 &pcie_intc1 2>, 588 <0 0 0 4 &pcie_intc1 3>; 589 pcie_intc1: interrupt-controller { 590 #address-cells = <0>; 591 #interrupt-cells = <1>; 592 interrupt-controller; 593 }; 594 }; 595 596 tphy: t-phy@11c50000 { 597 compatible = "mediatek,mt7986-tphy", 598 "mediatek,generic-tphy-v2"; 599 #address-cells = <2>; 600 #size-cells = <2>; 601 ranges; 602 status = "disabled"; 603 604 tphyu2port0: usb-phy@11c50000 { 605 reg = <0 0x11c50000 0 0x700>; 606 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; 607 clock-names = "ref"; 608 #phy-cells = <1>; 609 }; 610 611 tphyu3port0: usb-phy@11c50700 { 612 reg = <0 0x11c50700 0 0x900>; 613 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; 614 clock-names = "ref"; 615 #phy-cells = <1>; 616 }; 617 }; 618 619 620 topmisc: system-controller@11d10084 { 621 compatible = "mediatek,mt7988-topmisc", 622 "syscon"; 623 reg = <0 0x11d10084 0 0xff80>; 624 }; 625 626 xsphy: xs-phy@11e10000 { 627 compatible = "mediatek,mt7988-xsphy", 628 "mediatek,xsphy"; 629 #address-cells = <2>; 630 #size-cells = <2>; 631 ranges; 632 status = "disabled"; 633 634 xphyu2port0: usb-phy@11e10000 { 635 reg = <0 0x11e10000 0 0x400>; 636 clocks = <&infracfg CLK_INFRA_USB_UTMI>; 637 clock-names = "ref"; 638 #phy-cells = <1>; 639 }; 640 641 xphyu3port0: usb-phy@11e13000 { 642 reg = <0 0x11e13400 0 0x500>; 643 clocks = <&infracfg CLK_INFRA_USB_PIPE>; 644 clock-names = "ref"; 645 #phy-cells = <1>; 646 mediatek,syscon-type = <&topmisc 0x194 0>; 647 }; 648 }; 649 650 clock-controller@11f40000 { 651 compatible = "mediatek,mt7988-xfi-pll"; 652 reg = <0 0x11f40000 0 0x1000>; 653 resets = <&watchdog 16>; 654 #clock-cells = <1>; 655 }; 656 657 efuse@11f50000 { 658 compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; 659 reg = <0 0x11f50000 0 0x1000>; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 663 lvts_calibration: calib@918 { 664 reg = <0x918 0x28>; 665 }; 666 667 phy_calibration_p0: calib@940 { 668 reg = <0x940 0x10>; 669 }; 670 671 phy_calibration_p1: calib@954 { 672 reg = <0x954 0x10>; 673 }; 674 675 phy_calibration_p2: calib@968 { 676 reg = <0x968 0x10>; 677 }; 678 679 phy_calibration_p3: calib@97c { 680 reg = <0x97c 0x10>; 681 }; 682 }; 683 684 clock-controller@15000000 { 685 compatible = "mediatek,mt7988-ethsys", "syscon"; 686 reg = <0 0x15000000 0 0x1000>; 687 #clock-cells = <1>; 688 #reset-cells = <1>; 689 }; 690 691 clock-controller@15031000 { 692 compatible = "mediatek,mt7988-ethwarp"; 693 reg = <0 0x15031000 0 0x1000>; 694 #clock-cells = <1>; 695 #reset-cells = <1>; 696 }; 697 }; 698 699 thermal-zones { 700 cpu_thermal: cpu-thermal { 701 polling-delay-passive = <1000>; 702 polling-delay = <1000>; 703 thermal-sensors = <&lvts 0>; 704 trips { 705 cpu_trip_crit: crit { 706 temperature = <125000>; 707 hysteresis = <2000>; 708 type = "critical"; 709 }; 710 }; 711 }; 712 }; 713 714 timer { 715 compatible = "arm,armv8-timer"; 716 interrupt-parent = <&gic>; 717 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 718 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 719 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 720 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 721 }; 722}; 723