xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c (revision 9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d)
1 /*
2  * Copyright 2017 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "priv.h"
23 #include "chan.h"
24 #include "head.h"
25 #include "ior.h"
26 
27 #include <nvif/class.h>
28 
29 static const struct nvkm_ior_func
30 mcp77_sor = {
31 	.state = g94_sor_state,
32 	.power = nv50_sor_power,
33 	.clock = nv50_sor_clock,
34 	.bl = &nv50_sor_bl,
35 	.hdmi = &g84_sor_hdmi,
36 	.dp = &g94_sor_dp,
37 };
38 
39 static int
mcp77_sor_new(struct nvkm_disp * disp,int id)40 mcp77_sor_new(struct nvkm_disp *disp, int id)
41 {
42 	return nvkm_ior_new_(&mcp77_sor, disp, SOR, id, false);
43 }
44 
45 static const struct nvkm_disp_func
46 mcp77_disp = {
47 	.oneinit = nv50_disp_oneinit,
48 	.init = nv50_disp_init,
49 	.fini = nv50_disp_fini,
50 	.intr = nv50_disp_intr,
51 	.super = nv50_disp_super,
52 	.uevent = &nv50_disp_chan_uevent,
53 	.head = { .cnt = nv50_head_cnt, .new = nv50_head_new },
54 	.dac = { .cnt = nv50_dac_cnt, .new = nv50_dac_new },
55 	.sor = { .cnt = g94_sor_cnt, .new = mcp77_sor_new },
56 	.pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new },
57 	.root = { 0,0,GT206_DISP },
58 	.user = {
59 		{{0,0,  G82_DISP_CURSOR             }, nvkm_disp_chan_new, & nv50_disp_curs },
60 		{{0,0,  G82_DISP_OVERLAY            }, nvkm_disp_chan_new, & nv50_disp_oimm },
61 		{{0,0,GT200_DISP_BASE_CHANNEL_DMA   }, nvkm_disp_chan_new, &  g84_disp_base },
62 		{{0,0,GT206_DISP_CORE_CHANNEL_DMA   }, nvkm_disp_core_new, &  g94_disp_core },
63 		{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &gt200_disp_ovly },
64 		{}
65 	},
66 };
67 
68 int
mcp77_disp_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_disp ** pdisp)69 mcp77_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
70 	       struct nvkm_disp **pdisp)
71 {
72 	return nvkm_disp_new_(&mcp77_disp, device, type, inst, pdisp);
73 }
74