1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Microchip MCP3911, Two-channel Analog Front End
4 *
5 * Copyright (C) 2018 Marcus Folkesson <marcus.folkesson@gmail.com>
6 * Copyright (C) 2018 Kent Gustavsson <kent@minoris.se>
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dev_printk.h>
14 #include <linux/err.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/triggered_buffer.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/trigger.h>
27
28 #include <linux/unaligned.h>
29
30 #define MCP3911_REG_CHANNEL0 0x00
31 #define MCP3911_REG_CHANNEL1 0x03
32 #define MCP3911_REG_MOD 0x06
33 #define MCP3911_REG_PHASE 0x07
34 #define MCP3911_REG_GAIN 0x09
35 #define MCP3911_GAIN_MASK(ch) (GENMASK(2, 0) << 3 * (ch))
36 #define MCP3911_GAIN_VAL(ch, val) ((val << 3 * (ch)) & MCP3911_GAIN_MASK(ch))
37
38 #define MCP3911_REG_STATUSCOM 0x0a
39 #define MCP3911_STATUSCOM_DRHIZ BIT(12)
40 #define MCP3911_STATUSCOM_READ GENMASK(7, 6)
41 #define MCP3911_STATUSCOM_CH1_24WIDTH BIT(4)
42 #define MCP3911_STATUSCOM_CH0_24WIDTH BIT(3)
43 #define MCP3911_STATUSCOM_EN_OFFCAL BIT(2)
44 #define MCP3911_STATUSCOM_EN_GAINCAL BIT(1)
45
46 #define MCP3911_REG_CONFIG 0x0c
47 #define MCP3911_CONFIG_CLKEXT BIT(1)
48 #define MCP3911_CONFIG_VREFEXT BIT(2)
49 #define MCP3911_CONFIG_OSR GENMASK(13, 11)
50
51 #define MCP3911_REG_OFFCAL_CH0 0x0e
52 #define MCP3911_REG_GAINCAL_CH0 0x11
53 #define MCP3911_REG_OFFCAL_CH1 0x14
54 #define MCP3911_REG_GAINCAL_CH1 0x17
55 #define MCP3911_REG_VREFCAL 0x1a
56
57 #define MCP3911_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch) * 3)
58 #define MCP3911_OFFCAL(ch) (MCP3911_REG_OFFCAL_CH0 + (ch) * 6)
59
60 /* Internal voltage reference in mV */
61 #define MCP3911_INT_VREF_MV 1200
62
63 #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff)
64 #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff)
65 #define MCP3911_REG_MASK GENMASK(4, 1)
66
67 #define MCP3911_NUM_SCALES 6
68
69 /* Registers compatible with MCP3910 */
70 #define MCP3910_REG_STATUSCOM 0x0c
71 #define MCP3910_STATUSCOM_READ GENMASK(23, 22)
72 #define MCP3910_STATUSCOM_DRHIZ BIT(20)
73
74 #define MCP3910_REG_GAIN 0x0b
75
76 #define MCP3910_REG_CONFIG0 0x0d
77 #define MCP3910_CONFIG0_EN_OFFCAL BIT(23)
78 #define MCP3910_CONFIG0_OSR GENMASK(15, 13)
79
80 #define MCP3910_REG_CONFIG1 0x0e
81 #define MCP3910_CONFIG1_CLKEXT BIT(6)
82 #define MCP3910_CONFIG1_VREFEXT BIT(7)
83
84 #define MCP3910_CHANNEL(ch) (MCP3911_REG_CHANNEL0 + (ch))
85
86 #define MCP3910_REG_OFFCAL_CH0 0x0f
87 #define MCP3910_OFFCAL(ch) (MCP3910_REG_OFFCAL_CH0 + (ch) * 6)
88
89 /* Maximal number of channels used by the MCP39XX family */
90 #define MCP39XX_MAX_NUM_CHANNELS 8
91
92 static const int mcp3911_osr_table[] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 };
93 static u32 mcp3911_scale_table[MCP3911_NUM_SCALES][2];
94
95 enum mcp3911_id {
96 MCP3910,
97 MCP3911,
98 MCP3912,
99 MCP3913,
100 MCP3914,
101 MCP3918,
102 MCP3919,
103 };
104
105 struct mcp3911;
106 struct mcp3911_chip_info {
107 const struct iio_chan_spec *channels;
108 unsigned int num_channels;
109
110 int (*config)(struct mcp3911 *adc, bool external_vref);
111 int (*get_osr)(struct mcp3911 *adc, u32 *val);
112 int (*set_osr)(struct mcp3911 *adc, u32 val);
113 int (*enable_offset)(struct mcp3911 *adc, bool enable);
114 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
115 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
116 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
117 int (*get_raw)(struct mcp3911 *adc, int channel, int *val);
118 };
119
120 struct mcp3911 {
121 struct spi_device *spi;
122 struct mutex lock;
123 struct clk *clki;
124 u32 dev_addr;
125 struct iio_trigger *trig;
126 u32 gain[MCP39XX_MAX_NUM_CHANNELS];
127 const struct mcp3911_chip_info *chip;
128 struct {
129 u32 channels[MCP39XX_MAX_NUM_CHANNELS];
130 aligned_s64 ts;
131 } scan;
132
133 u8 tx_buf __aligned(IIO_DMA_MINALIGN);
134 u8 rx_buf[MCP39XX_MAX_NUM_CHANNELS * 3];
135 };
136
mcp3911_read(struct mcp3911 * adc,u8 reg,u32 * val,u8 len)137 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len)
138 {
139 int ret;
140
141 reg = MCP3911_REG_READ(reg, adc->dev_addr);
142 ret = spi_write_then_read(adc->spi, ®, 1, val, len);
143 if (ret < 0)
144 return ret;
145
146 be32_to_cpus(val);
147 *val >>= ((4 - len) * 8);
148 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val,
149 FIELD_GET(MCP3911_REG_MASK, reg));
150 return ret;
151 }
152
mcp3911_write(struct mcp3911 * adc,u8 reg,u32 val,u8 len)153 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len)
154 {
155 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg);
156
157 val <<= (3 - len) * 8;
158 cpu_to_be32s(&val);
159 val |= MCP3911_REG_WRITE(reg, adc->dev_addr);
160
161 return spi_write(adc->spi, &val, len + 1);
162 }
163
mcp3911_update(struct mcp3911 * adc,u8 reg,u32 mask,u32 val,u8 len)164 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len)
165 {
166 u32 tmp;
167 int ret;
168
169 ret = mcp3911_read(adc, reg, &tmp, len);
170 if (ret)
171 return ret;
172
173 val &= mask;
174 val |= tmp & ~mask;
175 return mcp3911_write(adc, reg, val, len);
176 }
177
mcp3911_read_s24(struct mcp3911 * const adc,u8 const reg,s32 * const val)178 static int mcp3911_read_s24(struct mcp3911 *const adc, u8 const reg, s32 *const val)
179 {
180 u32 uval;
181 int const ret = mcp3911_read(adc, reg, &uval, 3);
182
183 if (ret)
184 return ret;
185
186 *val = sign_extend32(uval, 23);
187 return ret;
188 }
189
mcp3910_enable_offset(struct mcp3911 * adc,bool enable)190 static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable)
191 {
192 unsigned int mask = MCP3910_CONFIG0_EN_OFFCAL;
193 unsigned int value = enable ? mask : 0;
194
195 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3);
196 }
197
mcp3910_get_offset(struct mcp3911 * adc,int channel,int * val)198 static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val)
199 {
200 return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3);
201 }
202
mcp3910_set_offset(struct mcp3911 * adc,int channel,int val)203 static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val)
204 {
205 int ret;
206
207 ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3);
208 if (ret)
209 return ret;
210
211 return adc->chip->enable_offset(adc, 1);
212 }
213
mcp3910_get_raw(struct mcp3911 * adc,int channel,s32 * val)214 static int mcp3910_get_raw(struct mcp3911 *adc, int channel, s32 *val)
215 {
216 return mcp3911_read_s24(adc, MCP3910_CHANNEL(channel), val);
217 }
218
mcp3911_enable_offset(struct mcp3911 * adc,bool enable)219 static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable)
220 {
221 unsigned int mask = MCP3911_STATUSCOM_EN_OFFCAL;
222 unsigned int value = enable ? mask : 0;
223
224 return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2);
225 }
226
mcp3911_get_offset(struct mcp3911 * adc,int channel,int * val)227 static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val)
228 {
229 return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3);
230 }
231
mcp3911_set_offset(struct mcp3911 * adc,int channel,int val)232 static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val)
233 {
234 int ret;
235
236 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3);
237 if (ret)
238 return ret;
239
240 return adc->chip->enable_offset(adc, 1);
241 }
242
mcp3911_get_raw(struct mcp3911 * adc,int channel,s32 * val)243 static int mcp3911_get_raw(struct mcp3911 *adc, int channel, s32 *val)
244 {
245 return mcp3911_read_s24(adc, MCP3911_CHANNEL(channel), val);
246 }
247
mcp3910_get_osr(struct mcp3911 * adc,u32 * val)248 static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val)
249 {
250 int ret;
251 unsigned int osr;
252
253 ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3);
254 if (ret)
255 return ret;
256
257 osr = FIELD_GET(MCP3910_CONFIG0_OSR, *val);
258 *val = 32 << osr;
259 return 0;
260 }
261
mcp3910_set_osr(struct mcp3911 * adc,u32 val)262 static int mcp3910_set_osr(struct mcp3911 *adc, u32 val)
263 {
264 unsigned int osr = FIELD_PREP(MCP3910_CONFIG0_OSR, val);
265 unsigned int mask = MCP3910_CONFIG0_OSR;
266
267 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3);
268 }
269
mcp3911_set_osr(struct mcp3911 * adc,u32 val)270 static int mcp3911_set_osr(struct mcp3911 *adc, u32 val)
271 {
272 unsigned int osr = FIELD_PREP(MCP3911_CONFIG_OSR, val);
273 unsigned int mask = MCP3911_CONFIG_OSR;
274
275 return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2);
276 }
277
mcp3911_get_osr(struct mcp3911 * adc,u32 * val)278 static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val)
279 {
280 int ret;
281 unsigned int osr;
282
283 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2);
284 if (ret)
285 return ret;
286
287 osr = FIELD_GET(MCP3911_CONFIG_OSR, *val);
288 *val = 32 << osr;
289 return ret;
290 }
291
mcp3910_set_scale(struct mcp3911 * adc,int channel,u32 val)292 static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val)
293 {
294 return mcp3911_update(adc, MCP3910_REG_GAIN,
295 MCP3911_GAIN_MASK(channel),
296 MCP3911_GAIN_VAL(channel, val), 3);
297 }
298
mcp3911_set_scale(struct mcp3911 * adc,int channel,u32 val)299 static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val)
300 {
301 return mcp3911_update(adc, MCP3911_REG_GAIN,
302 MCP3911_GAIN_MASK(channel),
303 MCP3911_GAIN_VAL(channel, val), 1);
304 }
305
mcp3911_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)306 static int mcp3911_write_raw_get_fmt(struct iio_dev *indio_dev,
307 struct iio_chan_spec const *chan,
308 long mask)
309 {
310 switch (mask) {
311 case IIO_CHAN_INFO_SCALE:
312 return IIO_VAL_INT_PLUS_NANO;
313 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
314 return IIO_VAL_INT;
315 default:
316 return IIO_VAL_INT_PLUS_NANO;
317 }
318 }
319
mcp3911_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)320 static int mcp3911_read_avail(struct iio_dev *indio_dev,
321 struct iio_chan_spec const *chan,
322 const int **vals, int *type, int *length,
323 long info)
324 {
325 switch (info) {
326 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
327 *type = IIO_VAL_INT;
328 *vals = mcp3911_osr_table;
329 *length = ARRAY_SIZE(mcp3911_osr_table);
330 return IIO_AVAIL_LIST;
331 case IIO_CHAN_INFO_SCALE:
332 *type = IIO_VAL_INT_PLUS_NANO;
333 *vals = (int *)mcp3911_scale_table;
334 *length = ARRAY_SIZE(mcp3911_scale_table) * 2;
335 return IIO_AVAIL_LIST;
336 default:
337 return -EINVAL;
338 }
339 }
340
mcp3911_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int * val,int * val2,long mask)341 static int mcp3911_read_raw(struct iio_dev *indio_dev,
342 struct iio_chan_spec const *channel, int *val,
343 int *val2, long mask)
344 {
345 struct mcp3911 *adc = iio_priv(indio_dev);
346 int ret;
347
348 guard(mutex)(&adc->lock);
349 switch (mask) {
350 case IIO_CHAN_INFO_RAW:
351 ret = adc->chip->get_raw(adc, channel->channel, val);
352 if (ret)
353 return ret;
354 return IIO_VAL_INT;
355 case IIO_CHAN_INFO_OFFSET:
356 ret = adc->chip->get_offset(adc, channel->channel, val);
357 if (ret)
358 return ret;
359
360 return IIO_VAL_INT;
361 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
362 ret = adc->chip->get_osr(adc, val);
363 if (ret)
364 return ret;
365
366 return IIO_VAL_INT;
367 case IIO_CHAN_INFO_SCALE:
368 *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0];
369 *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1];
370 return IIO_VAL_INT_PLUS_NANO;
371 default:
372 return -EINVAL;
373 }
374 }
375
mcp3911_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int val,int val2,long mask)376 static int mcp3911_write_raw(struct iio_dev *indio_dev,
377 struct iio_chan_spec const *channel, int val,
378 int val2, long mask)
379 {
380 struct mcp3911 *adc = iio_priv(indio_dev);
381
382 guard(mutex)(&adc->lock);
383 switch (mask) {
384 case IIO_CHAN_INFO_SCALE:
385 for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
386 if (val == mcp3911_scale_table[i][0] &&
387 val2 == mcp3911_scale_table[i][1]) {
388
389 adc->gain[channel->channel] = BIT(i);
390 return adc->chip->set_scale(adc, channel->channel, i);
391 }
392 }
393 return -EINVAL;
394 case IIO_CHAN_INFO_OFFSET:
395 if (val2 != 0)
396 return -EINVAL;
397
398 return adc->chip->set_offset(adc, channel->channel, val);
399 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
400 for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) {
401 if (val == mcp3911_osr_table[i]) {
402 return adc->chip->set_osr(adc, i);
403 }
404 }
405 return -EINVAL;
406 default:
407 return -EINVAL;
408 }
409 }
410
mcp3911_calc_scale_table(u32 vref_mv)411 static int mcp3911_calc_scale_table(u32 vref_mv)
412 {
413 u32 div;
414 u64 tmp;
415
416 /*
417 * For 24-bit Conversion
418 * Raw = ((Voltage)/(Vref) * 2^23 * Gain * 1.5
419 * Voltage = Raw * (Vref)/(2^23 * Gain * 1.5)
420 *
421 * ref = Reference voltage
422 * div = (2^23 * 1.5 * gain) = 12582912 * gain
423 */
424 for (int i = 0; i < MCP3911_NUM_SCALES; i++) {
425 div = 12582912 * BIT(i);
426 tmp = div_s64((s64)vref_mv * 1000000000LL, div);
427
428 mcp3911_scale_table[i][0] = 0;
429 mcp3911_scale_table[i][1] = tmp;
430 }
431
432 return 0;
433 }
434
435 #define MCP3911_CHAN(idx) { \
436 .type = IIO_VOLTAGE, \
437 .indexed = 1, \
438 .channel = idx, \
439 .scan_index = idx, \
440 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
441 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
442 BIT(IIO_CHAN_INFO_OFFSET) | \
443 BIT(IIO_CHAN_INFO_SCALE), \
444 .info_mask_shared_by_type_available = \
445 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
446 .info_mask_separate_available = \
447 BIT(IIO_CHAN_INFO_SCALE), \
448 .scan_type = { \
449 .sign = 's', \
450 .realbits = 24, \
451 .storagebits = 32, \
452 .endianness = IIO_BE, \
453 }, \
454 }
455
456 static const struct iio_chan_spec mcp3910_channels[] = {
457 MCP3911_CHAN(0),
458 MCP3911_CHAN(1),
459 IIO_CHAN_SOFT_TIMESTAMP(2),
460 };
461
462 static const struct iio_chan_spec mcp3911_channels[] = {
463 MCP3911_CHAN(0),
464 MCP3911_CHAN(1),
465 IIO_CHAN_SOFT_TIMESTAMP(2),
466 };
467
468 static const struct iio_chan_spec mcp3912_channels[] = {
469 MCP3911_CHAN(0),
470 MCP3911_CHAN(1),
471 MCP3911_CHAN(2),
472 MCP3911_CHAN(3),
473 IIO_CHAN_SOFT_TIMESTAMP(4),
474 };
475
476 static const struct iio_chan_spec mcp3913_channels[] = {
477 MCP3911_CHAN(0),
478 MCP3911_CHAN(1),
479 MCP3911_CHAN(2),
480 MCP3911_CHAN(3),
481 MCP3911_CHAN(4),
482 MCP3911_CHAN(5),
483 IIO_CHAN_SOFT_TIMESTAMP(6),
484 };
485
486 static const struct iio_chan_spec mcp3914_channels[] = {
487 MCP3911_CHAN(0),
488 MCP3911_CHAN(1),
489 MCP3911_CHAN(2),
490 MCP3911_CHAN(3),
491 MCP3911_CHAN(4),
492 MCP3911_CHAN(5),
493 MCP3911_CHAN(6),
494 MCP3911_CHAN(7),
495 IIO_CHAN_SOFT_TIMESTAMP(8),
496 };
497
498 static const struct iio_chan_spec mcp3918_channels[] = {
499 MCP3911_CHAN(0),
500 IIO_CHAN_SOFT_TIMESTAMP(1),
501 };
502
503 static const struct iio_chan_spec mcp3919_channels[] = {
504 MCP3911_CHAN(0),
505 MCP3911_CHAN(1),
506 MCP3911_CHAN(2),
507 IIO_CHAN_SOFT_TIMESTAMP(3),
508 };
509
mcp3911_trigger_handler(int irq,void * p)510 static irqreturn_t mcp3911_trigger_handler(int irq, void *p)
511 {
512 struct iio_poll_func *pf = p;
513 struct iio_dev *indio_dev = pf->indio_dev;
514 struct mcp3911 *adc = iio_priv(indio_dev);
515 struct device *dev = &adc->spi->dev;
516 struct spi_transfer xfer[] = {
517 {
518 .tx_buf = &adc->tx_buf,
519 .len = 1,
520 }, {
521 .rx_buf = adc->rx_buf,
522 .len = (adc->chip->num_channels - 1) * 3,
523 },
524 };
525 int scan_index;
526 int i = 0;
527 int ret;
528
529 guard(mutex)(&adc->lock);
530 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr);
531 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer));
532 if (ret < 0) {
533 dev_warn(dev, "failed to get conversion data\n");
534 goto out;
535 }
536
537 iio_for_each_active_channel(indio_dev, scan_index) {
538 const struct iio_chan_spec *scan_chan = &indio_dev->channels[scan_index];
539
540 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]);
541 i++;
542 }
543 iio_push_to_buffers_with_ts(indio_dev, &adc->scan, sizeof(adc->scan),
544 iio_get_time_ns(indio_dev));
545 out:
546 iio_trigger_notify_done(indio_dev->trig);
547
548 return IRQ_HANDLED;
549 }
550
551 static const struct iio_info mcp3911_info = {
552 .read_raw = mcp3911_read_raw,
553 .write_raw = mcp3911_write_raw,
554 .read_avail = mcp3911_read_avail,
555 .write_raw_get_fmt = mcp3911_write_raw_get_fmt,
556 };
557
mcp3911_config(struct mcp3911 * adc,bool external_vref)558 static int mcp3911_config(struct mcp3911 *adc, bool external_vref)
559 {
560 struct device *dev = &adc->spi->dev;
561 u32 regval;
562 int ret;
563
564 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2);
565 if (ret)
566 return ret;
567
568 regval &= ~MCP3911_CONFIG_VREFEXT;
569 if (external_vref) {
570 dev_dbg(dev, "use external voltage reference\n");
571 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 1);
572 } else {
573 dev_dbg(dev, "use internal voltage reference (1.2V)\n");
574 regval |= FIELD_PREP(MCP3911_CONFIG_VREFEXT, 0);
575 }
576
577 regval &= ~MCP3911_CONFIG_CLKEXT;
578 if (adc->clki) {
579 dev_dbg(dev, "use external clock as clocksource\n");
580 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 1);
581 } else {
582 dev_dbg(dev, "use crystal oscillator as clocksource\n");
583 regval |= FIELD_PREP(MCP3911_CONFIG_CLKEXT, 0);
584 }
585
586 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2);
587 if (ret)
588 return ret;
589
590 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2);
591 if (ret)
592 return ret;
593
594 /* Address counter incremented, cycle through register types */
595 regval &= ~MCP3911_STATUSCOM_READ;
596 regval |= FIELD_PREP(MCP3911_STATUSCOM_READ, 0x02);
597
598 regval &= ~MCP3911_STATUSCOM_DRHIZ;
599 if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
600 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 0);
601 else
602 regval |= FIELD_PREP(MCP3911_STATUSCOM_DRHIZ, 1);
603
604 /* Disable offset to ignore any old values in offset register */
605 regval &= ~MCP3911_STATUSCOM_EN_OFFCAL;
606
607 ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2);
608 if (ret)
609 return ret;
610
611 /* Set gain to 1 for all channels */
612 ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1);
613 if (ret)
614 return ret;
615
616 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
617 adc->gain[i] = 1;
618 regval &= ~MCP3911_GAIN_MASK(i);
619 }
620
621 return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1);
622 }
623
mcp3910_config(struct mcp3911 * adc,bool external_vref)624 static int mcp3910_config(struct mcp3911 *adc, bool external_vref)
625 {
626 struct device *dev = &adc->spi->dev;
627 u32 regval;
628 int ret;
629
630 ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3);
631 if (ret)
632 return ret;
633
634 regval &= ~MCP3910_CONFIG1_VREFEXT;
635 if (external_vref) {
636 dev_dbg(dev, "use external voltage reference\n");
637 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 1);
638 } else {
639 dev_dbg(dev, "use internal voltage reference (1.2V)\n");
640 regval |= FIELD_PREP(MCP3910_CONFIG1_VREFEXT, 0);
641 }
642
643 regval &= ~MCP3910_CONFIG1_CLKEXT;
644 if (adc->clki) {
645 dev_dbg(dev, "use external clock as clocksource\n");
646 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 1);
647 } else {
648 dev_dbg(dev, "use crystal oscillator as clocksource\n");
649 regval |= FIELD_PREP(MCP3910_CONFIG1_CLKEXT, 0);
650 }
651
652 ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3);
653 if (ret)
654 return ret;
655
656 ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3);
657 if (ret)
658 return ret;
659
660 /* Address counter incremented, cycle through register types */
661 regval &= ~MCP3910_STATUSCOM_READ;
662 regval |= FIELD_PREP(MCP3910_STATUSCOM_READ, 0x02);
663
664 regval &= ~MCP3910_STATUSCOM_DRHIZ;
665 if (device_property_read_bool(dev, "microchip,data-ready-hiz"))
666 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 0);
667 else
668 regval |= FIELD_PREP(MCP3910_STATUSCOM_DRHIZ, 1);
669
670 ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3);
671 if (ret)
672 return ret;
673
674 /* Set gain to 1 for all channels */
675 ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3);
676 if (ret)
677 return ret;
678
679 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
680 adc->gain[i] = 1;
681 regval &= ~MCP3911_GAIN_MASK(i);
682 }
683 ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3);
684 if (ret)
685 return ret;
686
687 /* Disable offset to ignore any old values in offset register */
688 return adc->chip->enable_offset(adc, 0);
689 }
690
mcp3911_set_trigger_state(struct iio_trigger * trig,bool enable)691 static int mcp3911_set_trigger_state(struct iio_trigger *trig, bool enable)
692 {
693 struct mcp3911 *adc = iio_trigger_get_drvdata(trig);
694
695 if (enable)
696 enable_irq(adc->spi->irq);
697 else
698 disable_irq(adc->spi->irq);
699
700 return 0;
701 }
702
703 static const struct iio_trigger_ops mcp3911_trigger_ops = {
704 .validate_device = iio_trigger_validate_own_device,
705 .set_trigger_state = mcp3911_set_trigger_state,
706 };
707
mcp3911_probe(struct spi_device * spi)708 static int mcp3911_probe(struct spi_device *spi)
709 {
710 struct device *dev = &spi->dev;
711 struct gpio_desc *gpio_reset;
712 struct iio_dev *indio_dev;
713 struct mcp3911 *adc;
714 bool external_vref;
715 u32 vref_mv;
716 int ret;
717
718 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
719 if (!indio_dev)
720 return -ENOMEM;
721
722 adc = iio_priv(indio_dev);
723 adc->spi = spi;
724 adc->chip = spi_get_device_match_data(spi);
725
726 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
727 if (ret < 0 && ret != -ENODEV)
728 return dev_err_probe(dev, ret, "failed to get vref voltage\n");
729
730 external_vref = ret != -ENODEV;
731 vref_mv = external_vref ? ret / 1000 : MCP3911_INT_VREF_MV;
732
733 adc->clki = devm_clk_get_enabled(dev, NULL);
734 if (IS_ERR(adc->clki)) {
735 if (PTR_ERR(adc->clki) == -ENOENT) {
736 adc->clki = NULL;
737 } else {
738 return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n");
739 }
740 }
741
742 /*
743 * Fallback to "device-addr" due to historical mismatch between
744 * dt-bindings and implementation.
745 */
746 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr);
747 if (ret)
748 device_property_read_u32(dev, "device-addr", &adc->dev_addr);
749 if (adc->dev_addr > 3) {
750 return dev_err_probe(dev, -EINVAL,
751 "invalid device address (%i). Must be in range 0-3.\n",
752 adc->dev_addr);
753 }
754 dev_dbg(dev, "use device address %i\n", adc->dev_addr);
755
756 gpio_reset = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_HIGH);
757 if (IS_ERR(gpio_reset))
758 return dev_err_probe(dev, PTR_ERR(gpio_reset),
759 "Cannot get reset GPIO\n");
760
761 if (gpio_reset) {
762 gpiod_set_value_cansleep(gpio_reset, 0);
763
764 /*
765 * Settling time after Hard Reset Mode (determined experimentally):
766 * 330 micro-seconds are too few; 470 micro-seconds are sufficient.
767 * Just in case, we add some safety factor...
768 */
769 fsleep(600);
770 }
771
772 ret = adc->chip->config(adc, external_vref);
773 if (ret)
774 return ret;
775
776 ret = mcp3911_calc_scale_table(vref_mv);
777 if (ret)
778 return ret;
779
780 /* Set gain to 1 for all channels */
781 for (int i = 0; i < adc->chip->num_channels - 1; i++) {
782 adc->gain[i] = 1;
783 ret = mcp3911_update(adc, MCP3911_REG_GAIN,
784 MCP3911_GAIN_MASK(i),
785 MCP3911_GAIN_VAL(i, 0), 1);
786 if (ret)
787 return ret;
788 }
789
790 indio_dev->name = spi_get_device_id(spi)->name;
791 indio_dev->modes = INDIO_DIRECT_MODE;
792 indio_dev->info = &mcp3911_info;
793 spi_set_drvdata(spi, indio_dev);
794
795 indio_dev->channels = adc->chip->channels;
796 indio_dev->num_channels = adc->chip->num_channels;
797
798 mutex_init(&adc->lock);
799
800 if (spi->irq > 0) {
801 adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
802 iio_device_id(indio_dev));
803 if (!adc->trig)
804 return -ENOMEM;
805
806 adc->trig->ops = &mcp3911_trigger_ops;
807 iio_trigger_set_drvdata(adc->trig, adc);
808 ret = devm_iio_trigger_register(dev, adc->trig);
809 if (ret)
810 return ret;
811
812 /*
813 * The device generates interrupts as long as it is powered up.
814 * Some platforms might not allow the option to power it down so
815 * don't enable the interrupt to avoid extra load on the system.
816 */
817 ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll,
818 IRQF_NO_AUTOEN | IRQF_ONESHOT,
819 indio_dev->name, adc->trig);
820 if (ret)
821 return ret;
822 }
823
824 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
825 mcp3911_trigger_handler, NULL);
826 if (ret)
827 return ret;
828
829 return devm_iio_device_register(dev, indio_dev);
830 }
831
832 static const struct mcp3911_chip_info mcp3911_chip_info[] = {
833 [MCP3910] = {
834 .channels = mcp3910_channels,
835 .num_channels = ARRAY_SIZE(mcp3910_channels),
836 .config = mcp3910_config,
837 .get_osr = mcp3910_get_osr,
838 .set_osr = mcp3910_set_osr,
839 .enable_offset = mcp3910_enable_offset,
840 .get_offset = mcp3910_get_offset,
841 .set_offset = mcp3910_set_offset,
842 .set_scale = mcp3910_set_scale,
843 .get_raw = mcp3910_get_raw,
844 },
845 [MCP3911] = {
846 .channels = mcp3911_channels,
847 .num_channels = ARRAY_SIZE(mcp3911_channels),
848 .config = mcp3911_config,
849 .get_osr = mcp3911_get_osr,
850 .set_osr = mcp3911_set_osr,
851 .enable_offset = mcp3911_enable_offset,
852 .get_offset = mcp3911_get_offset,
853 .set_offset = mcp3911_set_offset,
854 .set_scale = mcp3911_set_scale,
855 .get_raw = mcp3911_get_raw,
856 },
857 [MCP3912] = {
858 .channels = mcp3912_channels,
859 .num_channels = ARRAY_SIZE(mcp3912_channels),
860 .config = mcp3910_config,
861 .get_osr = mcp3910_get_osr,
862 .set_osr = mcp3910_set_osr,
863 .enable_offset = mcp3910_enable_offset,
864 .get_offset = mcp3910_get_offset,
865 .set_offset = mcp3910_set_offset,
866 .set_scale = mcp3910_set_scale,
867 .get_raw = mcp3910_get_raw,
868 },
869 [MCP3913] = {
870 .channels = mcp3913_channels,
871 .num_channels = ARRAY_SIZE(mcp3913_channels),
872 .config = mcp3910_config,
873 .get_osr = mcp3910_get_osr,
874 .set_osr = mcp3910_set_osr,
875 .enable_offset = mcp3910_enable_offset,
876 .get_offset = mcp3910_get_offset,
877 .set_offset = mcp3910_set_offset,
878 .set_scale = mcp3910_set_scale,
879 .get_raw = mcp3910_get_raw,
880 },
881 [MCP3914] = {
882 .channels = mcp3914_channels,
883 .num_channels = ARRAY_SIZE(mcp3914_channels),
884 .config = mcp3910_config,
885 .get_osr = mcp3910_get_osr,
886 .set_osr = mcp3910_set_osr,
887 .enable_offset = mcp3910_enable_offset,
888 .get_offset = mcp3910_get_offset,
889 .set_offset = mcp3910_set_offset,
890 .set_scale = mcp3910_set_scale,
891 .get_raw = mcp3910_get_raw,
892 },
893 [MCP3918] = {
894 .channels = mcp3918_channels,
895 .num_channels = ARRAY_SIZE(mcp3918_channels),
896 .config = mcp3910_config,
897 .get_osr = mcp3910_get_osr,
898 .set_osr = mcp3910_set_osr,
899 .enable_offset = mcp3910_enable_offset,
900 .get_offset = mcp3910_get_offset,
901 .set_offset = mcp3910_set_offset,
902 .set_scale = mcp3910_set_scale,
903 .get_raw = mcp3910_get_raw,
904 },
905 [MCP3919] = {
906 .channels = mcp3919_channels,
907 .num_channels = ARRAY_SIZE(mcp3919_channels),
908 .config = mcp3910_config,
909 .get_osr = mcp3910_get_osr,
910 .set_osr = mcp3910_set_osr,
911 .enable_offset = mcp3910_enable_offset,
912 .get_offset = mcp3910_get_offset,
913 .set_offset = mcp3910_set_offset,
914 .set_scale = mcp3910_set_scale,
915 .get_raw = mcp3910_get_raw,
916 },
917 };
918 static const struct of_device_id mcp3911_dt_ids[] = {
919 { .compatible = "microchip,mcp3910", .data = &mcp3911_chip_info[MCP3910] },
920 { .compatible = "microchip,mcp3911", .data = &mcp3911_chip_info[MCP3911] },
921 { .compatible = "microchip,mcp3912", .data = &mcp3911_chip_info[MCP3912] },
922 { .compatible = "microchip,mcp3913", .data = &mcp3911_chip_info[MCP3913] },
923 { .compatible = "microchip,mcp3914", .data = &mcp3911_chip_info[MCP3914] },
924 { .compatible = "microchip,mcp3918", .data = &mcp3911_chip_info[MCP3918] },
925 { .compatible = "microchip,mcp3919", .data = &mcp3911_chip_info[MCP3919] },
926 { }
927 };
928 MODULE_DEVICE_TABLE(of, mcp3911_dt_ids);
929
930 static const struct spi_device_id mcp3911_id[] = {
931 { "mcp3910", (kernel_ulong_t)&mcp3911_chip_info[MCP3910] },
932 { "mcp3911", (kernel_ulong_t)&mcp3911_chip_info[MCP3911] },
933 { "mcp3912", (kernel_ulong_t)&mcp3911_chip_info[MCP3912] },
934 { "mcp3913", (kernel_ulong_t)&mcp3911_chip_info[MCP3913] },
935 { "mcp3914", (kernel_ulong_t)&mcp3911_chip_info[MCP3914] },
936 { "mcp3918", (kernel_ulong_t)&mcp3911_chip_info[MCP3918] },
937 { "mcp3919", (kernel_ulong_t)&mcp3911_chip_info[MCP3919] },
938 { }
939 };
940 MODULE_DEVICE_TABLE(spi, mcp3911_id);
941
942 static struct spi_driver mcp3911_driver = {
943 .driver = {
944 .name = "mcp3911",
945 .of_match_table = mcp3911_dt_ids,
946 },
947 .probe = mcp3911_probe,
948 .id_table = mcp3911_id,
949 };
950 module_spi_driver(mcp3911_driver);
951
952 MODULE_AUTHOR("Marcus Folkesson <marcus.folkesson@gmail.com>");
953 MODULE_AUTHOR("Kent Gustavsson <kent@minoris.se>");
954 MODULE_DESCRIPTION("Microchip Technology MCP3911");
955 MODULE_LICENSE("GPL v2");
956