1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver 4 // 5 // Copyright 2021 Nuvoton Technology Corp. 6 // Author: John Hsu <kchsu0@nuvoton.com> 7 // Co-author: Seven Lee <wtli@nuvoton.com> 8 // 9 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/dmi.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/math64.h> 17 #include <linux/module.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <sound/core.h> 21 #include <sound/initval.h> 22 #include <sound/jack.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/tlv.h> 27 28 #include "nau8821.h" 29 30 #define NAU8821_QUIRK_JD_ACTIVE_HIGH BIT(0) 31 #define NAU8821_QUIRK_JD_DB_BYPASS BIT(1) 32 33 static int nau8821_quirk; 34 static int quirk_override = -1; 35 module_param_named(quirk, quirk_override, uint, 0444); 36 MODULE_PARM_DESC(quirk, "Board-specific quirk override"); 37 38 #define NAU_FREF_MAX 13500000 39 #define NAU_FVCO_MAX 100000000 40 #define NAU_FVCO_MIN 90000000 41 42 #define NAU8821_BUTTON SND_JACK_BTN_0 43 44 /* the maximum frequency of CLK_ADC and CLK_DAC */ 45 #define CLK_DA_AD_MAX 6144000 46 47 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 48 int clk_id, unsigned int freq); 49 static bool nau8821_is_jack_inserted(struct regmap *regmap); 50 51 struct nau8821_fll { 52 int mclk_src; 53 int ratio; 54 int fll_frac; 55 int fll_int; 56 int clk_ref_div; 57 }; 58 59 struct nau8821_fll_attr { 60 unsigned int param; 61 unsigned int val; 62 }; 63 64 /* scaling for mclk from sysclk_src output */ 65 static const struct nau8821_fll_attr mclk_src_scaling[] = { 66 { 1, 0x0 }, 67 { 2, 0x2 }, 68 { 4, 0x3 }, 69 { 8, 0x4 }, 70 { 16, 0x5 }, 71 { 32, 0x6 }, 72 { 3, 0x7 }, 73 { 6, 0xa }, 74 { 12, 0xb }, 75 { 24, 0xc }, 76 { 48, 0xd }, 77 { 96, 0xe }, 78 { 5, 0xf }, 79 }; 80 81 /* ratio for input clk freq */ 82 static const struct nau8821_fll_attr fll_ratio[] = { 83 { 512000, 0x01 }, 84 { 256000, 0x02 }, 85 { 128000, 0x04 }, 86 { 64000, 0x08 }, 87 { 32000, 0x10 }, 88 { 8000, 0x20 }, 89 { 4000, 0x40 }, 90 }; 91 92 static const struct nau8821_fll_attr fll_pre_scalar[] = { 93 { 0, 0x0 }, 94 { 1, 0x1 }, 95 { 2, 0x2 }, 96 { 3, 0x3 }, 97 }; 98 99 /* over sampling rate */ 100 struct nau8821_osr_attr { 101 unsigned int osr; 102 unsigned int clk_src; 103 }; 104 105 static const struct nau8821_osr_attr osr_dac_sel[] = { 106 { 64, 2 }, /* OSR 64, SRC 1/4 */ 107 { 256, 0 }, /* OSR 256, SRC 1 */ 108 { 128, 1 }, /* OSR 128, SRC 1/2 */ 109 { 0, 0 }, 110 { 32, 3 }, /* OSR 32, SRC 1/8 */ 111 }; 112 113 static const struct nau8821_osr_attr osr_adc_sel[] = { 114 { 32, 3 }, /* OSR 32, SRC 1/8 */ 115 { 64, 2 }, /* OSR 64, SRC 1/4 */ 116 { 128, 1 }, /* OSR 128, SRC 1/2 */ 117 { 256, 0 }, /* OSR 256, SRC 1 */ 118 }; 119 120 struct nau8821_dmic_speed { 121 unsigned int param; 122 unsigned int val; 123 }; 124 125 static const struct nau8821_dmic_speed dmic_speed_sel[] = { 126 { 0, 0x0 }, /*SPEED 1, SRC 1 */ 127 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */ 128 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */ 129 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */ 130 }; 131 132 static const struct reg_default nau8821_reg_defaults[] = { 133 { NAU8821_R01_ENA_CTRL, 0x00ff }, 134 { NAU8821_R03_CLK_DIVIDER, 0x0050 }, 135 { NAU8821_R04_FLL1, 0x0 }, 136 { NAU8821_R05_FLL2, 0x00bc }, 137 { NAU8821_R06_FLL3, 0x0008 }, 138 { NAU8821_R07_FLL4, 0x0010 }, 139 { NAU8821_R08_FLL5, 0x4000 }, 140 { NAU8821_R09_FLL6, 0x6900 }, 141 { NAU8821_R0A_FLL7, 0x0031 }, 142 { NAU8821_R0B_FLL8, 0x26e9 }, 143 { NAU8821_R0D_JACK_DET_CTRL, 0x0 }, 144 { NAU8821_R0F_INTERRUPT_MASK, 0x0 }, 145 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff }, 146 { NAU8821_R13_DMIC_CTRL, 0x0 }, 147 { NAU8821_R1A_GPIO12_CTRL, 0x0 }, 148 { NAU8821_R1B_TDM_CTRL, 0x0 }, 149 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a }, 150 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 }, 151 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 }, 152 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 }, 153 { NAU8821_R21_BIQ0_COF1, 0x0 }, 154 { NAU8821_R22_BIQ0_COF2, 0x0 }, 155 { NAU8821_R23_BIQ0_COF3, 0x0 }, 156 { NAU8821_R24_BIQ0_COF4, 0x0 }, 157 { NAU8821_R25_BIQ0_COF5, 0x0 }, 158 { NAU8821_R26_BIQ0_COF6, 0x0 }, 159 { NAU8821_R27_BIQ0_COF7, 0x0 }, 160 { NAU8821_R28_BIQ0_COF8, 0x0 }, 161 { NAU8821_R29_BIQ0_COF9, 0x0 }, 162 { NAU8821_R2A_BIQ0_COF10, 0x0 }, 163 { NAU8821_R2B_ADC_RATE, 0x0002 }, 164 { NAU8821_R2C_DAC_CTRL1, 0x0082 }, 165 { NAU8821_R2D_DAC_CTRL2, 0x0 }, 166 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 }, 167 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 }, 168 { NAU8821_R31_MUTE_CTRL, 0x0 }, 169 { NAU8821_R32_HSVOL_CTRL, 0x0 }, 170 { NAU8821_R34_DACR_CTRL, 0xcfcf }, 171 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf }, 172 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 }, 173 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 }, 174 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff }, 175 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 }, 176 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 }, 177 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 }, 178 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 }, 179 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 }, 180 { NAU8821_R41_BIQ1_COF1, 0x0 }, 181 { NAU8821_R42_BIQ1_COF2, 0x0 }, 182 { NAU8821_R43_BIQ1_COF3, 0x0 }, 183 { NAU8821_R44_BIQ1_COF4, 0x0 }, 184 { NAU8821_R45_BIQ1_COF5, 0x0 }, 185 { NAU8821_R46_BIQ1_COF6, 0x0 }, 186 { NAU8821_R47_BIQ1_COF7, 0x0 }, 187 { NAU8821_R48_BIQ1_COF8, 0x0 }, 188 { NAU8821_R49_BIQ1_COF9, 0x0 }, 189 { NAU8821_R4A_BIQ1_COF10, 0x0 }, 190 { NAU8821_R4B_CLASSG_CTRL, 0x0 }, 191 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 }, 192 { NAU8821_R4D_IMM_RMS_L, 0x0 }, 193 { NAU8821_R53_OTPDOUT_1, 0xaad8 }, 194 { NAU8821_R54_OTPDOUT_2, 0x0002 }, 195 { NAU8821_R55_MISC_CTRL, 0x0 }, 196 { NAU8821_R66_BIAS_ADJ, 0x0 }, 197 { NAU8821_R68_TRIM_SETTINGS, 0x0 }, 198 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 }, 199 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 }, 200 { NAU8821_R6B_PGA_MUTE, 0x0 }, 201 { NAU8821_R71_ANALOG_ADC_1, 0x0011 }, 202 { NAU8821_R72_ANALOG_ADC_2, 0x0020 }, 203 { NAU8821_R73_RDAC, 0x0008 }, 204 { NAU8821_R74_MIC_BIAS, 0x0006 }, 205 { NAU8821_R76_BOOST, 0x0 }, 206 { NAU8821_R77_FEPGA, 0x0 }, 207 { NAU8821_R7E_PGA_GAIN, 0x0 }, 208 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 }, 209 { NAU8821_R80_CHARGE_PUMP, 0x0 }, 210 }; 211 212 static bool nau8821_readable_reg(struct device *dev, unsigned int reg) 213 { 214 switch (reg) { 215 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 216 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 217 case NAU8821_R0D_JACK_DET_CTRL: 218 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL: 219 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 220 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 221 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 222 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 223 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3: 224 case NAU8821_R51_FUSE_CTRL1: 225 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL: 226 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 227 case NAU8821_R66_BIAS_ADJ: 228 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 229 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 230 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 231 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS: 232 return true; 233 default: 234 return false; 235 } 236 } 237 238 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg) 239 { 240 switch (reg) { 241 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL: 242 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8: 243 case NAU8821_R0D_JACK_DET_CTRL: 244 case NAU8821_R0F_INTERRUPT_MASK: 245 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL: 246 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT: 247 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2: 248 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL: 249 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY: 250 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL: 251 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3: 252 case NAU8821_R51_FUSE_CTRL1: 253 case NAU8821_R55_MISC_CTRL: 254 case NAU8821_R5A_SOFTWARE_RST: 255 case NAU8821_R66_BIAS_ADJ: 256 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE: 257 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS: 258 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA: 259 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP: 260 return true; 261 default: 262 return false; 263 } 264 } 265 266 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg) 267 { 268 switch (reg) { 269 case NAU8821_R00_RESET: 270 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS: 271 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10: 272 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10: 273 case NAU8821_R4D_IMM_RMS_L: 274 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2: 275 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST: 276 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS: 277 return true; 278 default: 279 return false; 280 } 281 } 282 283 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol, 284 struct snd_ctl_elem_value *ucontrol) 285 { 286 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 287 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 288 289 if (!component->regmap) 290 return -EINVAL; 291 292 return regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1, 293 ucontrol->value.bytes.data, params->max); 294 } 295 296 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol, 297 struct snd_ctl_elem_value *ucontrol) 298 { 299 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 300 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 301 void *data; 302 int ret; 303 304 if (!component->regmap) 305 return -EINVAL; 306 307 data = kmemdup(ucontrol->value.bytes.data, 308 params->max, GFP_KERNEL | GFP_DMA); 309 if (!data) 310 return -ENOMEM; 311 312 ret = regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1, 313 data, params->max); 314 315 kfree(data); 316 317 return ret; 318 } 319 320 static const char * const nau8821_adc_decimation[] = { 321 "32", "64", "128", "256" }; 322 323 static const struct soc_enum nau8821_adc_decimation_enum = 324 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT, 325 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation); 326 327 static const char * const nau8821_dac_oversampl[] = { 328 "64", "256", "128", "", "32" }; 329 330 static const struct soc_enum nau8821_dac_oversampl_enum = 331 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT, 332 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl); 333 334 static const char * const nau8821_adc_drc_noise_gate[] = { 335 "1:1", "2:1", "4:1", "8:1" }; 336 337 static const struct soc_enum nau8821_adc_drc_noise_gate_enum = 338 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT, 339 ARRAY_SIZE(nau8821_adc_drc_noise_gate), 340 nau8821_adc_drc_noise_gate); 341 342 static const char * const nau8821_adc_drc_expansion_slope[] = { 343 "1:1", "2:1", "4:1" }; 344 345 static const struct soc_enum nau8821_adc_drc_expansion_slope_enum = 346 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT, 347 ARRAY_SIZE(nau8821_adc_drc_expansion_slope), 348 nau8821_adc_drc_expansion_slope); 349 350 static const char * const nau8821_adc_drc_lower_region[] = { 351 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 352 353 static const struct soc_enum nau8821_adc_drc_lower_region_enum = 354 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 355 NAU8821_DRC_CMP2_SLP_ADC_SFT, 356 ARRAY_SIZE(nau8821_adc_drc_lower_region), 357 nau8821_adc_drc_lower_region); 358 359 static const char * const nau8821_higher_region[] = { 360 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" }; 361 362 static const struct soc_enum nau8821_higher_region_enum = 363 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 364 NAU8821_DRC_CMP1_SLP_ADC_SFT, 365 ARRAY_SIZE(nau8821_higher_region), 366 nau8821_higher_region); 367 368 static const char * const nau8821_limiter_slope[] = { 369 "0", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" }; 370 371 static const struct soc_enum nau8821_limiter_slope_enum = 372 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, 373 NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope), 374 nau8821_limiter_slope); 375 376 static const char * const nau8821_detection_attack_time[] = { 377 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 378 "", "511Ts" }; 379 380 static const struct soc_enum nau8821_detection_attack_time_enum = 381 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 382 NAU8821_DRC_PK_COEF1_ADC_SFT, 383 ARRAY_SIZE(nau8821_detection_attack_time), 384 nau8821_detection_attack_time); 385 386 static const char * const nau8821_detection_release_time[] = { 387 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 388 "8191Ts", "", "16383Ts" }; 389 390 static const struct soc_enum nau8821_detection_release_time_enum = 391 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, 392 NAU8821_DRC_PK_COEF2_ADC_SFT, 393 ARRAY_SIZE(nau8821_detection_release_time), 394 nau8821_detection_release_time); 395 396 static const char * const nau8821_attack_time[] = { 397 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts", 398 "511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" }; 399 400 static const struct soc_enum nau8821_attack_time_enum = 401 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT, 402 ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time); 403 404 static const char * const nau8821_decay_time[] = { 405 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts", 406 "8191Ts", "16383Ts", "32757Ts", "65535Ts" }; 407 408 static const struct soc_enum nau8821_decay_time_enum = 409 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT, 410 ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time); 411 412 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400); 413 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); 414 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0); 415 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1); 416 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 417 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400); 418 static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500); 419 static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800); 420 421 static const struct snd_kcontrol_new nau8821_controls[] = { 422 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1, 423 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT, 424 0xff, 0, adc_vol_tlv), 425 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL, 426 12, 8, 0x0f, 0, sidetone_vol_tlv), 427 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL, 428 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv), 429 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL, 430 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT, 431 0xcf, 0, playback_vol_tlv), 432 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN, 433 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT, 434 37, 0, fepga_gain_tlv), 435 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", 436 NAU8821_R2F_DAC_DGAIN_CTRL, 437 0, 8, 0xff, 0, crosstalk_vol_tlv), 438 SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34, 439 NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv), 440 SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34, 441 NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv), 442 443 SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum), 444 SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum), 445 SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum), 446 SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum), 447 SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum), 448 SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum), 449 SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum), 450 SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum), 451 SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum), 452 SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12, 453 NAU8821_DRC_ENA_ADC_SFT, 1, 0), 454 455 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum), 456 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum), 457 SND_SOC_BYTES_EXT("BIQ Coefficients", 20, 458 nau8821_biq_coeff_get, nau8821_biq_coeff_put), 459 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL, 460 NAU8821_ADCPHS_SFT, 1, 0), 461 }; 462 463 static const struct snd_kcontrol_new nau8821_dmic_mode_switch = 464 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL, 465 NAU8821_DMIC_EN_SFT, 1, 0); 466 467 static int dmic_clock_control(struct snd_soc_dapm_widget *w, 468 struct snd_kcontrol *k, int event) 469 { 470 struct snd_soc_component *component = 471 snd_soc_dapm_to_component(w->dapm); 472 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 473 int i, speed_selection = -1, clk_adc_src, clk_adc; 474 unsigned int clk_divider_r03; 475 476 /* The DMIC clock is gotten from adc clock divided by 477 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or 478 * less than nau8821->dmic_clk_threshold. 479 */ 480 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 481 &clk_divider_r03); 482 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK) 483 >> NAU8821_CLK_ADC_SRC_SFT; 484 clk_adc = (nau8821->fs * 256) >> clk_adc_src; 485 486 for (i = 0 ; i < 4 ; i++) 487 if ((clk_adc >> dmic_speed_sel[i].param) <= 488 nau8821->dmic_clk_threshold) { 489 speed_selection = dmic_speed_sel[i].val; 490 break; 491 } 492 if (i == 4) 493 return -EINVAL; 494 495 dev_dbg(nau8821->dev, 496 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n", 497 clk_adc, nau8821->dmic_clk_threshold, 498 dmic_speed_sel[i].param, dmic_speed_sel[i].val); 499 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL, 500 NAU8821_DMIC_SRC_MASK, 501 (speed_selection << NAU8821_DMIC_SRC_SFT)); 502 503 return 0; 504 } 505 506 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w, 507 struct snd_kcontrol *kcontrol, int event) 508 { 509 struct snd_soc_component *component = 510 snd_soc_dapm_to_component(w->dapm); 511 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 512 513 switch (event) { 514 case SND_SOC_DAPM_POST_PMU: 515 msleep(nau8821->adc_delay); 516 break; 517 case SND_SOC_DAPM_POST_PMD: 518 break; 519 default: 520 return -EINVAL; 521 } 522 523 return 0; 524 } 525 526 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w, 527 struct snd_kcontrol *kcontrol, int event) 528 { 529 struct snd_soc_component *component = 530 snd_soc_dapm_to_component(w->dapm); 531 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 532 533 switch (event) { 534 case SND_SOC_DAPM_POST_PMU: 535 msleep(nau8821->adc_delay); 536 break; 537 case SND_SOC_DAPM_POST_PMD: 538 break; 539 default: 540 return -EINVAL; 541 } 542 543 return 0; 544 } 545 546 static int nau8821_pump_event(struct snd_soc_dapm_widget *w, 547 struct snd_kcontrol *kcontrol, int event) 548 { 549 struct snd_soc_component *component = 550 snd_soc_dapm_to_component(w->dapm); 551 struct nau8821 *nau8821 = 552 snd_soc_component_get_drvdata(component); 553 554 switch (event) { 555 case SND_SOC_DAPM_POST_PMU: 556 /* Prevent startup click by letting charge pump to ramp up */ 557 msleep(20); 558 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 559 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW); 560 break; 561 case SND_SOC_DAPM_PRE_PMD: 562 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP, 563 NAU8821_JAMNODCLOW, 0); 564 break; 565 default: 566 return -EINVAL; 567 } 568 569 return 0; 570 } 571 572 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w, 573 struct snd_kcontrol *kcontrol, int event) 574 { 575 struct snd_soc_component *component = 576 snd_soc_dapm_to_component(w->dapm); 577 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 578 579 switch (event) { 580 case SND_SOC_DAPM_PRE_PMU: 581 /* Disables the TESTDAC to let DAC signal pass through. */ 582 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 583 NAU8821_BIAS_TESTDAC_EN, 0); 584 break; 585 case SND_SOC_DAPM_POST_PMD: 586 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ, 587 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN); 588 break; 589 default: 590 return -EINVAL; 591 } 592 593 return 0; 594 } 595 596 static int system_clock_control(struct snd_soc_dapm_widget *w, 597 struct snd_kcontrol *k, int event) 598 { 599 struct snd_soc_component *component = 600 snd_soc_dapm_to_component(w->dapm); 601 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 602 603 if (SND_SOC_DAPM_EVENT_OFF(event)) { 604 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n"); 605 /* Set clock source to disable or internal clock before the 606 * playback or capture end. Codec needs clock for Jack 607 * detection and button press if jack inserted; otherwise, 608 * the clock should be closed. 609 */ 610 if (nau8821_is_jack_inserted(nau8821->regmap)) { 611 nau8821_configure_sysclk(nau8821, 612 NAU8821_CLK_INTERNAL, 0); 613 } else { 614 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 615 } 616 } 617 return 0; 618 } 619 620 static int nau8821_left_fepga_event(struct snd_soc_dapm_widget *w, 621 struct snd_kcontrol *kcontrol, int event) 622 { 623 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 624 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 625 626 if (!nau8821->left_input_single_end) 627 return 0; 628 629 switch (event) { 630 case SND_SOC_DAPM_POST_PMU: 631 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 632 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 633 NAU8821_ACDC_VREF_MICN | NAU8821_FEPGA_MODEL_AAF); 634 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 635 NAU8821_HP_BOOST_DISCHRG_EN, NAU8821_HP_BOOST_DISCHRG_EN); 636 break; 637 case SND_SOC_DAPM_POST_PMD: 638 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA, 639 NAU8821_ACDC_CTRL_MASK | NAU8821_FEPGA_MODEL_MASK, 0); 640 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST, 641 NAU8821_HP_BOOST_DISCHRG_EN, 0); 642 break; 643 default: 644 break; 645 } 646 647 return 0; 648 } 649 650 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = { 651 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, 652 system_clock_control, SND_SOC_DAPM_POST_PMD), 653 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS, 654 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0), 655 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, 656 dmic_clock_control, SND_SOC_DAPM_POST_PMU), 657 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2, 658 NAU8821_POWERUP_ADCL_SFT, 0), 659 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2, 660 NAU8821_POWERUP_ADCR_SFT, 0), 661 /* single-ended design only on the left */ 662 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL, 663 NAU8821_PUP_PGA_L_SFT, 0, nau8821_left_fepga_event, 664 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 665 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL, 666 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0), 667 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL, 668 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event, 669 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 670 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL, 671 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event, 672 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 673 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM, 674 0, 0, &nau8821_dmic_mode_switch), 675 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2, 676 NAU8821_I2S_TRISTATE_SFT, 1), 677 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), 678 679 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC, 680 NAU8821_DACL_EN_SFT, 0, NULL, 0), 681 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC, 682 NAU8821_DACR_EN_SFT, 0, NULL, 0), 683 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC, 684 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0), 685 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC, 686 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0), 687 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL, 688 NAU8821_EN_DACR_SFT, 0), 689 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL, 690 NAU8821_EN_DACL_SFT, 0), 691 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL, 692 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0), 693 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL, 694 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0), 695 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP, 696 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event, 697 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 698 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, 699 NAU8821_R7F_POWER_UP_CONTROL, 700 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0), 701 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, 702 NAU8821_R7F_POWER_UP_CONTROL, 703 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0), 704 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, 705 NAU8821_R7F_POWER_UP_CONTROL, 706 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0), 707 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, 708 NAU8821_R7F_POWER_UP_CONTROL, 709 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0), 710 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, 711 NAU8821_R7F_POWER_UP_CONTROL, 712 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0), 713 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, 714 NAU8821_R7F_POWER_UP_CONTROL, 715 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0), 716 SND_SOC_DAPM_PGA_S("Output DACL", 7, 717 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT, 718 0, nau8821_output_dac_event, 719 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 720 SND_SOC_DAPM_PGA_S("Output DACR", 7, 721 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT, 722 0, nau8821_output_dac_event, 723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 724 725 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ 726 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, 727 NAU8821_R0D_JACK_DET_CTRL, 728 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0), 729 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, 730 NAU8821_R0D_JACK_DET_CTRL, 731 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0), 732 733 /* High current HPOL/R boost driver */ 734 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, 735 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0), 736 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL, 737 NAU8821_CLASSG_EN_SFT, 0, NULL, 0), 738 739 SND_SOC_DAPM_INPUT("MICL"), 740 SND_SOC_DAPM_INPUT("MICR"), 741 SND_SOC_DAPM_INPUT("DMIC"), 742 SND_SOC_DAPM_OUTPUT("HPOL"), 743 SND_SOC_DAPM_OUTPUT("HPOR"), 744 }; 745 746 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = { 747 {"DMIC Enable", "Switch", "DMIC"}, 748 {"DMIC Enable", NULL, "DMIC Clock"}, 749 750 {"Frontend PGA L", NULL, "MICL"}, 751 {"Frontend PGA R", NULL, "MICR"}, 752 {"Frontend PGA L", NULL, "MICBIAS"}, 753 {"Frontend PGA R", NULL, "MICBIAS"}, 754 755 {"ADCL Power", NULL, "Frontend PGA L"}, 756 {"ADCR Power", NULL, "Frontend PGA R"}, 757 758 {"ADCL Digital path", NULL, "ADCL Power"}, 759 {"ADCR Digital path", NULL, "ADCR Power"}, 760 {"ADCL Digital path", NULL, "DMIC Enable"}, 761 {"ADCR Digital path", NULL, "DMIC Enable"}, 762 763 {"AIFTX", NULL, "ADCL Digital path"}, 764 {"AIFTX", NULL, "ADCR Digital path"}, 765 766 {"AIFTX", NULL, "System Clock"}, 767 {"AIFRX", NULL, "System Clock"}, 768 769 {"DDACL", NULL, "AIFRX"}, 770 {"DDACR", NULL, "AIFRX"}, 771 772 {"HP amp L", NULL, "DDACL"}, 773 {"HP amp R", NULL, "DDACR"}, 774 775 {"Charge Pump", NULL, "HP amp L"}, 776 {"Charge Pump", NULL, "HP amp R"}, 777 778 {"ADACL", NULL, "Charge Pump"}, 779 {"ADACR", NULL, "Charge Pump"}, 780 {"ADACL Clock", NULL, "ADACL"}, 781 {"ADACR Clock", NULL, "ADACR"}, 782 783 {"Output Driver L Stage 1", NULL, "ADACL Clock"}, 784 {"Output Driver R Stage 1", NULL, "ADACR Clock"}, 785 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, 786 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, 787 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, 788 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, 789 {"Output DACL", NULL, "Output Driver L Stage 3"}, 790 {"Output DACR", NULL, "Output Driver R Stage 3"}, 791 792 {"HPOL Pulldown", NULL, "Output DACL"}, 793 {"HPOR Pulldown", NULL, "Output DACR"}, 794 {"HP Boost Driver", NULL, "HPOL Pulldown"}, 795 {"HP Boost Driver", NULL, "HPOR Pulldown"}, 796 797 {"Class G", NULL, "HP Boost Driver"}, 798 {"HPOL", NULL, "Class G"}, 799 {"HPOR", NULL, "Class G"}, 800 }; 801 802 static const struct nau8821_osr_attr * 803 nau8821_get_osr(struct nau8821 *nau8821, int stream) 804 { 805 unsigned int osr; 806 807 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 808 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr); 809 osr &= NAU8821_DAC_OVERSAMPLE_MASK; 810 811 if (osr >= ARRAY_SIZE(osr_dac_sel)) 812 return NULL; 813 814 return &osr_dac_sel[osr]; 815 } 816 817 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr); 818 osr &= NAU8821_ADC_SYNC_DOWN_MASK; 819 820 if (osr >= ARRAY_SIZE(osr_adc_sel)) 821 return NULL; 822 823 return &osr_adc_sel[osr]; 824 } 825 826 static int nau8821_dai_startup(struct snd_pcm_substream *substream, 827 struct snd_soc_dai *dai) 828 { 829 struct snd_soc_component *component = dai->component; 830 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 831 const struct nau8821_osr_attr *osr; 832 833 osr = nau8821_get_osr(nau8821, substream->stream); 834 if (!osr || !osr->osr) 835 return -EINVAL; 836 837 return snd_pcm_hw_constraint_minmax(substream->runtime, 838 SNDRV_PCM_HW_PARAM_RATE, 839 0, CLK_DA_AD_MAX / osr->osr); 840 } 841 842 static int nau8821_hw_params(struct snd_pcm_substream *substream, 843 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 844 { 845 struct snd_soc_component *component = dai->component; 846 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 847 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div; 848 const struct nau8821_osr_attr *osr; 849 850 nau8821->fs = params_rate(params); 851 /* CLK_DAC or CLK_ADC = OSR * FS 852 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) 853 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 854 * values must be selected such that the maximum frequency is less 855 * than 6.144 MHz. 856 */ 857 osr = nau8821_get_osr(nau8821, substream->stream); 858 if (!osr || !osr->osr) 859 return -EINVAL; 860 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX) 861 return -EINVAL; 862 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 863 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 864 NAU8821_CLK_DAC_SRC_MASK, 865 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT); 866 else 867 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 868 NAU8821_CLK_ADC_SRC_MASK, 869 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT); 870 871 /* make BCLK and LRC divde configuration if the codec as master. */ 872 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val); 873 if (ctrl_val & NAU8821_I2S_MS_MASTER) { 874 /* get the bclk and fs ratio */ 875 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs; 876 877 if (bclk_fs <= 32) 878 clk_div = 3; 879 else if (bclk_fs <= 64) 880 clk_div = 2; 881 else if (bclk_fs <= 128) 882 clk_div = 1; 883 else 884 return -EINVAL; 885 886 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 887 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK, 888 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div); 889 } 890 891 switch (params_width(params)) { 892 case 16: 893 val_len |= NAU8821_I2S_DL_16; 894 break; 895 case 20: 896 val_len |= NAU8821_I2S_DL_20; 897 break; 898 case 24: 899 val_len |= NAU8821_I2S_DL_24; 900 break; 901 case 32: 902 val_len |= NAU8821_I2S_DL_32; 903 break; 904 default: 905 return -EINVAL; 906 } 907 908 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 909 NAU8821_I2S_DL_MASK, val_len); 910 911 return 0; 912 } 913 914 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 915 { 916 struct snd_soc_component *component = codec_dai->component; 917 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 918 unsigned int ctrl1_val = 0, ctrl2_val = 0; 919 920 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 921 case SND_SOC_DAIFMT_CBP_CFP: 922 ctrl2_val |= NAU8821_I2S_MS_MASTER; 923 break; 924 case SND_SOC_DAIFMT_CBC_CFC: 925 break; 926 default: 927 return -EINVAL; 928 } 929 930 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 931 case SND_SOC_DAIFMT_NB_NF: 932 break; 933 case SND_SOC_DAIFMT_IB_NF: 934 ctrl1_val |= NAU8821_I2S_BP_INV; 935 break; 936 default: 937 return -EINVAL; 938 } 939 940 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 941 case SND_SOC_DAIFMT_I2S: 942 ctrl1_val |= NAU8821_I2S_DF_I2S; 943 break; 944 case SND_SOC_DAIFMT_LEFT_J: 945 ctrl1_val |= NAU8821_I2S_DF_LEFT; 946 break; 947 case SND_SOC_DAIFMT_RIGHT_J: 948 ctrl1_val |= NAU8821_I2S_DF_RIGTH; 949 break; 950 case SND_SOC_DAIFMT_DSP_A: 951 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 952 break; 953 case SND_SOC_DAIFMT_DSP_B: 954 ctrl1_val |= NAU8821_I2S_DF_PCM_AB; 955 ctrl1_val |= NAU8821_I2S_PCMB_EN; 956 break; 957 default: 958 return -EINVAL; 959 } 960 961 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1, 962 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK | 963 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val); 964 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, 965 NAU8821_I2S_MS_MASK, ctrl2_val); 966 967 return 0; 968 } 969 970 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute, 971 int direction) 972 { 973 struct snd_soc_component *component = dai->component; 974 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 975 unsigned int val = 0; 976 977 if (mute) 978 val = NAU8821_DAC_SOFT_MUTE; 979 980 return regmap_update_bits(nau8821->regmap, 981 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val); 982 } 983 984 static const struct snd_soc_dai_ops nau8821_dai_ops = { 985 .startup = nau8821_dai_startup, 986 .hw_params = nau8821_hw_params, 987 .set_fmt = nau8821_set_dai_fmt, 988 .mute_stream = nau8821_digital_mute, 989 .no_capture_mute = 1, 990 }; 991 992 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000 993 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 994 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 995 996 static struct snd_soc_dai_driver nau8821_dai = { 997 .name = NUVOTON_CODEC_DAI, 998 .playback = { 999 .stream_name = "Playback", 1000 .channels_min = 1, 1001 .channels_max = 2, 1002 .rates = NAU8821_RATES, 1003 .formats = NAU8821_FORMATS, 1004 }, 1005 .capture = { 1006 .stream_name = "Capture", 1007 .channels_min = 1, 1008 .channels_max = 2, 1009 .rates = NAU8821_RATES, 1010 .formats = NAU8821_FORMATS, 1011 }, 1012 .ops = &nau8821_dai_ops, 1013 }; 1014 1015 1016 static bool nau8821_is_jack_inserted(struct regmap *regmap) 1017 { 1018 bool active_high, is_high; 1019 int status, jkdet; 1020 1021 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet); 1022 active_high = jkdet & NAU8821_JACK_POLARITY; 1023 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status); 1024 is_high = status & NAU8821_GPIO2_IN; 1025 /* return jack connection status according to jack insertion logic 1026 * active high or active low. 1027 */ 1028 return active_high == is_high; 1029 } 1030 1031 static void nau8821_irq_status_clear(struct regmap *regmap, int active_irq) 1032 { 1033 int clear_irq, i; 1034 1035 if (active_irq) { 1036 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, active_irq); 1037 return; 1038 } 1039 1040 /* Reset the interruption status from rightmost bit if the 1041 * corresponding irq event occurs. 1042 */ 1043 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq); 1044 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) { 1045 clear_irq = (0x1 << i); 1046 if (active_irq & clear_irq) 1047 regmap_write(regmap, 1048 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq); 1049 } 1050 } 1051 1052 static void nau8821_eject_jack(struct nau8821 *nau8821) 1053 { 1054 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1055 struct regmap *regmap = nau8821->regmap; 1056 1057 /* Detach 2kOhm Resistors from MICBIAS to MICGND */ 1058 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1059 NAU8821_MICBIAS_JKR2, 0); 1060 /* HPL/HPR short to ground */ 1061 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1062 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1063 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1064 snd_soc_dapm_sync(dapm); 1065 1066 /* Disable & mask both insertion & ejection IRQs */ 1067 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1068 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 1069 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS); 1070 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1071 NAU8821_IRQ_INSERT_EN | NAU8821_IRQ_EJECT_EN, 1072 NAU8821_IRQ_INSERT_EN | NAU8821_IRQ_EJECT_EN); 1073 1074 /* Clear all interruption status */ 1075 nau8821_irq_status_clear(regmap, 0); 1076 1077 /* Enable & unmask the insertion IRQ */ 1078 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1079 NAU8821_IRQ_INSERT_DIS, 0); 1080 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1081 NAU8821_IRQ_INSERT_EN, 0); 1082 1083 /* Bypass de-bounce circuit */ 1084 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1085 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS); 1086 1087 /* Close clock for jack type detection at manual mode */ 1088 if (snd_soc_dapm_get_bias_level(dapm) < SND_SOC_BIAS_PREPARE) 1089 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1090 1091 /* Recover to normal channel input */ 1092 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1093 NAU8821_ADC_R_SRC_EN, 0); 1094 if (nau8821->key_enable) { 1095 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1096 NAU8821_IRQ_KEY_RELEASE_EN | 1097 NAU8821_IRQ_KEY_PRESS_EN, 1098 NAU8821_IRQ_KEY_RELEASE_EN | 1099 NAU8821_IRQ_KEY_PRESS_EN); 1100 regmap_update_bits(regmap, 1101 NAU8821_R12_INTERRUPT_DIS_CTRL, 1102 NAU8821_IRQ_KEY_RELEASE_DIS | 1103 NAU8821_IRQ_KEY_PRESS_DIS, 1104 NAU8821_IRQ_KEY_RELEASE_DIS | 1105 NAU8821_IRQ_KEY_PRESS_DIS); 1106 } 1107 } 1108 1109 static void nau8821_jdet_work(struct work_struct *work) 1110 { 1111 struct nau8821 *nau8821 = 1112 container_of(work, struct nau8821, jdet_work.work); 1113 struct snd_soc_dapm_context *dapm = nau8821->dapm; 1114 struct regmap *regmap = nau8821->regmap; 1115 int jack_status_reg, mic_detected, event = 0, event_mask = 0; 1116 1117 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg); 1118 mic_detected = !(jack_status_reg & NAU8821_KEYDET); 1119 if (mic_detected) { 1120 dev_dbg(nau8821->dev, "Headset connected\n"); 1121 event |= SND_JACK_HEADSET; 1122 1123 /* 2kOhm Resistor from MICBIAS to MICGND1 */ 1124 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1125 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2); 1126 /* Latch Right Channel Analog data 1127 * input into the Right Channel Filter 1128 */ 1129 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1130 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN); 1131 if (nau8821->key_enable) { 1132 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1133 NAU8821_IRQ_KEY_RELEASE_EN | 1134 NAU8821_IRQ_KEY_PRESS_EN, 0); 1135 regmap_update_bits(regmap, 1136 NAU8821_R12_INTERRUPT_DIS_CTRL, 1137 NAU8821_IRQ_KEY_RELEASE_DIS | 1138 NAU8821_IRQ_KEY_PRESS_DIS, 0); 1139 } else { 1140 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1141 snd_soc_dapm_sync(dapm); 1142 } 1143 } else { 1144 dev_dbg(nau8821->dev, "Headphone connected\n"); 1145 event |= SND_JACK_HEADPHONE; 1146 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 1147 snd_soc_dapm_sync(dapm); 1148 } 1149 1150 event_mask |= SND_JACK_HEADSET; 1151 snd_soc_jack_report(nau8821->jack, event, event_mask); 1152 } 1153 1154 /* Enable interruptions with internal clock. */ 1155 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821) 1156 { 1157 struct regmap *regmap = nau8821->regmap; 1158 1159 /* Disable & mask insertion IRQ */ 1160 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1161 NAU8821_IRQ_INSERT_DIS, NAU8821_IRQ_INSERT_DIS); 1162 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1163 NAU8821_IRQ_INSERT_EN, NAU8821_IRQ_INSERT_EN); 1164 1165 /* Clear insert IRQ status */ 1166 nau8821_irq_status_clear(regmap, NAU8821_JACK_INSERT_DETECTED); 1167 1168 /* Enable internal VCO needed for interruptions */ 1169 if (snd_soc_dapm_get_bias_level(nau8821->dapm) < SND_SOC_BIAS_PREPARE) 1170 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0); 1171 1172 /* Chip needs one FSCLK cycle in order to generate interruptions, 1173 * as we cannot guarantee one will be provided by the system. Turning 1174 * master mode on then off enables us to generate that FSCLK cycle 1175 * with a minimum of contention on the clock bus. 1176 */ 1177 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1178 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER); 1179 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2, 1180 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE); 1181 1182 /* Do not bypass de-bounce circuit */ 1183 if (!(nau8821_quirk & NAU8821_QUIRK_JD_DB_BYPASS)) 1184 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1185 NAU8821_JACK_DET_DB_BYPASS, 0); 1186 1187 /* Unmask & enable the ejection IRQs */ 1188 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1189 NAU8821_IRQ_EJECT_EN, 0); 1190 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1191 NAU8821_IRQ_EJECT_DIS, 0); 1192 } 1193 1194 static irqreturn_t nau8821_interrupt(int irq, void *data) 1195 { 1196 struct nau8821 *nau8821 = (struct nau8821 *)data; 1197 struct regmap *regmap = nau8821->regmap; 1198 int active_irq, event = 0, event_mask = 0; 1199 1200 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) { 1201 dev_err(nau8821->dev, "failed to read irq status\n"); 1202 return IRQ_NONE; 1203 } 1204 1205 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq); 1206 1207 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) == 1208 NAU8821_JACK_EJECT_DETECTED) { 1209 cancel_delayed_work_sync(&nau8821->jdet_work); 1210 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1211 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS); 1212 nau8821_eject_jack(nau8821); 1213 event_mask |= SND_JACK_HEADSET; 1214 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) { 1215 event |= NAU8821_BUTTON; 1216 event_mask |= NAU8821_BUTTON; 1217 nau8821_irq_status_clear(regmap, NAU8821_KEY_SHORT_PRESS_IRQ); 1218 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) { 1219 event_mask = NAU8821_BUTTON; 1220 nau8821_irq_status_clear(regmap, NAU8821_KEY_RELEASE_IRQ); 1221 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) == 1222 NAU8821_JACK_INSERT_DETECTED) { 1223 cancel_delayed_work_sync(&nau8821->jdet_work); 1224 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1, 1225 NAU8821_MICDET_MASK, NAU8821_MICDET_EN); 1226 if (nau8821_is_jack_inserted(regmap)) { 1227 /* Detect microphone and jack type */ 1228 snd_soc_dapm_force_enable_pin(nau8821->dapm, "MICBIAS"); 1229 snd_soc_dapm_sync(nau8821->dapm); 1230 schedule_delayed_work(&nau8821->jdet_work, msecs_to_jiffies(20)); 1231 /* Turn off insertion interruption at manual mode */ 1232 nau8821_setup_inserted_irq(nau8821); 1233 } else { 1234 dev_warn(nau8821->dev, 1235 "Inserted IRQ fired but not connected\n"); 1236 nau8821_eject_jack(nau8821); 1237 } 1238 } else { 1239 /* Clear the rightmost interrupt */ 1240 nau8821_irq_status_clear(regmap, active_irq); 1241 } 1242 1243 if (event_mask) 1244 snd_soc_jack_report(nau8821->jack, event, event_mask); 1245 1246 return IRQ_HANDLED; 1247 } 1248 1249 static const struct regmap_config nau8821_regmap_config = { 1250 .val_bits = NAU8821_REG_DATA_LEN, 1251 .reg_bits = NAU8821_REG_ADDR_LEN, 1252 1253 .max_register = NAU8821_REG_MAX, 1254 .readable_reg = nau8821_readable_reg, 1255 .writeable_reg = nau8821_writeable_reg, 1256 .volatile_reg = nau8821_volatile_reg, 1257 1258 .cache_type = REGCACHE_RBTREE, 1259 .reg_defaults = nau8821_reg_defaults, 1260 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults), 1261 }; 1262 1263 static int nau8821_component_probe(struct snd_soc_component *component) 1264 { 1265 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1266 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1267 1268 nau8821->dapm = dapm; 1269 1270 return 0; 1271 } 1272 1273 static void nau8821_component_remove(struct snd_soc_component *component) 1274 { 1275 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1276 1277 if (nau8821->jdet_active) 1278 cancel_delayed_work_sync(&nau8821->jdet_work); 1279 }; 1280 1281 /** 1282 * nau8821_calc_fll_param - Calculate FLL parameters. 1283 * @fll_in: external clock provided to codec. 1284 * @fs: sampling rate. 1285 * @fll_param: Pointer to structure of FLL parameters. 1286 * 1287 * Calculate FLL parameters to configure codec. 1288 * 1289 * Returns 0 for success or negative error code. 1290 */ 1291 static int nau8821_calc_fll_param(unsigned int fll_in, 1292 unsigned int fs, struct nau8821_fll *fll_param) 1293 { 1294 u64 fvco, fvco_max; 1295 unsigned int fref, i, fvco_sel; 1296 1297 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by 1298 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 1299 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK 1300 */ 1301 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 1302 fref = fll_in >> fll_pre_scalar[i].param; 1303 if (fref <= NAU_FREF_MAX) 1304 break; 1305 } 1306 if (i == ARRAY_SIZE(fll_pre_scalar)) 1307 return -EINVAL; 1308 fll_param->clk_ref_div = fll_pre_scalar[i].val; 1309 1310 /* Choose the FLL ratio based on FREF */ 1311 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 1312 if (fref >= fll_ratio[i].param) 1313 break; 1314 } 1315 if (i == ARRAY_SIZE(fll_ratio)) 1316 return -EINVAL; 1317 fll_param->ratio = fll_ratio[i].val; 1318 1319 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 1320 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be 1321 * guaranteed across the full range of operation. 1322 * FDCO = freq_out * 2 * mclk_src_scaling 1323 */ 1324 fvco_max = 0; 1325 fvco_sel = ARRAY_SIZE(mclk_src_scaling); 1326 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 1327 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 1328 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 1329 fvco_max < fvco) { 1330 fvco_max = fvco; 1331 fvco_sel = i; 1332 } 1333 } 1334 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 1335 return -EINVAL; 1336 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 1337 1338 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional 1339 * input based on FDCO, FREF and FLL ratio. 1340 */ 1341 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio); 1342 fll_param->fll_int = (fvco >> 24) & 0x3ff; 1343 fll_param->fll_frac = fvco & 0xffffff; 1344 1345 return 0; 1346 } 1347 1348 static void nau8821_fll_apply(struct nau8821 *nau8821, 1349 struct nau8821_fll *fll_param) 1350 { 1351 struct regmap *regmap = nau8821->regmap; 1352 1353 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1354 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK, 1355 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src); 1356 /* Make DSP operate at high speed for better performance. */ 1357 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1358 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK, 1359 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT)); 1360 /* FLL 24-bit fractional input */ 1361 regmap_write(regmap, NAU8821_R0A_FLL7, 1362 (fll_param->fll_frac >> 16) & 0xff); 1363 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff); 1364 /* FLL 10-bit integer input */ 1365 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1366 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int); 1367 /* FLL pre-scaler */ 1368 regmap_update_bits(regmap, NAU8821_R07_FLL4, 1369 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK, 1370 NAU8821_HIGHBW_EN | 1371 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT)); 1372 /* select divided VCO input */ 1373 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1374 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF); 1375 /* Disable free-running mode */ 1376 regmap_update_bits(regmap, 1377 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0); 1378 if (fll_param->fll_frac) { 1379 /* set FLL loop filter enable and cutoff frequency at 500Khz */ 1380 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1381 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1382 NAU8821_FLL_FTR_SW_MASK, 1383 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1384 NAU8821_FLL_FTR_SW_FILTER); 1385 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1386 NAU8821_SDM_EN | NAU8821_CUTOFF500, 1387 NAU8821_SDM_EN | NAU8821_CUTOFF500); 1388 } else { 1389 /* disable FLL loop filter and cutoff frequency */ 1390 regmap_update_bits(regmap, NAU8821_R08_FLL5, 1391 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN | 1392 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU); 1393 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1394 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0); 1395 } 1396 } 1397 1398 /** 1399 * nau8821_set_fll - FLL configuration of nau8821 1400 * @component: codec component 1401 * @pll_id: PLL requested 1402 * @source: clock source 1403 * @freq_in: frequency of input clock source 1404 * @freq_out: must be 256*Fs in order to achieve the best performance 1405 * 1406 * The FLL function can select BCLK or MCLK as the input clock source. 1407 * 1408 * Returns 0 if the parameters have been applied successfully 1409 * or negative error code. 1410 */ 1411 static int nau8821_set_fll(struct snd_soc_component *component, 1412 int pll_id, int source, unsigned int freq_in, unsigned int freq_out) 1413 { 1414 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1415 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param; 1416 int ret, fs; 1417 1418 fs = freq_out >> 8; 1419 ret = nau8821_calc_fll_param(freq_in, fs, fll_param); 1420 if (ret) { 1421 dev_err(nau8821->dev, 1422 "Unsupported input clock %d to output clock %d\n", 1423 freq_in, freq_out); 1424 return ret; 1425 } 1426 dev_dbg(nau8821->dev, 1427 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 1428 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac, 1429 fll_param->fll_int, fll_param->clk_ref_div); 1430 1431 nau8821_fll_apply(nau8821, fll_param); 1432 mdelay(2); 1433 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER, 1434 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1435 1436 return 0; 1437 } 1438 1439 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap) 1440 { 1441 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1442 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK); 1443 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1444 NAU8821_DCO_EN, 0); 1445 /* Make DSP operate as default setting for power saving. */ 1446 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1447 NAU8821_ICTRL_LATCH_MASK, 0); 1448 } 1449 1450 static int nau8821_configure_sysclk(struct nau8821 *nau8821, 1451 int clk_id, unsigned int freq) 1452 { 1453 struct regmap *regmap = nau8821->regmap; 1454 1455 switch (clk_id) { 1456 case NAU8821_CLK_DIS: 1457 /* Clock provided externally and disable internal VCO clock */ 1458 nau8821_configure_mclk_as_sysclk(regmap); 1459 break; 1460 case NAU8821_CLK_MCLK: 1461 nau8821_configure_mclk_as_sysclk(regmap); 1462 /* MCLK not changed by clock tree */ 1463 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1464 NAU8821_CLK_MCLK_SRC_MASK, 0); 1465 break; 1466 case NAU8821_CLK_INTERNAL: 1467 if (nau8821_is_jack_inserted(regmap)) { 1468 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1469 NAU8821_DCO_EN, NAU8821_DCO_EN); 1470 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1471 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO); 1472 /* Decrease the VCO frequency and make DSP operate 1473 * as default setting for power saving. 1474 */ 1475 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER, 1476 NAU8821_CLK_MCLK_SRC_MASK, 0xf); 1477 regmap_update_bits(regmap, NAU8821_R04_FLL1, 1478 NAU8821_ICTRL_LATCH_MASK | 1479 NAU8821_FLL_RATIO_MASK, 0x10); 1480 regmap_update_bits(regmap, NAU8821_R09_FLL6, 1481 NAU8821_SDM_EN, NAU8821_SDM_EN); 1482 } 1483 break; 1484 case NAU8821_CLK_FLL_MCLK: 1485 /* Higher FLL reference input frequency can only set lower 1486 * gain error, such as 0000 for input reference from MCLK 1487 * 12.288Mhz. 1488 */ 1489 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1490 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1491 NAU8821_FLL_CLK_SRC_MCLK | 0); 1492 break; 1493 case NAU8821_CLK_FLL_BLK: 1494 /* If FLL reference input is from low frequency source, 1495 * higher error gain can apply such as 0xf which has 1496 * the most sensitive gain error correction threshold, 1497 * Therefore, FLL has the most accurate DCO to 1498 * target frequency. 1499 */ 1500 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1501 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1502 NAU8821_FLL_CLK_SRC_BLK | 1503 (0xf << NAU8821_GAIN_ERR_SFT)); 1504 break; 1505 case NAU8821_CLK_FLL_FS: 1506 /* If FLL reference input is from low frequency source, 1507 * higher error gain can apply such as 0xf which has 1508 * the most sensitive gain error correction threshold, 1509 * Therefore, FLL has the most accurate DCO to 1510 * target frequency. 1511 */ 1512 regmap_update_bits(regmap, NAU8821_R06_FLL3, 1513 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK, 1514 NAU8821_FLL_CLK_SRC_FS | 1515 (0xf << NAU8821_GAIN_ERR_SFT)); 1516 break; 1517 default: 1518 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id); 1519 return -EINVAL; 1520 } 1521 nau8821->clk_id = clk_id; 1522 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq, 1523 nau8821->clk_id); 1524 1525 return 0; 1526 } 1527 1528 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id, 1529 int source, unsigned int freq, int dir) 1530 { 1531 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1532 1533 return nau8821_configure_sysclk(nau8821, clk_id, freq); 1534 } 1535 1536 static int nau8821_resume_setup(struct nau8821 *nau8821) 1537 { 1538 struct regmap *regmap = nau8821->regmap; 1539 1540 /* Close clock when jack type detection at manual mode */ 1541 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0); 1542 if (nau8821->irq) { 1543 /* Clear all interruption status */ 1544 nau8821_irq_status_clear(regmap, 0); 1545 1546 /* Enable both insertion and ejection interruptions, and then 1547 * bypass de-bounce circuit. 1548 */ 1549 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1550 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0); 1551 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1552 NAU8821_JACK_DET_DB_BYPASS, 1553 NAU8821_JACK_DET_DB_BYPASS); 1554 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL, 1555 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0); 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int nau8821_set_bias_level(struct snd_soc_component *component, 1562 enum snd_soc_bias_level level) 1563 { 1564 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1565 struct regmap *regmap = nau8821->regmap; 1566 1567 switch (level) { 1568 case SND_SOC_BIAS_ON: 1569 break; 1570 1571 case SND_SOC_BIAS_PREPARE: 1572 break; 1573 1574 case SND_SOC_BIAS_STANDBY: 1575 /* Setup codec configuration after resume */ 1576 if (snd_soc_dapm_get_bias_level(nau8821->dapm) == SND_SOC_BIAS_OFF) 1577 nau8821_resume_setup(nau8821); 1578 break; 1579 1580 case SND_SOC_BIAS_OFF: 1581 /* HPL/HPR short to ground */ 1582 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1583 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0); 1584 if (nau8821->irq) { 1585 /* Reset the configuration of jack type for detection. 1586 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2. 1587 */ 1588 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1589 NAU8821_MICBIAS_JKR2, 0); 1590 /* Turn off all interruptions before system shutdown. 1591 * Keep theinterruption quiet before resume 1592 * setup completes. 1593 */ 1594 regmap_write(regmap, 1595 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff); 1596 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1597 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 1598 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN); 1599 } 1600 break; 1601 default: 1602 break; 1603 } 1604 1605 return 0; 1606 } 1607 1608 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component) 1609 { 1610 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1611 1612 if (nau8821->irq) 1613 disable_irq(nau8821->irq); 1614 1615 if (nau8821->jdet_active) 1616 cancel_delayed_work_sync(&nau8821->jdet_work); 1617 1618 snd_soc_dapm_force_bias_level(nau8821->dapm, SND_SOC_BIAS_OFF); 1619 /* Power down codec power; don't support button wakeup */ 1620 snd_soc_dapm_disable_pin(nau8821->dapm, "MICBIAS"); 1621 snd_soc_dapm_sync(nau8821->dapm); 1622 regcache_cache_only(nau8821->regmap, true); 1623 regcache_mark_dirty(nau8821->regmap); 1624 1625 return 0; 1626 } 1627 1628 static int __maybe_unused nau8821_resume(struct snd_soc_component *component) 1629 { 1630 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1631 1632 regcache_cache_only(nau8821->regmap, false); 1633 regcache_sync(nau8821->regmap); 1634 if (nau8821->irq) 1635 enable_irq(nau8821->irq); 1636 1637 return 0; 1638 } 1639 1640 static const struct snd_soc_component_driver nau8821_component_driver = { 1641 .probe = nau8821_component_probe, 1642 .remove = nau8821_component_remove, 1643 .set_sysclk = nau8821_set_sysclk, 1644 .set_pll = nau8821_set_fll, 1645 .set_bias_level = nau8821_set_bias_level, 1646 .suspend = nau8821_suspend, 1647 .resume = nau8821_resume, 1648 .controls = nau8821_controls, 1649 .num_controls = ARRAY_SIZE(nau8821_controls), 1650 .dapm_widgets = nau8821_dapm_widgets, 1651 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets), 1652 .dapm_routes = nau8821_dapm_routes, 1653 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes), 1654 .suspend_bias_off = 1, 1655 .idle_bias_on = 1, 1656 .use_pmdown_time = 1, 1657 .endianness = 1, 1658 }; 1659 1660 /** 1661 * nau8821_enable_jack_detect - Specify a jack for event reporting 1662 * 1663 * @component: component to register the jack with 1664 * @jack: jack to use to report headset and button events on 1665 * 1666 * After this function has been called the headset insert/remove and button 1667 * events will be routed to the given jack. Jack can be null to stop 1668 * reporting. 1669 */ 1670 int nau8821_enable_jack_detect(struct snd_soc_component *component, 1671 struct snd_soc_jack *jack) 1672 { 1673 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component); 1674 int ret; 1675 1676 nau8821->jack = jack; 1677 1678 if (nau8821->jdet_active) 1679 return 0; 1680 1681 /* Initiate jack detection work queue */ 1682 INIT_DELAYED_WORK(&nau8821->jdet_work, nau8821_jdet_work); 1683 nau8821->jdet_active = true; 1684 1685 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL, 1686 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1687 "nau8821", nau8821); 1688 if (ret) 1689 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n", 1690 nau8821->irq, ret); 1691 1692 return ret; 1693 } 1694 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect); 1695 1696 static void nau8821_reset_chip(struct regmap *regmap) 1697 { 1698 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1699 regmap_write(regmap, NAU8821_R00_RESET, 0xffff); 1700 } 1701 1702 static void nau8821_print_device_properties(struct nau8821 *nau8821) 1703 { 1704 struct device *dev = nau8821->dev; 1705 1706 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable); 1707 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable); 1708 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up); 1709 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity); 1710 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage); 1711 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance); 1712 dev_dbg(dev, "jack-insert-debounce: %d\n", 1713 nau8821->jack_insert_debounce); 1714 dev_dbg(dev, "jack-eject-debounce: %d\n", 1715 nau8821->jack_eject_debounce); 1716 dev_dbg(dev, "dmic-clk-threshold: %d\n", 1717 nau8821->dmic_clk_threshold); 1718 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable); 1719 dev_dbg(dev, "adc-delay-ms: %d\n", nau8821->adc_delay); 1720 } 1721 1722 static int nau8821_read_device_properties(struct device *dev, 1723 struct nau8821 *nau8821) 1724 { 1725 int ret; 1726 1727 nau8821->jkdet_enable = device_property_read_bool(dev, 1728 "nuvoton,jkdet-enable"); 1729 nau8821->jkdet_pull_enable = device_property_read_bool(dev, 1730 "nuvoton,jkdet-pull-enable"); 1731 nau8821->jkdet_pull_up = device_property_read_bool(dev, 1732 "nuvoton,jkdet-pull-up"); 1733 nau8821->key_enable = device_property_read_bool(dev, 1734 "nuvoton,key-enable"); 1735 nau8821->left_input_single_end = device_property_read_bool(dev, 1736 "nuvoton,left-input-single-end"); 1737 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", 1738 &nau8821->jkdet_polarity); 1739 if (ret) 1740 nau8821->jkdet_polarity = 1; 1741 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", 1742 &nau8821->micbias_voltage); 1743 if (ret) 1744 nau8821->micbias_voltage = 6; 1745 ret = device_property_read_u32(dev, "nuvoton,vref-impedance", 1746 &nau8821->vref_impedance); 1747 if (ret) 1748 nau8821->vref_impedance = 2; 1749 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", 1750 &nau8821->jack_insert_debounce); 1751 if (ret) 1752 nau8821->jack_insert_debounce = 7; 1753 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", 1754 &nau8821->jack_eject_debounce); 1755 if (ret) 1756 nau8821->jack_eject_debounce = 0; 1757 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold", 1758 &nau8821->dmic_clk_threshold); 1759 if (ret) 1760 nau8821->dmic_clk_threshold = 3072000; 1761 ret = device_property_read_u32(dev, "nuvoton,dmic-slew-rate", 1762 &nau8821->dmic_slew_rate); 1763 if (ret) 1764 nau8821->dmic_slew_rate = 0; 1765 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", 1766 &nau8821->adc_delay); 1767 if (ret) 1768 nau8821->adc_delay = 125; 1769 if (nau8821->adc_delay < 125 || nau8821->adc_delay > 500) 1770 dev_warn(dev, "Please set the suitable delay time!\n"); 1771 1772 return 0; 1773 } 1774 1775 static void nau8821_init_regs(struct nau8821 *nau8821) 1776 { 1777 struct regmap *regmap = nau8821->regmap; 1778 1779 /* Enable Bias/Vmid */ 1780 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1781 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID); 1782 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1783 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN); 1784 /* VMID Tieoff setting and enable TESTDAC. 1785 * This sets the analog DAC inputs to a '0' input signal to avoid 1786 * any glitches due to power up transients in both the analog and 1787 * digital DAC circuit. 1788 */ 1789 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ, 1790 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN, 1791 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) | 1792 NAU8821_BIAS_TESTDAC_EN); 1793 /* Disable short Frame Sync detection logic */ 1794 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT, 1795 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET); 1796 /* Disable Boost Driver, Automatic Short circuit protection enable */ 1797 regmap_update_bits(regmap, NAU8821_R76_BOOST, 1798 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1799 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN, 1800 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS | 1801 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN); 1802 /* Class G timer 64ms */ 1803 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL, 1804 NAU8821_CLASSG_TIMER_MASK, 1805 0x20 << NAU8821_CLASSG_TIMER_SFT); 1806 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ 1807 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2, 1808 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1809 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB, 1810 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ | 1811 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB); 1812 /* Disable DACR/L power */ 1813 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP, 1814 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0); 1815 /* DAC clock delay 2ns, VREF */ 1816 regmap_update_bits(regmap, NAU8821_R73_RDAC, 1817 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK, 1818 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) | 1819 (0x3 << NAU8821_DAC_VREF_SFT)); 1820 1821 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1822 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage); 1823 /* Default oversampling/decimations settings are unusable 1824 * (audible hiss). Set it to something better. 1825 */ 1826 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE, 1827 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64); 1828 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1, 1829 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64); 1830 regmap_update_bits(regmap, NAU8821_R13_DMIC_CTRL, 1831 NAU8821_DMIC_SLEW_MASK, nau8821->dmic_slew_rate << 1832 NAU8821_DMIC_SLEW_SFT); 1833 if (nau8821->left_input_single_end) { 1834 regmap_update_bits(regmap, NAU8821_R6B_PGA_MUTE, 1835 NAU8821_MUTE_MICNL_EN, NAU8821_MUTE_MICNL_EN); 1836 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS, 1837 NAU8821_MICBIAS_LOWNOISE_EN, NAU8821_MICBIAS_LOWNOISE_EN); 1838 } 1839 } 1840 1841 static int nau8821_setup_irq(struct nau8821 *nau8821) 1842 { 1843 struct regmap *regmap = nau8821->regmap; 1844 1845 /* Jack detection */ 1846 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1847 NAU8821_JKDET_OUTPUT_EN, 1848 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN); 1849 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1850 NAU8821_JKDET_PULL_EN, 1851 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN); 1852 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL, 1853 NAU8821_JKDET_PULL_UP, 1854 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0); 1855 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1856 NAU8821_JACK_POLARITY, 1857 /* jkdet_polarity - 1 is for active-low */ 1858 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY); 1859 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1860 NAU8821_JACK_INSERT_DEBOUNCE_MASK, 1861 nau8821->jack_insert_debounce << 1862 NAU8821_JACK_INSERT_DEBOUNCE_SFT); 1863 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL, 1864 NAU8821_JACK_EJECT_DEBOUNCE_MASK, 1865 nau8821->jack_eject_debounce << 1866 NAU8821_JACK_EJECT_DEBOUNCE_SFT); 1867 /* Pull up IRQ pin */ 1868 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 1869 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN | 1870 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP | 1871 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN); 1872 /* Disable interruption before codec initiation done */ 1873 /* Mask unneeded IRQs: 1 - disable, 0 - enable */ 1874 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5); 1875 1876 return 0; 1877 } 1878 1879 /* Please keep this list alphabetically sorted */ 1880 static const struct dmi_system_id nau8821_quirk_table[] = { 1881 { 1882 /* Positivo CW14Q01P-V2 */ 1883 .matches = { 1884 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), 1885 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"), 1886 }, 1887 .driver_data = (void *)(NAU8821_QUIRK_JD_ACTIVE_HIGH), 1888 }, 1889 { 1890 /* Valve Steam Deck LCD */ 1891 .matches = { 1892 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 1893 DMI_MATCH(DMI_PRODUCT_NAME, "Jupiter"), 1894 }, 1895 .driver_data = (void *)(NAU8821_QUIRK_JD_DB_BYPASS), 1896 }, 1897 { 1898 /* Valve Steam Deck OLED */ 1899 .matches = { 1900 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 1901 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 1902 }, 1903 .driver_data = (void *)(NAU8821_QUIRK_JD_DB_BYPASS), 1904 }, 1905 {} 1906 }; 1907 1908 static void nau8821_check_quirks(void) 1909 { 1910 const struct dmi_system_id *dmi_id; 1911 1912 if (quirk_override != -1) { 1913 nau8821_quirk = quirk_override; 1914 return; 1915 } 1916 1917 dmi_id = dmi_first_match(nau8821_quirk_table); 1918 if (dmi_id) 1919 nau8821_quirk = (unsigned long)dmi_id->driver_data; 1920 } 1921 1922 static int nau8821_i2c_probe(struct i2c_client *i2c) 1923 { 1924 struct device *dev = &i2c->dev; 1925 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev); 1926 int ret, value; 1927 1928 if (!nau8821) { 1929 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL); 1930 if (!nau8821) 1931 return -ENOMEM; 1932 nau8821_read_device_properties(dev, nau8821); 1933 } 1934 i2c_set_clientdata(i2c, nau8821); 1935 1936 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config); 1937 if (IS_ERR(nau8821->regmap)) 1938 return PTR_ERR(nau8821->regmap); 1939 1940 nau8821->dev = dev; 1941 nau8821->irq = i2c->irq; 1942 1943 nau8821_check_quirks(); 1944 1945 if (nau8821_quirk & NAU8821_QUIRK_JD_ACTIVE_HIGH) 1946 nau8821->jkdet_polarity = 0; 1947 1948 if (nau8821_quirk & NAU8821_QUIRK_JD_DB_BYPASS) 1949 dev_dbg(dev, "Force bypassing jack detection debounce circuit\n"); 1950 1951 nau8821_print_device_properties(nau8821); 1952 1953 nau8821_reset_chip(nau8821->regmap); 1954 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value); 1955 if (ret) { 1956 dev_err(dev, "Failed to read device id (%d)\n", ret); 1957 return ret; 1958 } 1959 nau8821_init_regs(nau8821); 1960 1961 if (i2c->irq) 1962 nau8821_setup_irq(nau8821); 1963 1964 ret = devm_snd_soc_register_component(&i2c->dev, 1965 &nau8821_component_driver, &nau8821_dai, 1); 1966 1967 return ret; 1968 } 1969 1970 static const struct i2c_device_id nau8821_i2c_ids[] = { 1971 { "nau8821" }, 1972 { } 1973 }; 1974 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids); 1975 1976 #ifdef CONFIG_OF 1977 static const struct of_device_id nau8821_of_ids[] = { 1978 { .compatible = "nuvoton,nau8821", }, 1979 {} 1980 }; 1981 MODULE_DEVICE_TABLE(of, nau8821_of_ids); 1982 #endif 1983 1984 #ifdef CONFIG_ACPI 1985 static const struct acpi_device_id nau8821_acpi_match[] = { 1986 { "NVTN2020", 0 }, 1987 {}, 1988 }; 1989 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match); 1990 #endif 1991 1992 static struct i2c_driver nau8821_driver = { 1993 .driver = { 1994 .name = "nau8821", 1995 .of_match_table = of_match_ptr(nau8821_of_ids), 1996 .acpi_match_table = ACPI_PTR(nau8821_acpi_match), 1997 }, 1998 .probe = nau8821_i2c_probe, 1999 .id_table = nau8821_i2c_ids, 2000 }; 2001 module_i2c_driver(nau8821_driver); 2002 2003 MODULE_DESCRIPTION("ASoC nau8821 driver"); 2004 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>"); 2005 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>"); 2006 MODULE_LICENSE("GPL"); 2007