1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces 4 // 5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <dt-bindings/sound/microchip,pdmc.h> 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/tlv.h> 22 23 /* 24 * ---- PDMC Register map ---- 25 */ 26 #define MCHP_PDMC_CR 0x00 /* Control Register */ 27 #define MCHP_PDMC_MR 0x04 /* Mode Register */ 28 #define MCHP_PDMC_CFGR 0x08 /* Configuration Register */ 29 #define MCHP_PDMC_RHR 0x0C /* Receive Holding Register */ 30 #define MCHP_PDMC_IER 0x14 /* Interrupt Enable Register */ 31 #define MCHP_PDMC_IDR 0x18 /* Interrupt Disable Register */ 32 #define MCHP_PDMC_IMR 0x1C /* Interrupt Mask Register */ 33 #define MCHP_PDMC_ISR 0x20 /* Interrupt Status Register */ 34 #define MCHP_PDMC_VER 0x50 /* Version Register */ 35 36 /* 37 * ---- Control Register (Write-only) ---- 38 */ 39 #define MCHP_PDMC_CR_SWRST BIT(0) /* Software Reset */ 40 41 /* 42 * ---- Mode Register (Read/Write) ---- 43 */ 44 #define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0) 45 #define MCHP_PDMC_MR_PDMCEN(ch) (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK) 46 47 #define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16) 48 #define MCHP_PDMC_MR_OSR64 (1 << 16) 49 #define MCHP_PDMC_MR_OSR128 (2 << 16) 50 #define MCHP_PDMC_MR_OSR256 (3 << 16) 51 52 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20) 53 54 #define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24) 55 #define MCHP_PDMC_MR_SINC_OSR_DIS (0 << 24) 56 #define MCHP_PDMC_MR_SINC_OSR_8 (1 << 24) 57 #define MCHP_PDMC_MR_SINC_OSR_16 (2 << 24) 58 #define MCHP_PDMC_MR_SINC_OSR_32 (3 << 24) 59 #define MCHP_PDMC_MR_SINC_OSR_64 (4 << 24) 60 #define MCHP_PDMC_MR_SINC_OSR_128 (5 << 24) 61 #define MCHP_PDMC_MR_SINC_OSR_256 (6 << 24) 62 63 #define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28) 64 65 /* 66 * ---- Configuration Register (Read/Write) ---- 67 */ 68 #define MCHP_PDMC_CFGR_BSSEL_MASK (BIT(0) | BIT(2) | BIT(4) | BIT(6)) 69 #define MCHP_PDMC_CFGR_BSSEL(ch) BIT((ch) * 2) 70 71 #define MCHP_PDMC_CFGR_PDMSEL_MASK (BIT(16) | BIT(18) | BIT(20) | BIT(22)) 72 #define MCHP_PDMC_CFGR_PDMSEL(ch) BIT((ch) * 2 + 16) 73 74 /* 75 * ---- Interrupt Enable/Disable/Mask/Status Registers ---- 76 */ 77 #define MCHP_PDMC_IR_RXRDY BIT(0) 78 #define MCHP_PDMC_IR_RXEMPTY BIT(1) 79 #define MCHP_PDMC_IR_RXFULL BIT(2) 80 #define MCHP_PDMC_IR_RXCHUNK BIT(3) 81 #define MCHP_PDMC_IR_RXUDR BIT(4) 82 #define MCHP_PDMC_IR_RXOVR BIT(5) 83 84 /* 85 * ---- Version Register (Read-only) ---- 86 */ 87 #define MCHP_PDMC_VER_VERSION GENMASK(11, 0) 88 89 #define MCHP_PDMC_MAX_CHANNELS 4 90 #define MCHP_PDMC_DS_NO 2 91 #define MCHP_PDMC_EDGE_NO 2 92 93 /* 94 * ---- DMA chunk size allowed ---- 95 */ 96 #define MCHP_PDMC_DMA_8_WORD_CHUNK 8 97 #define MCHP_PDMC_DMA_4_WORD_CHUNK 4 98 #define MCHP_PDMC_DMA_2_WORD_CHUNK 2 99 #define MCHP_PDMC_DMA_1_WORD_CHUNK 1 100 #define DMA_BURST_ALIGNED(_p, _s, _w) !(_p % (_s * _w)) 101 102 struct mic_map { 103 int ds_pos; 104 int clk_edge; 105 }; 106 107 struct mchp_pdmc_chmap { 108 struct snd_pcm_chmap_elem *chmap; 109 struct mchp_pdmc *dd; 110 struct snd_pcm *pcm; 111 struct snd_kcontrol *kctl; 112 }; 113 114 struct mchp_pdmc { 115 struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS]; 116 struct device *dev; 117 struct snd_dmaengine_dai_dma_data addr; 118 struct regmap *regmap; 119 struct clk *pclk; 120 struct clk *gclk; 121 u32 pdmcen; 122 u32 suspend_irq; 123 u32 startup_delay_us; 124 int mic_no; 125 int sinc_order; 126 bool audio_filter_en; 127 atomic_t busy_stream; 128 }; 129 130 static const char *const mchp_pdmc_sinc_filter_order_text[] = { 131 "1", "2", "3", "4", "5" 132 }; 133 134 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = { 135 1, 2, 3, 4, 5, 136 }; 137 138 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = { 139 .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text), 140 .texts = mchp_pdmc_sinc_filter_order_text, 141 .values = mchp_pdmc_sinc_filter_order_values, 142 }; 143 144 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol, 145 struct snd_ctl_elem_value *uvalue) 146 { 147 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 148 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 149 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 150 unsigned int item; 151 152 item = snd_soc_enum_val_to_item(e, dd->sinc_order); 153 uvalue->value.enumerated.item[0] = item; 154 155 return 0; 156 } 157 158 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol, 159 struct snd_ctl_elem_value *uvalue) 160 { 161 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 162 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 163 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 164 unsigned int *item = uvalue->value.enumerated.item; 165 unsigned int val; 166 167 if (item[0] >= e->items) 168 return -EINVAL; 169 170 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 171 172 if (atomic_read(&dd->busy_stream)) 173 return -EBUSY; 174 175 if (val == dd->sinc_order) 176 return 0; 177 178 dd->sinc_order = val; 179 180 return 1; 181 } 182 183 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol, 184 struct snd_ctl_elem_value *uvalue) 185 { 186 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 187 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 188 189 uvalue->value.integer.value[0] = !!dd->audio_filter_en; 190 191 return 0; 192 } 193 194 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol, 195 struct snd_ctl_elem_value *uvalue) 196 { 197 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 198 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 199 bool af = uvalue->value.integer.value[0] ? true : false; 200 201 if (atomic_read(&dd->busy_stream)) 202 return -EBUSY; 203 204 if (dd->audio_filter_en == af) 205 return 0; 206 207 dd->audio_filter_en = af; 208 209 return 1; 210 } 211 212 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 213 { 214 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 215 216 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 217 uinfo->count = info->dd->mic_no; 218 uinfo->value.integer.min = 0; 219 uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */ 220 return 0; 221 } 222 223 static inline struct snd_pcm_substream * 224 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx) 225 { 226 struct snd_pcm_substream *s; 227 228 for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next) 229 if (s->number == idx) 230 return s; 231 return NULL; 232 } 233 234 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream, 235 struct mchp_pdmc_chmap *ch_info) 236 { 237 struct snd_pcm_chmap_elem *map; 238 239 for (map = ch_info->chmap; map->channels; map++) { 240 if (map->channels == substream->runtime->channels) 241 return map; 242 } 243 return NULL; 244 } 245 246 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol, 247 struct snd_ctl_elem_value *ucontrol) 248 { 249 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 250 struct mchp_pdmc *dd = info->dd; 251 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 252 struct snd_pcm_substream *substream; 253 const struct snd_pcm_chmap_elem *map; 254 int i; 255 u32 cfgr_val = 0; 256 257 if (!info->chmap) 258 return -EINVAL; 259 substream = mchp_pdmc_chmap_substream(info, idx); 260 if (!substream) 261 return -ENODEV; 262 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no); 263 if (!substream->runtime) 264 return 0; /* no channels set */ 265 266 map = mchp_pdmc_chmap_get(substream, info); 267 if (!map) 268 return -EINVAL; 269 270 for (i = 0; i < map->channels; i++) { 271 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 272 map->map[i] - SNDRV_CHMAP_FL; 273 274 /* make sure the reported channel map is the real one, so write the map */ 275 if (dd->channel_mic_map[map_idx].ds_pos) 276 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 277 if (dd->channel_mic_map[map_idx].clk_edge) 278 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 279 280 ucontrol->value.integer.value[i] = map->map[i]; 281 } 282 283 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 284 285 return 0; 286 } 287 288 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol, 289 struct snd_ctl_elem_value *ucontrol) 290 { 291 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 292 struct mchp_pdmc *dd = info->dd; 293 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 294 struct snd_pcm_substream *substream; 295 struct snd_pcm_chmap_elem *map; 296 u32 cfgr_val = 0; 297 int i; 298 299 if (!info->chmap) 300 return -EINVAL; 301 substream = mchp_pdmc_chmap_substream(info, idx); 302 if (!substream) 303 return -ENODEV; 304 305 map = mchp_pdmc_chmap_get(substream, info); 306 if (!map) 307 return -EINVAL; 308 309 for (i = 0; i < map->channels; i++) { 310 int map_idx; 311 312 map->map[i] = ucontrol->value.integer.value[i]; 313 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 314 map->map[i] - SNDRV_CHMAP_FL; 315 316 /* configure IP for the desired channel map */ 317 if (dd->channel_mic_map[map_idx].ds_pos) 318 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 319 if (dd->channel_mic_map[map_idx].clk_edge) 320 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 321 } 322 323 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 324 325 return 0; 326 } 327 328 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol) 329 { 330 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 331 332 info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL; 333 kfree(info); 334 } 335 336 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, 337 unsigned int size, unsigned int __user *tlv) 338 { 339 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 340 const struct snd_pcm_chmap_elem *map; 341 unsigned int __user *dst; 342 int c, count = 0; 343 344 if (!info->chmap) 345 return -EINVAL; 346 if (size < 8) 347 return -ENOMEM; 348 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv)) 349 return -EFAULT; 350 size -= 8; 351 dst = tlv + 2; 352 for (map = info->chmap; map->channels; map++) { 353 int chs_bytes = map->channels * 4; 354 355 if (size < 8) 356 return -ENOMEM; 357 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) || 358 put_user(chs_bytes, dst + 1)) 359 return -EFAULT; 360 dst += 2; 361 size -= 8; 362 count += 8; 363 if (size < chs_bytes) 364 return -ENOMEM; 365 size -= chs_bytes; 366 count += chs_bytes; 367 for (c = 0; c < map->channels; c++) { 368 if (put_user(map->map[c], dst)) 369 return -EFAULT; 370 dst++; 371 } 372 } 373 if (put_user(count, tlv + 1)) 374 return -EFAULT; 375 return 0; 376 } 377 378 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = { 379 SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put), 380 { 381 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 382 .name = "SINC Filter Order", 383 .info = snd_soc_info_enum_double, 384 .get = mchp_pdmc_sinc_order_get, 385 .put = mchp_pdmc_sinc_order_put, 386 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum, 387 }, 388 }; 389 390 static const struct snd_soc_component_driver mchp_pdmc_dai_component = { 391 .name = "mchp-pdmc", 392 .controls = mchp_pdmc_snd_controls, 393 .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls), 394 }; 395 396 static const unsigned int mchp_pdmc_1mic[] = {1}; 397 static const unsigned int mchp_pdmc_2mic[] = {1, 2}; 398 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3}; 399 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4}; 400 401 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = { 402 { 403 .list = mchp_pdmc_1mic, 404 .count = ARRAY_SIZE(mchp_pdmc_1mic), 405 }, 406 { 407 .list = mchp_pdmc_2mic, 408 .count = ARRAY_SIZE(mchp_pdmc_2mic), 409 }, 410 { 411 .list = mchp_pdmc_3mic, 412 .count = ARRAY_SIZE(mchp_pdmc_3mic), 413 }, 414 { 415 .list = mchp_pdmc_4mic, 416 .count = ARRAY_SIZE(mchp_pdmc_4mic), 417 }, 418 }; 419 420 static int mchp_pdmc_startup(struct snd_pcm_substream *substream, 421 struct snd_soc_dai *dai) 422 { 423 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 424 425 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST); 426 427 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 428 &mchp_pdmc_chan_constr[dd->mic_no - 1]); 429 430 return 0; 431 } 432 433 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai) 434 { 435 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 436 437 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr); 438 439 return 0; 440 } 441 442 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 443 { 444 unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK; 445 unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 446 447 /* IP needs to be bitclock master */ 448 if (fmt_master != SND_SOC_DAIFMT_BP_FP && 449 fmt_master != SND_SOC_DAIFMT_BP_FC) 450 return -EINVAL; 451 452 /* IP supports only PDM interface */ 453 if (fmt_format != SND_SOC_DAIFMT_PDM) 454 return -EINVAL; 455 456 return 0; 457 } 458 459 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr) 460 { 461 if (audio_filter_en) { 462 switch (osr) { 463 case 64: 464 return MCHP_PDMC_MR_OSR64; 465 case 128: 466 return MCHP_PDMC_MR_OSR128; 467 case 256: 468 return MCHP_PDMC_MR_OSR256; 469 } 470 } else { 471 switch (osr) { 472 case 8: 473 return MCHP_PDMC_MR_SINC_OSR_8; 474 case 16: 475 return MCHP_PDMC_MR_SINC_OSR_16; 476 case 32: 477 return MCHP_PDMC_MR_SINC_OSR_32; 478 case 64: 479 return MCHP_PDMC_MR_SINC_OSR_64; 480 case 128: 481 return MCHP_PDMC_MR_SINC_OSR_128; 482 case 256: 483 return MCHP_PDMC_MR_SINC_OSR_256; 484 } 485 } 486 return 0; 487 } 488 489 static inline int mchp_pdmc_period_to_maxburst(int period_size, int sample_size) 490 { 491 int p_size = period_size; 492 int s_size = sample_size; 493 494 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_PDMC_DMA_8_WORD_CHUNK)) 495 return MCHP_PDMC_DMA_8_WORD_CHUNK; 496 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_PDMC_DMA_4_WORD_CHUNK)) 497 return MCHP_PDMC_DMA_4_WORD_CHUNK; 498 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_PDMC_DMA_2_WORD_CHUNK)) 499 return MCHP_PDMC_DMA_2_WORD_CHUNK; 500 return MCHP_PDMC_DMA_1_WORD_CHUNK; 501 } 502 503 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = { 504 { .channels = 1, 505 .map = { SNDRV_CHMAP_MONO } }, 506 { .channels = 2, 507 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 508 { .channels = 3, 509 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 510 SNDRV_CHMAP_RL } }, 511 { .channels = 4, 512 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 513 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 514 { } 515 }; 516 517 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, 518 struct snd_pcm_hw_params *params, 519 struct snd_soc_dai *dai) 520 { 521 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 522 struct snd_soc_component *comp = dai->component; 523 unsigned long gclk_rate = 0; 524 unsigned long best_diff_rate = ~0UL; 525 unsigned int channels = params_channels(params); 526 unsigned int osr = 0, osr_start; 527 unsigned int fs = params_rate(params); 528 int sample_bytes = params_physical_width(params) / 8; 529 int period_bytes = params_period_size(params) * 530 params_channels(params) * sample_bytes; 531 int maxburst; 532 u32 mr_val = 0; 533 u32 cfgr_val = 0; 534 int i; 535 int ret; 536 537 dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u period_bytes=%d\n", 538 __func__, params_rate(params), params_format(params), 539 params_width(params), params_channels(params), period_bytes); 540 541 if (channels > dd->mic_no) { 542 dev_err(comp->dev, "more channels %u than microphones %d\n", 543 channels, dd->mic_no); 544 return -EINVAL; 545 } 546 547 dd->pdmcen = 0; 548 for (i = 0; i < channels; i++) { 549 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i); 550 if (dd->channel_mic_map[i].ds_pos) 551 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 552 if (dd->channel_mic_map[i].clk_edge) 553 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 554 } 555 556 /* 557 * from these point forward, we consider the controller busy, so the 558 * audio filter and SINC order can't be changed 559 */ 560 atomic_set(&dd->busy_stream, 1); 561 for (osr_start = dd->audio_filter_en ? 64 : 8; 562 osr_start <= 256 && best_diff_rate; osr_start *= 2) { 563 long round_rate; 564 unsigned long diff_rate; 565 566 round_rate = clk_round_rate(dd->gclk, 567 (unsigned long)fs * 16 * osr_start); 568 if (round_rate < 0) 569 continue; 570 diff_rate = abs((fs * 16 * osr_start) - round_rate); 571 if (diff_rate < best_diff_rate) { 572 best_diff_rate = diff_rate; 573 osr = osr_start; 574 gclk_rate = fs * 16 * osr; 575 } 576 } 577 if (!gclk_rate) { 578 dev_err(comp->dev, "invalid sampling rate: %u\n", fs); 579 return -EINVAL; 580 } 581 582 /* CLK is enabled by runtime PM. */ 583 clk_disable_unprepare(dd->gclk); 584 585 /* set the rate */ 586 ret = clk_set_rate(dd->gclk, gclk_rate); 587 clk_prepare_enable(dd->gclk); 588 if (ret) { 589 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", 590 gclk_rate, ret); 591 return ret; 592 } 593 594 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr); 595 596 mr_val |= FIELD_PREP(MCHP_PDMC_MR_SINCORDER_MASK, dd->sinc_order); 597 598 maxburst = mchp_pdmc_period_to_maxburst(period_bytes, sample_bytes); 599 dd->addr.maxburst = maxburst; 600 mr_val |= FIELD_PREP(MCHP_PDMC_MR_CHUNK_MASK, dd->addr.maxburst); 601 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst); 602 603 snd_soc_component_update_bits(comp, MCHP_PDMC_MR, 604 MCHP_PDMC_MR_OSR_MASK | 605 MCHP_PDMC_MR_SINCORDER_MASK | 606 MCHP_PDMC_MR_SINC_OSR_MASK | 607 MCHP_PDMC_MR_CHUNK_MASK, mr_val); 608 609 snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val); 610 611 return 0; 612 } 613 614 static void mchp_pdmc_noise_filter_workaround(struct mchp_pdmc *dd) 615 { 616 u32 tmp, steps = 16; 617 618 /* 619 * PDMC doesn't wait for microphones' startup time thus the acquisition 620 * may start before the microphones are ready leading to poc noises at 621 * the beginning of capture. To avoid this, we need to wait 50ms (in 622 * normal startup procedure) or 150 ms (worst case after resume from sleep 623 * states) after microphones are enabled and then clear the FIFOs (by 624 * reading the RHR 16 times) and possible interrupts before continuing. 625 * Also, for this to work the DMA needs to be started after interrupts 626 * are enabled. 627 */ 628 usleep_range(dd->startup_delay_us, dd->startup_delay_us + 5); 629 630 while (steps--) 631 regmap_read(dd->regmap, MCHP_PDMC_RHR, &tmp); 632 633 /* Clear interrupts. */ 634 regmap_read(dd->regmap, MCHP_PDMC_ISR, &tmp); 635 } 636 637 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, 638 int cmd, struct snd_soc_dai *dai) 639 { 640 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 641 struct snd_soc_component *cpu = dai->component; 642 #ifdef DEBUG 643 u32 val; 644 #endif 645 646 switch (cmd) { 647 case SNDRV_PCM_TRIGGER_RESUME: 648 case SNDRV_PCM_TRIGGER_START: 649 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 650 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 651 MCHP_PDMC_MR_PDMCEN_MASK, 652 dd->pdmcen); 653 654 mchp_pdmc_noise_filter_workaround(dd); 655 656 /* Enable interrupts. */ 657 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq | 658 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 659 dd->suspend_irq = 0; 660 break; 661 case SNDRV_PCM_TRIGGER_SUSPEND: 662 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq); 663 fallthrough; 664 case SNDRV_PCM_TRIGGER_STOP: 665 /* Disable overrun and underrun error interrupts */ 666 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq | 667 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 668 fallthrough; 669 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 670 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 671 MCHP_PDMC_MR_PDMCEN_MASK, 0); 672 break; 673 default: 674 return -EINVAL; 675 } 676 677 #ifdef DEBUG 678 regmap_read(dd->regmap, MCHP_PDMC_MR, &val); 679 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val); 680 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val); 681 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val); 682 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val); 683 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val); 684 #endif 685 686 return 0; 687 } 688 689 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd) 690 { 691 struct mchp_pdmc_chmap *info; 692 struct snd_kcontrol_new knew = { 693 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 694 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 695 SNDRV_CTL_ELEM_ACCESS_TLV_READ | 696 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, 697 .info = mchp_pdmc_chmap_ctl_info, 698 .get = mchp_pdmc_chmap_ctl_get, 699 .put = mchp_pdmc_chmap_ctl_put, 700 .tlv.c = mchp_pdmc_chmap_ctl_tlv, 701 }; 702 int err; 703 704 if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl)) 705 return -EBUSY; 706 info = kzalloc(sizeof(*info), GFP_KERNEL); 707 if (!info) 708 return -ENOMEM; 709 info->pcm = pcm; 710 info->dd = dd; 711 info->chmap = mchp_pdmc_std_chmaps; 712 knew.name = "Capture Channel Map"; 713 knew.device = pcm->device; 714 knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count; 715 info->kctl = snd_ctl_new1(&knew, info); 716 if (!info->kctl) { 717 kfree(info); 718 return -ENOMEM; 719 } 720 info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free; 721 err = snd_ctl_add(pcm->card, info->kctl); 722 if (err < 0) 723 return err; 724 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl; 725 return 0; 726 } 727 728 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd, 729 struct snd_soc_dai *dai) 730 { 731 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 732 int ret; 733 734 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd); 735 if (ret < 0) 736 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret); 737 738 return ret; 739 } 740 741 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = { 742 .probe = mchp_pdmc_dai_probe, 743 .set_fmt = mchp_pdmc_set_fmt, 744 .startup = mchp_pdmc_startup, 745 .hw_params = mchp_pdmc_hw_params, 746 .trigger = mchp_pdmc_trigger, 747 .pcm_new = &mchp_pdmc_pcm_new, 748 }; 749 750 static struct snd_soc_dai_driver mchp_pdmc_dai = { 751 .name = "mchp-pdmc", 752 .capture = { 753 .stream_name = "Capture", 754 .channels_min = 1, 755 .channels_max = 4, 756 .rate_min = 8000, 757 .rate_max = 192000, 758 .rates = SNDRV_PCM_RATE_KNOT, 759 .formats = SNDRV_PCM_FMTBIT_S24_LE, 760 }, 761 .ops = &mchp_pdmc_dai_ops, 762 }; 763 764 /* PDMC interrupt handler */ 765 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id) 766 { 767 struct mchp_pdmc *dd = dev_id; 768 u32 isr, msr, pending; 769 irqreturn_t ret = IRQ_NONE; 770 771 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr); 772 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr); 773 774 pending = isr & msr; 775 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n", 776 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending); 777 if (!pending) 778 return IRQ_NONE; 779 780 if (pending & MCHP_PDMC_IR_RXUDR) { 781 dev_warn(dd->dev, "underrun detected\n"); 782 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR); 783 ret = IRQ_HANDLED; 784 } 785 if (pending & MCHP_PDMC_IR_RXOVR) { 786 dev_warn(dd->dev, "overrun detected\n"); 787 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR); 788 ret = IRQ_HANDLED; 789 } 790 791 return ret; 792 } 793 794 /* regmap configuration */ 795 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg) 796 { 797 switch (reg) { 798 case MCHP_PDMC_MR: 799 case MCHP_PDMC_CFGR: 800 case MCHP_PDMC_IMR: 801 case MCHP_PDMC_ISR: 802 case MCHP_PDMC_RHR: 803 case MCHP_PDMC_VER: 804 return true; 805 default: 806 return false; 807 } 808 } 809 810 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg) 811 { 812 switch (reg) { 813 case MCHP_PDMC_CR: 814 case MCHP_PDMC_MR: 815 case MCHP_PDMC_CFGR: 816 case MCHP_PDMC_IER: 817 case MCHP_PDMC_IDR: 818 return true; 819 default: 820 return false; 821 } 822 } 823 824 static bool mchp_pdmc_volatile_reg(struct device *dev, unsigned int reg) 825 { 826 switch (reg) { 827 case MCHP_PDMC_ISR: 828 case MCHP_PDMC_RHR: 829 return true; 830 default: 831 return false; 832 } 833 } 834 835 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg) 836 { 837 switch (reg) { 838 case MCHP_PDMC_RHR: 839 case MCHP_PDMC_ISR: 840 return true; 841 default: 842 return false; 843 } 844 } 845 846 static const struct regmap_config mchp_pdmc_regmap_config = { 847 .reg_bits = 32, 848 .reg_stride = 4, 849 .val_bits = 32, 850 .max_register = MCHP_PDMC_VER, 851 .readable_reg = mchp_pdmc_readable_reg, 852 .writeable_reg = mchp_pdmc_writeable_reg, 853 .precious_reg = mchp_pdmc_precious_reg, 854 .volatile_reg = mchp_pdmc_volatile_reg, 855 .cache_type = REGCACHE_FLAT, 856 }; 857 858 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd) 859 { 860 struct device_node *np = dd->dev->of_node; 861 bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0}; 862 int i; 863 int ret; 864 865 if (!np) { 866 dev_err(dd->dev, "device node not found\n"); 867 return -EINVAL; 868 } 869 870 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos"); 871 if (dd->mic_no < 0) { 872 dev_err(dd->dev, "failed to get microchip,mic-pos: %d", 873 dd->mic_no); 874 return dd->mic_no; 875 } 876 if (!dd->mic_no || dd->mic_no % 2 || 877 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) { 878 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d", 879 dd->mic_no); 880 return -EINVAL; 881 } 882 883 dd->mic_no /= 2; 884 885 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no); 886 887 /* 888 * by default, we consider the order of microphones in 889 * microchip,mic-pos to be the same with the channel mapping; 890 * 1st microphone channel 0, 2nd microphone channel 1, etc. 891 */ 892 for (i = 0; i < dd->mic_no; i++) { 893 int ds; 894 int edge; 895 896 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2, 897 &ds); 898 if (ret) { 899 dev_err(dd->dev, 900 "failed to get value no %d value from microchip,mic-pos: %d", 901 i * 2, ret); 902 return ret; 903 } 904 if (ds >= MCHP_PDMC_DS_NO) { 905 dev_err(dd->dev, 906 "invalid DS index in microchip,mic-pos array: %d", 907 ds); 908 return -EINVAL; 909 } 910 911 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1, 912 &edge); 913 if (ret) { 914 dev_err(dd->dev, 915 "failed to get value no %d value from microchip,mic-pos: %d", 916 i * 2 + 1, ret); 917 return ret; 918 } 919 920 if (edge != MCHP_PDMC_CLK_POSITIVE && 921 edge != MCHP_PDMC_CLK_NEGATIVE) { 922 dev_err(dd->dev, 923 "invalid edge in microchip,mic-pos array: %d", edge); 924 return -EINVAL; 925 } 926 if (mic_ch[ds][edge]) { 927 dev_err(dd->dev, 928 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array", 929 ds, edge); 930 return -EINVAL; 931 } 932 mic_ch[ds][edge] = true; 933 dd->channel_mic_map[i].ds_pos = ds; 934 dd->channel_mic_map[i].clk_edge = edge; 935 } 936 937 dd->startup_delay_us = 150000; 938 of_property_read_u32(np, "microchip,startup-delay-us", &dd->startup_delay_us); 939 940 return 0; 941 } 942 943 /* used to clean the channel index found on RHR's MSB */ 944 static int mchp_pdmc_process(struct snd_pcm_substream *substream, 945 int channel, unsigned long hwoff, 946 unsigned long bytes) 947 { 948 struct snd_pcm_runtime *runtime = substream->runtime; 949 u8 *dma_ptr = runtime->dma_area + hwoff + 950 channel * (runtime->dma_bytes / runtime->channels); 951 u8 *dma_ptr_end = dma_ptr + bytes; 952 unsigned int sample_size = samples_to_bytes(runtime, 1); 953 954 for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size) 955 *dma_ptr = 0; 956 957 return 0; 958 } 959 960 static struct snd_dmaengine_pcm_config mchp_pdmc_config = { 961 .process = mchp_pdmc_process, 962 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 963 }; 964 965 static int mchp_pdmc_runtime_suspend(struct device *dev) 966 { 967 struct mchp_pdmc *dd = dev_get_drvdata(dev); 968 969 regcache_cache_only(dd->regmap, true); 970 971 clk_disable_unprepare(dd->gclk); 972 clk_disable_unprepare(dd->pclk); 973 974 return 0; 975 } 976 977 static int mchp_pdmc_runtime_resume(struct device *dev) 978 { 979 struct mchp_pdmc *dd = dev_get_drvdata(dev); 980 int ret; 981 982 ret = clk_prepare_enable(dd->pclk); 983 if (ret) { 984 dev_err(dd->dev, 985 "failed to enable the peripheral clock: %d\n", ret); 986 return ret; 987 } 988 ret = clk_prepare_enable(dd->gclk); 989 if (ret) { 990 dev_err(dd->dev, 991 "failed to enable generic clock: %d\n", ret); 992 goto disable_pclk; 993 } 994 995 regcache_cache_only(dd->regmap, false); 996 regcache_mark_dirty(dd->regmap); 997 ret = regcache_sync(dd->regmap); 998 if (ret) { 999 regcache_cache_only(dd->regmap, true); 1000 clk_disable_unprepare(dd->gclk); 1001 disable_pclk: 1002 clk_disable_unprepare(dd->pclk); 1003 } 1004 1005 return ret; 1006 } 1007 1008 static int mchp_pdmc_probe(struct platform_device *pdev) 1009 { 1010 struct device *dev = &pdev->dev; 1011 struct mchp_pdmc *dd; 1012 struct resource *res; 1013 void __iomem *io_base; 1014 u32 version; 1015 int irq; 1016 int ret; 1017 1018 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL); 1019 if (!dd) 1020 return -ENOMEM; 1021 1022 dd->dev = &pdev->dev; 1023 ret = mchp_pdmc_dt_init(dd); 1024 if (ret < 0) 1025 return ret; 1026 1027 irq = platform_get_irq(pdev, 0); 1028 if (irq < 0) 1029 return irq; 1030 1031 dd->pclk = devm_clk_get(dev, "pclk"); 1032 if (IS_ERR(dd->pclk)) { 1033 ret = PTR_ERR(dd->pclk); 1034 dev_err(dev, "failed to get peripheral clock: %d\n", ret); 1035 return ret; 1036 } 1037 1038 dd->gclk = devm_clk_get(dev, "gclk"); 1039 if (IS_ERR(dd->gclk)) { 1040 ret = PTR_ERR(dd->gclk); 1041 dev_err(dev, "failed to get GCK: %d\n", ret); 1042 return ret; 1043 } 1044 1045 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1046 if (IS_ERR(io_base)) { 1047 ret = PTR_ERR(io_base); 1048 dev_err(dev, "failed to remap register memory: %d\n", ret); 1049 return ret; 1050 } 1051 1052 dd->regmap = devm_regmap_init_mmio(dev, io_base, 1053 &mchp_pdmc_regmap_config); 1054 if (IS_ERR(dd->regmap)) { 1055 ret = PTR_ERR(dd->regmap); 1056 dev_err(dev, "failed to init register map: %d\n", ret); 1057 return ret; 1058 } 1059 1060 ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0, 1061 dev_name(&pdev->dev), dd); 1062 if (ret < 0) { 1063 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 1064 irq, ret); 1065 return ret; 1066 } 1067 1068 /* by default audio filter is enabled and the SINC Filter order 1069 * will be set to the recommended value, 3 1070 */ 1071 dd->audio_filter_en = true; 1072 dd->sinc_order = 3; 1073 1074 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR; 1075 platform_set_drvdata(pdev, dd); 1076 1077 pm_runtime_enable(dd->dev); 1078 if (!pm_runtime_enabled(dd->dev)) { 1079 ret = mchp_pdmc_runtime_resume(dd->dev); 1080 if (ret) 1081 return ret; 1082 } 1083 1084 /* register platform */ 1085 ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0); 1086 if (ret) { 1087 dev_err(dev, "could not register platform: %d\n", ret); 1088 goto pm_runtime_suspend; 1089 } 1090 1091 ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component, 1092 &mchp_pdmc_dai, 1); 1093 if (ret) { 1094 dev_err(dev, "could not register CPU DAI: %d\n", ret); 1095 goto pm_runtime_suspend; 1096 } 1097 1098 /* print IP version */ 1099 regmap_read(dd->regmap, MCHP_PDMC_VER, &version); 1100 dev_info(dd->dev, "hw version: %#lx\n", 1101 version & MCHP_PDMC_VER_VERSION); 1102 1103 return 0; 1104 1105 pm_runtime_suspend: 1106 if (!pm_runtime_status_suspended(dd->dev)) 1107 mchp_pdmc_runtime_suspend(dd->dev); 1108 pm_runtime_disable(dd->dev); 1109 1110 return ret; 1111 } 1112 1113 static void mchp_pdmc_remove(struct platform_device *pdev) 1114 { 1115 struct mchp_pdmc *dd = platform_get_drvdata(pdev); 1116 1117 atomic_set(&dd->busy_stream, 0); 1118 1119 if (!pm_runtime_status_suspended(dd->dev)) 1120 mchp_pdmc_runtime_suspend(dd->dev); 1121 1122 pm_runtime_disable(dd->dev); 1123 } 1124 1125 static const struct of_device_id mchp_pdmc_of_match[] = { 1126 { 1127 .compatible = "microchip,sama7g5-pdmc", 1128 }, { 1129 /* sentinel */ 1130 } 1131 }; 1132 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); 1133 1134 static const struct dev_pm_ops mchp_pdmc_pm_ops = { 1135 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1136 RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume, 1137 NULL) 1138 }; 1139 1140 static struct platform_driver mchp_pdmc_driver = { 1141 .driver = { 1142 .name = "mchp-pdmc", 1143 .of_match_table = of_match_ptr(mchp_pdmc_of_match), 1144 .pm = pm_ptr(&mchp_pdmc_pm_ops), 1145 }, 1146 .probe = mchp_pdmc_probe, 1147 .remove = mchp_pdmc_remove, 1148 }; 1149 module_platform_driver(mchp_pdmc_driver); 1150 1151 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture"); 1152 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 1153 MODULE_LICENSE("GPL v2"); 1154