1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef MEMORY_TEGRA_MC_H 7 #define MEMORY_TEGRA_MC_H 8 9 #include <linux/bits.h> 10 #include <linux/io.h> 11 #include <linux/types.h> 12 13 #include <soc/tegra/mc.h> 14 15 #define MC_INTSTATUS 0x00 16 /* Bit field of MC_INTSTATUS register */ 17 #define MC_INT_DECERR_EMEM BIT(6) 18 #define MC_INT_INVALID_GART_PAGE BIT(7) 19 #define MC_INT_SECURITY_VIOLATION BIT(8) 20 #define MC_INT_ARBITRATION_EMEM BIT(9) 21 #define MC_INT_INVALID_SMMU_PAGE BIT(10) 22 #define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) 23 #define MC_INT_DECERR_VPR BIT(12) 24 #define MC_INT_SECERR_SEC BIT(13) 25 #define MC_INT_DECERR_MTS BIT(16) 26 #define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) 27 #define MC_INT_DECERR_ROUTE_SANITY BIT(20) 28 #define MC_INT_DECERR_ROUTE_SANITY_GIC_MSI BIT(21) 29 30 #define MC_INTMASK 0x04 31 #define MC_GART_ERROR_REQ 0x30 32 #define MC_EMEM_ADR_CFG 0x54 33 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 34 35 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 36 #define MC_SECURITY_VIOLATION_STATUS 0x74 37 #define MC_EMEM_ARB_CFG 0x90 38 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff) 39 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 40 41 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 42 #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) 43 #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) 44 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff 45 46 #define MC_EMEM_ARB_TIMING_RCD 0x98 47 #define MC_EMEM_ARB_TIMING_RP 0x9c 48 #define MC_EMEM_ARB_TIMING_RC 0xa0 49 #define MC_EMEM_ARB_TIMING_RAS 0xa4 50 #define MC_EMEM_ARB_TIMING_FAW 0xa8 51 #define MC_EMEM_ARB_TIMING_RRD 0xac 52 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 53 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 54 #define MC_EMEM_ARB_TIMING_R2R 0xb8 55 #define MC_EMEM_ARB_TIMING_W2W 0xbc 56 #define MC_EMEM_ARB_TIMING_R2W 0xc0 57 #define MC_EMEM_ARB_TIMING_W2R 0xc4 58 #define MC_EMEM_ARB_MISC2 0xc8 59 #define MC_EMEM_ARB_DA_TURNS 0xd0 60 #define MC_EMEM_ARB_DA_COVERS 0xd4 61 #define MC_EMEM_ARB_MISC0 0xd8 62 #define MC_EMEM_ARB_MISC1 0xdc 63 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0 64 #define MC_EMEM_ARB_OVERRIDE 0xe8 65 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 66 67 #define MC_TIMING_CONTROL_DBG 0xf8 68 #define MC_TIMING_CONTROL 0xfc 69 #define MC_TIMING_UPDATE BIT(0) 70 71 #define MC_GLOBAL_INTSTATUS 0xf24 72 73 /* Bit field of MC_ERR_STATUS_0 register */ 74 #define MC_ERR_STATUS_RW BIT(16) 75 #define MC_ERR_STATUS_SECURITY BIT(17) 76 #define MC_ERR_STATUS_NONSECURE BIT(25) 77 #define MC_ERR_STATUS_WRITABLE BIT(26) 78 #define MC_ERR_STATUS_READABLE BIT(27) 79 80 #define MC_ERR_STATUS_GSC_ADR_HI_MASK 0xffff 81 #define MC_ERR_STATUS_GSC_ADR_HI_SHIFT 16 82 #define MC_ERR_STATUS_RT_ADR_HI_SHIFT 15 83 84 #define MC_ERR_STATUS_TYPE_SHIFT 28 85 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28) 86 #define MC_ERR_STATUS_RT_TYPE_MASK (0xf << 28) 87 #define MC_ERR_STATUS_RT_TYPE_SHIFT 28 88 89 #define MC_ERR_STATUS_ADR_HI_SHIFT 20 90 91 #define MC_BROADCAST_CHANNEL ~0 92 93 /* Tegra264 specific registers */ 94 95 /* Registers for MSS HUB */ 96 #define MSS_HUB_GLOBAL_INTSTATUS_0 0x6000 97 #define MSS_HUBC_INTR BIT(0) 98 #define MSS_HUB_GLOBAL_MASK 0x7F00 99 #define MSS_HUB_GLOBAL_SHIFT 8 100 101 #define MSS_HUB_HUBC_INTSTATUS_0 0x6008 102 #define MSS_HUB_INTRSTATUS_0 0x600c 103 #define MSS_HUB_HUBC_INTMASK_0 0x6010 104 #define MSS_HUB_HUBC_SCRUB_DONE_INTMASK BIT(0) 105 106 #define MSS_HUB_HUBC_INTPRIORITY_0 0x6014 107 #define MSS_HUB_INTRMASK_0 0x6018 108 #define MSS_HUB_COALESCER_ERR_INTMASK BIT(0) 109 #define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK BIT(1) 110 #define MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK BIT(2) 111 #define MSS_HUB_MSI_ERR_INTMASK BIT(3) 112 #define MSS_HUB_POISON_RSP_INTMASK BIT(4) 113 #define MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK BIT(5) 114 #define MSS_HUB_RESERVED_PA_ERR_INTMASK BIT(6) 115 116 #define MSS_HUB_INTRPRIORITY_0 0x601c 117 #define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0 0x6020 118 #define MSS_HUB_MSI_ERR_STATUS_0 0x6024 119 #define MSS_HUB_POISON_RSP_STATUS_0 0x6028 120 #define MSS_HUB_COALESCE_ERR_STATUS_0 0x60e0 121 #define MSS_HUB_COALESCE_ERR_ADR_HI_0 0x60e4 122 #define MSS_HUB_COALESCE_ERR_ADR_0 0x60e8 123 #define MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0 0x638c 124 #define MSS_HUB_RESERVED_PA_ERR_STATUS_0 0x6390 125 #define MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0 0x63b0 126 127 /* Registers for channels */ 128 #define MC_CH_INTSTATUS_0 0x82d4 129 #define MC_CH_INTMASK_0 0x82d8 130 #define WCAM_ERR_INTMASK BIT(19) 131 132 #define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0 0xbc74 133 134 /* Registers for MCF */ 135 #define MCF_COMMON_INTSTATUS0_0_0 0xce04 136 #define MCF_INTSTATUS_0 0xce2c 137 #define MCF_INTMASK_0 0xce30 138 #define MCF_INTPRIORITY_0 0xce34 139 140 /* Registers for SBS */ 141 #define MSS_SBS_INTSTATUS_0 0xec08 142 #define MSS_SBS_INTMASK_0 0xec0c 143 #define MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK BIT(0) 144 #define MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK BIT(1) 145 #define MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK BIT(2) 146 147 /* Bit field of MC_ERR_ROUTE_SANITY_STATUS_0 register */ 148 #define MC_ERR_ROUTE_SANITY_RW BIT(12) 149 #define MC_ERR_ROUTE_SANITY_SEC BIT(13) 150 151 #define ERR_GENERALIZED_APERTURE_ID_SHIFT 0 152 #define ERR_GENERALIZED_APERTURE_ID_MASK 0x1F 153 #define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT 5 154 #define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK 0x1F 155 156 static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) 157 { 158 val = val * percents; 159 do_div(val, 100); 160 161 return min_t(u64, val, U32_MAX); 162 } 163 164 static inline struct tegra_mc * 165 icc_provider_to_tegra_mc(struct icc_provider *provider) 166 { 167 return container_of(provider, struct tegra_mc, provider); 168 } 169 170 static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch, 171 unsigned long offset) 172 { 173 if (!mc->bcast_ch_regs) 174 return 0; 175 176 if (ch == MC_BROADCAST_CHANNEL) 177 return readl_relaxed(mc->bcast_ch_regs + offset); 178 179 return readl_relaxed(mc->ch_regs[ch] + offset); 180 } 181 182 static inline void mc_ch_writel(const struct tegra_mc *mc, int ch, 183 u32 value, unsigned long offset) 184 { 185 if (!mc->bcast_ch_regs) 186 return; 187 188 if (ch == MC_BROADCAST_CHANNEL) 189 writel_relaxed(value, mc->bcast_ch_regs + offset); 190 else 191 writel_relaxed(value, mc->ch_regs[ch] + offset); 192 } 193 194 static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) 195 { 196 return readl_relaxed(mc->regs + offset); 197 } 198 199 static inline void mc_writel(const struct tegra_mc *mc, u32 value, 200 unsigned long offset) 201 { 202 writel_relaxed(value, mc->regs + offset); 203 } 204 205 extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common; 206 207 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 208 extern const struct tegra_mc_soc tegra20_mc_soc; 209 #endif 210 211 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 212 extern const struct tegra_mc_soc tegra30_mc_soc; 213 #endif 214 215 #ifdef CONFIG_ARCH_TEGRA_114_SOC 216 extern const struct tegra_mc_soc tegra114_mc_soc; 217 #endif 218 219 #ifdef CONFIG_ARCH_TEGRA_124_SOC 220 extern const struct tegra_mc_soc tegra124_mc_soc; 221 #endif 222 223 #ifdef CONFIG_ARCH_TEGRA_132_SOC 224 extern const struct tegra_mc_soc tegra132_mc_soc; 225 #endif 226 227 #ifdef CONFIG_ARCH_TEGRA_210_SOC 228 extern const struct tegra_mc_soc tegra210_mc_soc; 229 #endif 230 231 #ifdef CONFIG_ARCH_TEGRA_186_SOC 232 extern const struct tegra_mc_soc tegra186_mc_soc; 233 #endif 234 235 #ifdef CONFIG_ARCH_TEGRA_194_SOC 236 extern const struct tegra_mc_soc tegra194_mc_soc; 237 #endif 238 239 #ifdef CONFIG_ARCH_TEGRA_234_SOC 240 extern const struct tegra_mc_soc tegra234_mc_soc; 241 #endif 242 243 #ifdef CONFIG_ARCH_TEGRA_264_SOC 244 extern const struct tegra_mc_soc tegra264_mc_soc; 245 #endif 246 247 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 248 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 249 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 250 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 251 defined(CONFIG_ARCH_TEGRA_210_SOC) 252 int tegra30_mc_probe(struct tegra_mc *mc); 253 extern const struct tegra_mc_ops tegra30_mc_ops; 254 #endif 255 256 #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ 257 defined(CONFIG_ARCH_TEGRA_194_SOC) || \ 258 defined(CONFIG_ARCH_TEGRA_234_SOC) || \ 259 defined(CONFIG_ARCH_TEGRA_264_SOC) 260 extern const struct tegra_mc_ops tegra186_mc_ops; 261 #endif 262 263 irqreturn_t tegra30_mc_handle_irq(int irq, void *data); 264 extern const irq_handler_t tegra30_mc_irq_handlers[1]; 265 extern const char * const tegra_mc_status_names[32]; 266 extern const char * const tegra20_mc_error_names[8]; 267 268 /* 269 * These IDs are for internal use of Tegra ICC drivers. The ID numbers are 270 * chosen such that they don't conflict with the device-tree ICC node IDs. 271 */ 272 #define TEGRA_ICC_MC 1000 273 #define TEGRA_ICC_EMC 1001 274 #define TEGRA_ICC_EMEM 1002 275 276 #endif /* MEMORY_TEGRA_MC_H */ 277