1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_CORE_H__ 34 #define __MLX5_CORE_H__ 35 36 #include <linux/types.h> 37 #include <linux/kernel.h> 38 #include <linux/sched.h> 39 #include <linux/if_link.h> 40 #include <linux/firmware.h> 41 #include <linux/mlx5/cq.h> 42 #include <linux/mlx5/fs.h> 43 #include <linux/mlx5/driver.h> 44 #include "lib/devcom.h" 45 46 extern uint mlx5_core_debug_mask; 47 48 #define mlx5_core_dbg(__dev, format, ...) \ 49 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \ 50 __func__, __LINE__, current->pid, \ 51 ##__VA_ARGS__) 52 53 #define mlx5_core_dbg_once(__dev, format, ...) \ 54 dev_dbg_once((__dev)->device, \ 55 "%s:%d:(pid %d): " format, \ 56 __func__, __LINE__, current->pid, \ 57 ##__VA_ARGS__) 58 59 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \ 60 do { \ 61 if ((mask) & mlx5_core_debug_mask) \ 62 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \ 63 } while (0) 64 65 #define mlx5_core_err(__dev, format, ...) \ 66 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \ 67 __func__, __LINE__, current->pid, \ 68 ##__VA_ARGS__) 69 70 #define mlx5_core_err_rl(__dev, format, ...) \ 71 dev_err_ratelimited((__dev)->device, \ 72 "%s:%d:(pid %d): " format, \ 73 __func__, __LINE__, current->pid, \ 74 ##__VA_ARGS__) 75 76 #define mlx5_core_warn(__dev, format, ...) \ 77 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \ 78 __func__, __LINE__, current->pid, \ 79 ##__VA_ARGS__) 80 81 #define mlx5_core_warn_once(__dev, format, ...) \ 82 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \ 83 __func__, __LINE__, current->pid, \ 84 ##__VA_ARGS__) 85 86 #define mlx5_core_warn_rl(__dev, format, ...) \ 87 dev_warn_ratelimited((__dev)->device, \ 88 "%s:%d:(pid %d): " format, \ 89 __func__, __LINE__, current->pid, \ 90 ##__VA_ARGS__) 91 92 #define mlx5_core_info(__dev, format, ...) \ 93 dev_info((__dev)->device, format, ##__VA_ARGS__) 94 95 #define mlx5_core_info_rl(__dev, format, ...) \ 96 dev_info_ratelimited((__dev)->device, \ 97 "%s:%d:(pid %d): " format, \ 98 __func__, __LINE__, current->pid, \ 99 ##__VA_ARGS__) 100 101 #define ACCESS_KEY_LEN 32 102 #define FT_ID_FT_TYPE_OFFSET 24 103 104 struct mlx5_cmd_allow_other_vhca_access_attr { 105 u16 obj_type; 106 u32 obj_id; 107 u8 access_key[ACCESS_KEY_LEN]; 108 }; 109 110 struct mlx5_cmd_alias_obj_create_attr { 111 u32 obj_id; 112 u16 vhca_id; 113 u8 vhca_id_type; 114 u16 obj_type; 115 u8 access_key[ACCESS_KEY_LEN]; 116 }; 117 118 struct mlx5_port_eth_proto { 119 u32 cap; 120 u32 admin; 121 u32 oper; 122 }; 123 124 struct mlx5_module_eeprom_query_params { 125 u16 size; 126 u16 offset; 127 u16 i2c_address; 128 u32 page; 129 u32 bank; 130 u32 module_number; 131 }; 132 133 struct mlx5_link_info { 134 u32 speed; 135 u32 lanes; 136 }; 137 138 static inline void mlx5_printk(struct mlx5_core_dev *dev, int level, const char *format, ...) 139 { 140 struct device *device = dev->device; 141 struct va_format vaf; 142 va_list args; 143 144 if (WARN_ONCE(level < LOGLEVEL_EMERG || level > LOGLEVEL_DEBUG, 145 "Level %d is out of range, set to default level\n", level)) 146 level = LOGLEVEL_DEFAULT; 147 148 va_start(args, format); 149 vaf.fmt = format; 150 vaf.va = &args; 151 152 dev_printk_emit(level, device, "%s %s: %pV", dev_driver_string(device), dev_name(device), 153 &vaf); 154 va_end(args); 155 } 156 157 #define mlx5_log(__dev, level, format, ...) \ 158 mlx5_printk(__dev, level, "%s:%d:(pid %d): " format, \ 159 __func__, __LINE__, current->pid, \ 160 ##__VA_ARGS__) 161 162 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev) 163 { 164 return &dev->pdev->dev; 165 } 166 167 enum { 168 MLX5_CMD_DATA, /* print command payload only */ 169 MLX5_CMD_TIME, /* print command execution time */ 170 }; 171 172 enum { 173 MLX5_DRIVER_STATUS_ABORTED = 0xfe, 174 MLX5_DRIVER_SYND = 0xbadd00de, 175 }; 176 177 enum mlx5_semaphore_space_address { 178 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA, 179 MLX5_SEMAPHORE_SW_RESET = 0x20, 180 }; 181 182 #define MLX5_DEFAULT_PROF 2 183 #define MLX5_SF_PROF 3 184 #define MLX5_NUM_FW_CMD_THREADS 8 185 #define MLX5_DEV_MAX_WQS MLX5_NUM_FW_CMD_THREADS 186 187 static inline int mlx5_flexible_inlen(struct mlx5_core_dev *dev, size_t fixed, 188 size_t item_size, size_t num_items, 189 const char *func, int line) 190 { 191 int inlen; 192 193 if (fixed > INT_MAX || item_size > INT_MAX || num_items > INT_MAX) { 194 mlx5_core_err(dev, "%s: %s:%d: input values too big: %zu + %zu * %zu\n", 195 __func__, func, line, fixed, item_size, num_items); 196 return -ENOMEM; 197 } 198 199 if (check_mul_overflow((int)item_size, (int)num_items, &inlen)) { 200 mlx5_core_err(dev, "%s: %s:%d: multiplication overflow: %zu + %zu * %zu\n", 201 __func__, func, line, fixed, item_size, num_items); 202 return -ENOMEM; 203 } 204 205 if (check_add_overflow((int)fixed, inlen, &inlen)) { 206 mlx5_core_err(dev, "%s: %s:%d: addition overflow: %zu + %zu * %zu\n", 207 __func__, func, line, fixed, item_size, num_items); 208 return -ENOMEM; 209 } 210 211 return inlen; 212 } 213 214 #define MLX5_FLEXIBLE_INLEN(dev, fixed, item_size, num_items) \ 215 mlx5_flexible_inlen(dev, fixed, item_size, num_items, __func__, __LINE__) 216 217 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 218 int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 219 enum mlx5_cap_mode cap_mode); 220 int mlx5_query_hca_caps(struct mlx5_core_dev *dev); 221 int mlx5_query_board_id(struct mlx5_core_dev *dev); 222 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 223 int mlx5_cmd_init(struct mlx5_core_dev *dev); 224 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 225 int mlx5_cmd_enable(struct mlx5_core_dev *dev); 226 void mlx5_cmd_disable(struct mlx5_core_dev *dev); 227 void mlx5_cmd_set_state(struct mlx5_core_dev *dev, 228 enum mlx5_cmdif_state cmdif_state); 229 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, u32 *sw_owner_id); 230 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev); 231 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev); 232 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev); 233 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force); 234 void mlx5_error_sw_reset(struct mlx5_core_dev *dev); 235 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev); 236 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev); 237 void mlx5_disable_device(struct mlx5_core_dev *dev); 238 int mlx5_recover_device(struct mlx5_core_dev *dev); 239 int mlx5_sriov_init(struct mlx5_core_dev *dev); 240 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev); 241 int mlx5_sriov_attach(struct mlx5_core_dev *dev); 242 void mlx5_sriov_detach(struct mlx5_core_dev *dev); 243 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs); 244 void mlx5_sriov_disable(struct pci_dev *pdev, bool num_vf_change); 245 int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count); 246 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id); 247 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id); 248 bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy); 249 bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy); 250 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 251 void *context, u32 *element_id); 252 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 253 void *context, u32 element_id, 254 u32 modify_bitmask); 255 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy, 256 u32 element_id); 257 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages); 258 259 void mlx5_cmd_flush(struct mlx5_core_dev *dev); 260 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 261 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 262 void mlx5_vhca_debugfs_init(struct mlx5_core_dev *dev); 263 264 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, 265 u8 access_reg_group); 266 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group, 267 u8 access_reg_group); 268 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam, 269 u8 feature_group, u8 access_reg_group); 270 int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir); 271 272 void mlx5_lag_add_netdev(struct mlx5_core_dev *dev, struct net_device *netdev); 273 void mlx5_lag_remove_netdev(struct mlx5_core_dev *dev, struct net_device *netdev); 274 void mlx5_lag_add_mdev(struct mlx5_core_dev *dev); 275 void mlx5_lag_remove_mdev(struct mlx5_core_dev *dev); 276 void mlx5_lag_disable_change(struct mlx5_core_dev *dev); 277 void mlx5_lag_enable_change(struct mlx5_core_dev *dev); 278 279 int mlx5_events_init(struct mlx5_core_dev *dev); 280 void mlx5_events_cleanup(struct mlx5_core_dev *dev); 281 void mlx5_events_start(struct mlx5_core_dev *dev); 282 void mlx5_events_stop(struct mlx5_core_dev *dev); 283 284 int mlx5_adev_idx_alloc(void); 285 void mlx5_adev_idx_free(int idx); 286 void mlx5_adev_cleanup(struct mlx5_core_dev *dev); 287 int mlx5_adev_init(struct mlx5_core_dev *dev); 288 289 int mlx5_attach_device(struct mlx5_core_dev *dev); 290 void mlx5_detach_device(struct mlx5_core_dev *dev, bool suspend); 291 int mlx5_register_device(struct mlx5_core_dev *dev); 292 void mlx5_unregister_device(struct mlx5_core_dev *dev); 293 void mlx5_dev_set_lightweight(struct mlx5_core_dev *dev); 294 bool mlx5_dev_is_lightweight(struct mlx5_core_dev *dev); 295 void mlx5_core_reps_aux_devs_remove(struct mlx5_core_dev *dev); 296 297 void mlx5_fw_reporters_create(struct mlx5_core_dev *dev); 298 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size); 299 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size); 300 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode); 301 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode); 302 303 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev); 304 void mlx5_dm_cleanup(struct mlx5_core_dev *dev); 305 306 #ifdef CONFIG_PCIE_TPH 307 struct mlx5_st *mlx5_st_create(struct mlx5_core_dev *dev); 308 void mlx5_st_destroy(struct mlx5_core_dev *dev); 309 #else 310 static inline struct mlx5_st * 311 mlx5_st_create(struct mlx5_core_dev *dev) { return NULL; } 312 static inline void mlx5_st_destroy(struct mlx5_core_dev *dev) { return; } 313 #endif 314 315 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 316 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, 317 enum mlx5_port_status status); 318 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 319 enum mlx5_port_status *status); 320 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration); 321 322 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port); 323 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause); 324 int mlx5_query_port_pause(struct mlx5_core_dev *dev, 325 u32 *rx_pause, u32 *tx_pause); 326 327 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); 328 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, 329 u8 *pfc_en_rx); 330 331 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, 332 u16 stall_critical_watermark, 333 u16 stall_minor_watermark); 334 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, 335 u16 *stall_critical_watermark, 336 u16 *stall_minor_watermark); 337 338 int mlx5_max_tc(struct mlx5_core_dev *mdev); 339 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc); 340 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, 341 u8 prio, u8 *tc); 342 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group); 343 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, 344 u8 tc, u8 *tc_group); 345 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw); 346 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, 347 u8 tc, u8 *bw_pct); 348 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, 349 u16 *max_bw_value, 350 u8 *max_bw_unit); 351 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, 352 u16 *max_bw_value, 353 u8 *max_bw_unit); 354 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode); 355 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode); 356 357 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen); 358 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen); 359 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable); 360 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, 361 bool *enabled); 362 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, 363 u16 offset, u16 size, u8 *data, u8 *status); 364 int 365 mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev, 366 struct mlx5_module_eeprom_query_params *params, 367 u8 *data, u8 *status); 368 369 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out); 370 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in); 371 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state); 372 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state); 373 int mlx5_query_port_buffer_ownership(struct mlx5_core_dev *mdev, 374 u8 *buffer_ownership); 375 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio); 376 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); 377 378 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, 379 struct mlx5_port_eth_proto *eproto); 380 bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev); 381 const struct mlx5_link_info *mlx5_port_ptys2info(struct mlx5_core_dev *mdev, 382 u32 eth_proto_oper, 383 bool force_legacy); 384 u32 mlx5_port_info2linkmodes(struct mlx5_core_dev *mdev, 385 struct mlx5_link_info *info, 386 bool force_legacy); 387 int mlx5_port_oper_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); 388 int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); 389 390 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ 391 MLX5_CAP_GEN((mdev), pps_modify) && \ 392 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \ 393 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj)) 394 395 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw, 396 struct netlink_ext_ack *extack); 397 void mlx5_fw_version_query(struct mlx5_core_dev *dev, u32 *running_ver, 398 u32 *stored_ver); 399 400 #ifdef CONFIG_MLX5_CORE_EN 401 int mlx5e_init(void); 402 void mlx5e_cleanup(void); 403 #else 404 static inline int mlx5e_init(void){ return 0; } 405 static inline void mlx5e_cleanup(void){} 406 #endif 407 408 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev) 409 { 410 return pci_num_vf(dev->pdev) ? true : false; 411 } 412 413 int mlx5_rescan_drivers_locked(struct mlx5_core_dev *dev); 414 static inline int mlx5_rescan_drivers(struct mlx5_core_dev *dev) 415 { 416 int ret; 417 418 mlx5_devcom_comp_lock(dev->priv.hca_devcom_comp); 419 ret = mlx5_rescan_drivers_locked(dev); 420 mlx5_devcom_comp_unlock(dev->priv.hca_devcom_comp); 421 return ret; 422 } 423 424 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev); 425 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state); 426 427 static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev) 428 { 429 return dev->coredev_type == MLX5_COREDEV_SF; 430 } 431 432 static inline struct auxiliary_device * 433 mlx5_sf_coredev_to_adev(struct mlx5_core_dev *mdev) 434 { 435 return container_of(mdev->device, struct auxiliary_device, dev); 436 } 437 438 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx); 439 void mlx5_mdev_uninit(struct mlx5_core_dev *dev); 440 int mlx5_frag_buf_pools_init(struct mlx5_core_dev *dev); 441 void mlx5_frag_buf_pools_cleanup(struct mlx5_core_dev *dev); 442 int mlx5_init_one(struct mlx5_core_dev *dev); 443 int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev); 444 void mlx5_uninit_one(struct mlx5_core_dev *dev); 445 void mlx5_unload_one(struct mlx5_core_dev *dev, bool suspend); 446 void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev, bool suspend); 447 int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery); 448 int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery); 449 int mlx5_init_one_light(struct mlx5_core_dev *dev); 450 void mlx5_uninit_one_light(struct mlx5_core_dev *dev); 451 void mlx5_unload_one_light(struct mlx5_core_dev *dev); 452 453 void mlx5_query_nic_sw_system_image_guid(struct mlx5_core_dev *mdev, u8 *buf, 454 u8 *len); 455 bool mlx5_vport_use_vhca_id_as_func_id(struct mlx5_core_dev *dev, 456 u16 vport_num, u16 *vhca_id); 457 int mlx5_vport_set_other_func_cap(struct mlx5_core_dev *dev, const void *hca_cap, u16 vport, 458 u16 opmod); 459 #define mlx5_vport_get_other_func_general_cap(dev, vport, out) \ 460 mlx5_vport_get_other_func_cap(dev, vport, out, MLX5_CAP_GENERAL) 461 462 #define mlx5_vport_set_other_func_general_cap(dev, hca_cap, vport) \ 463 mlx5_vport_set_other_func_cap(dev, hca_cap, vport, \ 464 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE) 465 466 static inline u32 mlx5_sriov_get_vf_total_msix(struct pci_dev *pdev) 467 { 468 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 469 470 return MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix); 471 } 472 473 bool mlx5_eth_supported(struct mlx5_core_dev *dev); 474 bool mlx5_rdma_supported(struct mlx5_core_dev *dev); 475 bool mlx5_vnet_supported(struct mlx5_core_dev *dev); 476 bool mlx5_same_hw_devs(struct mlx5_core_dev *dev, struct mlx5_core_dev *peer_dev); 477 int mlx5_cmd_allow_other_vhca_access(struct mlx5_core_dev *dev, 478 struct mlx5_cmd_allow_other_vhca_access_attr *attr); 479 int mlx5_cmd_alias_obj_create(struct mlx5_core_dev *dev, 480 struct mlx5_cmd_alias_obj_create_attr *alias_attr, 481 u32 *obj_id); 482 int mlx5_cmd_alias_obj_destroy(struct mlx5_core_dev *dev, u32 obj_id, u16 obj_type); 483 484 static inline u16 mlx5_core_ec_vf_vport_base(const struct mlx5_core_dev *dev) 485 { 486 return MLX5_CAP_GEN_2(dev, ec_vf_vport_base); 487 } 488 489 static inline u16 mlx5_core_ec_sriov_enabled(const struct mlx5_core_dev *dev) 490 { 491 return mlx5_core_is_ecpf(dev) && mlx5_core_ec_vf_vport_base(dev); 492 } 493 494 static inline bool mlx5_core_is_ec_vf_vport(const struct mlx5_core_dev *dev, u16 vport_num) 495 { 496 int base_vport = mlx5_core_ec_vf_vport_base(dev); 497 int max_vport = base_vport + mlx5_core_max_ec_vfs(dev); 498 499 if (!mlx5_core_ec_sriov_enabled(dev)) 500 return false; 501 502 return (vport_num >= base_vport && vport_num < max_vport); 503 } 504 505 static inline int mlx5_vport_to_func_id(const struct mlx5_core_dev *dev, u16 vport, bool ec_vf_func) 506 { 507 return ec_vf_func ? vport - mlx5_core_ec_vf_vport_base(dev) + 1 508 : vport; 509 } 510 511 static inline int mlx5_max_eq_cap_get(const struct mlx5_core_dev *dev) 512 { 513 if (MLX5_CAP_GEN_2(dev, max_num_eqs_24b)) 514 return MLX5_CAP_GEN_2(dev, max_num_eqs_24b); 515 516 if (MLX5_CAP_GEN(dev, max_num_eqs)) 517 return MLX5_CAP_GEN(dev, max_num_eqs); 518 519 return 1 << MLX5_CAP_GEN(dev, log_max_eq); 520 } 521 522 static inline bool mlx5_pcie_cong_event_supported(struct mlx5_core_dev *dev) 523 { 524 u64 features = MLX5_CAP_GEN_2_64(dev, general_obj_types_127_64); 525 526 if (!(features & MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT)) 527 return false; 528 529 if (dev->sd) 530 return false; 531 532 return true; 533 } 534 #endif /* __MLX5_CORE_H__ */ 535