xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_HW_CATALOG_H
8 #define _DPU_HW_CATALOG_H
9 
10 #include <linux/kernel.h>
11 #include <linux/bug.h>
12 #include <linux/bitmap.h>
13 #include <linux/err.h>
14 
15 /**
16  * Max hardware block count: For ex: max 12 SSPP pipes or
17  * 5 ctl paths. In all cases, it can have max 12 hardware blocks
18  * based on current design
19  */
20 #define MAX_BLOCKS    12
21 
22 #define DPU_HW_BLK_NAME_LEN	16
23 
24 #define MAX_IMG_WIDTH 0x3fff
25 #define MAX_IMG_HEIGHT 0x3fff
26 
27 #define CRTC_DUAL_MIXERS	2
28 
29 #define MAX_XIN_COUNT 16
30 
31 /**
32  * MDP TOP BLOCK features
33  * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe
34  * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
35  * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results
36  *			   in a failure
37  * @DPU_MDP_VSYNC_SEL      Enables vsync source selection via MDP_VSYNC_SEL register
38  *                         (moved into INTF block since DPU 5.0.0)
39  * @DPU_MDP_MAX            Maximum value
40 
41  */
42 enum {
43 	DPU_MDP_PANIC_PER_PIPE = 0x1,
44 	DPU_MDP_10BIT_SUPPORT,
45 	DPU_MDP_AUDIO_SELECT,
46 	DPU_MDP_PERIPH_0_REMOVED,
47 	DPU_MDP_VSYNC_SEL,
48 	DPU_MDP_MAX
49 };
50 
51 /**
52  * SSPP sub-blocks/features
53  * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
54  * @DPU_SSPP_SCALER_QSEED3_COMPATIBLE,  QSEED3-compatible alogorithm support (includes QSEED3, QSEED3LITE and QSEED4)
55  * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
56  * @DPU_SSPP_CSC,            Support of Color space converion
57  * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
58  * @DPU_SSPP_CURSOR,         SSPP can be used as a cursor layer
59  * @DPU_SSPP_QOS,            SSPP support QoS control, danger/safe/creq
60  * @DPU_SSPP_QOS_8LVL,       SSPP support 8-level QoS control
61  * @DPU_SSPP_EXCL_RECT,      SSPP supports exclusion rect
62  * @DPU_SSPP_SMART_DMA_V1,   SmartDMA 1.0 support
63  * @DPU_SSPP_SMART_DMA_V2,   SmartDMA 2.0 support
64  * @DPU_SSPP_TS_PREFILL      Supports prefill with traffic shaper
65  * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
66  * @DPU_SSPP_CDP             Supports client driven prefetch
67  * @DPU_SSPP_INLINE_ROTATION Support inline rotation
68  * @DPU_SSPP_MAX             maximum value
69  */
70 enum {
71 	DPU_SSPP_SCALER_QSEED2 = 0x1,
72 	DPU_SSPP_SCALER_QSEED3_COMPATIBLE,
73 	DPU_SSPP_SCALER_RGB,
74 	DPU_SSPP_CSC,
75 	DPU_SSPP_CSC_10BIT,
76 	DPU_SSPP_CURSOR,
77 	DPU_SSPP_QOS,
78 	DPU_SSPP_QOS_8LVL,
79 	DPU_SSPP_EXCL_RECT,
80 	DPU_SSPP_SMART_DMA_V1,
81 	DPU_SSPP_SMART_DMA_V2,
82 	DPU_SSPP_TS_PREFILL,
83 	DPU_SSPP_TS_PREFILL_REC1,
84 	DPU_SSPP_CDP,
85 	DPU_SSPP_INLINE_ROTATION,
86 	DPU_SSPP_MAX
87 };
88 
89 /*
90  * MIXER sub-blocks/features
91  * @DPU_MIXER_LAYER           Layer mixer layer blend configuration,
92  * @DPU_MIXER_SOURCESPLIT     Layer mixer supports source-split configuration
93  * @DPU_MIXER_GC              Gamma correction block
94  * @DPU_DIM_LAYER             Layer mixer supports dim layer
95  * @DPU_MIXER_COMBINED_ALPHA  Layer mixer has combined alpha register
96  * @DPU_MIXER_MAX             maximum value
97  */
98 enum {
99 	DPU_MIXER_LAYER = 0x1,
100 	DPU_MIXER_SOURCESPLIT,
101 	DPU_MIXER_GC,
102 	DPU_DIM_LAYER,
103 	DPU_MIXER_COMBINED_ALPHA,
104 	DPU_MIXER_MAX
105 };
106 
107 /**
108  * DSPP sub-blocks
109  * @DPU_DSPP_PCC             Panel color correction block
110  */
111 enum {
112 	DPU_DSPP_PCC = 0x1,
113 	DPU_DSPP_MAX
114 };
115 
116 /**
117  * PINGPONG sub-blocks
118  * @DPU_PINGPONG_TE2        Additional tear check block for split pipes
119  * @DPU_PINGPONG_SPLIT      PP block supports split fifo
120  * @DPU_PINGPONG_SLAVE      PP block is a suitable slave for split fifo
121  * @DPU_PINGPONG_DITHER     Dither blocks
122  * @DPU_PINGPONG_DSC        PP block supports DSC
123  * @DPU_PINGPONG_MAX
124  */
125 enum {
126 	DPU_PINGPONG_TE2 = 0x1,
127 	DPU_PINGPONG_SPLIT,
128 	DPU_PINGPONG_SLAVE,
129 	DPU_PINGPONG_DITHER,
130 	DPU_PINGPONG_DSC,
131 	DPU_PINGPONG_MAX
132 };
133 
134 /**
135  * CTL sub-blocks
136  * @DPU_CTL_SPLIT_DISPLAY:	CTL supports video mode split display
137  * @DPU_CTL_FETCH_ACTIVE:	Active CTL for fetch HW (SSPPs)
138  * @DPU_CTL_VM_CFG:		CTL config to support multiple VMs
139  * @DPU_CTL_HAS_LAYER_EXT4:	CTL has the CTL_LAYER_EXT4 register
140  * @DPU_CTL_DSPP_BLOCK_FLUSH:	CTL config to support dspp sub-block flush
141  * @DPU_CTL_MAX
142  */
143 enum {
144 	DPU_CTL_SPLIT_DISPLAY = 0x1,
145 	DPU_CTL_ACTIVE_CFG,
146 	DPU_CTL_FETCH_ACTIVE,
147 	DPU_CTL_VM_CFG,
148 	DPU_CTL_HAS_LAYER_EXT4,
149 	DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
150 	DPU_CTL_MAX
151 };
152 
153 /**
154  * INTF sub-blocks
155  * @DPU_INTF_INPUT_CTRL             Supports the setting of pp block from which
156  *                                  pixel data arrives to this INTF
157  * @DPU_DATA_HCTL_EN                Allows data to be transferred at different rate
158  *                                  than video timing
159  * @DPU_INTF_STATUS_SUPPORTED       INTF block has INTF_STATUS register
160  * @DPU_INTF_MAX
161  */
162 enum {
163 	DPU_INTF_INPUT_CTRL = 0x1,
164 	DPU_DATA_HCTL_EN,
165 	DPU_INTF_STATUS_SUPPORTED,
166 	DPU_INTF_MAX
167 };
168 
169 /**
170   * WB sub-blocks and features
171   * @DPU_WB_LINE_MODE        Writeback module supports line/linear mode
172   * @DPU_WB_BLOCK_MODE       Writeback module supports block mode read
173   * @DPU_WB_CHROMA_DOWN,     Writeback chroma down block,
174   * @DPU_WB_DOWNSCALE,       Writeback integer downscaler,
175   * @DPU_WB_DITHER,          Dither block
176   * @DPU_WB_TRAFFIC_SHAPER,  Writeback traffic shaper bloc
177   * @DPU_WB_UBWC,            Writeback Universal bandwidth compression
178   * @DPU_WB_YUV_CONFIG       Writeback supports output of YUV colorspace
179   * @DPU_WB_PIPE_ALPHA       Writeback supports pipe alpha
180   * @DPU_WB_XY_ROI_OFFSET    Writeback supports x/y-offset of out ROI in
181   *                          the destination image
182   * @DPU_WB_QOS,             Writeback supports QoS control, danger/safe/creq
183   * @DPU_WB_QOS_8LVL,        Writeback supports 8-level QoS control
184   * @DPU_WB_CDP              Writeback supports client driven prefetch
185   * @DPU_WB_INPUT_CTRL       Writeback supports from which pp block input pixel
186   *                          data arrives.
187   * @DPU_WB_CROP             CWB supports cropping
188   * @DPU_WB_MAX              maximum value
189   */
190 enum {
191 	DPU_WB_LINE_MODE = 0x1,
192 	DPU_WB_BLOCK_MODE,
193 	DPU_WB_UBWC,
194 	DPU_WB_YUV_CONFIG,
195 	DPU_WB_PIPE_ALPHA,
196 	DPU_WB_XY_ROI_OFFSET,
197 	DPU_WB_QOS,
198 	DPU_WB_QOS_8LVL,
199 	DPU_WB_CDP,
200 	DPU_WB_INPUT_CTRL,
201 	DPU_WB_CROP,
202 	DPU_WB_MAX
203 };
204 
205 /**
206  * VBIF sub-blocks and features
207  * @DPU_VBIF_QOS_OTLIM        VBIF supports OT Limit
208  * @DPU_VBIF_QOS_REMAP        VBIF supports QoS priority remap
209  * @DPU_VBIF_MAX              maximum value
210  */
211 enum {
212 	DPU_VBIF_QOS_OTLIM = 0x1,
213 	DPU_VBIF_QOS_REMAP,
214 	DPU_VBIF_MAX
215 };
216 
217 /**
218  * DSC sub-blocks/features
219  * @DPU_DSC_OUTPUT_CTRL       Configure which PINGPONG block gets
220  *                            the pixel output from this DSC.
221  * @DPU_DSC_HW_REV_1_2        DSC block supports DSC 1.1 and 1.2
222  * @DPU_DSC_NATIVE_42x_EN     Supports NATIVE_422_EN and NATIVE_420_EN encoding
223  * @DPU_DSC_MAX
224  */
225 enum {
226 	DPU_DSC_OUTPUT_CTRL = 0x1,
227 	DPU_DSC_HW_REV_1_2,
228 	DPU_DSC_NATIVE_42x_EN,
229 	DPU_DSC_MAX
230 };
231 
232 /**
233  * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
234  * @name:              string name for debug purposes
235  * @id:                enum identifying this block
236  * @base:              register base offset to mdss
237  * @len:               length of hardware block
238  * @features           bit mask identifying sub-blocks/features
239  */
240 #define DPU_HW_BLK_INFO \
241 	char name[DPU_HW_BLK_NAME_LEN]; \
242 	u32 id; \
243 	u32 base; \
244 	u32 len; \
245 	unsigned long features
246 
247 /**
248  * struct dpu_scaler_blk: Scaler information
249  * @name: string name for debug purposes
250  * @base: offset of this sub-block relative to the block offset
251  * @len: register block length of this sub-block
252  * @version: qseed block revision, on QSEED3+ platforms this is the value of
253  *           scaler_blk.base + QSEED3_HW_VERSION registers.
254  */
255 struct dpu_scaler_blk {
256 	char name[DPU_HW_BLK_NAME_LEN];
257 	u32 base;
258 	u32 len;
259 	u32 version;
260 };
261 
262 struct dpu_csc_blk {
263 	char name[DPU_HW_BLK_NAME_LEN];
264 	u32 base;
265 	u32 len;
266 };
267 
268 /**
269  * struct dpu_pp_blk : Pixel processing sub-blk information
270  * @name: string name for debug purposes
271  * @base: offset of this sub-block relative to the block offset
272  * @len: register block length of this sub-block
273  * @version: HW Algorithm version
274  */
275 struct dpu_pp_blk {
276 	char name[DPU_HW_BLK_NAME_LEN];
277 	u32 base;
278 	u32 len;
279 	u32 version;
280 };
281 
282 /**
283  * struct dpu_dsc_blk - DSC Encoder sub-blk information
284  * @name: string name for debug purposes
285  * @base: offset of this sub-block relative to the block offset
286  * @len: register block length of this sub-block
287  */
288 struct dpu_dsc_blk {
289 	char name[DPU_HW_BLK_NAME_LEN];
290 	u32 base;
291 	u32 len;
292 };
293 
294 /**
295  * enum dpu_qos_lut_usage - define QoS LUT use cases
296  */
297 enum dpu_qos_lut_usage {
298 	DPU_QOS_LUT_USAGE_LINEAR,
299 	DPU_QOS_LUT_USAGE_MACROTILE,
300 	DPU_QOS_LUT_USAGE_NRT,
301 	DPU_QOS_LUT_USAGE_MAX,
302 };
303 
304 /**
305  * struct dpu_qos_lut_entry - define QoS LUT table entry
306  * @fl: fill level, or zero on last entry to indicate default lut
307  * @lut: lut to use if equal to or less than fill level
308  */
309 struct dpu_qos_lut_entry {
310 	u32 fl;
311 	u64 lut;
312 };
313 
314 /**
315  * struct dpu_qos_lut_tbl - define QoS LUT table
316  * @nentry: number of entry in this table
317  * @entries: Pointer to table entries
318  */
319 struct dpu_qos_lut_tbl {
320 	u32 nentry;
321 	const struct dpu_qos_lut_entry *entries;
322 };
323 
324 /**
325  * struct dpu_rotation_cfg - define inline rotation config
326  * @rot_maxheight: max pre rotated height allowed for rotation
327  * @rot_num_formats: number of elements in @rot_format_list
328  * @rot_format_list: list of supported rotator formats
329  */
330 struct dpu_rotation_cfg {
331 	u32 rot_maxheight;
332 	size_t rot_num_formats;
333 	const u32 *rot_format_list;
334 };
335 
336 /**
337  * struct dpu_caps - define DPU capabilities
338  * @max_mixer_width    max layer mixer line width support.
339  * @max_mixer_blendstages max layer mixer blend stages or
340  *                       supported z order
341  * @has_src_split      source split feature status
342  * @has_dim_layer      dim layer feature status
343  * @has_idle_pc        indicate if idle power collapse feature is supported
344  * @has_3d_merge       indicate if 3D merge is supported
345  * @max_linewidth      max linewidth for sspp
346  * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
347  * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
348  * @max_vdeci_exp      max vertical decimation supported (max is 2^value)
349  */
350 struct dpu_caps {
351 	u32 max_mixer_width;
352 	u32 max_mixer_blendstages;
353 	bool has_src_split;
354 	bool has_dim_layer;
355 	bool has_idle_pc;
356 	bool has_3d_merge;
357 	/* SSPP limits */
358 	u32 max_linewidth;
359 	u32 pixel_ram_size;
360 	u32 max_hdeci_exp;
361 	u32 max_vdeci_exp;
362 };
363 
364 /**
365  * struct dpu_sspp_sub_blks : SSPP sub-blocks
366  * common: Pointer to common configurations shared by sub blocks
367  * @maxdwnscale: max downscale ratio supported(without DECIMATION)
368  * @maxupscale:  maxupscale ratio supported
369  * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
370  * @qseed_ver: qseed version
371  * @scaler_blk:
372  * @csc_blk:
373  * @format_list: Pointer to list of supported formats
374  * @num_formats: Number of supported formats
375  * @virt_format_list: Pointer to list of supported formats for virtual planes
376  * @virt_num_formats: Number of supported formats for virtual planes
377  * @dpu_rotation_cfg: inline rotation configuration
378  */
379 struct dpu_sspp_sub_blks {
380 	u32 maxdwnscale;
381 	u32 maxupscale;
382 	u32 max_per_pipe_bw;
383 	u32 qseed_ver;
384 	struct dpu_scaler_blk scaler_blk;
385 	struct dpu_pp_blk csc_blk;
386 
387 	const u32 *format_list;
388 	u32 num_formats;
389 	const u32 *virt_format_list;
390 	u32 virt_num_formats;
391 	const struct dpu_rotation_cfg *rotation_cfg;
392 };
393 
394 /**
395  * struct dpu_lm_sub_blks:      information of mixer block
396  * @maxwidth:               Max pixel width supported by this mixer
397  * @maxblendstages:         Max number of blend-stages supported
398  * @blendstage_base:        Blend-stage register base offset
399  */
400 struct dpu_lm_sub_blks {
401 	u32 maxwidth;
402 	u32 maxblendstages;
403 	u32 blendstage_base[MAX_BLOCKS];
404 };
405 
406 /**
407  * struct dpu_dspp_sub_blks: Information of DSPP block
408  * @pcc: pixel color correction block
409  */
410 struct dpu_dspp_sub_blks {
411 	struct dpu_pp_blk pcc;
412 };
413 
414 struct dpu_pingpong_sub_blks {
415 	struct dpu_pp_blk te;
416 	struct dpu_pp_blk te2;
417 	struct dpu_pp_blk dither;
418 };
419 
420 /**
421  * struct dpu_dsc_sub_blks - DSC sub-blks
422  * @enc: DSC encoder sub-block
423  * @ctl: DSC controller sub-block
424  */
425 struct dpu_dsc_sub_blks {
426 	struct dpu_dsc_blk enc;
427 	struct dpu_dsc_blk ctl;
428 };
429 
430 /**
431  * dpu_clk_ctrl_type - Defines top level clock control signals
432  */
433 enum dpu_clk_ctrl_type {
434 	DPU_CLK_CTRL_NONE,
435 	DPU_CLK_CTRL_VIG0,
436 	DPU_CLK_CTRL_VIG1,
437 	DPU_CLK_CTRL_VIG2,
438 	DPU_CLK_CTRL_VIG3,
439 	DPU_CLK_CTRL_VIG4,
440 	DPU_CLK_CTRL_RGB0,
441 	DPU_CLK_CTRL_RGB1,
442 	DPU_CLK_CTRL_RGB2,
443 	DPU_CLK_CTRL_RGB3,
444 	DPU_CLK_CTRL_DMA0,
445 	DPU_CLK_CTRL_DMA1,
446 	DPU_CLK_CTRL_DMA2,
447 	DPU_CLK_CTRL_DMA3,
448 	DPU_CLK_CTRL_DMA4,
449 	DPU_CLK_CTRL_DMA5,
450 	DPU_CLK_CTRL_CURSOR0,
451 	DPU_CLK_CTRL_CURSOR1,
452 	DPU_CLK_CTRL_INLINE_ROT0_SSPP,
453 	DPU_CLK_CTRL_REG_DMA,
454 	DPU_CLK_CTRL_WB2,
455 	DPU_CLK_CTRL_MAX,
456 };
457 
458 /* struct dpu_clk_ctrl_reg : Clock control register
459  * @reg_off:           register offset
460  * @bit_off:           bit offset
461  */
462 struct dpu_clk_ctrl_reg {
463 	u32 reg_off;
464 	u32 bit_off;
465 };
466 
467 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
468  * @id:                index identifying this block
469  * @base:              register base offset to mdss
470  * @features           bit mask identifying sub-blocks/features
471  * @clk_ctrls          clock control register definition
472  */
473 struct dpu_mdp_cfg {
474 	DPU_HW_BLK_INFO;
475 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
476 };
477 
478 /* struct dpu_ctl_cfg : MDP CTL instance info
479  * @id:                index identifying this block
480  * @base:              register base offset to mdss
481  * @features           bit mask identifying sub-blocks/features
482  * @intr_start:        interrupt index for CTL_START
483  */
484 struct dpu_ctl_cfg {
485 	DPU_HW_BLK_INFO;
486 	unsigned int intr_start;
487 };
488 
489 /**
490  * struct dpu_sspp_cfg - information of source pipes
491  * @id:                index identifying this block
492  * @base               register offset of this block
493  * @features           bit mask identifying sub-blocks/features
494  * @sblk:              SSPP sub-blocks information
495  * @xin_id:            bus client identifier
496  * @clk_ctrl           clock control identifier
497  * @type               sspp type identifier
498  */
499 struct dpu_sspp_cfg {
500 	DPU_HW_BLK_INFO;
501 	const struct dpu_sspp_sub_blks *sblk;
502 	u32 xin_id;
503 	enum dpu_clk_ctrl_type clk_ctrl;
504 	u32 type;
505 };
506 
507 /**
508  * struct dpu_lm_cfg - information of layer mixer blocks
509  * @id:                index identifying this block
510  * @base               register offset of this block
511  * @features           bit mask identifying sub-blocks/features
512  * @sblk:              LM Sub-blocks information
513  * @pingpong:          ID of connected PingPong, PINGPONG_NONE if unsupported
514  * @lm_pair:           ID of LM that can be controlled by same CTL
515  */
516 struct dpu_lm_cfg {
517 	DPU_HW_BLK_INFO;
518 	const struct dpu_lm_sub_blks *sblk;
519 	u32 pingpong;
520 	u32 dspp;
521 	unsigned long lm_pair;
522 };
523 
524 /**
525  * struct dpu_dspp_cfg - information of DSPP blocks
526  * @id                 enum identifying this block
527  * @base               register offset of this block
528  * @features           bit mask identifying sub-blocks/features
529  *                     supported by this block
530  * @sblk               sub-blocks information
531  */
532 struct dpu_dspp_cfg  {
533 	DPU_HW_BLK_INFO;
534 	const struct dpu_dspp_sub_blks *sblk;
535 };
536 
537 /**
538  * struct dpu_pingpong_cfg - information of PING-PONG blocks
539  * @id                 enum identifying this block
540  * @base               register offset of this block
541  * @features           bit mask identifying sub-blocks/features
542  * @intr_done:         index for PINGPONG done interrupt
543  * @intr_rdptr:        index for PINGPONG readpointer done interrupt
544  * @sblk               sub-blocks information
545  */
546 struct dpu_pingpong_cfg  {
547 	DPU_HW_BLK_INFO;
548 	u32 merge_3d;
549 	unsigned int intr_done;
550 	unsigned int intr_rdptr;
551 	const struct dpu_pingpong_sub_blks *sblk;
552 };
553 
554 /**
555  * struct dpu_merge_3d_cfg - information of DSPP blocks
556  * @id                 enum identifying this block
557  * @base               register offset of this block
558  * @features           bit mask identifying sub-blocks/features
559  *                     supported by this block
560  * @sblk               sub-blocks information
561  */
562 struct dpu_merge_3d_cfg  {
563 	DPU_HW_BLK_INFO;
564 	const struct dpu_merge_3d_sub_blks *sblk;
565 };
566 
567 /**
568  * struct dpu_dsc_cfg - information of DSC blocks
569  * @id                 enum identifying this block
570  * @base               register offset of this block
571  * @len:               length of hardware block
572  * @features           bit mask identifying sub-blocks/features
573  * @sblk:              sub-blocks information
574  */
575 struct dpu_dsc_cfg {
576 	DPU_HW_BLK_INFO;
577 	const struct dpu_dsc_sub_blks *sblk;
578 };
579 
580 /**
581  * struct dpu_intf_cfg - information of timing engine blocks
582  * @id                 enum identifying this block
583  * @base               register offset of this block
584  * @features           bit mask identifying sub-blocks/features
585  * @type:              Interface type(DSI, DP, HDMI)
586  * @controller_id:     Controller Instance ID in case of multiple of intf type
587  * @prog_fetch_lines_worst_case	Worst case latency num lines needed to prefetch
588  * @intr_underrun:	index for INTF underrun interrupt
589  * @intr_vsync:	        index for INTF VSYNC interrupt
590  * @intr_tear_rd_ptr:  Index for INTF TEAR_RD_PTR interrupt
591  */
592 struct dpu_intf_cfg  {
593 	DPU_HW_BLK_INFO;
594 	u32 type;   /* interface type*/
595 	u32 controller_id;
596 	u32 prog_fetch_lines_worst_case;
597 	unsigned int intr_underrun;
598 	unsigned int intr_vsync;
599 	unsigned int intr_tear_rd_ptr;
600 };
601 
602 /**
603  * struct dpu_wb_cfg - information of writeback blocks
604  * @DPU_HW_BLK_INFO:    refer to the description above for DPU_HW_BLK_INFO
605  * @vbif_idx:           vbif client index
606  * @maxlinewidth:       max line width supported by writeback block
607  * @xin_id:             bus client identifier
608  * @intr_wb_done:       interrupt index for WB_DONE
609  * @format_list:	    list of formats supported by this writeback block
610  * @num_formats:	    number of formats supported by this writeback block
611  * @clk_ctrl:	        clock control identifier
612  */
613 struct dpu_wb_cfg {
614 	DPU_HW_BLK_INFO;
615 	u8 vbif_idx;
616 	u32 maxlinewidth;
617 	u32 xin_id;
618 	unsigned int intr_wb_done;
619 	const u32 *format_list;
620 	u32 num_formats;
621 	enum dpu_clk_ctrl_type clk_ctrl;
622 };
623 
624 /**
625  * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
626  * @pps                pixel per seconds
627  * @ot_limit           OT limit to use up to specified pixel per second
628  */
629 struct dpu_vbif_dynamic_ot_cfg {
630 	u64 pps;
631 	u32 ot_limit;
632 };
633 
634 /**
635  * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table
636  * @count              length of cfg
637  * @cfg                pointer to array of configuration settings with
638  *                     ascending requirements
639  */
640 struct dpu_vbif_dynamic_ot_tbl {
641 	u32 count;
642 	const struct dpu_vbif_dynamic_ot_cfg *cfg;
643 };
644 
645 /**
646  * struct dpu_vbif_qos_tbl - QoS priority table
647  * @npriority_lvl      num of priority level
648  * @priority_lvl       pointer to array of priority level in ascending order
649  */
650 struct dpu_vbif_qos_tbl {
651 	u32 npriority_lvl;
652 	const u32 *priority_lvl;
653 };
654 
655 /**
656  * struct dpu_vbif_cfg - information of VBIF blocks
657  * @id                 enum identifying this block
658  * @base               register offset of this block
659  * @features           bit mask identifying sub-blocks/features
660  * @ot_rd_limit        default OT read limit
661  * @ot_wr_limit        default OT write limit
662  * @xin_halt_timeout   maximum time (in usec) for xin to halt
663  * @qos_rp_remap_size  size of VBIF_XINL_QOS_RP_REMAP register space
664  * @dynamic_ot_rd_tbl  dynamic OT read configuration table
665  * @dynamic_ot_wr_tbl  dynamic OT write configuration table
666  * @qos_rt_tbl         real-time QoS priority table
667  * @qos_nrt_tbl        non-real-time QoS priority table
668  * @memtype_count      number of defined memtypes
669  * @memtype            array of xin memtype definitions
670  */
671 struct dpu_vbif_cfg {
672 	DPU_HW_BLK_INFO;
673 	u32 default_ot_rd_limit;
674 	u32 default_ot_wr_limit;
675 	u32 xin_halt_timeout;
676 	u32 qos_rp_remap_size;
677 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
678 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
679 	struct dpu_vbif_qos_tbl qos_rt_tbl;
680 	struct dpu_vbif_qos_tbl qos_nrt_tbl;
681 	u32 memtype_count;
682 	u32 memtype[MAX_XIN_COUNT];
683 };
684 
685 /**
686  * struct dpu_cdm_cfg - information of chroma down blocks
687  * @name               string name for debug purposes
688  * @id                 enum identifying this block
689  * @base               register offset of this block
690  * @features           bit mask identifying sub-blocks/features
691  */
692 struct dpu_cdm_cfg {
693 	DPU_HW_BLK_INFO;
694 };
695 
696 /**
697  * Define CDP use cases
698  * @DPU_PERF_CDP_UDAGE_RT: real-time use cases
699  * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
700  */
701 enum {
702 	DPU_PERF_CDP_USAGE_RT,
703 	DPU_PERF_CDP_USAGE_NRT,
704 	DPU_PERF_CDP_USAGE_MAX
705 };
706 
707 /**
708  * struct dpu_perf_cdp_cfg - define CDP use case configuration
709  * @rd_enable: true if read pipe CDP is enabled
710  * @wr_enable: true if write pipe CDP is enabled
711  */
712 struct dpu_perf_cdp_cfg {
713 	bool rd_enable;
714 	bool wr_enable;
715 };
716 
717 /**
718  * struct dpu_mdss_version - DPU's major and minor versions
719  * @core_major_ver: DPU core's major version
720  * @core_minor_ver: DPU core's minor version
721  */
722 struct dpu_mdss_version {
723 	u8 core_major_ver;
724 	u8 core_minor_ver;
725 };
726 
727 /**
728  * struct dpu_perf_cfg - performance control settings
729  * @max_bw_low         low threshold of maximum bandwidth (kbps)
730  * @max_bw_high        high threshold of maximum bandwidth (kbps)
731  * @min_core_ib        minimum bandwidth for core (kbps)
732  * @min_core_ib        minimum mnoc ib vote in kbps
733  * @min_llcc_ib        minimum llcc ib vote in kbps
734  * @min_dram_ib        minimum dram ib vote in kbps
735  * @undersized_prefill_lines   undersized prefill in lines
736  * @xtra_prefill_lines         extra prefill latency in lines
737  * @dest_scale_prefill_lines   destination scaler latency in lines
738  * @macrotile_perfill_lines    macrotile latency in lines
739  * @yuv_nv12_prefill_lines     yuv_nv12 latency in lines
740  * @linear_prefill_lines       linear latency in lines
741  * @downscaling_prefill_lines  downscaling latency in lines
742  * @amortizable_theshold minimum y position for traffic shaping prefill
743  * @min_prefill_lines  minimum pipeline latency in lines
744  * @clk_inefficiency_factor DPU src clock inefficiency factor
745  * @bw_inefficiency_factor DPU axi bus bw inefficiency factor
746  * @safe_lut_tbl: LUT tables for safe signals
747  * @danger_lut_tbl: LUT tables for danger signals
748  * @qos_lut_tbl: LUT tables for QoS signals
749  * @cdp_cfg            cdp use case configurations
750  */
751 struct dpu_perf_cfg {
752 	u32 max_bw_low;
753 	u32 max_bw_high;
754 	u32 min_core_ib;
755 	u32 min_llcc_ib;
756 	u32 min_dram_ib;
757 	u32 undersized_prefill_lines;
758 	u32 xtra_prefill_lines;
759 	u32 dest_scale_prefill_lines;
760 	u32 macrotile_prefill_lines;
761 	u32 yuv_nv12_prefill_lines;
762 	u32 linear_prefill_lines;
763 	u32 downscaling_prefill_lines;
764 	u32 amortizable_threshold;
765 	u32 min_prefill_lines;
766 	u32 clk_inefficiency_factor;
767 	u32 bw_inefficiency_factor;
768 	u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
769 	u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
770 	struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
771 	struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
772 };
773 
774 /**
775  * struct dpu_mdss_cfg - information of MDSS HW
776  * This is the main catalog data structure representing
777  * this HW version. Contains dpu's major and minor versions,
778  * number of instances, register offsets, capabilities of the
779  * all MDSS HW sub-blocks.
780  *
781  * @dma_formats        Supported formats for dma pipe
782  * @cursor_formats     Supported formats for cursor pipe
783  * @vig_formats        Supported formats for vig pipe
784  */
785 struct dpu_mdss_cfg {
786 	const struct dpu_mdss_version *mdss_ver;
787 
788 	const struct dpu_caps *caps;
789 
790 	const struct dpu_mdp_cfg *mdp;
791 
792 	u32 ctl_count;
793 	const struct dpu_ctl_cfg *ctl;
794 
795 	u32 sspp_count;
796 	const struct dpu_sspp_cfg *sspp;
797 
798 	u32 mixer_count;
799 	const struct dpu_lm_cfg *mixer;
800 
801 	u32 pingpong_count;
802 	const struct dpu_pingpong_cfg *pingpong;
803 
804 	u32 merge_3d_count;
805 	const struct dpu_merge_3d_cfg *merge_3d;
806 
807 	u32 dsc_count;
808 	const struct dpu_dsc_cfg *dsc;
809 
810 	u32 intf_count;
811 	const struct dpu_intf_cfg *intf;
812 
813 	u32 vbif_count;
814 	const struct dpu_vbif_cfg *vbif;
815 
816 	u32 wb_count;
817 	const struct dpu_wb_cfg *wb;
818 
819 	const struct dpu_cdm_cfg *cdm;
820 
821 	u32 ad_count;
822 
823 	u32 dspp_count;
824 	const struct dpu_dspp_cfg *dspp;
825 
826 	/* Add additional block data structures here */
827 
828 	const struct dpu_perf_cfg *perf;
829 	const struct dpu_format_extended *dma_formats;
830 	const struct dpu_format_extended *cursor_formats;
831 	const struct dpu_format_extended *vig_formats;
832 };
833 
834 extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
835 extern const struct dpu_mdss_cfg dpu_sdm630_cfg;
836 extern const struct dpu_mdss_cfg dpu_sdm660_cfg;
837 extern const struct dpu_mdss_cfg dpu_sdm845_cfg;
838 extern const struct dpu_mdss_cfg dpu_sdm670_cfg;
839 extern const struct dpu_mdss_cfg dpu_sm8150_cfg;
840 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
841 extern const struct dpu_mdss_cfg dpu_sm7150_cfg;
842 extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
843 extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
844 extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
845 extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
846 extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
847 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
848 extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
849 extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
850 extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
851 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
852 extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
853 extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
854 extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
855 extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
856 
857 #endif /* _DPU_HW_CATALOG_H */
858