1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_BLK_NAME_LEN 16 23 24 #define DPU_MAX_IMG_WIDTH 0x3fff 25 #define DPU_MAX_IMG_HEIGHT 0x3fff 26 27 #define CRTC_QUAD_MIXERS 4 28 29 #define MAX_XIN_COUNT 16 30 31 /** 32 * SSPP sub-blocks/features 33 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 34 * @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEED3LITE and QSEED4) 35 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 36 * @DPU_SSPP_CSC, Support of Color space converion 37 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 38 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 39 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 40 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 41 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 42 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 43 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 44 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 45 * @DPU_SSPP_CDP Supports client driven prefetch 46 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 47 * @DPU_SSPP_MAX maximum value 48 */ 49 enum { 50 DPU_SSPP_SCALER_QSEED2 = 0x1, 51 DPU_SSPP_SCALER_QSEED3_COMPATIBLE, 52 DPU_SSPP_SCALER_RGB, 53 DPU_SSPP_CSC, 54 DPU_SSPP_CSC_10BIT, 55 DPU_SSPP_CURSOR, 56 DPU_SSPP_QOS, 57 DPU_SSPP_EXCL_RECT, 58 DPU_SSPP_SMART_DMA_V1, 59 DPU_SSPP_SMART_DMA_V2, 60 DPU_SSPP_TS_PREFILL, 61 DPU_SSPP_TS_PREFILL_REC1, 62 DPU_SSPP_CDP, 63 DPU_SSPP_INLINE_ROTATION, 64 DPU_SSPP_MAX 65 }; 66 67 /* 68 * MIXER sub-blocks/features 69 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 70 * @DPU_MIXER_MAX maximum value 71 */ 72 enum { 73 DPU_MIXER_SOURCESPLIT = 0x1, 74 DPU_MIXER_MAX, 75 }; 76 77 /** 78 * DSPP sub-blocks 79 * @DPU_DSPP_PCC Panel color correction block 80 */ 81 enum { 82 DPU_DSPP_PCC = 0x1, 83 DPU_DSPP_MAX 84 }; 85 86 /** 87 * CTL sub-blocks 88 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 89 * @DPU_CTL_MAX 90 */ 91 enum { 92 DPU_CTL_SPLIT_DISPLAY = 0x1, 93 DPU_CTL_MAX 94 }; 95 96 /** 97 * WB sub-blocks and features 98 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 99 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 100 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 101 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 102 * @DPU_WB_DITHER, Dither block 103 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 104 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 105 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 106 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 107 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 108 * the destination image 109 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 110 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 111 * @DPU_WB_CDP Writeback supports client driven prefetch 112 * @DPU_WB_CROP CWB supports cropping 113 * @DPU_WB_MAX maximum value 114 */ 115 enum { 116 DPU_WB_LINE_MODE = 0x1, 117 DPU_WB_BLOCK_MODE, 118 DPU_WB_UBWC, 119 DPU_WB_YUV_CONFIG, 120 DPU_WB_PIPE_ALPHA, 121 DPU_WB_XY_ROI_OFFSET, 122 DPU_WB_QOS, 123 DPU_WB_QOS_8LVL, 124 DPU_WB_CDP, 125 DPU_WB_CROP, 126 DPU_WB_MAX 127 }; 128 129 /** 130 * VBIF sub-blocks and features 131 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 132 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 133 * @DPU_VBIF_MAX maximum value 134 */ 135 enum { 136 DPU_VBIF_QOS_OTLIM = 0x1, 137 DPU_VBIF_QOS_REMAP, 138 DPU_VBIF_MAX 139 }; 140 141 /** 142 * DSC sub-blocks/features 143 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding 144 * @DPU_DSC_MAX 145 */ 146 enum { 147 DPU_DSC_NATIVE_42x_EN = 0x1, 148 DPU_DSC_MAX 149 }; 150 151 /** 152 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 153 * @name: string name for debug purposes 154 * @id: enum identifying this block 155 * @base: register base offset to mdss 156 * @len: length of hardware block 157 */ 158 #define DPU_HW_BLK_INFO \ 159 char name[DPU_HW_BLK_NAME_LEN]; \ 160 u32 id; \ 161 u32 base; \ 162 u32 len 163 164 /** 165 * struct dpu_scaler_blk: Scaler information 166 * @name: string name for debug purposes 167 * @base: offset of this sub-block relative to the block offset 168 * @len: register block length of this sub-block 169 * @version: qseed block revision, on QSEED3+ platforms this is the value of 170 * scaler_blk.base + QSEED3_HW_VERSION registers. 171 */ 172 struct dpu_scaler_blk { 173 char name[DPU_HW_BLK_NAME_LEN]; 174 u32 base; 175 u32 len; 176 u32 version; 177 }; 178 179 struct dpu_csc_blk { 180 char name[DPU_HW_BLK_NAME_LEN]; 181 u32 base; 182 u32 len; 183 }; 184 185 /** 186 * struct dpu_pp_blk : Pixel processing sub-blk information 187 * @name: string name for debug purposes 188 * @base: offset of this sub-block relative to the block offset 189 * @len: register block length of this sub-block 190 * @version: HW Algorithm version 191 */ 192 struct dpu_pp_blk { 193 char name[DPU_HW_BLK_NAME_LEN]; 194 u32 base; 195 u32 len; 196 u32 version; 197 }; 198 199 /** 200 * struct dpu_dsc_blk - DSC Encoder sub-blk information 201 * @name: string name for debug purposes 202 * @base: offset of this sub-block relative to the block offset 203 * @len: register block length of this sub-block 204 */ 205 struct dpu_dsc_blk { 206 char name[DPU_HW_BLK_NAME_LEN]; 207 u32 base; 208 u32 len; 209 }; 210 211 /** 212 * enum dpu_qos_lut_usage - define QoS LUT use cases 213 */ 214 enum dpu_qos_lut_usage { 215 DPU_QOS_LUT_USAGE_LINEAR, 216 DPU_QOS_LUT_USAGE_MACROTILE, 217 DPU_QOS_LUT_USAGE_NRT, 218 DPU_QOS_LUT_USAGE_MAX, 219 }; 220 221 /** 222 * struct dpu_qos_lut_entry - define QoS LUT table entry 223 * @fl: fill level, or zero on last entry to indicate default lut 224 * @lut: lut to use if equal to or less than fill level 225 */ 226 struct dpu_qos_lut_entry { 227 u32 fl; 228 u64 lut; 229 }; 230 231 /** 232 * struct dpu_qos_lut_tbl - define QoS LUT table 233 * @nentry: number of entry in this table 234 * @entries: Pointer to table entries 235 */ 236 struct dpu_qos_lut_tbl { 237 u32 nentry; 238 const struct dpu_qos_lut_entry *entries; 239 }; 240 241 /** 242 * struct dpu_rotation_cfg - define inline rotation config 243 * @rot_maxheight: max pre rotated height allowed for rotation 244 * @rot_num_formats: number of elements in @rot_format_list 245 * @rot_format_list: list of supported rotator formats 246 */ 247 struct dpu_rotation_cfg { 248 u32 rot_maxheight; 249 size_t rot_num_formats; 250 const u32 *rot_format_list; 251 }; 252 253 /** 254 * struct dpu_caps - define DPU capabilities 255 * @max_mixer_width max layer mixer line width support. 256 * @max_mixer_blendstages max layer mixer blend stages or 257 * supported z order 258 * @has_src_split source split feature status 259 * @has_dim_layer dim layer feature status 260 * @has_idle_pc indicate if idle power collapse feature is supported 261 * @has_3d_merge indicate if 3D merge is supported 262 * @max_linewidth max linewidth for sspp 263 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 264 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 265 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 266 */ 267 struct dpu_caps { 268 u32 max_mixer_width; 269 u32 max_mixer_blendstages; 270 bool has_src_split; 271 bool has_dim_layer; 272 bool has_idle_pc; 273 bool has_3d_merge; 274 /* SSPP limits */ 275 u32 max_linewidth; 276 u32 pixel_ram_size; 277 u32 max_hdeci_exp; 278 u32 max_vdeci_exp; 279 }; 280 281 /** 282 * struct dpu_sspp_sub_blks : SSPP sub-blocks 283 * common: Pointer to common configurations shared by sub blocks 284 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 285 * @qseed_ver: qseed version 286 * @scaler_blk: 287 * @csc_blk: 288 * @format_list: Pointer to list of supported formats 289 * @num_formats: Number of supported formats 290 * @dpu_rotation_cfg: inline rotation configuration 291 */ 292 struct dpu_sspp_sub_blks { 293 u32 max_per_pipe_bw; 294 u32 qseed_ver; 295 struct dpu_scaler_blk scaler_blk; 296 struct dpu_pp_blk csc_blk; 297 298 const u32 *format_list; 299 u32 num_formats; 300 const struct dpu_rotation_cfg *rotation_cfg; 301 }; 302 303 /** 304 * struct dpu_lm_sub_blks: information of mixer block 305 * @maxwidth: Max pixel width supported by this mixer 306 * @maxblendstages: Max number of blend-stages supported 307 * @blendstage_base: Blend-stage register base offset 308 */ 309 struct dpu_lm_sub_blks { 310 u32 maxblendstages; 311 u32 blendstage_base[MAX_BLOCKS]; 312 }; 313 314 /** 315 * struct dpu_dspp_sub_blks: Information of DSPP block 316 * @pcc: pixel color correction block 317 */ 318 struct dpu_dspp_sub_blks { 319 struct dpu_pp_blk pcc; 320 }; 321 322 struct dpu_pingpong_sub_blks { 323 struct dpu_pp_blk dither; 324 }; 325 326 /** 327 * struct dpu_dsc_sub_blks - DSC sub-blks 328 * @enc: DSC encoder sub-block 329 * @ctl: DSC controller sub-block 330 */ 331 struct dpu_dsc_sub_blks { 332 struct dpu_dsc_blk enc; 333 struct dpu_dsc_blk ctl; 334 }; 335 336 /** 337 * dpu_clk_ctrl_type - Defines top level clock control signals 338 */ 339 enum dpu_clk_ctrl_type { 340 DPU_CLK_CTRL_NONE, 341 DPU_CLK_CTRL_VIG0, 342 DPU_CLK_CTRL_VIG1, 343 DPU_CLK_CTRL_VIG2, 344 DPU_CLK_CTRL_VIG3, 345 DPU_CLK_CTRL_VIG4, 346 DPU_CLK_CTRL_RGB0, 347 DPU_CLK_CTRL_RGB1, 348 DPU_CLK_CTRL_RGB2, 349 DPU_CLK_CTRL_RGB3, 350 DPU_CLK_CTRL_DMA0, 351 DPU_CLK_CTRL_DMA1, 352 DPU_CLK_CTRL_DMA2, 353 DPU_CLK_CTRL_DMA3, 354 DPU_CLK_CTRL_DMA4, 355 DPU_CLK_CTRL_DMA5, 356 DPU_CLK_CTRL_CURSOR0, 357 DPU_CLK_CTRL_CURSOR1, 358 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 359 DPU_CLK_CTRL_REG_DMA, 360 DPU_CLK_CTRL_WB2, 361 DPU_CLK_CTRL_MAX, 362 }; 363 364 /* struct dpu_clk_ctrl_reg : Clock control register 365 * @reg_off: register offset 366 * @bit_off: bit offset 367 */ 368 struct dpu_clk_ctrl_reg { 369 u32 reg_off; 370 u32 bit_off; 371 }; 372 373 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 374 * @id: index identifying this block 375 * @base: register base offset to mdss 376 * @clk_ctrls clock control register definition 377 */ 378 struct dpu_mdp_cfg { 379 DPU_HW_BLK_INFO; 380 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 381 }; 382 383 /* struct dpu_ctl_cfg : MDP CTL instance info 384 * @id: index identifying this block 385 * @base: register base offset to mdss 386 * @features bit mask identifying sub-blocks/features 387 * @intr_start: interrupt index for CTL_START 388 */ 389 struct dpu_ctl_cfg { 390 DPU_HW_BLK_INFO; 391 unsigned long features; 392 unsigned int intr_start; 393 }; 394 395 /** 396 * struct dpu_sspp_cfg - information of source pipes 397 * @id: index identifying this block 398 * @base register offset of this block 399 * @features bit mask identifying sub-blocks/features 400 * @sblk: SSPP sub-blocks information 401 * @xin_id: bus client identifier 402 * @clk_ctrl clock control identifier 403 * @type sspp type identifier 404 */ 405 struct dpu_sspp_cfg { 406 DPU_HW_BLK_INFO; 407 unsigned long features; 408 const struct dpu_sspp_sub_blks *sblk; 409 u32 xin_id; 410 enum dpu_clk_ctrl_type clk_ctrl; 411 u32 type; 412 }; 413 414 /** 415 * struct dpu_lm_cfg - information of layer mixer blocks 416 * @id: index identifying this block 417 * @base register offset of this block 418 * @features bit mask identifying sub-blocks/features 419 * @sblk: LM Sub-blocks information 420 * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported 421 * @lm_pair: ID of LM that can be controlled by same CTL 422 */ 423 struct dpu_lm_cfg { 424 DPU_HW_BLK_INFO; 425 unsigned long features; 426 const struct dpu_lm_sub_blks *sblk; 427 u32 pingpong; 428 u32 dspp; 429 unsigned long lm_pair; 430 }; 431 432 /** 433 * struct dpu_dspp_cfg - information of DSPP blocks 434 * @id enum identifying this block 435 * @base register offset of this block 436 * supported by this block 437 * @sblk sub-blocks information 438 */ 439 struct dpu_dspp_cfg { 440 DPU_HW_BLK_INFO; 441 const struct dpu_dspp_sub_blks *sblk; 442 }; 443 444 /** 445 * struct dpu_pingpong_cfg - information of PING-PONG blocks 446 * @id enum identifying this block 447 * @base register offset of this block 448 * @intr_done: index for PINGPONG done interrupt 449 * @intr_rdptr: index for PINGPONG readpointer done interrupt 450 * @sblk sub-blocks information 451 */ 452 struct dpu_pingpong_cfg { 453 DPU_HW_BLK_INFO; 454 u32 merge_3d; 455 unsigned int intr_done; 456 unsigned int intr_rdptr; 457 const struct dpu_pingpong_sub_blks *sblk; 458 }; 459 460 /** 461 * struct dpu_merge_3d_cfg - information of DSPP blocks 462 * @id enum identifying this block 463 * @base register offset of this block 464 * @sblk sub-blocks information 465 */ 466 struct dpu_merge_3d_cfg { 467 DPU_HW_BLK_INFO; 468 const struct dpu_merge_3d_sub_blks *sblk; 469 }; 470 471 /** 472 * struct dpu_dsc_cfg - information of DSC blocks 473 * @id enum identifying this block 474 * @base register offset of this block 475 * @len: length of hardware block 476 * @features bit mask identifying sub-blocks/features 477 * @sblk: sub-blocks information 478 */ 479 struct dpu_dsc_cfg { 480 DPU_HW_BLK_INFO; 481 unsigned long features; 482 const struct dpu_dsc_sub_blks *sblk; 483 }; 484 485 /** 486 * struct dpu_intf_cfg - information of timing engine blocks 487 * @id enum identifying this block 488 * @base register offset of this block 489 * @type: Interface type(DSI, DP, HDMI) 490 * @controller_id: Controller Instance ID in case of multiple of intf type 491 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 492 * @intr_underrun: index for INTF underrun interrupt 493 * @intr_vsync: index for INTF VSYNC interrupt 494 * @intr_tear_rd_ptr: Index for INTF TEAR_RD_PTR interrupt 495 */ 496 struct dpu_intf_cfg { 497 DPU_HW_BLK_INFO; 498 u32 type; /* interface type*/ 499 u32 controller_id; 500 u32 prog_fetch_lines_worst_case; 501 unsigned int intr_underrun; 502 unsigned int intr_vsync; 503 unsigned int intr_tear_rd_ptr; 504 }; 505 506 /** 507 * struct dpu_wb_cfg - information of writeback blocks 508 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 509 * @vbif_idx: vbif client index 510 * @maxlinewidth: max line width supported by writeback block 511 * @xin_id: bus client identifier 512 * @intr_wb_done: interrupt index for WB_DONE 513 * @format_list: list of formats supported by this writeback block 514 * @num_formats: number of formats supported by this writeback block 515 * @clk_ctrl: clock control identifier 516 */ 517 struct dpu_wb_cfg { 518 DPU_HW_BLK_INFO; 519 unsigned long features; 520 u8 vbif_idx; 521 u32 maxlinewidth; 522 u32 xin_id; 523 unsigned int intr_wb_done; 524 const u32 *format_list; 525 u32 num_formats; 526 enum dpu_clk_ctrl_type clk_ctrl; 527 }; 528 529 /* 530 * struct dpu_cwb_cfg : MDP CWB mux instance info 531 * @id: enum identifying this block 532 * @base: register base offset to mdss 533 * @features bit mask identifying sub-blocks/features 534 */ 535 struct dpu_cwb_cfg { 536 DPU_HW_BLK_INFO; 537 }; 538 539 /** 540 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 541 * @pps pixel per seconds 542 * @ot_limit OT limit to use up to specified pixel per second 543 */ 544 struct dpu_vbif_dynamic_ot_cfg { 545 u64 pps; 546 u32 ot_limit; 547 }; 548 549 /** 550 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 551 * @count length of cfg 552 * @cfg pointer to array of configuration settings with 553 * ascending requirements 554 */ 555 struct dpu_vbif_dynamic_ot_tbl { 556 u32 count; 557 const struct dpu_vbif_dynamic_ot_cfg *cfg; 558 }; 559 560 /** 561 * struct dpu_vbif_qos_tbl - QoS priority table 562 * @npriority_lvl num of priority level 563 * @priority_lvl pointer to array of priority level in ascending order 564 */ 565 struct dpu_vbif_qos_tbl { 566 u32 npriority_lvl; 567 const u32 *priority_lvl; 568 }; 569 570 /** 571 * struct dpu_vbif_cfg - information of VBIF blocks 572 * @id enum identifying this block 573 * @base register offset of this block 574 * @features bit mask identifying sub-blocks/features 575 * @ot_rd_limit default OT read limit 576 * @ot_wr_limit default OT write limit 577 * @xin_halt_timeout maximum time (in usec) for xin to halt 578 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 579 * @dynamic_ot_rd_tbl dynamic OT read configuration table 580 * @dynamic_ot_wr_tbl dynamic OT write configuration table 581 * @qos_rt_tbl real-time QoS priority table 582 * @qos_nrt_tbl non-real-time QoS priority table 583 * @memtype_count number of defined memtypes 584 * @memtype array of xin memtype definitions 585 */ 586 struct dpu_vbif_cfg { 587 DPU_HW_BLK_INFO; 588 unsigned long features; 589 u32 default_ot_rd_limit; 590 u32 default_ot_wr_limit; 591 u32 xin_halt_timeout; 592 u32 qos_rp_remap_size; 593 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 594 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 595 struct dpu_vbif_qos_tbl qos_rt_tbl; 596 struct dpu_vbif_qos_tbl qos_nrt_tbl; 597 u32 memtype_count; 598 u32 memtype[MAX_XIN_COUNT]; 599 }; 600 601 /** 602 * struct dpu_cdm_cfg - information of chroma down blocks 603 * @name string name for debug purposes 604 * @id enum identifying this block 605 * @base register offset of this block 606 */ 607 struct dpu_cdm_cfg { 608 DPU_HW_BLK_INFO; 609 }; 610 611 /** 612 * Define CDP use cases 613 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 614 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 615 */ 616 enum { 617 DPU_PERF_CDP_USAGE_RT, 618 DPU_PERF_CDP_USAGE_NRT, 619 DPU_PERF_CDP_USAGE_MAX 620 }; 621 622 /** 623 * struct dpu_perf_cdp_cfg - define CDP use case configuration 624 * @rd_enable: true if read pipe CDP is enabled 625 * @wr_enable: true if write pipe CDP is enabled 626 */ 627 struct dpu_perf_cdp_cfg { 628 bool rd_enable; 629 bool wr_enable; 630 }; 631 632 /** 633 * struct dpu_mdss_version - DPU's major and minor versions 634 * @core_major_ver: DPU core's major version 635 * @core_minor_ver: DPU core's minor version 636 */ 637 struct dpu_mdss_version { 638 u8 core_major_ver; 639 u8 core_minor_ver; 640 }; 641 642 /** 643 * struct dpu_perf_cfg - performance control settings 644 * @max_bw_low low threshold of maximum bandwidth (kbps) 645 * @max_bw_high high threshold of maximum bandwidth (kbps) 646 * @min_core_ib minimum bandwidth for core (kbps) 647 * @min_core_ib minimum mnoc ib vote in kbps 648 * @min_llcc_ib minimum llcc ib vote in kbps 649 * @min_dram_ib minimum dram ib vote in kbps 650 * @undersized_prefill_lines undersized prefill in lines 651 * @xtra_prefill_lines extra prefill latency in lines 652 * @dest_scale_prefill_lines destination scaler latency in lines 653 * @macrotile_perfill_lines macrotile latency in lines 654 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 655 * @linear_prefill_lines linear latency in lines 656 * @downscaling_prefill_lines downscaling latency in lines 657 * @amortizable_theshold minimum y position for traffic shaping prefill 658 * @min_prefill_lines minimum pipeline latency in lines 659 * @clk_inefficiency_factor DPU src clock inefficiency factor 660 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 661 * @safe_lut_tbl: LUT tables for safe signals 662 * @danger_lut_tbl: LUT tables for danger signals 663 * @qos_lut_tbl: LUT tables for QoS signals 664 * @cdp_cfg cdp use case configurations 665 */ 666 struct dpu_perf_cfg { 667 u32 max_bw_low; 668 u32 max_bw_high; 669 u32 min_core_ib; 670 u32 min_llcc_ib; 671 u32 min_dram_ib; 672 u32 undersized_prefill_lines; 673 u32 xtra_prefill_lines; 674 u32 dest_scale_prefill_lines; 675 u32 macrotile_prefill_lines; 676 u32 yuv_nv12_prefill_lines; 677 u32 linear_prefill_lines; 678 u32 downscaling_prefill_lines; 679 u32 amortizable_threshold; 680 u32 min_prefill_lines; 681 u32 clk_inefficiency_factor; 682 u32 bw_inefficiency_factor; 683 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 684 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 685 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 686 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 687 }; 688 689 /** 690 * struct dpu_mdss_cfg - information of MDSS HW 691 * This is the main catalog data structure representing 692 * this HW version. Contains dpu's major and minor versions, 693 * number of instances, register offsets, capabilities of the 694 * all MDSS HW sub-blocks. 695 * 696 * @dma_formats Supported formats for dma pipe 697 * @cursor_formats Supported formats for cursor pipe 698 * @vig_formats Supported formats for vig pipe 699 */ 700 struct dpu_mdss_cfg { 701 const struct dpu_mdss_version *mdss_ver; 702 703 const struct dpu_caps *caps; 704 705 const struct dpu_mdp_cfg *mdp; 706 707 u32 ctl_count; 708 const struct dpu_ctl_cfg *ctl; 709 710 u32 sspp_count; 711 const struct dpu_sspp_cfg *sspp; 712 713 u32 mixer_count; 714 const struct dpu_lm_cfg *mixer; 715 716 u32 pingpong_count; 717 const struct dpu_pingpong_cfg *pingpong; 718 719 u32 merge_3d_count; 720 const struct dpu_merge_3d_cfg *merge_3d; 721 722 u32 dsc_count; 723 const struct dpu_dsc_cfg *dsc; 724 725 u32 intf_count; 726 const struct dpu_intf_cfg *intf; 727 728 u32 vbif_count; 729 const struct dpu_vbif_cfg *vbif; 730 731 u32 wb_count; 732 const struct dpu_wb_cfg *wb; 733 734 const struct dpu_cdm_cfg *cdm; 735 736 u32 ad_count; 737 738 u32 dspp_count; 739 const struct dpu_dspp_cfg *dspp; 740 741 u32 cwb_count; 742 const struct dpu_cwb_cfg *cwb; 743 744 /* Add additional block data structures here */ 745 746 const struct dpu_perf_cfg *perf; 747 const struct dpu_format_extended *dma_formats; 748 const struct dpu_format_extended *cursor_formats; 749 const struct dpu_format_extended *vig_formats; 750 }; 751 752 extern const struct dpu_mdss_cfg dpu_glymur_cfg; 753 extern const struct dpu_mdss_cfg dpu_msm8917_cfg; 754 extern const struct dpu_mdss_cfg dpu_msm8937_cfg; 755 extern const struct dpu_mdss_cfg dpu_msm8953_cfg; 756 extern const struct dpu_mdss_cfg dpu_msm8996_cfg; 757 extern const struct dpu_mdss_cfg dpu_msm8998_cfg; 758 extern const struct dpu_mdss_cfg dpu_sar2130p_cfg; 759 extern const struct dpu_mdss_cfg dpu_sdm630_cfg; 760 extern const struct dpu_mdss_cfg dpu_sdm660_cfg; 761 extern const struct dpu_mdss_cfg dpu_sdm845_cfg; 762 extern const struct dpu_mdss_cfg dpu_sdm670_cfg; 763 extern const struct dpu_mdss_cfg dpu_sm8150_cfg; 764 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; 765 extern const struct dpu_mdss_cfg dpu_sm7150_cfg; 766 extern const struct dpu_mdss_cfg dpu_sm8250_cfg; 767 extern const struct dpu_mdss_cfg dpu_sc7180_cfg; 768 extern const struct dpu_mdss_cfg dpu_sm6115_cfg; 769 extern const struct dpu_mdss_cfg dpu_sm6125_cfg; 770 extern const struct dpu_mdss_cfg dpu_sm6150_cfg; 771 extern const struct dpu_mdss_cfg dpu_sm6350_cfg; 772 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; 773 extern const struct dpu_mdss_cfg dpu_sm6375_cfg; 774 extern const struct dpu_mdss_cfg dpu_sm8350_cfg; 775 extern const struct dpu_mdss_cfg dpu_sc7280_cfg; 776 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; 777 extern const struct dpu_mdss_cfg dpu_sm8450_cfg; 778 extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; 779 extern const struct dpu_mdss_cfg dpu_sm8550_cfg; 780 extern const struct dpu_mdss_cfg dpu_sm8650_cfg; 781 extern const struct dpu_mdss_cfg dpu_sm8750_cfg; 782 extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; 783 784 #endif /* _DPU_HW_CATALOG_H */ 785