1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/sched/smt.h>
20 #include <linux/list.h>
21 #include <linux/cpu.h>
22 #include <linux/cpufreq.h>
23 #include <linux/sysfs.h>
24 #include <linux/types.h>
25 #include <linux/fs.h>
26 #include <linux/acpi.h>
27 #include <linux/vmalloc.h>
28 #include <linux/pm_qos.h>
29 #include <linux/bitfield.h>
30 #include <trace/events/power.h>
31 #include <linux/units.h>
32
33 #include <asm/cpu.h>
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39 #include "../drivers/thermal/intel/thermal_interrupt.h"
40
41 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
42
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
45 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
46
47 #ifdef CONFIG_ACPI
48 #include <acpi/processor.h>
49 #include <acpi/cppc_acpi.h>
50 #endif
51
52 #define FRAC_BITS 8
53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
54 #define fp_toint(X) ((X) >> FRAC_BITS)
55
56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
57
58 #define EXT_BITS 6
59 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
60 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
61 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
62
mul_fp(int32_t x,int32_t y)63 static inline int32_t mul_fp(int32_t x, int32_t y)
64 {
65 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
66 }
67
div_fp(s64 x,s64 y)68 static inline int32_t div_fp(s64 x, s64 y)
69 {
70 return div64_s64((int64_t)x << FRAC_BITS, y);
71 }
72
ceiling_fp(int32_t x)73 static inline int ceiling_fp(int32_t x)
74 {
75 int mask, ret;
76
77 ret = fp_toint(x);
78 mask = (1 << FRAC_BITS) - 1;
79 if (x & mask)
80 ret += 1;
81 return ret;
82 }
83
mul_ext_fp(u64 x,u64 y)84 static inline u64 mul_ext_fp(u64 x, u64 y)
85 {
86 return (x * y) >> EXT_FRAC_BITS;
87 }
88
div_ext_fp(u64 x,u64 y)89 static inline u64 div_ext_fp(u64 x, u64 y)
90 {
91 return div64_u64(x << EXT_FRAC_BITS, y);
92 }
93
94 /**
95 * struct sample - Store performance sample
96 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
97 * performance during last sample period
98 * @busy_scaled: Scaled busy value which is used to calculate next
99 * P state. This can be different than core_avg_perf
100 * to account for cpu idle period
101 * @aperf: Difference of actual performance frequency clock count
102 * read from APERF MSR between last and current sample
103 * @mperf: Difference of maximum performance frequency clock count
104 * read from MPERF MSR between last and current sample
105 * @tsc: Difference of time stamp counter between last and
106 * current sample
107 * @time: Current time from scheduler
108 *
109 * This structure is used in the cpudata structure to store performance sample
110 * data for choosing next P State.
111 */
112 struct sample {
113 int32_t core_avg_perf;
114 int32_t busy_scaled;
115 u64 aperf;
116 u64 mperf;
117 u64 tsc;
118 u64 time;
119 };
120
121 /**
122 * struct pstate_data - Store P state data
123 * @current_pstate: Current requested P state
124 * @min_pstate: Min P state possible for this platform
125 * @max_pstate: Max P state possible for this platform
126 * @max_pstate_physical:This is physical Max P state for a processor
127 * This can be higher than the max_pstate which can
128 * be limited by platform thermal design power limits
129 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
130 * @scaling: Scaling factor between performance and frequency
131 * @turbo_pstate: Max Turbo P state possible for this platform
132 * @min_freq: @min_pstate frequency in cpufreq units
133 * @max_freq: @max_pstate frequency in cpufreq units
134 * @turbo_freq: @turbo_pstate frequency in cpufreq units
135 *
136 * Stores the per cpu model P state limits and current P state.
137 */
138 struct pstate_data {
139 int current_pstate;
140 int min_pstate;
141 int max_pstate;
142 int max_pstate_physical;
143 int perf_ctl_scaling;
144 int scaling;
145 int turbo_pstate;
146 unsigned int min_freq;
147 unsigned int max_freq;
148 unsigned int turbo_freq;
149 };
150
151 /**
152 * struct vid_data - Stores voltage information data
153 * @min: VID data for this platform corresponding to
154 * the lowest P state
155 * @max: VID data corresponding to the highest P State.
156 * @turbo: VID data for turbo P state
157 * @ratio: Ratio of (vid max - vid min) /
158 * (max P state - Min P State)
159 *
160 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
161 * This data is used in Atom platforms, where in addition to target P state,
162 * the voltage data needs to be specified to select next P State.
163 */
164 struct vid_data {
165 int min;
166 int max;
167 int turbo;
168 int32_t ratio;
169 };
170
171 /**
172 * struct global_params - Global parameters, mostly tunable via sysfs.
173 * @no_turbo: Whether or not to use turbo P-states.
174 * @turbo_disabled: Whether or not turbo P-states are available at all,
175 * based on the MSR_IA32_MISC_ENABLE value and whether or
176 * not the maximum reported turbo P-state is different from
177 * the maximum reported non-turbo one.
178 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
179 * P-state capacity.
180 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
181 * P-state capacity.
182 */
183 struct global_params {
184 bool no_turbo;
185 bool turbo_disabled;
186 int max_perf_pct;
187 int min_perf_pct;
188 };
189
190 /**
191 * struct cpudata - Per CPU instance data storage
192 * @cpu: CPU number for this instance data
193 * @policy: CPUFreq policy value
194 * @update_util: CPUFreq utility callback information
195 * @update_util_set: CPUFreq utility callback is set
196 * @iowait_boost: iowait-related boost fraction
197 * @last_update: Time of the last update.
198 * @pstate: Stores P state limits for this CPU
199 * @vid: Stores VID limits for this CPU
200 * @last_sample_time: Last Sample time
201 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
202 * @prev_aperf: Last APERF value read from APERF MSR
203 * @prev_mperf: Last MPERF value read from MPERF MSR
204 * @prev_tsc: Last timestamp counter (TSC) value
205 * @sample: Storage for storing last Sample data
206 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
207 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
208 * @acpi_perf_data: Stores ACPI perf information read from _PSS
209 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
210 * @epp_powersave: Last saved HWP energy performance preference
211 * (EPP) or energy performance bias (EPB),
212 * when policy switched to performance
213 * @epp_policy: Last saved policy used to set EPP/EPB
214 * @epp_default: Power on default HWP energy performance
215 * preference/bias
216 * @epp_cached: Cached HWP energy-performance preference value
217 * @hwp_req_cached: Cached value of the last HWP Request MSR
218 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
219 * @last_io_update: Last time when IO wake flag was set
220 * @capacity_perf: Highest perf used for scale invariance
221 * @sched_flags: Store scheduler flags for possible cross CPU update
222 * @hwp_boost_min: Last HWP boosted min performance
223 * @suspended: Whether or not the driver has been suspended.
224 * @pd_registered: Set when a perf domain is registered for this CPU.
225 * @hwp_notify_work: workqueue for HWP notifications.
226 *
227 * This structure stores per CPU instance data for all CPUs.
228 */
229 struct cpudata {
230 int cpu;
231
232 unsigned int policy;
233 struct update_util_data update_util;
234 bool update_util_set;
235
236 struct pstate_data pstate;
237 struct vid_data vid;
238
239 u64 last_update;
240 u64 last_sample_time;
241 u64 aperf_mperf_shift;
242 u64 prev_aperf;
243 u64 prev_mperf;
244 u64 prev_tsc;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
248 #ifdef CONFIG_ACPI
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
251 #endif
252 unsigned int iowait_boost;
253 s16 epp_powersave;
254 s16 epp_policy;
255 s16 epp_default;
256 s16 epp_cached;
257 u64 hwp_req_cached;
258 u64 hwp_cap_cached;
259 u64 last_io_update;
260 unsigned int capacity_perf;
261 unsigned int sched_flags;
262 u32 hwp_boost_min;
263 bool suspended;
264 #ifdef CONFIG_ENERGY_MODEL
265 bool pd_registered;
266 #endif
267 struct delayed_work hwp_notify_work;
268 };
269
270 static struct cpudata **all_cpu_data;
271
272 /**
273 * struct pstate_funcs - Per CPU model specific callbacks
274 * @get_max: Callback to get maximum non turbo effective P state
275 * @get_max_physical: Callback to get maximum non turbo physical P state
276 * @get_min: Callback to get minimum P state
277 * @get_turbo: Callback to get turbo P state
278 * @get_scaling: Callback to get frequency scaling factor
279 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
280 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
281 * @get_val: Callback to convert P state to actual MSR write value
282 * @get_vid: Callback to get VID data for Atom platforms
283 *
284 * Core and Atom CPU models have different way to get P State limits. This
285 * structure is used to store those callbacks.
286 */
287 struct pstate_funcs {
288 int (*get_max)(int cpu);
289 int (*get_max_physical)(int cpu);
290 int (*get_min)(int cpu);
291 int (*get_turbo)(int cpu);
292 int (*get_scaling)(void);
293 int (*get_cpu_scaling)(int cpu);
294 int (*get_aperf_mperf_shift)(void);
295 u64 (*get_val)(struct cpudata*, int pstate);
296 void (*get_vid)(struct cpudata *);
297 };
298
299 static struct pstate_funcs pstate_funcs __read_mostly;
300
301 static bool hwp_active __ro_after_init;
302 static int hwp_mode_bdw __ro_after_init;
303 static bool per_cpu_limits __ro_after_init;
304 static bool hwp_forced __ro_after_init;
305 static bool hwp_boost __read_mostly;
306 static bool hwp_is_hybrid;
307
308 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
309
310 #define INTEL_PSTATE_CORE_SCALING 100000
311 #define HYBRID_SCALING_FACTOR_ADL 78741
312 #define HYBRID_SCALING_FACTOR_MTL 80000
313 #define HYBRID_SCALING_FACTOR_LNL 86957
314
315 static int hybrid_scaling_factor;
316
core_get_scaling(void)317 static inline int core_get_scaling(void)
318 {
319 return INTEL_PSTATE_CORE_SCALING;
320 }
321
322 #ifdef CONFIG_ACPI
323 static bool acpi_ppc;
324 #endif
325
326 static struct global_params global;
327
328 static DEFINE_MUTEX(intel_pstate_driver_lock);
329 static DEFINE_MUTEX(intel_pstate_limits_lock);
330
331 #ifdef CONFIG_ACPI
332
intel_pstate_acpi_pm_profile_server(void)333 static bool intel_pstate_acpi_pm_profile_server(void)
334 {
335 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
336 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
337 return true;
338
339 return false;
340 }
341
intel_pstate_get_ppc_enable_status(void)342 static bool intel_pstate_get_ppc_enable_status(void)
343 {
344 if (intel_pstate_acpi_pm_profile_server())
345 return true;
346
347 return acpi_ppc;
348 }
349
350 #ifdef CONFIG_ACPI_CPPC_LIB
351
352 /* The work item is needed to avoid CPU hotplug locking issues */
intel_pstste_sched_itmt_work_fn(struct work_struct * work)353 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
354 {
355 sched_set_itmt_support();
356 }
357
358 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
359
360 #define CPPC_MAX_PERF U8_MAX
361
intel_pstate_set_itmt_prio(int cpu)362 static void intel_pstate_set_itmt_prio(int cpu)
363 {
364 struct cppc_perf_caps cppc_perf;
365 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
366 int ret;
367
368 ret = cppc_get_perf_caps(cpu, &cppc_perf);
369 /*
370 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0].
371 *
372 * Also, on some systems with overclocking enabled, CPPC.highest_perf is
373 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT.
374 * Fall back to MSR_HWP_CAPABILITIES then too.
375 */
376 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF)
377 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
378
379 /*
380 * The priorities can be set regardless of whether or not
381 * sched_set_itmt_support(true) has been called and it is valid to
382 * update them at any time after it has been called.
383 */
384 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
385
386 if (max_highest_perf <= min_highest_perf) {
387 if (cppc_perf.highest_perf > max_highest_perf)
388 max_highest_perf = cppc_perf.highest_perf;
389
390 if (cppc_perf.highest_perf < min_highest_perf)
391 min_highest_perf = cppc_perf.highest_perf;
392
393 if (max_highest_perf > min_highest_perf) {
394 /*
395 * This code can be run during CPU online under the
396 * CPU hotplug locks, so sched_set_itmt_support()
397 * cannot be called from here. Queue up a work item
398 * to invoke it.
399 */
400 schedule_work(&sched_itmt_work);
401 }
402 }
403 }
404
intel_pstate_get_cppc_guaranteed(int cpu)405 static int intel_pstate_get_cppc_guaranteed(int cpu)
406 {
407 struct cppc_perf_caps cppc_perf;
408 int ret;
409
410 ret = cppc_get_perf_caps(cpu, &cppc_perf);
411 if (ret)
412 return ret;
413
414 if (cppc_perf.guaranteed_perf)
415 return cppc_perf.guaranteed_perf;
416
417 return cppc_perf.nominal_perf;
418 }
419
intel_pstate_cppc_get_scaling(int cpu)420 static int intel_pstate_cppc_get_scaling(int cpu)
421 {
422 struct cppc_perf_caps cppc_perf;
423
424 /*
425 * Compute the perf-to-frequency scaling factor for the given CPU if
426 * possible, unless it would be 0.
427 */
428 if (!cppc_get_perf_caps(cpu, &cppc_perf) &&
429 cppc_perf.nominal_perf && cppc_perf.nominal_freq)
430 return div_u64(cppc_perf.nominal_freq * KHZ_PER_MHZ,
431 cppc_perf.nominal_perf);
432
433 return core_get_scaling();
434 }
435
436 #else /* CONFIG_ACPI_CPPC_LIB */
intel_pstate_set_itmt_prio(int cpu)437 static inline void intel_pstate_set_itmt_prio(int cpu)
438 {
439 }
440 #endif /* CONFIG_ACPI_CPPC_LIB */
441
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)442 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
443 {
444 struct cpudata *cpu;
445 int ret;
446 int i;
447
448 if (hwp_active) {
449 intel_pstate_set_itmt_prio(policy->cpu);
450 return;
451 }
452
453 if (!intel_pstate_get_ppc_enable_status())
454 return;
455
456 cpu = all_cpu_data[policy->cpu];
457
458 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
459 policy->cpu);
460 if (ret)
461 return;
462
463 /*
464 * Check if the control value in _PSS is for PERF_CTL MSR, which should
465 * guarantee that the states returned by it map to the states in our
466 * list directly.
467 */
468 if (cpu->acpi_perf_data.control_register.space_id !=
469 ACPI_ADR_SPACE_FIXED_HARDWARE)
470 goto err;
471
472 /*
473 * If there is only one entry _PSS, simply ignore _PSS and continue as
474 * usual without taking _PSS into account
475 */
476 if (cpu->acpi_perf_data.state_count < 2)
477 goto err;
478
479 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
480 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
481 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
482 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
483 (u32) cpu->acpi_perf_data.states[i].core_frequency,
484 (u32) cpu->acpi_perf_data.states[i].power,
485 (u32) cpu->acpi_perf_data.states[i].control);
486 }
487
488 cpu->valid_pss_table = true;
489 pr_debug("_PPC limits will be enforced\n");
490
491 return;
492
493 err:
494 cpu->valid_pss_table = false;
495 acpi_processor_unregister_performance(policy->cpu);
496 }
497
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)498 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
499 {
500 struct cpudata *cpu;
501
502 cpu = all_cpu_data[policy->cpu];
503 if (!cpu->valid_pss_table)
504 return;
505
506 acpi_processor_unregister_performance(policy->cpu);
507 }
508 #else /* CONFIG_ACPI */
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)509 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
510 {
511 }
512
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)513 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
514 {
515 }
516
intel_pstate_acpi_pm_profile_server(void)517 static inline bool intel_pstate_acpi_pm_profile_server(void)
518 {
519 return false;
520 }
521 #endif /* CONFIG_ACPI */
522
523 #ifndef CONFIG_ACPI_CPPC_LIB
intel_pstate_get_cppc_guaranteed(int cpu)524 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
525 {
526 return -ENOTSUPP;
527 }
528
intel_pstate_cppc_get_scaling(int cpu)529 static int intel_pstate_cppc_get_scaling(int cpu)
530 {
531 return core_get_scaling();
532 }
533 #endif /* CONFIG_ACPI_CPPC_LIB */
534
intel_pstate_freq_to_hwp_rel(struct cpudata * cpu,int freq,unsigned int relation)535 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
536 unsigned int relation)
537 {
538 if (freq == cpu->pstate.turbo_freq)
539 return cpu->pstate.turbo_pstate;
540
541 if (freq == cpu->pstate.max_freq)
542 return cpu->pstate.max_pstate;
543
544 switch (relation) {
545 case CPUFREQ_RELATION_H:
546 return freq / cpu->pstate.scaling;
547 case CPUFREQ_RELATION_C:
548 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
549 }
550
551 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
552 }
553
intel_pstate_freq_to_hwp(struct cpudata * cpu,int freq)554 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
555 {
556 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
557 }
558
559 /**
560 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
561 * @cpu: Target CPU.
562 *
563 * On hybrid processors, HWP may expose more performance levels than there are
564 * P-states accessible through the PERF_CTL interface. If that happens, the
565 * scaling factor between HWP performance levels and CPU frequency will be less
566 * than the scaling factor between P-state values and CPU frequency.
567 *
568 * In that case, adjust the CPU parameters used in computations accordingly.
569 */
intel_pstate_hybrid_hwp_adjust(struct cpudata * cpu)570 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
571 {
572 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
573 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
574 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
575 int scaling = cpu->pstate.scaling;
576 int freq;
577
578 pr_debug("CPU%d: PERF_CTL max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
579 pr_debug("CPU%d: PERF_CTL turbo = %d\n", cpu->cpu, perf_ctl_turbo);
580 pr_debug("CPU%d: PERF_CTL scaling = %d\n", cpu->cpu, perf_ctl_scaling);
581 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
582 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
583 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
584
585 if (scaling == perf_ctl_scaling)
586 return;
587
588 hwp_is_hybrid = true;
589
590 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
591 perf_ctl_scaling);
592 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
593 perf_ctl_scaling);
594
595 freq = perf_ctl_max_phys * perf_ctl_scaling;
596 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
597
598 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
599 cpu->pstate.min_freq = freq;
600 /*
601 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
602 * the effective range of HWP performance levels.
603 */
604 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
605 }
606
turbo_is_disabled(void)607 static bool turbo_is_disabled(void)
608 {
609 u64 misc_en;
610
611 rdmsrq(MSR_IA32_MISC_ENABLE, misc_en);
612
613 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
614 }
615
min_perf_pct_min(void)616 static int min_perf_pct_min(void)
617 {
618 struct cpudata *cpu = all_cpu_data[0];
619 int turbo_pstate = cpu->pstate.turbo_pstate;
620
621 return turbo_pstate ?
622 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
623 }
624
intel_pstate_get_epp(struct cpudata * cpu_data,u64 hwp_req_data)625 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
626 {
627 s16 epp = -EOPNOTSUPP;
628
629 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
630 /*
631 * When hwp_req_data is 0, means that caller didn't read
632 * MSR_HWP_REQUEST, so need to read and get EPP.
633 */
634 if (!hwp_req_data) {
635 epp = rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
636 &hwp_req_data);
637 if (epp)
638 return epp;
639 }
640 epp = (hwp_req_data >> 24) & 0xff;
641 }
642
643 return epp;
644 }
645
646 /*
647 * EPP display strings corresponding to EPP index in the
648 * energy_perf_strings[]
649 * index String
650 *-------------------------------------
651 * 0 default
652 * 1 performance
653 * 2 balance_performance
654 * 3 balance_power
655 * 4 power
656 */
657
658 enum energy_perf_value_index {
659 EPP_INDEX_DEFAULT = 0,
660 EPP_INDEX_PERFORMANCE,
661 EPP_INDEX_BALANCE_PERFORMANCE,
662 EPP_INDEX_BALANCE_POWERSAVE,
663 EPP_INDEX_POWERSAVE,
664 };
665
666 static const char * const energy_perf_strings[] = {
667 [EPP_INDEX_DEFAULT] = "default",
668 [EPP_INDEX_PERFORMANCE] = "performance",
669 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
670 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
671 [EPP_INDEX_POWERSAVE] = "power",
672 NULL
673 };
674 static unsigned int epp_values[] = {
675 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
676 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
677 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
678 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
679 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
680 };
681
intel_pstate_get_energy_pref_index(struct cpudata * cpu_data,int * raw_epp)682 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
683 {
684 s16 epp;
685 int index = -EINVAL;
686
687 *raw_epp = 0;
688 epp = intel_pstate_get_epp(cpu_data, 0);
689 if (epp < 0)
690 return epp;
691
692 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
693 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
694 return EPP_INDEX_PERFORMANCE;
695 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
696 return EPP_INDEX_BALANCE_PERFORMANCE;
697 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
698 return EPP_INDEX_BALANCE_POWERSAVE;
699 if (epp == epp_values[EPP_INDEX_POWERSAVE])
700 return EPP_INDEX_POWERSAVE;
701 *raw_epp = epp;
702 return 0;
703 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
704 /*
705 * Range:
706 * 0x00-0x03 : Performance
707 * 0x04-0x07 : Balance performance
708 * 0x08-0x0B : Balance power
709 * 0x0C-0x0F : Power
710 * The EPB is a 4 bit value, but our ranges restrict the
711 * value which can be set. Here only using top two bits
712 * effectively.
713 */
714 index = (epp >> 2) + 1;
715 }
716
717 return index;
718 }
719
intel_pstate_set_epp(struct cpudata * cpu,u32 epp)720 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
721 {
722 int ret;
723
724 /*
725 * Use the cached HWP Request MSR value, because in the active mode the
726 * register itself may be updated by intel_pstate_hwp_boost_up() or
727 * intel_pstate_hwp_boost_down() at any time.
728 */
729 u64 value = READ_ONCE(cpu->hwp_req_cached);
730
731 value &= ~GENMASK_ULL(31, 24);
732 value |= (u64)epp << 24;
733 /*
734 * The only other updater of hwp_req_cached in the active mode,
735 * intel_pstate_hwp_set(), is called under the same lock as this
736 * function, so it cannot run in parallel with the update below.
737 */
738 WRITE_ONCE(cpu->hwp_req_cached, value);
739 ret = wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
740 if (!ret)
741 cpu->epp_cached = epp;
742
743 return ret;
744 }
745
intel_pstate_set_energy_pref_index(struct cpudata * cpu_data,int pref_index,bool use_raw,u32 raw_epp)746 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
747 int pref_index, bool use_raw,
748 u32 raw_epp)
749 {
750 int epp = -EINVAL;
751 int ret = -EOPNOTSUPP;
752
753 if (!pref_index)
754 epp = cpu_data->epp_default;
755
756 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
757 if (use_raw)
758 epp = raw_epp;
759 else if (epp == -EINVAL)
760 epp = epp_values[pref_index];
761
762 /*
763 * To avoid confusion, refuse to set EPP to any values different
764 * from 0 (performance) if the current policy is "performance",
765 * because those values would be overridden.
766 */
767 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
768 return -EBUSY;
769
770 ret = intel_pstate_set_epp(cpu_data, epp);
771 }
772
773 return ret;
774 }
775
show_energy_performance_available_preferences(struct cpufreq_policy * policy,char * buf)776 static ssize_t show_energy_performance_available_preferences(
777 struct cpufreq_policy *policy, char *buf)
778 {
779 int i = 0;
780 int ret = 0;
781
782 while (energy_perf_strings[i] != NULL)
783 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
784
785 ret += sprintf(&buf[ret], "\n");
786
787 return ret;
788 }
789
790 cpufreq_freq_attr_ro(energy_performance_available_preferences);
791
792 static struct cpufreq_driver intel_pstate;
793
store_energy_performance_preference(struct cpufreq_policy * policy,const char * buf,size_t count)794 static ssize_t store_energy_performance_preference(
795 struct cpufreq_policy *policy, const char *buf, size_t count)
796 {
797 struct cpudata *cpu = all_cpu_data[policy->cpu];
798 char str_preference[21];
799 bool raw = false;
800 ssize_t ret;
801 u32 epp = 0;
802
803 ret = sscanf(buf, "%20s", str_preference);
804 if (ret != 1)
805 return -EINVAL;
806
807 ret = match_string(energy_perf_strings, -1, str_preference);
808 if (ret < 0) {
809 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
810 return ret;
811
812 ret = kstrtouint(buf, 10, &epp);
813 if (ret)
814 return ret;
815
816 if (epp > 255)
817 return -EINVAL;
818
819 raw = true;
820 }
821
822 /*
823 * This function runs with the policy R/W semaphore held, which
824 * guarantees that the driver pointer will not change while it is
825 * running.
826 */
827 if (!intel_pstate_driver)
828 return -EAGAIN;
829
830 mutex_lock(&intel_pstate_limits_lock);
831
832 if (intel_pstate_driver == &intel_pstate) {
833 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
834 } else {
835 /*
836 * In the passive mode the governor needs to be stopped on the
837 * target CPU before the EPP update and restarted after it,
838 * which is super-heavy-weight, so make sure it is worth doing
839 * upfront.
840 */
841 if (!raw)
842 epp = ret ? epp_values[ret] : cpu->epp_default;
843
844 if (cpu->epp_cached != epp) {
845 int err;
846
847 cpufreq_stop_governor(policy);
848 ret = intel_pstate_set_epp(cpu, epp);
849 err = cpufreq_start_governor(policy);
850 if (!ret)
851 ret = err;
852 } else {
853 ret = 0;
854 }
855 }
856
857 mutex_unlock(&intel_pstate_limits_lock);
858
859 return ret ?: count;
860 }
861
show_energy_performance_preference(struct cpufreq_policy * policy,char * buf)862 static ssize_t show_energy_performance_preference(
863 struct cpufreq_policy *policy, char *buf)
864 {
865 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
866 int preference, raw_epp;
867
868 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
869 if (preference < 0)
870 return preference;
871
872 if (raw_epp)
873 return sprintf(buf, "%d\n", raw_epp);
874 else
875 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
876 }
877
878 cpufreq_freq_attr_rw(energy_performance_preference);
879
show_base_frequency(struct cpufreq_policy * policy,char * buf)880 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
881 {
882 struct cpudata *cpu = all_cpu_data[policy->cpu];
883 int ratio, freq;
884
885 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
886 if (ratio <= 0) {
887 u64 cap;
888
889 rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
890 ratio = HWP_GUARANTEED_PERF(cap);
891 }
892
893 freq = ratio * cpu->pstate.scaling;
894 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
895 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
896
897 return sprintf(buf, "%d\n", freq);
898 }
899
900 cpufreq_freq_attr_ro(base_frequency);
901
902 enum hwp_cpufreq_attr_index {
903 HWP_BASE_FREQUENCY_INDEX = 0,
904 HWP_PERFORMANCE_PREFERENCE_INDEX,
905 HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX,
906 HWP_CPUFREQ_ATTR_COUNT,
907 };
908
909 static struct freq_attr *hwp_cpufreq_attrs[] = {
910 [HWP_BASE_FREQUENCY_INDEX] = &base_frequency,
911 [HWP_PERFORMANCE_PREFERENCE_INDEX] = &energy_performance_preference,
912 [HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] =
913 &energy_performance_available_preferences,
914 [HWP_CPUFREQ_ATTR_COUNT] = NULL,
915 };
916
hybrid_get_cpu_type(unsigned int cpu)917 static u8 hybrid_get_cpu_type(unsigned int cpu)
918 {
919 return cpu_data(cpu).topo.intel_type;
920 }
921
922 static bool no_cas __ro_after_init;
923
924 static struct cpudata *hybrid_max_perf_cpu __read_mostly;
925 /*
926 * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata,
927 * and the x86 arch scale-invariance information from concurrent updates.
928 */
929 static DEFINE_MUTEX(hybrid_capacity_lock);
930
931 #ifdef CONFIG_ENERGY_MODEL
932 #define HYBRID_EM_STATE_COUNT 4
933
hybrid_active_power(struct device * dev,unsigned long * power,unsigned long * freq)934 static int hybrid_active_power(struct device *dev, unsigned long *power,
935 unsigned long *freq)
936 {
937 /*
938 * Create four "states" corresponding to 40%, 60%, 80%, and 100% of the
939 * full capacity.
940 *
941 * For this purpose, return the "frequency" of 2 for the first
942 * performance level and otherwise leave the value set by the caller.
943 */
944 if (!*freq)
945 *freq = 2;
946
947 /* No power information. */
948 *power = EM_MAX_POWER;
949
950 return 0;
951 }
952
hybrid_has_l3(unsigned int cpu)953 static bool hybrid_has_l3(unsigned int cpu)
954 {
955 struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(cpu);
956 unsigned int i;
957
958 if (!cacheinfo)
959 return false;
960
961 for (i = 0; i < cacheinfo->num_leaves; i++) {
962 if (cacheinfo->info_list[i].level == 3)
963 return true;
964 }
965
966 return false;
967 }
968
hybrid_get_cost(struct device * dev,unsigned long freq,unsigned long * cost)969 static int hybrid_get_cost(struct device *dev, unsigned long freq,
970 unsigned long *cost)
971 {
972 /* Facilitate load balancing between CPUs of the same type. */
973 *cost = freq;
974 /*
975 * Adjust the cost depending on CPU type.
976 *
977 * The idea is to start loading up LPE-cores before E-cores and start
978 * to populate E-cores when LPE-cores are utilized above 60% of the
979 * capacity. Similarly, P-cores start to be populated when E-cores are
980 * utilized above 60% of the capacity.
981 */
982 if (hybrid_get_cpu_type(dev->id) == INTEL_CPU_TYPE_ATOM) {
983 if (hybrid_has_l3(dev->id)) /* E-core */
984 *cost += 1;
985 } else { /* P-core */
986 *cost += 2;
987 }
988
989 return 0;
990 }
991
hybrid_register_perf_domain(unsigned int cpu)992 static bool hybrid_register_perf_domain(unsigned int cpu)
993 {
994 static const struct em_data_callback cb
995 = EM_ADV_DATA_CB(hybrid_active_power, hybrid_get_cost);
996 struct cpudata *cpudata = all_cpu_data[cpu];
997 struct device *cpu_dev;
998
999 /*
1000 * Registering EM perf domains without enabling asymmetric CPU capacity
1001 * support is not really useful and one domain should not be registered
1002 * more than once.
1003 */
1004 if (!hybrid_max_perf_cpu || cpudata->pd_registered)
1005 return false;
1006
1007 cpu_dev = get_cpu_device(cpu);
1008 if (!cpu_dev)
1009 return false;
1010
1011 if (em_dev_register_pd_no_update(cpu_dev, HYBRID_EM_STATE_COUNT, &cb,
1012 cpumask_of(cpu), false))
1013 return false;
1014
1015 cpudata->pd_registered = true;
1016
1017 return true;
1018 }
1019
hybrid_register_all_perf_domains(void)1020 static void hybrid_register_all_perf_domains(void)
1021 {
1022 unsigned int cpu;
1023
1024 for_each_online_cpu(cpu)
1025 hybrid_register_perf_domain(cpu);
1026 }
1027
hybrid_update_perf_domain(struct cpudata * cpu)1028 static void hybrid_update_perf_domain(struct cpudata *cpu)
1029 {
1030 if (cpu->pd_registered)
1031 em_adjust_cpu_capacity(cpu->cpu);
1032 }
1033 #else /* !CONFIG_ENERGY_MODEL */
hybrid_register_perf_domain(unsigned int cpu)1034 static inline bool hybrid_register_perf_domain(unsigned int cpu) { return false; }
hybrid_register_all_perf_domains(void)1035 static inline void hybrid_register_all_perf_domains(void) {}
hybrid_update_perf_domain(struct cpudata * cpu)1036 static inline void hybrid_update_perf_domain(struct cpudata *cpu) {}
1037 #endif /* CONFIG_ENERGY_MODEL */
1038
hybrid_set_cpu_capacity(struct cpudata * cpu)1039 static void hybrid_set_cpu_capacity(struct cpudata *cpu)
1040 {
1041 arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf,
1042 hybrid_max_perf_cpu->capacity_perf,
1043 cpu->capacity_perf,
1044 cpu->pstate.max_pstate_physical);
1045 hybrid_update_perf_domain(cpu);
1046
1047 topology_set_cpu_scale(cpu->cpu, arch_scale_cpu_capacity(cpu->cpu));
1048
1049 pr_debug("CPU%d: capacity perf = %u, base perf = %u, sys max perf = %u\n",
1050 cpu->cpu, cpu->capacity_perf, cpu->pstate.max_pstate_physical,
1051 hybrid_max_perf_cpu->capacity_perf);
1052 }
1053
hybrid_clear_cpu_capacity(unsigned int cpunum)1054 static void hybrid_clear_cpu_capacity(unsigned int cpunum)
1055 {
1056 arch_set_cpu_capacity(cpunum, 1, 1, 1, 1);
1057 }
1058
hybrid_get_capacity_perf(struct cpudata * cpu)1059 static void hybrid_get_capacity_perf(struct cpudata *cpu)
1060 {
1061 if (READ_ONCE(global.no_turbo)) {
1062 cpu->capacity_perf = cpu->pstate.max_pstate_physical;
1063 return;
1064 }
1065
1066 cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1067 }
1068
hybrid_set_capacity_of_cpus(void)1069 static void hybrid_set_capacity_of_cpus(void)
1070 {
1071 int cpunum;
1072
1073 for_each_online_cpu(cpunum) {
1074 struct cpudata *cpu = all_cpu_data[cpunum];
1075
1076 if (cpu)
1077 hybrid_set_cpu_capacity(cpu);
1078 }
1079 }
1080
hybrid_update_cpu_capacity_scaling(void)1081 static void hybrid_update_cpu_capacity_scaling(void)
1082 {
1083 struct cpudata *max_perf_cpu = NULL;
1084 unsigned int max_cap_perf = 0;
1085 int cpunum;
1086
1087 for_each_online_cpu(cpunum) {
1088 struct cpudata *cpu = all_cpu_data[cpunum];
1089
1090 if (!cpu)
1091 continue;
1092
1093 /*
1094 * During initialization, CPU performance at full capacity needs
1095 * to be determined.
1096 */
1097 if (!hybrid_max_perf_cpu)
1098 hybrid_get_capacity_perf(cpu);
1099
1100 /*
1101 * If hybrid_max_perf_cpu is not NULL at this point, it is
1102 * being replaced, so don't take it into account when looking
1103 * for the new one.
1104 */
1105 if (cpu == hybrid_max_perf_cpu)
1106 continue;
1107
1108 if (cpu->capacity_perf > max_cap_perf) {
1109 max_cap_perf = cpu->capacity_perf;
1110 max_perf_cpu = cpu;
1111 }
1112 }
1113
1114 if (max_perf_cpu) {
1115 hybrid_max_perf_cpu = max_perf_cpu;
1116 hybrid_set_capacity_of_cpus();
1117 } else {
1118 pr_info("Found no CPUs with nonzero maximum performance\n");
1119 /* Revert to the flat CPU capacity structure. */
1120 for_each_online_cpu(cpunum)
1121 hybrid_clear_cpu_capacity(cpunum);
1122 }
1123 }
1124
__hybrid_refresh_cpu_capacity_scaling(void)1125 static void __hybrid_refresh_cpu_capacity_scaling(void)
1126 {
1127 hybrid_max_perf_cpu = NULL;
1128 hybrid_update_cpu_capacity_scaling();
1129 }
1130
hybrid_refresh_cpu_capacity_scaling(void)1131 static void hybrid_refresh_cpu_capacity_scaling(void)
1132 {
1133 guard(mutex)(&hybrid_capacity_lock);
1134
1135 __hybrid_refresh_cpu_capacity_scaling();
1136 /*
1137 * Perf domains are not registered before setting hybrid_max_perf_cpu,
1138 * so register them all after setting up CPU capacity scaling.
1139 */
1140 hybrid_register_all_perf_domains();
1141 }
1142
hybrid_init_cpu_capacity_scaling(bool refresh)1143 static void hybrid_init_cpu_capacity_scaling(bool refresh)
1144 {
1145 /* Bail out if enabling capacity-aware scheduling is prohibited. */
1146 if (no_cas)
1147 return;
1148
1149 /*
1150 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity
1151 * scaling has been enabled already and the driver is just changing the
1152 * operation mode.
1153 */
1154 if (refresh) {
1155 hybrid_refresh_cpu_capacity_scaling();
1156 return;
1157 }
1158
1159 /*
1160 * On hybrid systems, use asym capacity instead of ITMT, but because
1161 * the capacity of SMT threads is not deterministic even approximately,
1162 * do not do that when SMT is in use.
1163 */
1164 if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) {
1165 hybrid_refresh_cpu_capacity_scaling();
1166 /*
1167 * Disabling ITMT causes sched domains to be rebuilt to disable asym
1168 * packing and enable asym capacity and EAS.
1169 */
1170 sched_clear_itmt_support();
1171 }
1172 }
1173
hybrid_clear_max_perf_cpu(void)1174 static bool hybrid_clear_max_perf_cpu(void)
1175 {
1176 bool ret;
1177
1178 guard(mutex)(&hybrid_capacity_lock);
1179
1180 ret = !!hybrid_max_perf_cpu;
1181 hybrid_max_perf_cpu = NULL;
1182
1183 return ret;
1184 }
1185
__intel_pstate_get_hwp_cap(struct cpudata * cpu)1186 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
1187 {
1188 u64 cap;
1189
1190 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
1191 WRITE_ONCE(cpu->hwp_cap_cached, cap);
1192 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
1193 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
1194 }
1195
intel_pstate_get_hwp_cap(struct cpudata * cpu)1196 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
1197 {
1198 int scaling = cpu->pstate.scaling;
1199
1200 __intel_pstate_get_hwp_cap(cpu);
1201
1202 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
1203 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
1204 if (scaling != cpu->pstate.perf_ctl_scaling) {
1205 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
1206
1207 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
1208 perf_ctl_scaling);
1209 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
1210 perf_ctl_scaling);
1211 }
1212 }
1213
hybrid_update_capacity(struct cpudata * cpu)1214 static void hybrid_update_capacity(struct cpudata *cpu)
1215 {
1216 unsigned int max_cap_perf;
1217
1218 mutex_lock(&hybrid_capacity_lock);
1219
1220 if (!hybrid_max_perf_cpu)
1221 goto unlock;
1222
1223 /*
1224 * The maximum performance of the CPU may have changed, but assume
1225 * that the performance of the other CPUs has not changed.
1226 */
1227 max_cap_perf = hybrid_max_perf_cpu->capacity_perf;
1228
1229 intel_pstate_get_hwp_cap(cpu);
1230
1231 hybrid_get_capacity_perf(cpu);
1232 /* Should hybrid_max_perf_cpu be replaced by this CPU? */
1233 if (cpu->capacity_perf > max_cap_perf) {
1234 hybrid_max_perf_cpu = cpu;
1235 hybrid_set_capacity_of_cpus();
1236 goto unlock;
1237 }
1238
1239 /* If this CPU is hybrid_max_perf_cpu, should it be replaced? */
1240 if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) {
1241 hybrid_update_cpu_capacity_scaling();
1242 goto unlock;
1243 }
1244
1245 hybrid_set_cpu_capacity(cpu);
1246 /*
1247 * If the CPU was offline to start with and it is going online for the
1248 * first time, a perf domain needs to be registered for it if hybrid
1249 * capacity scaling has been enabled already. In that case, sched
1250 * domains need to be rebuilt to take the new perf domain into account.
1251 */
1252 if (hybrid_register_perf_domain(cpu->cpu))
1253 em_rebuild_sched_domains();
1254
1255 unlock:
1256 mutex_unlock(&hybrid_capacity_lock);
1257 }
1258
intel_pstate_hwp_set(unsigned int cpu)1259 static void intel_pstate_hwp_set(unsigned int cpu)
1260 {
1261 struct cpudata *cpu_data = all_cpu_data[cpu];
1262 int max, min;
1263 u64 value;
1264 s16 epp;
1265
1266 max = cpu_data->max_perf_ratio;
1267 min = cpu_data->min_perf_ratio;
1268
1269 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
1270 min = max;
1271
1272 rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value);
1273
1274 value &= ~HWP_MIN_PERF(~0L);
1275 value |= HWP_MIN_PERF(min);
1276
1277 value &= ~HWP_MAX_PERF(~0L);
1278 value |= HWP_MAX_PERF(max);
1279
1280 if (cpu_data->epp_policy == cpu_data->policy)
1281 goto skip_epp;
1282
1283 cpu_data->epp_policy = cpu_data->policy;
1284
1285 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
1286 epp = intel_pstate_get_epp(cpu_data, value);
1287 cpu_data->epp_powersave = epp;
1288 /* If EPP read was failed, then don't try to write */
1289 if (epp < 0)
1290 goto skip_epp;
1291
1292 epp = 0;
1293 } else {
1294 /* skip setting EPP, when saved value is invalid */
1295 if (cpu_data->epp_powersave < 0)
1296 goto skip_epp;
1297
1298 /*
1299 * No need to restore EPP when it is not zero. This
1300 * means:
1301 * - Policy is not changed
1302 * - user has manually changed
1303 * - Error reading EPB
1304 */
1305 epp = intel_pstate_get_epp(cpu_data, value);
1306 if (epp)
1307 goto skip_epp;
1308
1309 epp = cpu_data->epp_powersave;
1310 }
1311 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1312 value &= ~GENMASK_ULL(31, 24);
1313 value |= (u64)epp << 24;
1314 }
1315
1316 skip_epp:
1317 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1318 wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value);
1319 }
1320
1321 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1322
intel_pstate_hwp_offline(struct cpudata * cpu)1323 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1324 {
1325 u64 value = READ_ONCE(cpu->hwp_req_cached);
1326 int min_perf;
1327
1328 intel_pstate_disable_hwp_interrupt(cpu);
1329
1330 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1331 /*
1332 * In case the EPP has been set to "performance" by the
1333 * active mode "performance" scaling algorithm, replace that
1334 * temporary value with the cached EPP one.
1335 */
1336 value &= ~GENMASK_ULL(31, 24);
1337 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1338 /*
1339 * However, make sure that EPP will be set to "performance" when
1340 * the CPU is brought back online again and the "performance"
1341 * scaling algorithm is still in effect.
1342 */
1343 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1344 }
1345
1346 /*
1347 * Clear the desired perf field in the cached HWP request value to
1348 * prevent nonzero desired values from being leaked into the active
1349 * mode.
1350 */
1351 value &= ~HWP_DESIRED_PERF(~0L);
1352 WRITE_ONCE(cpu->hwp_req_cached, value);
1353
1354 value &= ~GENMASK_ULL(31, 0);
1355 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1356
1357 /* Set hwp_max = hwp_min */
1358 value |= HWP_MAX_PERF(min_perf);
1359 value |= HWP_MIN_PERF(min_perf);
1360
1361 /* Set EPP to min */
1362 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1363 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1364
1365 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1366
1367 mutex_lock(&hybrid_capacity_lock);
1368
1369 if (!hybrid_max_perf_cpu) {
1370 mutex_unlock(&hybrid_capacity_lock);
1371
1372 return;
1373 }
1374
1375 if (hybrid_max_perf_cpu == cpu)
1376 hybrid_update_cpu_capacity_scaling();
1377
1378 mutex_unlock(&hybrid_capacity_lock);
1379
1380 /* Reset the capacity of the CPU going offline to the initial value. */
1381 hybrid_clear_cpu_capacity(cpu->cpu);
1382 }
1383
1384 #define POWER_CTL_EE_ENABLE 1
1385 #define POWER_CTL_EE_DISABLE 2
1386
1387 /* Enable bit for Dynamic Efficiency Control (DEC) */
1388 #define POWER_CTL_DEC_ENABLE 27
1389
1390 static int power_ctl_ee_state;
1391
set_power_ctl_ee_state(bool input)1392 static void set_power_ctl_ee_state(bool input)
1393 {
1394 u64 power_ctl;
1395
1396 guard(mutex)(&intel_pstate_driver_lock);
1397
1398 rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
1399 if (input) {
1400 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1401 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1402 } else {
1403 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1404 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1405 }
1406 wrmsrq(MSR_IA32_POWER_CTL, power_ctl);
1407 }
1408
1409 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1410
intel_pstate_hwp_reenable(struct cpudata * cpu)1411 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1412 {
1413 intel_pstate_hwp_enable(cpu);
1414 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1415 }
1416
intel_pstate_suspend(struct cpufreq_policy * policy)1417 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1418 {
1419 struct cpudata *cpu = all_cpu_data[policy->cpu];
1420
1421 pr_debug("CPU %d suspending\n", cpu->cpu);
1422
1423 cpu->suspended = true;
1424
1425 /* disable HWP interrupt and cancel any pending work */
1426 intel_pstate_disable_hwp_interrupt(cpu);
1427
1428 return 0;
1429 }
1430
intel_pstate_resume(struct cpufreq_policy * policy)1431 static int intel_pstate_resume(struct cpufreq_policy *policy)
1432 {
1433 struct cpudata *cpu = all_cpu_data[policy->cpu];
1434
1435 pr_debug("CPU %d resuming\n", cpu->cpu);
1436
1437 /* Only restore if the system default is changed */
1438 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1439 set_power_ctl_ee_state(true);
1440 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1441 set_power_ctl_ee_state(false);
1442
1443 if (cpu->suspended && hwp_active) {
1444 mutex_lock(&intel_pstate_limits_lock);
1445
1446 /* Re-enable HWP, because "online" has not done that. */
1447 intel_pstate_hwp_reenable(cpu);
1448
1449 mutex_unlock(&intel_pstate_limits_lock);
1450 }
1451
1452 cpu->suspended = false;
1453
1454 return 0;
1455 }
1456
intel_pstate_update_policies(void)1457 static void intel_pstate_update_policies(void)
1458 {
1459 int cpu;
1460
1461 for_each_possible_cpu(cpu)
1462 cpufreq_update_policy(cpu);
1463 }
1464
__intel_pstate_update_max_freq(struct cpufreq_policy * policy,struct cpudata * cpudata)1465 static void __intel_pstate_update_max_freq(struct cpufreq_policy *policy,
1466 struct cpudata *cpudata)
1467 {
1468 guard(cpufreq_policy_write)(policy);
1469
1470 if (hwp_active)
1471 intel_pstate_get_hwp_cap(cpudata);
1472
1473 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
1474 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1475
1476 refresh_frequency_limits(policy);
1477 }
1478
intel_pstate_update_max_freq(struct cpudata * cpudata)1479 static bool intel_pstate_update_max_freq(struct cpudata *cpudata)
1480 {
1481 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpudata->cpu);
1482 if (!policy)
1483 return false;
1484
1485 __intel_pstate_update_max_freq(policy, cpudata);
1486
1487 return true;
1488 }
1489
intel_pstate_update_limits(struct cpufreq_policy * policy)1490 static void intel_pstate_update_limits(struct cpufreq_policy *policy)
1491 {
1492 struct cpudata *cpudata = all_cpu_data[policy->cpu];
1493
1494 __intel_pstate_update_max_freq(policy, cpudata);
1495
1496 hybrid_update_capacity(cpudata);
1497 }
1498
intel_pstate_update_limits_for_all(void)1499 static void intel_pstate_update_limits_for_all(void)
1500 {
1501 int cpu;
1502
1503 for_each_possible_cpu(cpu)
1504 intel_pstate_update_max_freq(all_cpu_data[cpu]);
1505
1506 mutex_lock(&hybrid_capacity_lock);
1507
1508 if (hybrid_max_perf_cpu)
1509 __hybrid_refresh_cpu_capacity_scaling();
1510
1511 mutex_unlock(&hybrid_capacity_lock);
1512 }
1513
1514 /************************** sysfs begin ************************/
1515 #define show_one(file_name, object) \
1516 static ssize_t show_##file_name \
1517 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1518 { \
1519 return sprintf(buf, "%u\n", global.object); \
1520 }
1521
1522 static ssize_t intel_pstate_show_status(char *buf);
1523 static int intel_pstate_update_status(const char *buf, size_t size);
1524
show_status(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1525 static ssize_t show_status(struct kobject *kobj,
1526 struct kobj_attribute *attr, char *buf)
1527 {
1528 guard(mutex)(&intel_pstate_driver_lock);
1529
1530 return intel_pstate_show_status(buf);
1531 }
1532
store_status(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1533 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1534 const char *buf, size_t count)
1535 {
1536 char *p = memchr(buf, '\n', count);
1537 int ret;
1538
1539 guard(mutex)(&intel_pstate_driver_lock);
1540
1541 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1542 if (ret < 0)
1543 return ret;
1544
1545 return count;
1546 }
1547
show_turbo_pct(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1548 static ssize_t show_turbo_pct(struct kobject *kobj,
1549 struct kobj_attribute *attr, char *buf)
1550 {
1551 struct cpudata *cpu;
1552 int total, no_turbo, turbo_pct;
1553 uint32_t turbo_fp;
1554
1555 guard(mutex)(&intel_pstate_driver_lock);
1556
1557 if (!intel_pstate_driver)
1558 return -EAGAIN;
1559
1560 cpu = all_cpu_data[0];
1561
1562 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1563 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1564 turbo_fp = div_fp(no_turbo, total);
1565 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1566
1567 return sprintf(buf, "%u\n", turbo_pct);
1568 }
1569
show_num_pstates(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1570 static ssize_t show_num_pstates(struct kobject *kobj,
1571 struct kobj_attribute *attr, char *buf)
1572 {
1573 struct cpudata *cpu;
1574 int total;
1575
1576 guard(mutex)(&intel_pstate_driver_lock);
1577
1578 if (!intel_pstate_driver)
1579 return -EAGAIN;
1580
1581 cpu = all_cpu_data[0];
1582 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1583
1584 return sprintf(buf, "%u\n", total);
1585 }
1586
show_no_turbo(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1587 static ssize_t show_no_turbo(struct kobject *kobj,
1588 struct kobj_attribute *attr, char *buf)
1589 {
1590 guard(mutex)(&intel_pstate_driver_lock);
1591
1592 if (!intel_pstate_driver)
1593 return -EAGAIN;
1594
1595 return sprintf(buf, "%u\n", global.no_turbo);
1596 }
1597
store_no_turbo(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1598 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1599 const char *buf, size_t count)
1600 {
1601 unsigned int input;
1602 bool no_turbo;
1603
1604 if (sscanf(buf, "%u", &input) != 1)
1605 return -EINVAL;
1606
1607 guard(mutex)(&intel_pstate_driver_lock);
1608
1609 if (!intel_pstate_driver)
1610 return -EAGAIN;
1611
1612 no_turbo = !!clamp_t(int, input, 0, 1);
1613
1614 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled());
1615 if (global.turbo_disabled && !no_turbo) {
1616 pr_notice("Turbo disabled by BIOS or unavailable on processor\n");
1617 if (global.no_turbo)
1618 return -EPERM;
1619
1620 no_turbo = 1;
1621 }
1622
1623 if (no_turbo == global.no_turbo)
1624 return count;
1625
1626 WRITE_ONCE(global.no_turbo, no_turbo);
1627
1628 mutex_lock(&intel_pstate_limits_lock);
1629
1630 if (no_turbo) {
1631 struct cpudata *cpu = all_cpu_data[0];
1632 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1633
1634 /* Squash the global minimum into the permitted range. */
1635 if (global.min_perf_pct > pct)
1636 global.min_perf_pct = pct;
1637 }
1638
1639 mutex_unlock(&intel_pstate_limits_lock);
1640
1641 intel_pstate_update_limits_for_all();
1642 arch_set_max_freq_ratio(no_turbo);
1643
1644 return count;
1645 }
1646
update_cpu_qos_request(int cpu,enum freq_qos_req_type type)1647 static void update_cpu_qos_request(int cpu, enum freq_qos_req_type type)
1648 {
1649 struct cpudata *cpudata = all_cpu_data[cpu];
1650 unsigned int freq = cpudata->pstate.turbo_freq;
1651 struct freq_qos_request *req;
1652
1653 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu);
1654 if (!policy)
1655 return;
1656
1657 req = policy->driver_data;
1658 if (!req)
1659 return;
1660
1661 if (hwp_active)
1662 intel_pstate_get_hwp_cap(cpudata);
1663
1664 if (type == FREQ_QOS_MIN) {
1665 freq = DIV_ROUND_UP(freq * global.min_perf_pct, 100);
1666 } else {
1667 req++;
1668 freq = (freq * global.max_perf_pct) / 100;
1669 }
1670
1671 if (freq_qos_update_request(req, freq) < 0)
1672 pr_warn("Failed to update freq constraint: CPU%d\n", cpu);
1673 }
1674
update_qos_requests(enum freq_qos_req_type type)1675 static void update_qos_requests(enum freq_qos_req_type type)
1676 {
1677 int i;
1678
1679 for_each_possible_cpu(i)
1680 update_cpu_qos_request(i, type);
1681 }
1682
store_max_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1683 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1684 const char *buf, size_t count)
1685 {
1686 unsigned int input;
1687 int ret;
1688
1689 ret = sscanf(buf, "%u", &input);
1690 if (ret != 1)
1691 return -EINVAL;
1692
1693 guard(mutex)(&intel_pstate_driver_lock);
1694
1695 if (!intel_pstate_driver)
1696 return -EAGAIN;
1697
1698 mutex_lock(&intel_pstate_limits_lock);
1699
1700 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1701
1702 mutex_unlock(&intel_pstate_limits_lock);
1703
1704 if (intel_pstate_driver == &intel_pstate)
1705 intel_pstate_update_policies();
1706 else
1707 update_qos_requests(FREQ_QOS_MAX);
1708
1709 return count;
1710 }
1711
store_min_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1712 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1713 const char *buf, size_t count)
1714 {
1715 unsigned int input;
1716 int ret;
1717
1718 ret = sscanf(buf, "%u", &input);
1719 if (ret != 1)
1720 return -EINVAL;
1721
1722 guard(mutex)(&intel_pstate_driver_lock);
1723
1724 if (!intel_pstate_driver)
1725 return -EAGAIN;
1726
1727 mutex_lock(&intel_pstate_limits_lock);
1728
1729 global.min_perf_pct = clamp_t(int, input,
1730 min_perf_pct_min(), global.max_perf_pct);
1731
1732 mutex_unlock(&intel_pstate_limits_lock);
1733
1734 if (intel_pstate_driver == &intel_pstate)
1735 intel_pstate_update_policies();
1736 else
1737 update_qos_requests(FREQ_QOS_MIN);
1738
1739 return count;
1740 }
1741
show_hwp_dynamic_boost(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1742 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1743 struct kobj_attribute *attr, char *buf)
1744 {
1745 return sprintf(buf, "%u\n", hwp_boost);
1746 }
1747
store_hwp_dynamic_boost(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1748 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1749 struct kobj_attribute *b,
1750 const char *buf, size_t count)
1751 {
1752 unsigned int input;
1753 int ret;
1754
1755 ret = kstrtouint(buf, 10, &input);
1756 if (ret)
1757 return ret;
1758
1759 guard(mutex)(&intel_pstate_driver_lock);
1760
1761 hwp_boost = !!input;
1762 intel_pstate_update_policies();
1763
1764 return count;
1765 }
1766
show_energy_efficiency(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1767 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1768 char *buf)
1769 {
1770 u64 power_ctl;
1771 int enable;
1772
1773 rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
1774 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1775 return sprintf(buf, "%d\n", !enable);
1776 }
1777
store_energy_efficiency(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1778 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1779 const char *buf, size_t count)
1780 {
1781 bool input;
1782 int ret;
1783
1784 ret = kstrtobool(buf, &input);
1785 if (ret)
1786 return ret;
1787
1788 set_power_ctl_ee_state(input);
1789
1790 return count;
1791 }
1792
1793 show_one(max_perf_pct, max_perf_pct);
1794 show_one(min_perf_pct, min_perf_pct);
1795
1796 define_one_global_rw(status);
1797 define_one_global_rw(no_turbo);
1798 define_one_global_rw(max_perf_pct);
1799 define_one_global_rw(min_perf_pct);
1800 define_one_global_ro(turbo_pct);
1801 define_one_global_ro(num_pstates);
1802 define_one_global_rw(hwp_dynamic_boost);
1803 define_one_global_rw(energy_efficiency);
1804
1805 static struct attribute *intel_pstate_attributes[] = {
1806 &status.attr,
1807 &no_turbo.attr,
1808 NULL
1809 };
1810
1811 static const struct attribute_group intel_pstate_attr_group = {
1812 .attrs = intel_pstate_attributes,
1813 };
1814
1815 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1816
1817 static struct kobject *intel_pstate_kobject;
1818
intel_pstate_sysfs_expose_params(void)1819 static void __init intel_pstate_sysfs_expose_params(void)
1820 {
1821 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1822 int rc;
1823
1824 if (dev_root) {
1825 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1826 put_device(dev_root);
1827 }
1828 if (WARN_ON(!intel_pstate_kobject))
1829 return;
1830
1831 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1832 if (WARN_ON(rc))
1833 return;
1834
1835 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1836 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1837 WARN_ON(rc);
1838
1839 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1840 WARN_ON(rc);
1841 }
1842
1843 /*
1844 * If per cpu limits are enforced there are no global limits, so
1845 * return without creating max/min_perf_pct attributes
1846 */
1847 if (per_cpu_limits)
1848 return;
1849
1850 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1851 WARN_ON(rc);
1852
1853 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1854 WARN_ON(rc);
1855
1856 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1857 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1858 WARN_ON(rc);
1859 }
1860 }
1861
intel_pstate_sysfs_remove(void)1862 static void __init intel_pstate_sysfs_remove(void)
1863 {
1864 if (!intel_pstate_kobject)
1865 return;
1866
1867 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1868
1869 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1870 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1871 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1872 }
1873
1874 if (!per_cpu_limits) {
1875 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1876 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1877
1878 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1879 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1880 }
1881
1882 kobject_put(intel_pstate_kobject);
1883 }
1884
intel_pstate_sysfs_expose_hwp_dynamic_boost(void)1885 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1886 {
1887 int rc;
1888
1889 if (!hwp_active)
1890 return;
1891
1892 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1893 WARN_ON_ONCE(rc);
1894 }
1895
intel_pstate_sysfs_hide_hwp_dynamic_boost(void)1896 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1897 {
1898 if (!hwp_active)
1899 return;
1900
1901 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1902 }
1903
1904 /************************** sysfs end ************************/
1905
intel_pstate_notify_work(struct work_struct * work)1906 static void intel_pstate_notify_work(struct work_struct *work)
1907 {
1908 struct cpudata *cpudata =
1909 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1910
1911 if (intel_pstate_update_max_freq(cpudata)) {
1912 /*
1913 * The driver will not be unregistered while this function is
1914 * running, so update the capacity without acquiring the driver
1915 * lock.
1916 */
1917 hybrid_update_capacity(cpudata);
1918 }
1919
1920 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1921 }
1922
1923 static DEFINE_RAW_SPINLOCK(hwp_notify_lock);
1924 static cpumask_t hwp_intr_enable_mask;
1925
1926 #define HWP_GUARANTEED_PERF_CHANGE_STATUS BIT(0)
1927 #define HWP_HIGHEST_PERF_CHANGE_STATUS BIT(3)
1928
notify_hwp_interrupt(void)1929 void notify_hwp_interrupt(void)
1930 {
1931 unsigned int this_cpu = smp_processor_id();
1932 u64 value, status_mask;
1933 unsigned long flags;
1934
1935 if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1936 return;
1937
1938 status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS;
1939 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1940 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS;
1941
1942 rdmsrq_safe(MSR_HWP_STATUS, &value);
1943 if (!(value & status_mask))
1944 return;
1945
1946 raw_spin_lock_irqsave(&hwp_notify_lock, flags);
1947
1948 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1949 goto ack_intr;
1950
1951 schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work,
1952 msecs_to_jiffies(10));
1953
1954 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1955
1956 return;
1957
1958 ack_intr:
1959 wrmsrq_safe(MSR_HWP_STATUS, 0);
1960 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1961 }
1962
intel_pstate_disable_hwp_interrupt(struct cpudata * cpudata)1963 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1964 {
1965 bool cancel_work;
1966
1967 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1968 return;
1969
1970 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */
1971 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1972
1973 raw_spin_lock_irq(&hwp_notify_lock);
1974 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1975 raw_spin_unlock_irq(&hwp_notify_lock);
1976
1977 if (cancel_work)
1978 cancel_delayed_work_sync(&cpudata->hwp_notify_work);
1979 }
1980
1981 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0)
1982 #define HWP_HIGHEST_PERF_CHANGE_REQ BIT(2)
1983
intel_pstate_enable_hwp_interrupt(struct cpudata * cpudata)1984 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1985 {
1986 /* Enable HWP notification interrupt for performance change */
1987 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1988 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ;
1989
1990 raw_spin_lock_irq(&hwp_notify_lock);
1991 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1992 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1993 raw_spin_unlock_irq(&hwp_notify_lock);
1994
1995 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1996 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ;
1997
1998 /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */
1999 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
2000 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
2001 }
2002 }
2003
intel_pstate_update_epp_defaults(struct cpudata * cpudata)2004 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
2005 {
2006 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
2007
2008 /*
2009 * If the EPP is set by firmware, which means that firmware enabled HWP
2010 * - Is equal or less than 0x80 (default balance_perf EPP)
2011 * - But less performance oriented than performance EPP
2012 * then use this as new balance_perf EPP.
2013 */
2014 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
2015 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
2016 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
2017 return;
2018 }
2019
2020 /*
2021 * If this CPU gen doesn't call for change in balance_perf
2022 * EPP return.
2023 */
2024 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
2025 return;
2026
2027 /*
2028 * Use hard coded value per gen to update the balance_perf
2029 * and default EPP.
2030 */
2031 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
2032 intel_pstate_set_epp(cpudata, cpudata->epp_default);
2033 }
2034
intel_pstate_hwp_enable(struct cpudata * cpudata)2035 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2036 {
2037 /* First disable HWP notification interrupt till we activate again */
2038 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
2039 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
2040
2041 wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
2042
2043 intel_pstate_enable_hwp_interrupt(cpudata);
2044
2045 if (cpudata->epp_default >= 0)
2046 return;
2047
2048 intel_pstate_update_epp_defaults(cpudata);
2049 }
2050
get_perf_ctl_val(int pstate)2051 static u64 get_perf_ctl_val(int pstate)
2052 {
2053 u64 val;
2054
2055 val = (u64)pstate << 8;
2056 if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) &&
2057 cpu_feature_enabled(X86_FEATURE_IDA))
2058 val |= (u64)1 << 32;
2059
2060 return val;
2061 }
2062
atom_get_min_pstate(int not_used)2063 static int atom_get_min_pstate(int not_used)
2064 {
2065 u64 value;
2066
2067 rdmsrq(MSR_ATOM_CORE_RATIOS, value);
2068 return (value >> 8) & 0x7F;
2069 }
2070
atom_get_max_pstate(int not_used)2071 static int atom_get_max_pstate(int not_used)
2072 {
2073 u64 value;
2074
2075 rdmsrq(MSR_ATOM_CORE_RATIOS, value);
2076 return (value >> 16) & 0x7F;
2077 }
2078
atom_get_turbo_pstate(int not_used)2079 static int atom_get_turbo_pstate(int not_used)
2080 {
2081 u64 value;
2082
2083 rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS, value);
2084 return value & 0x7F;
2085 }
2086
atom_get_val(struct cpudata * cpudata,int pstate)2087 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
2088 {
2089 u64 val = get_perf_ctl_val(pstate);
2090 int32_t vid_fp;
2091 u32 vid;
2092
2093 vid_fp = cpudata->vid.min + mul_fp(
2094 int_tofp(pstate - cpudata->pstate.min_pstate),
2095 cpudata->vid.ratio);
2096
2097 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
2098 vid = ceiling_fp(vid_fp);
2099
2100 if (pstate > cpudata->pstate.max_pstate)
2101 vid = cpudata->vid.turbo;
2102
2103 return val | vid;
2104 }
2105
silvermont_get_scaling(void)2106 static int silvermont_get_scaling(void)
2107 {
2108 u64 value;
2109 int i;
2110 /* Defined in Table 35-6 from SDM (Sept 2015) */
2111 static int silvermont_freq_table[] = {
2112 83300, 100000, 133300, 116700, 80000};
2113
2114 rdmsrq(MSR_FSB_FREQ, value);
2115 i = value & 0x7;
2116 WARN_ON(i > 4);
2117
2118 return silvermont_freq_table[i];
2119 }
2120
airmont_get_scaling(void)2121 static int airmont_get_scaling(void)
2122 {
2123 u64 value;
2124 int i;
2125 /* Defined in Table 35-10 from SDM (Sept 2015) */
2126 static int airmont_freq_table[] = {
2127 83300, 100000, 133300, 116700, 80000,
2128 93300, 90000, 88900, 87500};
2129
2130 rdmsrq(MSR_FSB_FREQ, value);
2131 i = value & 0xF;
2132 WARN_ON(i > 8);
2133
2134 return airmont_freq_table[i];
2135 }
2136
atom_get_vid(struct cpudata * cpudata)2137 static void atom_get_vid(struct cpudata *cpudata)
2138 {
2139 u64 value;
2140
2141 rdmsrq(MSR_ATOM_CORE_VIDS, value);
2142 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
2143 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
2144 cpudata->vid.ratio = div_fp(
2145 cpudata->vid.max - cpudata->vid.min,
2146 int_tofp(cpudata->pstate.max_pstate -
2147 cpudata->pstate.min_pstate));
2148
2149 rdmsrq(MSR_ATOM_CORE_TURBO_VIDS, value);
2150 cpudata->vid.turbo = value & 0x7f;
2151 }
2152
core_get_min_pstate(int cpu)2153 static int core_get_min_pstate(int cpu)
2154 {
2155 u64 value;
2156
2157 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2158 return (value >> 40) & 0xFF;
2159 }
2160
core_get_max_pstate_physical(int cpu)2161 static int core_get_max_pstate_physical(int cpu)
2162 {
2163 u64 value;
2164
2165 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2166 return (value >> 8) & 0xFF;
2167 }
2168
core_get_tdp_ratio(int cpu,u64 plat_info)2169 static int core_get_tdp_ratio(int cpu, u64 plat_info)
2170 {
2171 /* Check how many TDP levels present */
2172 if (plat_info & 0x600000000) {
2173 u64 tdp_ctrl;
2174 u64 tdp_ratio;
2175 int tdp_msr;
2176 int err;
2177
2178 /* Get the TDP level (0, 1, 2) to get ratios */
2179 err = rdmsrq_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
2180 if (err)
2181 return err;
2182
2183 /* TDP MSR are continuous starting at 0x648 */
2184 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
2185 err = rdmsrq_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
2186 if (err)
2187 return err;
2188
2189 /* For level 1 and 2, bits[23:16] contain the ratio */
2190 if (tdp_ctrl & 0x03)
2191 tdp_ratio >>= 16;
2192
2193 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
2194 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
2195
2196 return (int)tdp_ratio;
2197 }
2198
2199 return -ENXIO;
2200 }
2201
core_get_max_pstate(int cpu)2202 static int core_get_max_pstate(int cpu)
2203 {
2204 u64 tar;
2205 u64 plat_info;
2206 int max_pstate;
2207 int tdp_ratio;
2208 int err;
2209
2210 rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
2211 max_pstate = (plat_info >> 8) & 0xFF;
2212
2213 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
2214 if (tdp_ratio <= 0)
2215 return max_pstate;
2216
2217 if (hwp_active) {
2218 /* Turbo activation ratio is not used on HWP platforms */
2219 return tdp_ratio;
2220 }
2221
2222 err = rdmsrq_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
2223 if (!err) {
2224 int tar_levels;
2225
2226 /* Do some sanity checking for safety */
2227 tar_levels = tar & 0xff;
2228 if (tdp_ratio - 1 == tar_levels) {
2229 max_pstate = tar_levels;
2230 pr_debug("max_pstate=TAC %x\n", max_pstate);
2231 }
2232 }
2233
2234 return max_pstate;
2235 }
2236
core_get_turbo_pstate(int cpu)2237 static int core_get_turbo_pstate(int cpu)
2238 {
2239 u64 value;
2240 int nont, ret;
2241
2242 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2243 nont = core_get_max_pstate(cpu);
2244 ret = (value) & 255;
2245 if (ret <= nont)
2246 ret = nont;
2247 return ret;
2248 }
2249
core_get_val(struct cpudata * cpudata,int pstate)2250 static u64 core_get_val(struct cpudata *cpudata, int pstate)
2251 {
2252 return get_perf_ctl_val(pstate);
2253 }
2254
knl_get_aperf_mperf_shift(void)2255 static int knl_get_aperf_mperf_shift(void)
2256 {
2257 return 10;
2258 }
2259
knl_get_turbo_pstate(int cpu)2260 static int knl_get_turbo_pstate(int cpu)
2261 {
2262 u64 value;
2263 int nont, ret;
2264
2265 rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2266 nont = core_get_max_pstate(cpu);
2267 ret = (((value) >> 8) & 0xFF);
2268 if (ret <= nont)
2269 ret = nont;
2270 return ret;
2271 }
2272
hwp_get_cpu_scaling(int cpu)2273 static int hwp_get_cpu_scaling(int cpu)
2274 {
2275 if (hybrid_scaling_factor) {
2276 /*
2277 * Return the hybrid scaling factor for P-cores and use the
2278 * default core scaling for E-cores.
2279 */
2280 if (hybrid_get_cpu_type(cpu) == INTEL_CPU_TYPE_CORE)
2281 return hybrid_scaling_factor;
2282
2283 return core_get_scaling();
2284 }
2285
2286 /* Use core scaling on non-hybrid systems. */
2287 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
2288 return core_get_scaling();
2289
2290 /*
2291 * The system is hybrid, but the hybrid scaling factor is not known or
2292 * the CPU type is not one of the above, so use CPPC to compute the
2293 * scaling factor for this CPU.
2294 */
2295 return intel_pstate_cppc_get_scaling(cpu);
2296 }
2297
intel_pstate_set_pstate(struct cpudata * cpu,int pstate)2298 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2299 {
2300 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2301 cpu->pstate.current_pstate = pstate;
2302 /*
2303 * Generally, there is no guarantee that this code will always run on
2304 * the CPU being updated, so force the register update to run on the
2305 * right CPU.
2306 */
2307 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2308 pstate_funcs.get_val(cpu, pstate));
2309 }
2310
intel_pstate_set_min_pstate(struct cpudata * cpu)2311 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2312 {
2313 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2314 }
2315
intel_pstate_get_cpu_pstates(struct cpudata * cpu)2316 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2317 {
2318 int perf_ctl_scaling = pstate_funcs.get_scaling();
2319
2320 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(cpu->cpu);
2321 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2322 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2323
2324 if (hwp_active && !hwp_mode_bdw) {
2325 __intel_pstate_get_hwp_cap(cpu);
2326
2327 if (pstate_funcs.get_cpu_scaling) {
2328 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2329 intel_pstate_hybrid_hwp_adjust(cpu);
2330 } else {
2331 cpu->pstate.scaling = perf_ctl_scaling;
2332 }
2333 /*
2334 * If the CPU is going online for the first time and it was
2335 * offline initially, asym capacity scaling needs to be updated.
2336 */
2337 hybrid_update_capacity(cpu);
2338 } else {
2339 cpu->pstate.scaling = perf_ctl_scaling;
2340 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2341 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2342 }
2343
2344 if (cpu->pstate.scaling == perf_ctl_scaling) {
2345 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2346 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2347 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2348 }
2349
2350 if (pstate_funcs.get_aperf_mperf_shift)
2351 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2352
2353 if (pstate_funcs.get_vid)
2354 pstate_funcs.get_vid(cpu);
2355
2356 intel_pstate_set_min_pstate(cpu);
2357 }
2358
2359 /*
2360 * Long hold time will keep high perf limits for long time,
2361 * which negatively impacts perf/watt for some workloads,
2362 * like specpower. 3ms is based on experiements on some
2363 * workoads.
2364 */
2365 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2366
intel_pstate_hwp_boost_up(struct cpudata * cpu)2367 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2368 {
2369 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2370 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2371 u32 max_limit = (hwp_req & 0xff00) >> 8;
2372 u32 min_limit = (hwp_req & 0xff);
2373 u32 boost_level1;
2374
2375 /*
2376 * Cases to consider (User changes via sysfs or boot time):
2377 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2378 * No boost, return.
2379 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2380 * Should result in one level boost only for P0.
2381 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2382 * Should result in two level boost:
2383 * (min + p1)/2 and P1.
2384 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2385 * Should result in three level boost:
2386 * (min + p1)/2, P1 and P0.
2387 */
2388
2389 /* If max and min are equal or already at max, nothing to boost */
2390 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2391 return;
2392
2393 if (!cpu->hwp_boost_min)
2394 cpu->hwp_boost_min = min_limit;
2395
2396 /* level at half way mark between min and guranteed */
2397 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2398
2399 if (cpu->hwp_boost_min < boost_level1)
2400 cpu->hwp_boost_min = boost_level1;
2401 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2402 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2403 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2404 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2405 cpu->hwp_boost_min = max_limit;
2406 else
2407 return;
2408
2409 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2410 wrmsrq(MSR_HWP_REQUEST, hwp_req);
2411 cpu->last_update = cpu->sample.time;
2412 }
2413
intel_pstate_hwp_boost_down(struct cpudata * cpu)2414 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2415 {
2416 if (cpu->hwp_boost_min) {
2417 bool expired;
2418
2419 /* Check if we are idle for hold time to boost down */
2420 expired = time_after64(cpu->sample.time, cpu->last_update +
2421 hwp_boost_hold_time_ns);
2422 if (expired) {
2423 wrmsrq(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2424 cpu->hwp_boost_min = 0;
2425 }
2426 }
2427 cpu->last_update = cpu->sample.time;
2428 }
2429
intel_pstate_update_util_hwp_local(struct cpudata * cpu,u64 time)2430 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2431 u64 time)
2432 {
2433 cpu->sample.time = time;
2434
2435 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2436 bool do_io = false;
2437
2438 cpu->sched_flags = 0;
2439 /*
2440 * Set iowait_boost flag and update time. Since IO WAIT flag
2441 * is set all the time, we can't just conclude that there is
2442 * some IO bound activity is scheduled on this CPU with just
2443 * one occurrence. If we receive at least two in two
2444 * consecutive ticks, then we treat as boost candidate.
2445 */
2446 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2447 do_io = true;
2448
2449 cpu->last_io_update = time;
2450
2451 if (do_io)
2452 intel_pstate_hwp_boost_up(cpu);
2453
2454 } else {
2455 intel_pstate_hwp_boost_down(cpu);
2456 }
2457 }
2458
intel_pstate_update_util_hwp(struct update_util_data * data,u64 time,unsigned int flags)2459 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2460 u64 time, unsigned int flags)
2461 {
2462 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2463
2464 cpu->sched_flags |= flags;
2465
2466 if (smp_processor_id() == cpu->cpu)
2467 intel_pstate_update_util_hwp_local(cpu, time);
2468 }
2469
intel_pstate_calc_avg_perf(struct cpudata * cpu)2470 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2471 {
2472 struct sample *sample = &cpu->sample;
2473
2474 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2475 }
2476
intel_pstate_sample(struct cpudata * cpu,u64 time)2477 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2478 {
2479 u64 aperf, mperf;
2480 unsigned long flags;
2481 u64 tsc;
2482
2483 local_irq_save(flags);
2484 rdmsrq(MSR_IA32_APERF, aperf);
2485 rdmsrq(MSR_IA32_MPERF, mperf);
2486 tsc = rdtsc();
2487 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2488 local_irq_restore(flags);
2489 return false;
2490 }
2491 local_irq_restore(flags);
2492
2493 cpu->last_sample_time = cpu->sample.time;
2494 cpu->sample.time = time;
2495 cpu->sample.aperf = aperf;
2496 cpu->sample.mperf = mperf;
2497 cpu->sample.tsc = tsc;
2498 cpu->sample.aperf -= cpu->prev_aperf;
2499 cpu->sample.mperf -= cpu->prev_mperf;
2500 cpu->sample.tsc -= cpu->prev_tsc;
2501
2502 cpu->prev_aperf = aperf;
2503 cpu->prev_mperf = mperf;
2504 cpu->prev_tsc = tsc;
2505 /*
2506 * First time this function is invoked in a given cycle, all of the
2507 * previous sample data fields are equal to zero or stale and they must
2508 * be populated with meaningful numbers for things to work, so assume
2509 * that sample.time will always be reset before setting the utilization
2510 * update hook and make the caller skip the sample then.
2511 */
2512 if (likely(cpu->last_sample_time)) {
2513 intel_pstate_calc_avg_perf(cpu);
2514 return true;
2515 }
2516 return false;
2517 }
2518
get_avg_frequency(struct cpudata * cpu)2519 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2520 {
2521 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2522 }
2523
get_avg_pstate(struct cpudata * cpu)2524 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2525 {
2526 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2527 cpu->sample.core_avg_perf);
2528 }
2529
get_target_pstate(struct cpudata * cpu)2530 static inline int32_t get_target_pstate(struct cpudata *cpu)
2531 {
2532 struct sample *sample = &cpu->sample;
2533 int32_t busy_frac;
2534 int target, avg_pstate;
2535
2536 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2537 sample->tsc);
2538
2539 if (busy_frac < cpu->iowait_boost)
2540 busy_frac = cpu->iowait_boost;
2541
2542 sample->busy_scaled = busy_frac * 100;
2543
2544 target = READ_ONCE(global.no_turbo) ?
2545 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2546 target += target >> 2;
2547 target = mul_fp(target, busy_frac);
2548 if (target < cpu->pstate.min_pstate)
2549 target = cpu->pstate.min_pstate;
2550
2551 /*
2552 * If the average P-state during the previous cycle was higher than the
2553 * current target, add 50% of the difference to the target to reduce
2554 * possible performance oscillations and offset possible performance
2555 * loss related to moving the workload from one CPU to another within
2556 * a package/module.
2557 */
2558 avg_pstate = get_avg_pstate(cpu);
2559 if (avg_pstate > target)
2560 target += (avg_pstate - target) >> 1;
2561
2562 return target;
2563 }
2564
intel_pstate_prepare_request(struct cpudata * cpu,int pstate)2565 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2566 {
2567 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2568 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2569
2570 return clamp_t(int, pstate, min_pstate, max_pstate);
2571 }
2572
intel_pstate_update_pstate(struct cpudata * cpu,int pstate)2573 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2574 {
2575 if (pstate == cpu->pstate.current_pstate)
2576 return;
2577
2578 cpu->pstate.current_pstate = pstate;
2579 wrmsrq(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2580 }
2581
intel_pstate_adjust_pstate(struct cpudata * cpu)2582 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2583 {
2584 int from = cpu->pstate.current_pstate;
2585 struct sample *sample;
2586 int target_pstate;
2587
2588 target_pstate = get_target_pstate(cpu);
2589 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2590 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2591 intel_pstate_update_pstate(cpu, target_pstate);
2592
2593 sample = &cpu->sample;
2594 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2595 fp_toint(sample->busy_scaled),
2596 from,
2597 cpu->pstate.current_pstate,
2598 sample->mperf,
2599 sample->aperf,
2600 sample->tsc,
2601 get_avg_frequency(cpu),
2602 fp_toint(cpu->iowait_boost * 100));
2603 }
2604
intel_pstate_update_util(struct update_util_data * data,u64 time,unsigned int flags)2605 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2606 unsigned int flags)
2607 {
2608 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2609 u64 delta_ns;
2610
2611 /* Don't allow remote callbacks */
2612 if (smp_processor_id() != cpu->cpu)
2613 return;
2614
2615 delta_ns = time - cpu->last_update;
2616 if (flags & SCHED_CPUFREQ_IOWAIT) {
2617 /* Start over if the CPU may have been idle. */
2618 if (delta_ns > TICK_NSEC) {
2619 cpu->iowait_boost = ONE_EIGHTH_FP;
2620 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2621 cpu->iowait_boost <<= 1;
2622 if (cpu->iowait_boost > int_tofp(1))
2623 cpu->iowait_boost = int_tofp(1);
2624 } else {
2625 cpu->iowait_boost = ONE_EIGHTH_FP;
2626 }
2627 } else if (cpu->iowait_boost) {
2628 /* Clear iowait_boost if the CPU may have been idle. */
2629 if (delta_ns > TICK_NSEC)
2630 cpu->iowait_boost = 0;
2631 else
2632 cpu->iowait_boost >>= 1;
2633 }
2634 cpu->last_update = time;
2635 delta_ns = time - cpu->sample.time;
2636 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2637 return;
2638
2639 if (intel_pstate_sample(cpu, time))
2640 intel_pstate_adjust_pstate(cpu);
2641 }
2642
2643 static struct pstate_funcs core_funcs = {
2644 .get_max = core_get_max_pstate,
2645 .get_max_physical = core_get_max_pstate_physical,
2646 .get_min = core_get_min_pstate,
2647 .get_turbo = core_get_turbo_pstate,
2648 .get_scaling = core_get_scaling,
2649 .get_val = core_get_val,
2650 };
2651
2652 static const struct pstate_funcs silvermont_funcs = {
2653 .get_max = atom_get_max_pstate,
2654 .get_max_physical = atom_get_max_pstate,
2655 .get_min = atom_get_min_pstate,
2656 .get_turbo = atom_get_turbo_pstate,
2657 .get_val = atom_get_val,
2658 .get_scaling = silvermont_get_scaling,
2659 .get_vid = atom_get_vid,
2660 };
2661
2662 static const struct pstate_funcs airmont_funcs = {
2663 .get_max = atom_get_max_pstate,
2664 .get_max_physical = atom_get_max_pstate,
2665 .get_min = atom_get_min_pstate,
2666 .get_turbo = atom_get_turbo_pstate,
2667 .get_val = atom_get_val,
2668 .get_scaling = airmont_get_scaling,
2669 .get_vid = atom_get_vid,
2670 };
2671
2672 static const struct pstate_funcs knl_funcs = {
2673 .get_max = core_get_max_pstate,
2674 .get_max_physical = core_get_max_pstate_physical,
2675 .get_min = core_get_min_pstate,
2676 .get_turbo = knl_get_turbo_pstate,
2677 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2678 .get_scaling = core_get_scaling,
2679 .get_val = core_get_val,
2680 };
2681
2682 #define X86_MATCH(vfm, policy) \
2683 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy)
2684
2685 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2686 X86_MATCH(INTEL_SANDYBRIDGE, core_funcs),
2687 X86_MATCH(INTEL_SANDYBRIDGE_X, core_funcs),
2688 X86_MATCH(INTEL_ATOM_SILVERMONT, silvermont_funcs),
2689 X86_MATCH(INTEL_IVYBRIDGE, core_funcs),
2690 X86_MATCH(INTEL_HASWELL, core_funcs),
2691 X86_MATCH(INTEL_BROADWELL, core_funcs),
2692 X86_MATCH(INTEL_IVYBRIDGE_X, core_funcs),
2693 X86_MATCH(INTEL_HASWELL_X, core_funcs),
2694 X86_MATCH(INTEL_HASWELL_L, core_funcs),
2695 X86_MATCH(INTEL_HASWELL_G, core_funcs),
2696 X86_MATCH(INTEL_BROADWELL_G, core_funcs),
2697 X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs),
2698 X86_MATCH(INTEL_SKYLAKE_L, core_funcs),
2699 X86_MATCH(INTEL_BROADWELL_X, core_funcs),
2700 X86_MATCH(INTEL_SKYLAKE, core_funcs),
2701 X86_MATCH(INTEL_BROADWELL_D, core_funcs),
2702 X86_MATCH(INTEL_XEON_PHI_KNL, knl_funcs),
2703 X86_MATCH(INTEL_XEON_PHI_KNM, knl_funcs),
2704 X86_MATCH(INTEL_ATOM_GOLDMONT, core_funcs),
2705 X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS, core_funcs),
2706 X86_MATCH(INTEL_SKYLAKE_X, core_funcs),
2707 X86_MATCH(INTEL_COMETLAKE, core_funcs),
2708 X86_MATCH(INTEL_ICELAKE_X, core_funcs),
2709 X86_MATCH(INTEL_TIGERLAKE, core_funcs),
2710 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs),
2711 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs),
2712 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs),
2713 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs),
2714 {}
2715 };
2716 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2717
2718 #ifdef CONFIG_ACPI
2719 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2720 X86_MATCH(INTEL_BROADWELL_D, core_funcs),
2721 X86_MATCH(INTEL_BROADWELL_X, core_funcs),
2722 X86_MATCH(INTEL_SKYLAKE_X, core_funcs),
2723 X86_MATCH(INTEL_ICELAKE_X, core_funcs),
2724 X86_MATCH(INTEL_SAPPHIRERAPIDS_X, core_funcs),
2725 X86_MATCH(INTEL_EMERALDRAPIDS_X, core_funcs),
2726 X86_MATCH(INTEL_GRANITERAPIDS_D, core_funcs),
2727 X86_MATCH(INTEL_GRANITERAPIDS_X, core_funcs),
2728 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs),
2729 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs),
2730 X86_MATCH(INTEL_ATOM_DARKMONT_X, core_funcs),
2731 X86_MATCH(INTEL_DIAMONDRAPIDS_X, core_funcs),
2732 {}
2733 };
2734 #endif
2735
2736 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2737 X86_MATCH(INTEL_KABYLAKE, core_funcs),
2738 {}
2739 };
2740
intel_pstate_init_cpu(unsigned int cpunum)2741 static int intel_pstate_init_cpu(unsigned int cpunum)
2742 {
2743 struct cpudata *cpu;
2744
2745 cpu = all_cpu_data[cpunum];
2746
2747 if (!cpu) {
2748 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2749 if (!cpu)
2750 return -ENOMEM;
2751
2752 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2753
2754 cpu->cpu = cpunum;
2755
2756 cpu->epp_default = -EINVAL;
2757
2758 if (hwp_active) {
2759 intel_pstate_hwp_enable(cpu);
2760
2761 if (intel_pstate_acpi_pm_profile_server())
2762 hwp_boost = true;
2763 }
2764 } else if (hwp_active) {
2765 /*
2766 * Re-enable HWP in case this happens after a resume from ACPI
2767 * S3 if the CPU was offline during the whole system/resume
2768 * cycle.
2769 */
2770 intel_pstate_hwp_reenable(cpu);
2771 }
2772
2773 cpu->epp_powersave = -EINVAL;
2774 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
2775
2776 intel_pstate_get_cpu_pstates(cpu);
2777
2778 pr_debug("controlling: cpu %d\n", cpunum);
2779
2780 return 0;
2781 }
2782
intel_pstate_set_update_util_hook(unsigned int cpu_num)2783 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2784 {
2785 struct cpudata *cpu = all_cpu_data[cpu_num];
2786
2787 if (hwp_active && !hwp_boost)
2788 return;
2789
2790 if (cpu->update_util_set)
2791 return;
2792
2793 /* Prevent intel_pstate_update_util() from using stale data. */
2794 cpu->sample.time = 0;
2795 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2796 (hwp_active ?
2797 intel_pstate_update_util_hwp :
2798 intel_pstate_update_util));
2799 cpu->update_util_set = true;
2800 }
2801
intel_pstate_clear_update_util_hook(unsigned int cpu)2802 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2803 {
2804 struct cpudata *cpu_data = all_cpu_data[cpu];
2805
2806 if (!cpu_data->update_util_set)
2807 return;
2808
2809 cpufreq_remove_update_util_hook(cpu);
2810 cpu_data->update_util_set = false;
2811 synchronize_rcu();
2812 }
2813
intel_pstate_get_max_freq(struct cpudata * cpu)2814 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2815 {
2816 return READ_ONCE(global.no_turbo) ?
2817 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2818 }
2819
intel_pstate_update_perf_limits(struct cpudata * cpu,unsigned int policy_min,unsigned int policy_max)2820 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2821 unsigned int policy_min,
2822 unsigned int policy_max)
2823 {
2824 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2825 int32_t max_policy_perf, min_policy_perf;
2826
2827 max_policy_perf = policy_max / perf_ctl_scaling;
2828 if (policy_max == policy_min) {
2829 min_policy_perf = max_policy_perf;
2830 } else {
2831 min_policy_perf = policy_min / perf_ctl_scaling;
2832 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2833 0, max_policy_perf);
2834 }
2835
2836 /*
2837 * HWP needs some special consideration, because HWP_REQUEST uses
2838 * abstract values to represent performance rather than pure ratios.
2839 */
2840 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2841 int freq;
2842
2843 freq = max_policy_perf * perf_ctl_scaling;
2844 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2845 freq = min_policy_perf * perf_ctl_scaling;
2846 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2847 }
2848
2849 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2850 cpu->cpu, min_policy_perf, max_policy_perf);
2851
2852 /* Normalize user input to [min_perf, max_perf] */
2853 if (per_cpu_limits) {
2854 cpu->min_perf_ratio = min_policy_perf;
2855 cpu->max_perf_ratio = max_policy_perf;
2856 } else {
2857 int turbo_max = cpu->pstate.turbo_pstate;
2858 int32_t global_min, global_max;
2859
2860 /* Global limits are in percent of the maximum turbo P-state. */
2861 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2862 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2863 global_min = clamp_t(int32_t, global_min, 0, global_max);
2864
2865 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2866 global_min, global_max);
2867
2868 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2869 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2870 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2871 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2872
2873 /* Make sure min_perf <= max_perf */
2874 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2875 cpu->max_perf_ratio);
2876
2877 }
2878 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2879 cpu->max_perf_ratio,
2880 cpu->min_perf_ratio);
2881 }
2882
intel_pstate_set_policy(struct cpufreq_policy * policy)2883 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2884 {
2885 struct cpudata *cpu;
2886
2887 if (!policy->cpuinfo.max_freq)
2888 return -ENODEV;
2889
2890 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2891 policy->cpuinfo.max_freq, policy->max);
2892
2893 cpu = all_cpu_data[policy->cpu];
2894 cpu->policy = policy->policy;
2895
2896 mutex_lock(&intel_pstate_limits_lock);
2897
2898 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2899
2900 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2901 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2902
2903 /*
2904 * NOHZ_FULL CPUs need this as the governor callback may not
2905 * be invoked on them.
2906 */
2907 intel_pstate_clear_update_util_hook(policy->cpu);
2908 intel_pstate_set_pstate(cpu, pstate);
2909 } else {
2910 intel_pstate_set_update_util_hook(policy->cpu);
2911 }
2912
2913 if (hwp_active) {
2914 /*
2915 * When hwp_boost was active before and dynamically it
2916 * was turned off, in that case we need to clear the
2917 * update util hook.
2918 */
2919 if (!hwp_boost)
2920 intel_pstate_clear_update_util_hook(policy->cpu);
2921 intel_pstate_hwp_set(policy->cpu);
2922 }
2923 /*
2924 * policy->cur is never updated with the intel_pstate driver, but it
2925 * is used as a stale frequency value. So, keep it within limits.
2926 */
2927 policy->cur = policy->min;
2928
2929 mutex_unlock(&intel_pstate_limits_lock);
2930
2931 return 0;
2932 }
2933
intel_pstate_adjust_policy_max(struct cpudata * cpu,struct cpufreq_policy_data * policy)2934 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2935 struct cpufreq_policy_data *policy)
2936 {
2937 if (!hwp_active &&
2938 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2939 policy->max < policy->cpuinfo.max_freq &&
2940 policy->max > cpu->pstate.max_freq) {
2941 pr_debug("policy->max > max non turbo frequency\n");
2942 policy->max = policy->cpuinfo.max_freq;
2943 }
2944 }
2945
intel_pstate_verify_cpu_policy(struct cpudata * cpu,struct cpufreq_policy_data * policy)2946 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2947 struct cpufreq_policy_data *policy)
2948 {
2949 int max_freq;
2950
2951 if (hwp_active) {
2952 intel_pstate_get_hwp_cap(cpu);
2953 max_freq = READ_ONCE(global.no_turbo) ?
2954 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2955 } else {
2956 max_freq = intel_pstate_get_max_freq(cpu);
2957 }
2958 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2959
2960 intel_pstate_adjust_policy_max(cpu, policy);
2961 }
2962
intel_pstate_verify_policy(struct cpufreq_policy_data * policy)2963 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2964 {
2965 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2966
2967 return 0;
2968 }
2969
intel_cpufreq_cpu_offline(struct cpufreq_policy * policy)2970 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2971 {
2972 struct cpudata *cpu = all_cpu_data[policy->cpu];
2973
2974 pr_debug("CPU %d going offline\n", cpu->cpu);
2975
2976 if (cpu->suspended)
2977 return 0;
2978
2979 /*
2980 * If the CPU is an SMT thread and it goes offline with the performance
2981 * settings different from the minimum, it will prevent its sibling
2982 * from getting to lower performance levels, so force the minimum
2983 * performance on CPU offline to prevent that from happening.
2984 */
2985 if (hwp_active)
2986 intel_pstate_hwp_offline(cpu);
2987 else
2988 intel_pstate_set_min_pstate(cpu);
2989
2990 intel_pstate_exit_perf_limits(policy);
2991
2992 return 0;
2993 }
2994
intel_pstate_cpu_online(struct cpufreq_policy * policy)2995 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2996 {
2997 struct cpudata *cpu = all_cpu_data[policy->cpu];
2998
2999 pr_debug("CPU %d going online\n", cpu->cpu);
3000
3001 intel_pstate_init_acpi_perf_limits(policy);
3002
3003 if (hwp_active) {
3004 /*
3005 * Re-enable HWP and clear the "suspended" flag to let "resume"
3006 * know that it need not do that.
3007 */
3008 intel_pstate_hwp_reenable(cpu);
3009 cpu->suspended = false;
3010
3011 hybrid_update_capacity(cpu);
3012 }
3013
3014 return 0;
3015 }
3016
intel_pstate_cpu_offline(struct cpufreq_policy * policy)3017 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
3018 {
3019 intel_pstate_clear_update_util_hook(policy->cpu);
3020
3021 return intel_cpufreq_cpu_offline(policy);
3022 }
3023
intel_pstate_cpu_exit(struct cpufreq_policy * policy)3024 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy)
3025 {
3026 pr_debug("CPU %d exiting\n", policy->cpu);
3027
3028 policy->fast_switch_possible = false;
3029 }
3030
__intel_pstate_cpu_init(struct cpufreq_policy * policy)3031 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
3032 {
3033 struct cpudata *cpu;
3034 int rc;
3035
3036 rc = intel_pstate_init_cpu(policy->cpu);
3037 if (rc)
3038 return rc;
3039
3040 cpu = all_cpu_data[policy->cpu];
3041
3042 cpu->max_perf_ratio = 0xFF;
3043 cpu->min_perf_ratio = 0;
3044
3045 /* cpuinfo and default policy values */
3046 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
3047 policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
3048 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
3049
3050 policy->min = policy->cpuinfo.min_freq;
3051 policy->max = policy->cpuinfo.max_freq;
3052
3053 intel_pstate_init_acpi_perf_limits(policy);
3054
3055 policy->fast_switch_possible = true;
3056
3057 return 0;
3058 }
3059
intel_pstate_cpu_init(struct cpufreq_policy * policy)3060 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
3061 {
3062 int ret = __intel_pstate_cpu_init(policy);
3063
3064 if (ret)
3065 return ret;
3066
3067 /*
3068 * Set the policy to powersave to provide a valid fallback value in case
3069 * the default cpufreq governor is neither powersave nor performance.
3070 */
3071 policy->policy = CPUFREQ_POLICY_POWERSAVE;
3072
3073 if (hwp_active) {
3074 struct cpudata *cpu = all_cpu_data[policy->cpu];
3075
3076 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
3077 }
3078
3079 return 0;
3080 }
3081
3082 static struct cpufreq_driver intel_pstate = {
3083 .flags = CPUFREQ_CONST_LOOPS,
3084 .verify = intel_pstate_verify_policy,
3085 .setpolicy = intel_pstate_set_policy,
3086 .suspend = intel_pstate_suspend,
3087 .resume = intel_pstate_resume,
3088 .init = intel_pstate_cpu_init,
3089 .exit = intel_pstate_cpu_exit,
3090 .offline = intel_pstate_cpu_offline,
3091 .online = intel_pstate_cpu_online,
3092 .update_limits = intel_pstate_update_limits,
3093 .name = "intel_pstate",
3094 };
3095
intel_cpufreq_verify_policy(struct cpufreq_policy_data * policy)3096 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
3097 {
3098 struct cpudata *cpu = all_cpu_data[policy->cpu];
3099
3100 intel_pstate_verify_cpu_policy(cpu, policy);
3101 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
3102
3103 return 0;
3104 }
3105
3106 /* Use of trace in passive mode:
3107 *
3108 * In passive mode the trace core_busy field (also known as the
3109 * performance field, and lablelled as such on the graphs; also known as
3110 * core_avg_perf) is not needed and so is re-assigned to indicate if the
3111 * driver call was via the normal or fast switch path. Various graphs
3112 * output from the intel_pstate_tracer.py utility that include core_busy
3113 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
3114 * so we use 10 to indicate the normal path through the driver, and
3115 * 90 to indicate the fast switch path through the driver.
3116 * The scaled_busy field is not used, and is set to 0.
3117 */
3118
3119 #define INTEL_PSTATE_TRACE_TARGET 10
3120 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
3121
intel_cpufreq_trace(struct cpudata * cpu,unsigned int trace_type,int old_pstate)3122 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
3123 {
3124 struct sample *sample;
3125
3126 if (!trace_pstate_sample_enabled())
3127 return;
3128
3129 if (!intel_pstate_sample(cpu, ktime_get()))
3130 return;
3131
3132 sample = &cpu->sample;
3133 trace_pstate_sample(trace_type,
3134 0,
3135 old_pstate,
3136 cpu->pstate.current_pstate,
3137 sample->mperf,
3138 sample->aperf,
3139 sample->tsc,
3140 get_avg_frequency(cpu),
3141 fp_toint(cpu->iowait_boost * 100));
3142 }
3143
intel_cpufreq_hwp_update(struct cpudata * cpu,u32 min,u32 max,u32 desired,bool fast_switch)3144 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
3145 u32 desired, bool fast_switch)
3146 {
3147 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
3148
3149 value &= ~HWP_MIN_PERF(~0L);
3150 value |= HWP_MIN_PERF(min);
3151
3152 value &= ~HWP_MAX_PERF(~0L);
3153 value |= HWP_MAX_PERF(max);
3154
3155 value &= ~HWP_DESIRED_PERF(~0L);
3156 value |= HWP_DESIRED_PERF(desired);
3157
3158 if (value == prev)
3159 return;
3160
3161 WRITE_ONCE(cpu->hwp_req_cached, value);
3162 if (fast_switch)
3163 wrmsrq(MSR_HWP_REQUEST, value);
3164 else
3165 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3166 }
3167
intel_cpufreq_perf_ctl_update(struct cpudata * cpu,u32 target_pstate,bool fast_switch)3168 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
3169 u32 target_pstate, bool fast_switch)
3170 {
3171 if (fast_switch)
3172 wrmsrq(MSR_IA32_PERF_CTL,
3173 pstate_funcs.get_val(cpu, target_pstate));
3174 else
3175 wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
3176 pstate_funcs.get_val(cpu, target_pstate));
3177 }
3178
intel_cpufreq_update_pstate(struct cpufreq_policy * policy,int target_pstate,bool fast_switch)3179 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
3180 int target_pstate, bool fast_switch)
3181 {
3182 struct cpudata *cpu = all_cpu_data[policy->cpu];
3183 int old_pstate = cpu->pstate.current_pstate;
3184
3185 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
3186 if (hwp_active) {
3187 int max_pstate = policy->strict_target ?
3188 target_pstate : cpu->max_perf_ratio;
3189
3190 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate,
3191 target_pstate, fast_switch);
3192 } else if (target_pstate != old_pstate) {
3193 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
3194 }
3195
3196 cpu->pstate.current_pstate = target_pstate;
3197
3198 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
3199 INTEL_PSTATE_TRACE_TARGET, old_pstate);
3200
3201 return target_pstate;
3202 }
3203
intel_cpufreq_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)3204 static int intel_cpufreq_target(struct cpufreq_policy *policy,
3205 unsigned int target_freq,
3206 unsigned int relation)
3207 {
3208 struct cpudata *cpu = all_cpu_data[policy->cpu];
3209 struct cpufreq_freqs freqs;
3210 int target_pstate;
3211
3212 freqs.old = policy->cur;
3213 freqs.new = target_freq;
3214
3215 cpufreq_freq_transition_begin(policy, &freqs);
3216
3217 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
3218 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
3219
3220 freqs.new = target_pstate * cpu->pstate.scaling;
3221
3222 cpufreq_freq_transition_end(policy, &freqs, false);
3223
3224 return 0;
3225 }
3226
intel_cpufreq_fast_switch(struct cpufreq_policy * policy,unsigned int target_freq)3227 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
3228 unsigned int target_freq)
3229 {
3230 struct cpudata *cpu = all_cpu_data[policy->cpu];
3231 int target_pstate;
3232
3233 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
3234
3235 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
3236
3237 return target_pstate * cpu->pstate.scaling;
3238 }
3239
intel_cpufreq_adjust_perf(unsigned int cpunum,unsigned long min_perf,unsigned long target_perf,unsigned long capacity)3240 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
3241 unsigned long min_perf,
3242 unsigned long target_perf,
3243 unsigned long capacity)
3244 {
3245 struct cpudata *cpu = all_cpu_data[cpunum];
3246 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
3247 int old_pstate = cpu->pstate.current_pstate;
3248 int cap_pstate, min_pstate, max_pstate, target_pstate;
3249
3250 cap_pstate = READ_ONCE(global.no_turbo) ?
3251 HWP_GUARANTEED_PERF(hwp_cap) :
3252 HWP_HIGHEST_PERF(hwp_cap);
3253
3254 /* Optimization: Avoid unnecessary divisions. */
3255
3256 target_pstate = cap_pstate;
3257 if (target_perf < capacity)
3258 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
3259
3260 min_pstate = cap_pstate;
3261 if (min_perf < capacity)
3262 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
3263
3264 if (min_pstate < cpu->pstate.min_pstate)
3265 min_pstate = cpu->pstate.min_pstate;
3266
3267 if (min_pstate < cpu->min_perf_ratio)
3268 min_pstate = cpu->min_perf_ratio;
3269
3270 if (min_pstate > cpu->max_perf_ratio)
3271 min_pstate = cpu->max_perf_ratio;
3272
3273 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
3274 if (max_pstate < min_pstate)
3275 max_pstate = min_pstate;
3276
3277 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
3278
3279 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
3280
3281 cpu->pstate.current_pstate = target_pstate;
3282 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3283 }
3284
intel_cpufreq_cpu_init(struct cpufreq_policy * policy)3285 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3286 {
3287 struct freq_qos_request *req;
3288 struct cpudata *cpu;
3289 struct device *dev;
3290 int ret, freq;
3291
3292 dev = get_cpu_device(policy->cpu);
3293 if (!dev)
3294 return -ENODEV;
3295
3296 ret = __intel_pstate_cpu_init(policy);
3297 if (ret)
3298 return ret;
3299
3300 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3301 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3302 policy->cur = policy->cpuinfo.min_freq;
3303
3304 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3305 if (!req) {
3306 ret = -ENOMEM;
3307 goto pstate_exit;
3308 }
3309
3310 cpu = all_cpu_data[policy->cpu];
3311
3312 if (hwp_active) {
3313 u64 value;
3314
3315 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3316
3317 intel_pstate_get_hwp_cap(cpu);
3318
3319 rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3320 WRITE_ONCE(cpu->hwp_req_cached, value);
3321
3322 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3323 } else {
3324 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3325 }
3326
3327 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3328
3329 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3330 freq);
3331 if (ret < 0) {
3332 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3333 goto free_req;
3334 }
3335
3336 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3337
3338 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3339 freq);
3340 if (ret < 0) {
3341 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3342 goto remove_min_req;
3343 }
3344
3345 policy->driver_data = req;
3346
3347 return 0;
3348
3349 remove_min_req:
3350 freq_qos_remove_request(req);
3351 free_req:
3352 kfree(req);
3353 pstate_exit:
3354 intel_pstate_exit_perf_limits(policy);
3355
3356 return ret;
3357 }
3358
intel_cpufreq_cpu_exit(struct cpufreq_policy * policy)3359 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3360 {
3361 struct freq_qos_request *req;
3362
3363 req = policy->driver_data;
3364
3365 freq_qos_remove_request(req + 1);
3366 freq_qos_remove_request(req);
3367 kfree(req);
3368
3369 intel_pstate_cpu_exit(policy);
3370 }
3371
intel_cpufreq_suspend(struct cpufreq_policy * policy)3372 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3373 {
3374 intel_pstate_suspend(policy);
3375
3376 if (hwp_active) {
3377 struct cpudata *cpu = all_cpu_data[policy->cpu];
3378 u64 value = READ_ONCE(cpu->hwp_req_cached);
3379
3380 /*
3381 * Clear the desired perf field in MSR_HWP_REQUEST in case
3382 * intel_cpufreq_adjust_perf() is in use and the last value
3383 * written by it may not be suitable.
3384 */
3385 value &= ~HWP_DESIRED_PERF(~0L);
3386 wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3387 WRITE_ONCE(cpu->hwp_req_cached, value);
3388 }
3389
3390 return 0;
3391 }
3392
3393 static struct cpufreq_driver intel_cpufreq = {
3394 .flags = CPUFREQ_CONST_LOOPS,
3395 .verify = intel_cpufreq_verify_policy,
3396 .target = intel_cpufreq_target,
3397 .fast_switch = intel_cpufreq_fast_switch,
3398 .init = intel_cpufreq_cpu_init,
3399 .exit = intel_cpufreq_cpu_exit,
3400 .offline = intel_cpufreq_cpu_offline,
3401 .online = intel_pstate_cpu_online,
3402 .suspend = intel_cpufreq_suspend,
3403 .resume = intel_pstate_resume,
3404 .update_limits = intel_pstate_update_limits,
3405 .name = "intel_cpufreq",
3406 };
3407
3408 static struct cpufreq_driver *default_driver;
3409
intel_pstate_driver_cleanup(void)3410 static void intel_pstate_driver_cleanup(void)
3411 {
3412 unsigned int cpu;
3413
3414 cpus_read_lock();
3415 for_each_online_cpu(cpu) {
3416 if (all_cpu_data[cpu]) {
3417 if (intel_pstate_driver == &intel_pstate)
3418 intel_pstate_clear_update_util_hook(cpu);
3419
3420 kfree(all_cpu_data[cpu]);
3421 WRITE_ONCE(all_cpu_data[cpu], NULL);
3422 }
3423 }
3424 cpus_read_unlock();
3425
3426 intel_pstate_driver = NULL;
3427 }
3428
intel_pstate_register_driver(struct cpufreq_driver * driver)3429 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3430 {
3431 bool refresh_cpu_cap_scaling;
3432 int ret;
3433
3434 if (driver == &intel_pstate)
3435 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3436
3437 memset(&global, 0, sizeof(global));
3438 global.max_perf_pct = 100;
3439 global.turbo_disabled = turbo_is_disabled();
3440 global.no_turbo = global.turbo_disabled;
3441
3442 arch_set_max_freq_ratio(global.turbo_disabled);
3443
3444 refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu();
3445
3446 intel_pstate_driver = driver;
3447 ret = cpufreq_register_driver(intel_pstate_driver);
3448 if (ret) {
3449 intel_pstate_driver_cleanup();
3450 return ret;
3451 }
3452
3453 global.min_perf_pct = min_perf_pct_min();
3454
3455 hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling);
3456
3457 return 0;
3458 }
3459
intel_pstate_show_status(char * buf)3460 static ssize_t intel_pstate_show_status(char *buf)
3461 {
3462 if (!intel_pstate_driver)
3463 return sprintf(buf, "off\n");
3464
3465 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3466 "active" : "passive");
3467 }
3468
intel_pstate_update_status(const char * buf,size_t size)3469 static int intel_pstate_update_status(const char *buf, size_t size)
3470 {
3471 if (size == 3 && !strncmp(buf, "off", size)) {
3472 if (!intel_pstate_driver)
3473 return -EINVAL;
3474
3475 if (hwp_active)
3476 return -EBUSY;
3477
3478 cpufreq_unregister_driver(intel_pstate_driver);
3479 intel_pstate_driver_cleanup();
3480 return 0;
3481 }
3482
3483 if (size == 6 && !strncmp(buf, "active", size)) {
3484 if (intel_pstate_driver) {
3485 if (intel_pstate_driver == &intel_pstate)
3486 return 0;
3487
3488 cpufreq_unregister_driver(intel_pstate_driver);
3489 }
3490
3491 return intel_pstate_register_driver(&intel_pstate);
3492 }
3493
3494 if (size == 7 && !strncmp(buf, "passive", size)) {
3495 if (intel_pstate_driver) {
3496 if (intel_pstate_driver == &intel_cpufreq)
3497 return 0;
3498
3499 cpufreq_unregister_driver(intel_pstate_driver);
3500 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3501 }
3502
3503 return intel_pstate_register_driver(&intel_cpufreq);
3504 }
3505
3506 return -EINVAL;
3507 }
3508
3509 static int no_load __initdata;
3510 static int no_hwp __initdata;
3511 static int hwp_only __initdata;
3512 static unsigned int force_load __initdata;
3513
intel_pstate_msrs_not_valid(void)3514 static int __init intel_pstate_msrs_not_valid(void)
3515 {
3516 if (!pstate_funcs.get_max(0) ||
3517 !pstate_funcs.get_min(0) ||
3518 !pstate_funcs.get_turbo(0))
3519 return -ENODEV;
3520
3521 return 0;
3522 }
3523
copy_cpu_funcs(struct pstate_funcs * funcs)3524 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3525 {
3526 pstate_funcs.get_max = funcs->get_max;
3527 pstate_funcs.get_max_physical = funcs->get_max_physical;
3528 pstate_funcs.get_min = funcs->get_min;
3529 pstate_funcs.get_turbo = funcs->get_turbo;
3530 pstate_funcs.get_scaling = funcs->get_scaling;
3531 pstate_funcs.get_val = funcs->get_val;
3532 pstate_funcs.get_vid = funcs->get_vid;
3533 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3534 }
3535
3536 #ifdef CONFIG_ACPI
3537
intel_pstate_no_acpi_pss(void)3538 static bool __init intel_pstate_no_acpi_pss(void)
3539 {
3540 int i;
3541
3542 for_each_possible_cpu(i) {
3543 acpi_status status;
3544 union acpi_object *pss;
3545 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3546 struct acpi_processor *pr = per_cpu(processors, i);
3547
3548 if (!pr)
3549 continue;
3550
3551 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3552 if (ACPI_FAILURE(status))
3553 continue;
3554
3555 pss = buffer.pointer;
3556 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3557 kfree(pss);
3558 return false;
3559 }
3560
3561 kfree(pss);
3562 }
3563
3564 pr_debug("ACPI _PSS not found\n");
3565 return true;
3566 }
3567
intel_pstate_no_acpi_pcch(void)3568 static bool __init intel_pstate_no_acpi_pcch(void)
3569 {
3570 acpi_status status;
3571 acpi_handle handle;
3572
3573 status = acpi_get_handle(NULL, "\\_SB", &handle);
3574 if (ACPI_FAILURE(status))
3575 goto not_found;
3576
3577 if (acpi_has_method(handle, "PCCH"))
3578 return false;
3579
3580 not_found:
3581 pr_debug("ACPI PCCH not found\n");
3582 return true;
3583 }
3584
intel_pstate_has_acpi_ppc(void)3585 static bool __init intel_pstate_has_acpi_ppc(void)
3586 {
3587 int i;
3588
3589 for_each_possible_cpu(i) {
3590 struct acpi_processor *pr = per_cpu(processors, i);
3591
3592 if (!pr)
3593 continue;
3594 if (acpi_has_method(pr->handle, "_PPC"))
3595 return true;
3596 }
3597 pr_debug("ACPI _PPC not found\n");
3598 return false;
3599 }
3600
3601 enum {
3602 PSS,
3603 PPC,
3604 };
3605
3606 /* Hardware vendor-specific info that has its own power management modes */
3607 static struct acpi_platform_list plat_info[] __initdata = {
3608 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3609 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3610 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3611 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3612 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3613 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3614 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3615 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3616 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3617 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3618 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3619 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3620 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3621 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3622 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3623 { } /* End */
3624 };
3625
3626 #define BITMASK_OOB (BIT(8) | BIT(18))
3627
intel_pstate_platform_pwr_mgmt_exists(void)3628 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3629 {
3630 const struct x86_cpu_id *id;
3631 u64 misc_pwr;
3632 int idx;
3633
3634 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3635 if (id) {
3636 rdmsrq(MSR_MISC_PWR_MGMT, misc_pwr);
3637 if (misc_pwr & BITMASK_OOB) {
3638 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3639 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3640 return true;
3641 }
3642 }
3643
3644 idx = acpi_match_platform_list(plat_info);
3645 if (idx < 0)
3646 return false;
3647
3648 switch (plat_info[idx].data) {
3649 case PSS:
3650 if (!intel_pstate_no_acpi_pss())
3651 return false;
3652
3653 return intel_pstate_no_acpi_pcch();
3654 case PPC:
3655 return intel_pstate_has_acpi_ppc() && !force_load;
3656 }
3657
3658 return false;
3659 }
3660
intel_pstate_request_control_from_smm(void)3661 static void intel_pstate_request_control_from_smm(void)
3662 {
3663 /*
3664 * It may be unsafe to request P-states control from SMM if _PPC support
3665 * has not been enabled.
3666 */
3667 if (acpi_ppc)
3668 acpi_processor_pstate_control();
3669 }
3670 #else /* CONFIG_ACPI not enabled */
intel_pstate_platform_pwr_mgmt_exists(void)3671 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
intel_pstate_has_acpi_ppc(void)3672 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
intel_pstate_request_control_from_smm(void)3673 static inline void intel_pstate_request_control_from_smm(void) {}
3674 #endif /* CONFIG_ACPI */
3675
3676 #define INTEL_PSTATE_HWP_BROADWELL 0x01
3677
3678 #define X86_MATCH_HWP(vfm, hwp_mode) \
3679 X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode)
3680
3681 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3682 X86_MATCH_HWP(INTEL_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3683 X86_MATCH_HWP(INTEL_BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3684 X86_MATCH_HWP(INTEL_ANY, 0),
3685 {}
3686 };
3687
intel_pstate_hwp_is_enabled(void)3688 static bool intel_pstate_hwp_is_enabled(void)
3689 {
3690 u64 value;
3691
3692 rdmsrq(MSR_PM_ENABLE, value);
3693 return !!(value & 0x1);
3694 }
3695
3696 #define POWERSAVE_MASK GENMASK(7, 0)
3697 #define BALANCE_POWER_MASK GENMASK(15, 8)
3698 #define BALANCE_PERFORMANCE_MASK GENMASK(23, 16)
3699 #define PERFORMANCE_MASK GENMASK(31, 24)
3700
3701 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3702 (FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3703 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3704 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3705 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3706
3707 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3708 (HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3709 balance_perf, HWP_EPP_PERFORMANCE))
3710
3711 static const struct x86_cpu_id intel_epp_default[] = {
3712 /*
3713 * Set EPP value as 102, this is the max suggested EPP
3714 * which can result in one core turbo frequency for
3715 * AlderLake Mobile CPUs.
3716 */
3717 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3718 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3719 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3720 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3721 X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3722 X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3723 179, 64, 16)),
3724 X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3725 179, 64, 16)),
3726 {}
3727 };
3728
3729 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3730 X86_MATCH_VFM(INTEL_ALDERLAKE, HYBRID_SCALING_FACTOR_ADL),
3731 X86_MATCH_VFM(INTEL_ALDERLAKE_L, HYBRID_SCALING_FACTOR_ADL),
3732 X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL),
3733 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL),
3734 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL),
3735 X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3736 X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL),
3737 {}
3738 };
3739
hwp_check_epp(void)3740 static bool hwp_check_epp(void)
3741 {
3742 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
3743 return true;
3744
3745 /* Without EPP support, don't expose EPP-related sysfs attributes. */
3746 hwp_cpufreq_attrs[HWP_PERFORMANCE_PREFERENCE_INDEX] = NULL;
3747 hwp_cpufreq_attrs[HWP_PERFORMANCE_AVAILABLE_PREFERENCES_INDEX] = NULL;
3748
3749 return false;
3750 }
3751
hwp_check_dec(void)3752 static bool hwp_check_dec(void)
3753 {
3754 u64 power_ctl;
3755
3756 rdmsrq(MSR_IA32_POWER_CTL, power_ctl);
3757 return !!(power_ctl & BIT(POWER_CTL_DEC_ENABLE));
3758 }
3759
intel_pstate_init(void)3760 static int __init intel_pstate_init(void)
3761 {
3762 static struct cpudata **_all_cpu_data;
3763 const struct x86_cpu_id *id;
3764 int rc;
3765
3766 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3767 return -ENODEV;
3768
3769 /*
3770 * The Intel pstate driver will be ignored if the platform
3771 * firmware has its own power management modes.
3772 */
3773 if (intel_pstate_platform_pwr_mgmt_exists()) {
3774 pr_info("P-states controlled by the platform\n");
3775 return -ENODEV;
3776 }
3777
3778 id = x86_match_cpu(hwp_support_ids);
3779 if (id) {
3780 bool epp_present = hwp_check_epp();
3781
3782 /*
3783 * If HWP is enabled already, there is no choice but to deal
3784 * with it.
3785 */
3786 hwp_forced = intel_pstate_hwp_is_enabled();
3787 if (hwp_forced) {
3788 pr_info("HWP enabled by BIOS\n");
3789 no_hwp = 0;
3790 } else if (no_load) {
3791 return -ENODEV;
3792 } else if (!epp_present && !hwp_check_dec()) {
3793 /*
3794 * Avoid enabling HWP for processors without EPP support
3795 * unless the Dynamic Efficiency Control (DEC) enable
3796 * bit (MSR_IA32_POWER_CTL, bit 27) is set because that
3797 * means incomplete HWP implementation which is a corner
3798 * case and supporting it is generally problematic.
3799 */
3800 no_hwp = 1;
3801 }
3802
3803 copy_cpu_funcs(&core_funcs);
3804
3805 if (!no_hwp) {
3806 hwp_active = true;
3807 hwp_mode_bdw = id->driver_data;
3808 intel_pstate.attr = hwp_cpufreq_attrs;
3809 intel_cpufreq.attr = hwp_cpufreq_attrs;
3810 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3811 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3812 if (!default_driver)
3813 default_driver = &intel_pstate;
3814
3815 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3816
3817 goto hwp_cpu_matched;
3818 }
3819 pr_info("HWP not enabled\n");
3820 } else {
3821 if (no_load)
3822 return -ENODEV;
3823
3824 id = x86_match_cpu(intel_pstate_cpu_ids);
3825 if (!id) {
3826 pr_info("CPU model not supported\n");
3827 return -ENODEV;
3828 }
3829
3830 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3831 }
3832
3833 if (intel_pstate_msrs_not_valid()) {
3834 pr_info("Invalid MSRs\n");
3835 return -ENODEV;
3836 }
3837 /* Without HWP start in the passive mode. */
3838 if (!default_driver)
3839 default_driver = &intel_cpufreq;
3840
3841 hwp_cpu_matched:
3842 if (!hwp_active && hwp_only)
3843 return -ENOTSUPP;
3844
3845 pr_info("Intel P-state driver initializing\n");
3846
3847 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3848 if (!_all_cpu_data)
3849 return -ENOMEM;
3850
3851 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3852
3853 intel_pstate_request_control_from_smm();
3854
3855 intel_pstate_sysfs_expose_params();
3856
3857 if (hwp_active) {
3858 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default);
3859 const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3860
3861 if (id) {
3862 epp_values[EPP_INDEX_POWERSAVE] =
3863 FIELD_GET(POWERSAVE_MASK, id->driver_data);
3864 epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3865 FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3866 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3867 FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3868 epp_values[EPP_INDEX_PERFORMANCE] =
3869 FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3870 pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3871 epp_values[EPP_INDEX_POWERSAVE],
3872 epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3873 epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3874 epp_values[EPP_INDEX_PERFORMANCE]);
3875 }
3876
3877 if (hybrid_id) {
3878 hybrid_scaling_factor = hybrid_id->driver_data;
3879 pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3880 }
3881
3882 }
3883
3884 scoped_guard(mutex, &intel_pstate_driver_lock) {
3885 rc = intel_pstate_register_driver(default_driver);
3886 }
3887 if (rc) {
3888 intel_pstate_sysfs_remove();
3889 return rc;
3890 }
3891
3892 if (hwp_active) {
3893 const struct x86_cpu_id *id;
3894
3895 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3896 if (id) {
3897 set_power_ctl_ee_state(false);
3898 pr_info("Disabling energy efficiency optimization\n");
3899 }
3900
3901 pr_info("HWP enabled\n");
3902 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3903 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3904 }
3905
3906 return 0;
3907 }
3908 device_initcall(intel_pstate_init);
3909
intel_pstate_setup(char * str)3910 static int __init intel_pstate_setup(char *str)
3911 {
3912 if (!str)
3913 return -EINVAL;
3914
3915 if (!strcmp(str, "disable"))
3916 no_load = 1;
3917 else if (!strcmp(str, "active"))
3918 default_driver = &intel_pstate;
3919 else if (!strcmp(str, "passive"))
3920 default_driver = &intel_cpufreq;
3921
3922 if (!strcmp(str, "no_hwp"))
3923 no_hwp = 1;
3924
3925 if (!strcmp(str, "no_cas"))
3926 no_cas = true;
3927
3928 if (!strcmp(str, "force"))
3929 force_load = 1;
3930 if (!strcmp(str, "hwp_only"))
3931 hwp_only = 1;
3932 if (!strcmp(str, "per_cpu_perf_limits"))
3933 per_cpu_limits = true;
3934
3935 #ifdef CONFIG_ACPI
3936 if (!strcmp(str, "support_acpi_ppc"))
3937 acpi_ppc = true;
3938 #endif
3939
3940 return 0;
3941 }
3942 early_param("intel_pstate", intel_pstate_setup);
3943
3944 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3945 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3946