1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2023, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 #include "ice_ptp_hw.h" 9 #include <linux/packing.h> 10 11 #define ICE_PF_RESET_WAIT_COUNT 300 12 #define ICE_MAX_NETLIST_SIZE 10 13 14 static const char * const ice_link_mode_str_low[] = { 15 [0] = "100BASE_TX", 16 [1] = "100M_SGMII", 17 [2] = "1000BASE_T", 18 [3] = "1000BASE_SX", 19 [4] = "1000BASE_LX", 20 [5] = "1000BASE_KX", 21 [6] = "1G_SGMII", 22 [7] = "2500BASE_T", 23 [8] = "2500BASE_X", 24 [9] = "2500BASE_KX", 25 [10] = "5GBASE_T", 26 [11] = "5GBASE_KR", 27 [12] = "10GBASE_T", 28 [13] = "10G_SFI_DA", 29 [14] = "10GBASE_SR", 30 [15] = "10GBASE_LR", 31 [16] = "10GBASE_KR_CR1", 32 [17] = "10G_SFI_AOC_ACC", 33 [18] = "10G_SFI_C2C", 34 [19] = "25GBASE_T", 35 [20] = "25GBASE_CR", 36 [21] = "25GBASE_CR_S", 37 [22] = "25GBASE_CR1", 38 [23] = "25GBASE_SR", 39 [24] = "25GBASE_LR", 40 [25] = "25GBASE_KR", 41 [26] = "25GBASE_KR_S", 42 [27] = "25GBASE_KR1", 43 [28] = "25G_AUI_AOC_ACC", 44 [29] = "25G_AUI_C2C", 45 [30] = "40GBASE_CR4", 46 [31] = "40GBASE_SR4", 47 [32] = "40GBASE_LR4", 48 [33] = "40GBASE_KR4", 49 [34] = "40G_XLAUI_AOC_ACC", 50 [35] = "40G_XLAUI", 51 [36] = "50GBASE_CR2", 52 [37] = "50GBASE_SR2", 53 [38] = "50GBASE_LR2", 54 [39] = "50GBASE_KR2", 55 [40] = "50G_LAUI2_AOC_ACC", 56 [41] = "50G_LAUI2", 57 [42] = "50G_AUI2_AOC_ACC", 58 [43] = "50G_AUI2", 59 [44] = "50GBASE_CP", 60 [45] = "50GBASE_SR", 61 [46] = "50GBASE_FR", 62 [47] = "50GBASE_LR", 63 [48] = "50GBASE_KR_PAM4", 64 [49] = "50G_AUI1_AOC_ACC", 65 [50] = "50G_AUI1", 66 [51] = "100GBASE_CR4", 67 [52] = "100GBASE_SR4", 68 [53] = "100GBASE_LR4", 69 [54] = "100GBASE_KR4", 70 [55] = "100G_CAUI4_AOC_ACC", 71 [56] = "100G_CAUI4", 72 [57] = "100G_AUI4_AOC_ACC", 73 [58] = "100G_AUI4", 74 [59] = "100GBASE_CR_PAM4", 75 [60] = "100GBASE_KR_PAM4", 76 [61] = "100GBASE_CP2", 77 [62] = "100GBASE_SR2", 78 [63] = "100GBASE_DR", 79 }; 80 81 static const char * const ice_link_mode_str_high[] = { 82 [0] = "100GBASE_KR2_PAM4", 83 [1] = "100G_CAUI2_AOC_ACC", 84 [2] = "100G_CAUI2", 85 [3] = "100G_AUI2_AOC_ACC", 86 [4] = "100G_AUI2", 87 }; 88 89 /** 90 * ice_dump_phy_type - helper function to dump phy_type 91 * @hw: pointer to the HW structure 92 * @low: 64 bit value for phy_type_low 93 * @high: 64 bit value for phy_type_high 94 * @prefix: prefix string to differentiate multiple dumps 95 */ 96 static void 97 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 98 { 99 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 100 101 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 102 if (low & BIT_ULL(i)) 103 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 104 prefix, i, ice_link_mode_str_low[i]); 105 } 106 107 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 108 109 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 110 if (high & BIT_ULL(i)) 111 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 112 prefix, i, ice_link_mode_str_high[i]); 113 } 114 } 115 116 /** 117 * ice_set_mac_type - Sets MAC type 118 * @hw: pointer to the HW structure 119 * 120 * This function sets the MAC type of the adapter based on the 121 * vendor ID and device ID stored in the HW structure. 122 */ 123 static int ice_set_mac_type(struct ice_hw *hw) 124 { 125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 126 return -ENODEV; 127 128 switch (hw->device_id) { 129 case ICE_DEV_ID_E810C_BACKPLANE: 130 case ICE_DEV_ID_E810C_QSFP: 131 case ICE_DEV_ID_E810C_SFP: 132 case ICE_DEV_ID_E810_XXV_BACKPLANE: 133 case ICE_DEV_ID_E810_XXV_QSFP: 134 case ICE_DEV_ID_E810_XXV_SFP: 135 hw->mac_type = ICE_MAC_E810; 136 break; 137 case ICE_DEV_ID_E823C_10G_BASE_T: 138 case ICE_DEV_ID_E823C_BACKPLANE: 139 case ICE_DEV_ID_E823C_QSFP: 140 case ICE_DEV_ID_E823C_SFP: 141 case ICE_DEV_ID_E823C_SGMII: 142 case ICE_DEV_ID_E822C_10G_BASE_T: 143 case ICE_DEV_ID_E822C_BACKPLANE: 144 case ICE_DEV_ID_E822C_QSFP: 145 case ICE_DEV_ID_E822C_SFP: 146 case ICE_DEV_ID_E822C_SGMII: 147 case ICE_DEV_ID_E822L_10G_BASE_T: 148 case ICE_DEV_ID_E822L_BACKPLANE: 149 case ICE_DEV_ID_E822L_SFP: 150 case ICE_DEV_ID_E822L_SGMII: 151 case ICE_DEV_ID_E823L_10G_BASE_T: 152 case ICE_DEV_ID_E823L_1GBE: 153 case ICE_DEV_ID_E823L_BACKPLANE: 154 case ICE_DEV_ID_E823L_QSFP: 155 case ICE_DEV_ID_E823L_SFP: 156 hw->mac_type = ICE_MAC_GENERIC; 157 break; 158 case ICE_DEV_ID_E825C_BACKPLANE: 159 case ICE_DEV_ID_E825C_QSFP: 160 case ICE_DEV_ID_E825C_SFP: 161 case ICE_DEV_ID_E825C_SGMII: 162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; 163 break; 164 case ICE_DEV_ID_E830CC_BACKPLANE: 165 case ICE_DEV_ID_E830CC_QSFP56: 166 case ICE_DEV_ID_E830CC_SFP: 167 case ICE_DEV_ID_E830CC_SFP_DD: 168 case ICE_DEV_ID_E830C_BACKPLANE: 169 case ICE_DEV_ID_E830_XXV_BACKPLANE: 170 case ICE_DEV_ID_E830C_QSFP: 171 case ICE_DEV_ID_E830_XXV_QSFP: 172 case ICE_DEV_ID_E830C_SFP: 173 case ICE_DEV_ID_E830_XXV_SFP: 174 case ICE_DEV_ID_E835CC_BACKPLANE: 175 case ICE_DEV_ID_E835CC_QSFP56: 176 case ICE_DEV_ID_E835CC_SFP: 177 case ICE_DEV_ID_E835C_BACKPLANE: 178 case ICE_DEV_ID_E835C_QSFP: 179 case ICE_DEV_ID_E835C_SFP: 180 case ICE_DEV_ID_E835_L_BACKPLANE: 181 case ICE_DEV_ID_E835_L_QSFP: 182 case ICE_DEV_ID_E835_L_SFP: 183 hw->mac_type = ICE_MAC_E830; 184 break; 185 default: 186 hw->mac_type = ICE_MAC_UNKNOWN; 187 break; 188 } 189 190 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 191 return 0; 192 } 193 194 /** 195 * ice_is_generic_mac - check if device's mac_type is generic 196 * @hw: pointer to the hardware structure 197 * 198 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise. 199 */ 200 bool ice_is_generic_mac(struct ice_hw *hw) 201 { 202 return (hw->mac_type == ICE_MAC_GENERIC || 203 hw->mac_type == ICE_MAC_GENERIC_3K_E825); 204 } 205 206 /** 207 * ice_clear_pf_cfg - Clear PF configuration 208 * @hw: pointer to the hardware structure 209 * 210 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 211 * configuration, flow director filters, etc.). 212 */ 213 int ice_clear_pf_cfg(struct ice_hw *hw) 214 { 215 struct libie_aq_desc desc; 216 217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 218 219 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 220 } 221 222 /** 223 * ice_aq_manage_mac_read - manage MAC address read command 224 * @hw: pointer to the HW struct 225 * @buf: a virtual buffer to hold the manage MAC read response 226 * @buf_size: Size of the virtual buffer 227 * @cd: pointer to command details structure or NULL 228 * 229 * This function is used to return per PF station MAC address (0x0107). 230 * NOTE: Upon successful completion of this command, MAC address information 231 * is returned in user specified buffer. Please interpret user specified 232 * buffer as "manage_mac_read" response. 233 * Response such as various MAC addresses are stored in HW struct (port.mac) 234 * ice_discover_dev_caps is expected to be called before this function is 235 * called. 236 */ 237 static int 238 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 239 struct ice_sq_cd *cd) 240 { 241 struct ice_aqc_manage_mac_read_resp *resp; 242 struct ice_aqc_manage_mac_read *cmd; 243 struct libie_aq_desc desc; 244 int status; 245 u16 flags; 246 u8 i; 247 248 cmd = libie_aq_raw(&desc); 249 250 if (buf_size < sizeof(*resp)) 251 return -EINVAL; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 254 255 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 256 if (status) 257 return status; 258 259 resp = buf; 260 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 261 262 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 263 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 264 return -EIO; 265 } 266 267 /* A single port can report up to two (LAN and WoL) addresses */ 268 for (i = 0; i < cmd->num_addr; i++) 269 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 270 ether_addr_copy(hw->port_info->mac.lan_addr, 271 resp[i].mac_addr); 272 ether_addr_copy(hw->port_info->mac.perm_addr, 273 resp[i].mac_addr); 274 break; 275 } 276 277 return 0; 278 } 279 280 /** 281 * ice_aq_get_phy_caps - returns PHY capabilities 282 * @pi: port information structure 283 * @qual_mods: report qualified modules 284 * @report_mode: report mode capabilities 285 * @pcaps: structure for PHY capabilities to be filled 286 * @cd: pointer to command details structure or NULL 287 * 288 * Returns the various PHY capabilities supported on the Port (0x0600) 289 */ 290 int 291 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 292 struct ice_aqc_get_phy_caps_data *pcaps, 293 struct ice_sq_cd *cd) 294 { 295 struct ice_aqc_get_phy_caps *cmd; 296 u16 pcaps_size = sizeof(*pcaps); 297 struct libie_aq_desc desc; 298 const char *prefix; 299 struct ice_hw *hw; 300 int status; 301 302 cmd = libie_aq_raw(&desc); 303 304 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 305 return -EINVAL; 306 hw = pi->hw; 307 308 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 309 !ice_fw_supports_report_dflt_cfg(hw)) 310 return -EINVAL; 311 312 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 313 314 if (qual_mods) 315 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 316 317 cmd->param0 |= cpu_to_le16(report_mode); 318 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 319 320 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 321 322 switch (report_mode) { 323 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 324 prefix = "phy_caps_media"; 325 break; 326 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 327 prefix = "phy_caps_no_media"; 328 break; 329 case ICE_AQC_REPORT_ACTIVE_CFG: 330 prefix = "phy_caps_active"; 331 break; 332 case ICE_AQC_REPORT_DFLT_CFG: 333 prefix = "phy_caps_default"; 334 break; 335 default: 336 prefix = "phy_caps_invalid"; 337 } 338 339 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 340 le64_to_cpu(pcaps->phy_type_high), prefix); 341 342 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 343 prefix, report_mode); 344 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 345 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 346 pcaps->low_power_ctrl_an); 347 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 348 pcaps->eee_cap); 349 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 350 pcaps->eeer_value); 351 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 352 pcaps->link_fec_options); 353 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 354 prefix, pcaps->module_compliance_enforcement); 355 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 356 prefix, pcaps->extended_compliance_code); 357 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 358 pcaps->module_type[0]); 359 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 360 pcaps->module_type[1]); 361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 362 pcaps->module_type[2]); 363 364 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 365 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 366 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 367 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 368 sizeof(pi->phy.link_info.module_type)); 369 } 370 371 return status; 372 } 373 374 /** 375 * ice_aq_get_link_topo_handle - get link topology node return status 376 * @pi: port information structure 377 * @node_type: requested node type 378 * @cd: pointer to command details structure or NULL 379 * 380 * Get link topology node return status for specified node type (0x06E0) 381 * 382 * Node type cage can be used to determine if cage is present. If AQC 383 * returns error (ENOENT), then no cage present. If no cage present, then 384 * connection type is backplane or BASE-T. 385 */ 386 static int 387 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 388 struct ice_sq_cd *cd) 389 { 390 struct ice_aqc_get_link_topo *cmd; 391 struct libie_aq_desc desc; 392 393 cmd = libie_aq_raw(&desc); 394 395 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 396 397 cmd->addr.topo_params.node_type_ctx = 398 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 399 ICE_AQC_LINK_TOPO_NODE_CTX_S); 400 401 /* set node type */ 402 cmd->addr.topo_params.node_type_ctx |= 403 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 404 405 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 406 } 407 408 /** 409 * ice_aq_get_netlist_node 410 * @hw: pointer to the hw struct 411 * @cmd: get_link_topo AQ structure 412 * @node_part_number: output node part number if node found 413 * @node_handle: output node handle parameter if node found 414 * 415 * Get netlist node handle. 416 */ 417 int 418 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 419 u8 *node_part_number, u16 *node_handle) 420 { 421 struct ice_aqc_get_link_topo *resp; 422 struct libie_aq_desc desc; 423 424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 425 resp = libie_aq_raw(&desc); 426 *resp = *cmd; 427 428 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) 429 return -EINTR; 430 431 if (node_handle) 432 *node_handle = le16_to_cpu(resp->addr.handle); 433 if (node_part_number) 434 *node_part_number = resp->node_part_num; 435 436 return 0; 437 } 438 439 /** 440 * ice_find_netlist_node 441 * @hw: pointer to the hw struct 442 * @node_type: type of netlist node to look for 443 * @ctx: context of the search 444 * @node_part_number: node part number to look for 445 * @node_handle: output parameter if node found - optional 446 * 447 * Scan the netlist for a node handle of the given node type and part number. 448 * 449 * If node_handle is non-NULL it will be modified on function exit. It is only 450 * valid if the function returns zero, and should be ignored on any non-zero 451 * return value. 452 * 453 * Return: 454 * * 0 if the node is found, 455 * * -ENOENT if no handle was found, 456 * * negative error code on failure to access the AQ. 457 */ 458 static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx, 459 u8 node_part_number, u16 *node_handle) 460 { 461 u8 idx; 462 463 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { 464 struct ice_aqc_get_link_topo cmd = {}; 465 u8 rec_node_part_number; 466 int status; 467 468 cmd.addr.topo_params.node_type_ctx = 469 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) | 470 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx); 471 cmd.addr.topo_params.index = idx; 472 473 status = ice_aq_get_netlist_node(hw, &cmd, 474 &rec_node_part_number, 475 node_handle); 476 if (status) 477 return status; 478 479 if (rec_node_part_number == node_part_number) 480 return 0; 481 } 482 483 return -ENOENT; 484 } 485 486 /** 487 * ice_is_media_cage_present 488 * @pi: port information structure 489 * 490 * Returns true if media cage is present, else false. If no cage, then 491 * media type is backplane or BASE-T. 492 */ 493 static bool ice_is_media_cage_present(struct ice_port_info *pi) 494 { 495 /* Node type cage can be used to determine if cage is present. If AQC 496 * returns error (ENOENT), then no cage present. If no cage present then 497 * connection type is backplane or BASE-T. 498 */ 499 return !ice_aq_get_link_topo_handle(pi, 500 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 501 NULL); 502 } 503 504 /** 505 * ice_get_media_type - Gets media type 506 * @pi: port information structure 507 */ 508 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 509 { 510 struct ice_link_status *hw_link_info; 511 512 if (!pi) 513 return ICE_MEDIA_UNKNOWN; 514 515 hw_link_info = &pi->phy.link_info; 516 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 517 /* If more than one media type is selected, report unknown */ 518 return ICE_MEDIA_UNKNOWN; 519 520 if (hw_link_info->phy_type_low) { 521 /* 1G SGMII is a special case where some DA cable PHYs 522 * may show this as an option when it really shouldn't 523 * be since SGMII is meant to be between a MAC and a PHY 524 * in a backplane. Try to detect this case and handle it 525 */ 526 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 527 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 528 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 529 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 530 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 531 return ICE_MEDIA_DA; 532 533 switch (hw_link_info->phy_type_low) { 534 case ICE_PHY_TYPE_LOW_1000BASE_SX: 535 case ICE_PHY_TYPE_LOW_1000BASE_LX: 536 case ICE_PHY_TYPE_LOW_10GBASE_SR: 537 case ICE_PHY_TYPE_LOW_10GBASE_LR: 538 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 539 case ICE_PHY_TYPE_LOW_25GBASE_SR: 540 case ICE_PHY_TYPE_LOW_25GBASE_LR: 541 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 542 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 543 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 544 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 545 case ICE_PHY_TYPE_LOW_50GBASE_SR: 546 case ICE_PHY_TYPE_LOW_50GBASE_FR: 547 case ICE_PHY_TYPE_LOW_50GBASE_LR: 548 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 549 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 550 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 551 case ICE_PHY_TYPE_LOW_100GBASE_DR: 552 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 553 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 554 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 555 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 556 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 557 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 558 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 559 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 560 return ICE_MEDIA_FIBER; 561 case ICE_PHY_TYPE_LOW_100BASE_TX: 562 case ICE_PHY_TYPE_LOW_1000BASE_T: 563 case ICE_PHY_TYPE_LOW_2500BASE_T: 564 case ICE_PHY_TYPE_LOW_5GBASE_T: 565 case ICE_PHY_TYPE_LOW_10GBASE_T: 566 case ICE_PHY_TYPE_LOW_25GBASE_T: 567 return ICE_MEDIA_BASET; 568 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 569 case ICE_PHY_TYPE_LOW_25GBASE_CR: 570 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 571 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 572 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 573 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 574 case ICE_PHY_TYPE_LOW_50GBASE_CP: 575 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 576 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 577 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 578 return ICE_MEDIA_DA; 579 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 580 case ICE_PHY_TYPE_LOW_40G_XLAUI: 581 case ICE_PHY_TYPE_LOW_50G_LAUI2: 582 case ICE_PHY_TYPE_LOW_50G_AUI2: 583 case ICE_PHY_TYPE_LOW_50G_AUI1: 584 case ICE_PHY_TYPE_LOW_100G_AUI4: 585 case ICE_PHY_TYPE_LOW_100G_CAUI4: 586 if (ice_is_media_cage_present(pi)) 587 return ICE_MEDIA_DA; 588 fallthrough; 589 case ICE_PHY_TYPE_LOW_1000BASE_KX: 590 case ICE_PHY_TYPE_LOW_2500BASE_KX: 591 case ICE_PHY_TYPE_LOW_2500BASE_X: 592 case ICE_PHY_TYPE_LOW_5GBASE_KR: 593 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 594 case ICE_PHY_TYPE_LOW_25GBASE_KR: 595 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 596 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 597 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 598 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 599 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 600 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 601 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 602 return ICE_MEDIA_BACKPLANE; 603 } 604 } else { 605 switch (hw_link_info->phy_type_high) { 606 case ICE_PHY_TYPE_HIGH_100G_AUI2: 607 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 608 if (ice_is_media_cage_present(pi)) 609 return ICE_MEDIA_DA; 610 fallthrough; 611 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 612 return ICE_MEDIA_BACKPLANE; 613 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 614 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 615 return ICE_MEDIA_FIBER; 616 } 617 } 618 return ICE_MEDIA_UNKNOWN; 619 } 620 621 /** 622 * ice_get_link_status_datalen 623 * @hw: pointer to the HW struct 624 * 625 * Returns datalength for the Get Link Status AQ command, which is bigger for 626 * newer adapter families handled by ice driver. 627 */ 628 static u16 ice_get_link_status_datalen(struct ice_hw *hw) 629 { 630 switch (hw->mac_type) { 631 case ICE_MAC_E830: 632 return ICE_AQC_LS_DATA_SIZE_V2; 633 case ICE_MAC_E810: 634 default: 635 return ICE_AQC_LS_DATA_SIZE_V1; 636 } 637 } 638 639 /** 640 * ice_aq_get_link_info 641 * @pi: port information structure 642 * @ena_lse: enable/disable LinkStatusEvent reporting 643 * @link: pointer to link status structure - optional 644 * @cd: pointer to command details structure or NULL 645 * 646 * Get Link Status (0x607). Returns the link status of the adapter. 647 */ 648 int 649 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 650 struct ice_link_status *link, struct ice_sq_cd *cd) 651 { 652 struct ice_aqc_get_link_status_data link_data = { 0 }; 653 struct ice_aqc_get_link_status *resp; 654 struct ice_link_status *li_old, *li; 655 enum ice_media_type *hw_media_type; 656 struct ice_fc_info *hw_fc_info; 657 struct libie_aq_desc desc; 658 bool tx_pause, rx_pause; 659 struct ice_hw *hw; 660 u16 cmd_flags; 661 int status; 662 663 if (!pi) 664 return -EINVAL; 665 hw = pi->hw; 666 li_old = &pi->phy.link_info_old; 667 hw_media_type = &pi->phy.media_type; 668 li = &pi->phy.link_info; 669 hw_fc_info = &pi->fc; 670 671 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 672 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 673 resp = libie_aq_raw(&desc); 674 resp->cmd_flags = cpu_to_le16(cmd_flags); 675 resp->lport_num = pi->lport; 676 677 status = ice_aq_send_cmd(hw, &desc, &link_data, 678 ice_get_link_status_datalen(hw), cd); 679 if (status) 680 return status; 681 682 /* save off old link status information */ 683 *li_old = *li; 684 685 /* update current link status information */ 686 li->link_speed = le16_to_cpu(link_data.link_speed); 687 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 688 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 689 *hw_media_type = ice_get_media_type(pi); 690 li->link_info = link_data.link_info; 691 li->link_cfg_err = link_data.link_cfg_err; 692 li->an_info = link_data.an_info; 693 li->ext_info = link_data.ext_info; 694 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 695 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 696 li->topo_media_conflict = link_data.topo_media_conflict; 697 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 698 ICE_AQ_CFG_PACING_TYPE_M); 699 700 /* update fc info */ 701 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 702 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 703 if (tx_pause && rx_pause) 704 hw_fc_info->current_mode = ICE_FC_FULL; 705 else if (tx_pause) 706 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 707 else if (rx_pause) 708 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 709 else 710 hw_fc_info->current_mode = ICE_FC_NONE; 711 712 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 713 714 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 715 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 716 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 717 (unsigned long long)li->phy_type_low); 718 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 719 (unsigned long long)li->phy_type_high); 720 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 721 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 722 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 723 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 724 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 725 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 726 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 727 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 728 li->max_frame_size); 729 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 730 731 /* save link status information */ 732 if (link) 733 *link = *li; 734 735 /* flag cleared so calling functions don't call AQ again */ 736 pi->phy.get_link_info = false; 737 738 return 0; 739 } 740 741 /** 742 * ice_fill_tx_timer_and_fc_thresh 743 * @hw: pointer to the HW struct 744 * @cmd: pointer to MAC cfg structure 745 * 746 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 747 * descriptor 748 */ 749 static void 750 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 751 struct ice_aqc_set_mac_cfg *cmd) 752 { 753 u32 val, fc_thres_m; 754 755 /* We read back the transmit timer and FC threshold value of 756 * LFC. Thus, we will use index = 757 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 758 * 759 * Also, because we are operating on transmit timer and FC 760 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 761 */ 762 #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 763 #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR 764 765 if (hw->mac_type == ICE_MAC_E830) { 766 /* Retrieve the transmit timer */ 767 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT); 768 cmd->tx_tmr_value = 769 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M); 770 771 /* Retrieve the fc threshold */ 772 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR); 773 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M; 774 } else { 775 /* Retrieve the transmit timer */ 776 val = rd32(hw, 777 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC)); 778 cmd->tx_tmr_value = 779 le16_encode_bits(val, 780 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M); 781 782 /* Retrieve the fc threshold */ 783 val = rd32(hw, 784 E800_REFRESH_TMR(E800_IDX_OF_LFC)); 785 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M; 786 } 787 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); 788 } 789 790 /** 791 * ice_aq_set_mac_cfg 792 * @hw: pointer to the HW struct 793 * @max_frame_size: Maximum Frame Size to be supported 794 * @cd: pointer to command details structure or NULL 795 * 796 * Set MAC configuration (0x0603) 797 */ 798 int 799 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 800 { 801 struct ice_aqc_set_mac_cfg *cmd; 802 struct libie_aq_desc desc; 803 804 cmd = libie_aq_raw(&desc); 805 806 if (max_frame_size == 0) 807 return -EINVAL; 808 809 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 810 811 cmd->max_frame_size = cpu_to_le16(max_frame_size); 812 813 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 814 815 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 816 } 817 818 /** 819 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 820 * @hw: pointer to the HW struct 821 */ 822 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 823 { 824 struct ice_switch_info *sw; 825 int status; 826 827 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 828 sizeof(*hw->switch_info), GFP_KERNEL); 829 sw = hw->switch_info; 830 831 if (!sw) 832 return -ENOMEM; 833 834 INIT_LIST_HEAD(&sw->vsi_list_map_head); 835 sw->prof_res_bm_init = 0; 836 837 /* Initialize recipe count with default recipes read from NVM */ 838 sw->recp_cnt = ICE_SW_LKUP_LAST; 839 840 status = ice_init_def_sw_recp(hw); 841 if (status) { 842 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 843 return status; 844 } 845 return 0; 846 } 847 848 /** 849 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 850 * @hw: pointer to the HW struct 851 */ 852 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 853 { 854 struct ice_switch_info *sw = hw->switch_info; 855 struct ice_vsi_list_map_info *v_pos_map; 856 struct ice_vsi_list_map_info *v_tmp_map; 857 struct ice_sw_recipe *recps; 858 u8 i; 859 860 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 861 list_entry) { 862 list_del(&v_pos_map->list_entry); 863 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 864 } 865 recps = sw->recp_list; 866 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 867 recps[i].root_rid = i; 868 869 if (recps[i].adv_rule) { 870 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 871 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 872 873 mutex_destroy(&recps[i].filt_rule_lock); 874 list_for_each_entry_safe(lst_itr, tmp_entry, 875 &recps[i].filt_rules, 876 list_entry) { 877 list_del(&lst_itr->list_entry); 878 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 879 devm_kfree(ice_hw_to_dev(hw), lst_itr); 880 } 881 } else { 882 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 883 884 mutex_destroy(&recps[i].filt_rule_lock); 885 list_for_each_entry_safe(lst_itr, tmp_entry, 886 &recps[i].filt_rules, 887 list_entry) { 888 list_del(&lst_itr->list_entry); 889 devm_kfree(ice_hw_to_dev(hw), lst_itr); 890 } 891 } 892 } 893 ice_rm_all_sw_replay_rule_info(hw); 894 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 895 devm_kfree(ice_hw_to_dev(hw), sw); 896 } 897 898 /** 899 * ice_get_itr_intrl_gran 900 * @hw: pointer to the HW struct 901 * 902 * Determines the ITR/INTRL granularities based on the maximum aggregate 903 * bandwidth according to the device's configuration during power-on. 904 */ 905 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 906 { 907 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M, 908 rd32(hw, GL_PWR_MODE_CTL)); 909 910 switch (max_agg_bw) { 911 case ICE_MAX_AGG_BW_200G: 912 case ICE_MAX_AGG_BW_100G: 913 case ICE_MAX_AGG_BW_50G: 914 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 915 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 916 break; 917 case ICE_MAX_AGG_BW_25G: 918 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 919 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 920 break; 921 } 922 } 923 924 /** 925 * ice_wait_fw_load - wait for PHY firmware loading to complete 926 * @hw: pointer to the hardware structure 927 * @timeout: milliseconds that can elapse before timing out, 0 to bypass waiting 928 * 929 * Return: 930 * * 0 on success 931 * * negative on timeout 932 */ 933 static int ice_wait_fw_load(struct ice_hw *hw, u32 timeout) 934 { 935 int fw_loading_reg; 936 937 if (!timeout) 938 return 0; 939 940 fw_loading_reg = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_LOADING_M; 941 /* notify the user only once if PHY FW is still loading */ 942 if (fw_loading_reg) 943 dev_info(ice_hw_to_dev(hw), "Link initialization is blocked by PHY FW initialization. Link initialization will continue after PHY FW initialization completes.\n"); 944 else 945 return 0; 946 947 return rd32_poll_timeout(hw, GL_MNG_FWSM, fw_loading_reg, 948 !(fw_loading_reg & GL_MNG_FWSM_FW_LOADING_M), 949 10000, timeout * 1000); 950 } 951 952 static int __fwlog_send_cmd(void *priv, struct libie_aq_desc *desc, void *buf, 953 u16 size) 954 { 955 struct ice_hw *hw = priv; 956 957 return ice_aq_send_cmd(hw, desc, buf, size, NULL); 958 } 959 960 static int __fwlog_init(struct ice_hw *hw) 961 { 962 struct ice_pf *pf = hw->back; 963 struct libie_fwlog_api api = { 964 .pdev = pf->pdev, 965 .send_cmd = __fwlog_send_cmd, 966 .priv = hw, 967 }; 968 int err; 969 970 /* only support fw log commands on PF 0 */ 971 if (hw->bus.func) 972 return -EINVAL; 973 974 err = ice_debugfs_pf_init(pf); 975 if (err) 976 return err; 977 978 api.debugfs_root = pf->ice_debugfs_pf; 979 980 return libie_fwlog_init(&hw->fwlog, &api); 981 } 982 983 /** 984 * ice_init_hw - main hardware initialization routine 985 * @hw: pointer to the hardware structure 986 */ 987 int ice_init_hw(struct ice_hw *hw) 988 { 989 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 990 void *mac_buf __free(kfree) = NULL; 991 u16 mac_buf_len; 992 int status; 993 994 /* Set MAC type based on DeviceID */ 995 status = ice_set_mac_type(hw); 996 if (status) 997 return status; 998 999 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); 1000 1001 status = ice_reset(hw, ICE_RESET_PFR); 1002 if (status) 1003 return status; 1004 1005 ice_get_itr_intrl_gran(hw); 1006 1007 status = ice_create_all_ctrlq(hw); 1008 if (status) 1009 goto err_unroll_cqinit; 1010 1011 status = __fwlog_init(hw); 1012 if (status) 1013 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n", 1014 status); 1015 1016 status = ice_clear_pf_cfg(hw); 1017 if (status) 1018 goto err_unroll_cqinit; 1019 1020 /* Set bit to enable Flow Director filters */ 1021 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1022 INIT_LIST_HEAD(&hw->fdir_list_head); 1023 1024 ice_clear_pxe_mode(hw); 1025 1026 status = ice_init_nvm(hw); 1027 if (status) 1028 goto err_unroll_cqinit; 1029 1030 status = ice_get_caps(hw); 1031 if (status) 1032 goto err_unroll_cqinit; 1033 1034 if (!hw->port_info) 1035 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1036 sizeof(*hw->port_info), 1037 GFP_KERNEL); 1038 if (!hw->port_info) { 1039 status = -ENOMEM; 1040 goto err_unroll_cqinit; 1041 } 1042 1043 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; 1044 /* set the back pointer to HW */ 1045 hw->port_info->hw = hw; 1046 1047 /* Initialize port_info struct with switch configuration data */ 1048 status = ice_get_initial_sw_cfg(hw); 1049 if (status) 1050 goto err_unroll_alloc; 1051 1052 hw->evb_veb = true; 1053 1054 xa_init_flags(&hw->sched_node_ids, XA_FLAGS_ALLOC); 1055 1056 /* Query the allocated resources for Tx scheduler */ 1057 status = ice_sched_query_res_alloc(hw); 1058 if (status) { 1059 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1060 goto err_unroll_xarray; 1061 } 1062 ice_sched_get_psm_clk_freq(hw); 1063 1064 /* Initialize port_info struct with scheduler data */ 1065 status = ice_sched_init_port(hw->port_info); 1066 if (status) 1067 goto err_unroll_sched; 1068 1069 pcaps = kzalloc_obj(*pcaps); 1070 if (!pcaps) { 1071 status = -ENOMEM; 1072 goto err_unroll_sched; 1073 } 1074 1075 /* Initialize port_info struct with PHY capabilities */ 1076 status = ice_aq_get_phy_caps(hw->port_info, false, 1077 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1078 NULL); 1079 if (status) 1080 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1081 status); 1082 1083 /* Initialize port_info struct with link information */ 1084 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1085 if (status) 1086 goto err_unroll_sched; 1087 1088 /* need a valid SW entry point to build a Tx tree */ 1089 if (!hw->sw_entry_point_layer) { 1090 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1091 status = -EIO; 1092 goto err_unroll_sched; 1093 } 1094 INIT_LIST_HEAD(&hw->agg_list); 1095 /* Initialize max burst size */ 1096 if (!hw->max_burst_size) 1097 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1098 1099 status = ice_init_fltr_mgmt_struct(hw); 1100 if (status) 1101 goto err_unroll_sched; 1102 1103 /* Get MAC information */ 1104 /* A single port can report up to two (LAN and WoL) addresses */ 1105 mac_buf = kzalloc_objs(struct ice_aqc_manage_mac_read_resp, 2); 1106 if (!mac_buf) { 1107 status = -ENOMEM; 1108 goto err_unroll_fltr_mgmt_struct; 1109 } 1110 1111 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1112 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1113 1114 if (status) 1115 goto err_unroll_fltr_mgmt_struct; 1116 /* enable jumbo frame support at MAC level */ 1117 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1118 if (status) 1119 goto err_unroll_fltr_mgmt_struct; 1120 /* Obtain counter base index which would be used by flow director */ 1121 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1122 if (status) 1123 goto err_unroll_fltr_mgmt_struct; 1124 status = ice_init_hw_tbls(hw); 1125 if (status) 1126 goto err_unroll_fltr_mgmt_struct; 1127 1128 mutex_init(&hw->tnl_lock); 1129 ice_init_chk_recipe_reuse_support(hw); 1130 1131 /* Some cards require longer initialization times 1132 * due to necessity of loading FW from an external source. 1133 * This can take even half a minute. 1134 */ 1135 status = ice_wait_fw_load(hw, 30000); 1136 if (status) { 1137 dev_err(ice_hw_to_dev(hw), "ice_wait_fw_load timed out"); 1138 goto err_unroll_fltr_mgmt_struct; 1139 } 1140 1141 hw->lane_num = ice_get_phy_lane_number(hw); 1142 1143 return 0; 1144 err_unroll_fltr_mgmt_struct: 1145 ice_cleanup_fltr_mgmt_struct(hw); 1146 err_unroll_sched: 1147 ice_sched_cleanup_all(hw); 1148 err_unroll_xarray: 1149 xa_destroy(&hw->sched_node_ids); 1150 err_unroll_alloc: 1151 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1152 err_unroll_cqinit: 1153 ice_destroy_all_ctrlq(hw); 1154 return status; 1155 } 1156 1157 static void __fwlog_deinit(struct ice_hw *hw) 1158 { 1159 /* only support fw log commands on PF 0 */ 1160 if (hw->bus.func) 1161 return; 1162 1163 ice_debugfs_pf_deinit(hw->back); 1164 libie_fwlog_deinit(&hw->fwlog); 1165 } 1166 1167 /** 1168 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1169 * @hw: pointer to the hardware structure 1170 * 1171 * This should be called only during nominal operation, not as a result of 1172 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1173 * applicable initializations if it fails for any reason. 1174 */ 1175 void ice_deinit_hw(struct ice_hw *hw) 1176 { 1177 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1178 ice_cleanup_fltr_mgmt_struct(hw); 1179 1180 ice_sched_cleanup_all(hw); 1181 ice_sched_clear_agg(hw); 1182 ice_free_seg(hw); 1183 ice_free_hw_tbls(hw); 1184 mutex_destroy(&hw->tnl_lock); 1185 __fwlog_deinit(hw); 1186 ice_destroy_all_ctrlq(hw); 1187 1188 /* Clear VSI contexts if not already cleared */ 1189 ice_clear_all_vsi_ctx(hw); 1190 1191 xa_destroy(&hw->sched_node_ids); 1192 } 1193 1194 /** 1195 * ice_check_reset - Check to see if a global reset is complete 1196 * @hw: pointer to the hardware structure 1197 */ 1198 int ice_check_reset(struct ice_hw *hw) 1199 { 1200 u32 cnt, reg = 0, grst_timeout, uld_mask; 1201 1202 /* Poll for Device Active state in case a recent CORER, GLOBR, 1203 * or EMPR has occurred. The grst delay value is in 100ms units. 1204 * Add 1sec for outstanding AQ commands that can take a long time. 1205 */ 1206 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M, 1207 rd32(hw, GLGEN_RSTCTL)) + 10; 1208 1209 for (cnt = 0; cnt < grst_timeout; cnt++) { 1210 mdelay(100); 1211 reg = rd32(hw, GLGEN_RSTAT); 1212 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1213 break; 1214 } 1215 1216 if (cnt == grst_timeout) { 1217 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1218 return -EIO; 1219 } 1220 1221 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1222 GLNVM_ULD_PCIER_DONE_1_M |\ 1223 GLNVM_ULD_CORER_DONE_M |\ 1224 GLNVM_ULD_GLOBR_DONE_M |\ 1225 GLNVM_ULD_POR_DONE_M |\ 1226 GLNVM_ULD_POR_DONE_1_M |\ 1227 GLNVM_ULD_PCIER_DONE_2_M) 1228 1229 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1230 GLNVM_ULD_PE_DONE_M : 0); 1231 1232 /* Device is Active; check Global Reset processes are done */ 1233 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1234 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1235 if (reg == uld_mask) { 1236 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1237 break; 1238 } 1239 mdelay(10); 1240 } 1241 1242 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1243 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1244 reg); 1245 return -EIO; 1246 } 1247 1248 return 0; 1249 } 1250 1251 /** 1252 * ice_pf_reset - Reset the PF 1253 * @hw: pointer to the hardware structure 1254 * 1255 * If a global reset has been triggered, this function checks 1256 * for its completion and then issues the PF reset 1257 */ 1258 static int ice_pf_reset(struct ice_hw *hw) 1259 { 1260 u32 cnt, reg; 1261 1262 /* If at function entry a global reset was already in progress, i.e. 1263 * state is not 'device active' or any of the reset done bits are not 1264 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1265 * global reset is done. 1266 */ 1267 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1268 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1269 /* poll on global reset currently in progress until done */ 1270 if (ice_check_reset(hw)) 1271 return -EIO; 1272 1273 return 0; 1274 } 1275 1276 /* Reset the PF */ 1277 reg = rd32(hw, PFGEN_CTRL); 1278 1279 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1280 1281 /* Wait for the PFR to complete. The wait time is the global config lock 1282 * timeout plus the PFR timeout which will account for a possible reset 1283 * that is occurring during a download package operation. 1284 */ 1285 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1286 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1287 reg = rd32(hw, PFGEN_CTRL); 1288 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1289 break; 1290 1291 mdelay(1); 1292 } 1293 1294 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1295 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1296 return -EIO; 1297 } 1298 1299 return 0; 1300 } 1301 1302 /** 1303 * ice_reset - Perform different types of reset 1304 * @hw: pointer to the hardware structure 1305 * @req: reset request 1306 * 1307 * This function triggers a reset as specified by the req parameter. 1308 * 1309 * Note: 1310 * If anything other than a PF reset is triggered, PXE mode is restored. 1311 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1312 * interface has been restored in the rebuild flow. 1313 */ 1314 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1315 { 1316 u32 val = 0; 1317 1318 switch (req) { 1319 case ICE_RESET_PFR: 1320 return ice_pf_reset(hw); 1321 case ICE_RESET_CORER: 1322 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1323 val = GLGEN_RTRIG_CORER_M; 1324 break; 1325 case ICE_RESET_GLOBR: 1326 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1327 val = GLGEN_RTRIG_GLOBR_M; 1328 break; 1329 default: 1330 return -EINVAL; 1331 } 1332 1333 val |= rd32(hw, GLGEN_RTRIG); 1334 wr32(hw, GLGEN_RTRIG, val); 1335 ice_flush(hw); 1336 1337 /* wait for the FW to be ready */ 1338 return ice_check_reset(hw); 1339 } 1340 1341 /** 1342 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers 1343 * @hw: pointer to the hardware structure 1344 * @rxq_ctx: pointer to the packed Rx queue context 1345 * @rxq_index: the index of the Rx queue 1346 */ 1347 static void ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, 1348 const ice_rxq_ctx_buf_t *rxq_ctx, 1349 u32 rxq_index) 1350 { 1351 /* Copy each dword separately to HW */ 1352 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1353 u32 ctx = ((const u32 *)rxq_ctx)[i]; 1354 1355 wr32(hw, QRX_CONTEXT(i, rxq_index), ctx); 1356 1357 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx); 1358 } 1359 } 1360 1361 /** 1362 * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers 1363 * @hw: pointer to the hardware structure 1364 * @rxq_ctx: pointer to the packed Rx queue context 1365 * @rxq_index: the index of the Rx queue 1366 */ 1367 static void ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, 1368 ice_rxq_ctx_buf_t *rxq_ctx, 1369 u32 rxq_index) 1370 { 1371 u32 *ctx = (u32 *)rxq_ctx; 1372 1373 /* Copy each dword separately from HW */ 1374 for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) { 1375 *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); 1376 1377 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); 1378 } 1379 } 1380 1381 #define ICE_CTX_STORE(struct_name, struct_field, width, lsb) \ 1382 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field) 1383 1384 /* LAN Rx Queue Context */ 1385 static const struct packed_field_u8 ice_rlan_ctx_fields[] = { 1386 /* Field Width LSB */ 1387 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1388 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1389 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1390 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1391 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1392 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1393 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1394 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1395 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1396 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1397 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1398 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1399 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1400 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1401 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1402 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1403 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1404 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1405 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1406 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1407 }; 1408 1409 /** 1410 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer 1411 * @ctx: the Rx queue context to pack 1412 * @buf: the HW buffer to pack into 1413 * 1414 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its 1415 * bit-packed HW layout. 1416 */ 1417 static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, 1418 ice_rxq_ctx_buf_t *buf) 1419 { 1420 pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1421 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1422 } 1423 1424 /** 1425 * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer 1426 * @buf: the HW buffer to unpack from 1427 * @ctx: the Rx queue context to unpack 1428 * 1429 * Unpack the Rx queue context from the HW buffer into the CPU-friendly 1430 * structure. 1431 */ 1432 static void ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, 1433 struct ice_rlan_ctx *ctx) 1434 { 1435 unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields, 1436 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1437 } 1438 1439 /** 1440 * ice_write_rxq_ctx - Write Rx Queue context to hardware 1441 * @hw: pointer to the hardware structure 1442 * @rlan_ctx: pointer to the unpacked Rx queue context 1443 * @rxq_index: the index of the Rx queue 1444 * 1445 * Pack the sparse Rx Queue context into dense hardware format and write it 1446 * into the HW register space. 1447 * 1448 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid. 1449 */ 1450 int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1451 u32 rxq_index) 1452 { 1453 ice_rxq_ctx_buf_t buf = {}; 1454 1455 if (rxq_index > QRX_CTRL_MAX_INDEX) 1456 return -EINVAL; 1457 1458 ice_pack_rxq_ctx(rlan_ctx, &buf); 1459 ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index); 1460 1461 return 0; 1462 } 1463 1464 /** 1465 * ice_read_rxq_ctx - Read Rx queue context from HW 1466 * @hw: pointer to the hardware structure 1467 * @rlan_ctx: pointer to the Rx queue context 1468 * @rxq_index: the index of the Rx queue 1469 * 1470 * Read the Rx queue context from the hardware registers, and unpack it into 1471 * the sparse Rx queue context structure. 1472 * 1473 * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid. 1474 */ 1475 int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1476 u32 rxq_index) 1477 { 1478 ice_rxq_ctx_buf_t buf = {}; 1479 1480 if (rxq_index > QRX_CTRL_MAX_INDEX) 1481 return -EINVAL; 1482 1483 ice_copy_rxq_ctx_from_hw(hw, &buf, rxq_index); 1484 ice_unpack_rxq_ctx(&buf, rlan_ctx); 1485 1486 return 0; 1487 } 1488 1489 /* LAN Tx Queue Context */ 1490 static const struct packed_field_u8 ice_tlan_ctx_fields[] = { 1491 /* Field Width LSB */ 1492 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1493 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1494 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1495 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1496 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1497 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1498 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1499 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1500 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1501 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1502 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1503 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1504 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1505 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1506 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1507 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1508 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1509 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1510 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1511 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1512 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1513 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1514 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1515 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1516 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1517 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1518 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1519 }; 1520 1521 /** 1522 * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer 1523 * @ctx: the Tx queue context to pack 1524 * @buf: the Admin Queue HW buffer to pack into 1525 * 1526 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1527 * bit-packed Admin Queue layout. 1528 */ 1529 void ice_pack_txq_ctx(const struct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf) 1530 { 1531 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1532 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1533 } 1534 1535 /** 1536 * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer 1537 * @ctx: the Tx queue context to pack 1538 * @buf: the HW buffer to pack into 1539 * 1540 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its 1541 * bit-packed HW layout, including the internal data portion. 1542 */ 1543 static void ice_pack_txq_ctx_full(const struct ice_tlan_ctx *ctx, 1544 ice_txq_ctx_buf_full_t *buf) 1545 { 1546 pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1547 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1548 } 1549 1550 /** 1551 * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer 1552 * @buf: the HW buffer to unpack from 1553 * @ctx: the Tx queue context to unpack 1554 * 1555 * Unpack the Tx queue context from the HW buffer (including the full internal 1556 * state) into the CPU-friendly structure. 1557 */ 1558 static void ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, 1559 struct ice_tlan_ctx *ctx) 1560 { 1561 unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields, 1562 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1563 } 1564 1565 /** 1566 * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers 1567 * @hw: pointer to the hardware structure 1568 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1569 * @txq_index: the index of the Tx queue 1570 * 1571 * Copy Tx Queue context from HW register space to dense structure 1572 */ 1573 static void ice_copy_txq_ctx_from_hw(struct ice_hw *hw, 1574 ice_txq_ctx_buf_full_t *txq_ctx, 1575 u32 txq_index) 1576 { 1577 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1578 u32 *ctx = (u32 *)txq_ctx; 1579 u32 txq_base, reg; 1580 1581 /* Get Tx queue base within card space */ 1582 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1583 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1584 1585 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1586 GLCOMM_QTX_CNTX_CTL_CMD_READ) | 1587 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1588 txq_base + txq_index) | 1589 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1590 1591 /* Prevent other PFs on the same adapter from accessing the Tx queue 1592 * context interface concurrently. 1593 */ 1594 spin_lock(&pf->adapter->txq_ctx_lock); 1595 1596 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1597 ice_flush(hw); 1598 1599 /* Copy each dword separately from HW */ 1600 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++, ctx++) { 1601 *ctx = rd32(hw, GLCOMM_QTX_CNTX_DATA(i)); 1602 1603 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, *ctx); 1604 } 1605 1606 spin_unlock(&pf->adapter->txq_ctx_lock); 1607 } 1608 1609 /** 1610 * ice_copy_txq_ctx_to_hw - Copy Tx Queue context into HW registers 1611 * @hw: pointer to the hardware structure 1612 * @txq_ctx: pointer to the packed Tx queue context, including internal state 1613 * @txq_index: the index of the Tx queue 1614 */ 1615 static void ice_copy_txq_ctx_to_hw(struct ice_hw *hw, 1616 const ice_txq_ctx_buf_full_t *txq_ctx, 1617 u32 txq_index) 1618 { 1619 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1620 u32 txq_base, reg; 1621 1622 /* Get Tx queue base within card space */ 1623 txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id)); 1624 txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base); 1625 1626 reg = FIELD_PREP(GLCOMM_QTX_CNTX_CTL_CMD_M, 1627 GLCOMM_QTX_CNTX_CTL_CMD_WRITE_NO_DYN) | 1628 FIELD_PREP(GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M, 1629 txq_base + txq_index) | 1630 GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M; 1631 1632 /* Prevent other PFs on the same adapter from accessing the Tx queue 1633 * context interface concurrently. 1634 */ 1635 spin_lock(&pf->adapter->txq_ctx_lock); 1636 1637 /* Copy each dword separately to HW */ 1638 for (int i = 0; i < ICE_TXQ_CTX_FULL_SIZE_DWORDS; i++) { 1639 u32 ctx = ((const u32 *)txq_ctx)[i]; 1640 1641 wr32(hw, GLCOMM_QTX_CNTX_DATA(i), ctx); 1642 1643 ice_debug(hw, ICE_DBG_QCTX, "qtxdata[%d]: %08X\n", i, ctx); 1644 } 1645 1646 wr32(hw, GLCOMM_QTX_CNTX_CTL, reg); 1647 ice_flush(hw); 1648 1649 spin_unlock(&pf->adapter->txq_ctx_lock); 1650 } 1651 1652 /** 1653 * ice_read_txq_ctx - Read Tx queue context from HW 1654 * @hw: pointer to the hardware structure 1655 * @tlan_ctx: pointer to the Tx queue context 1656 * @txq_index: the index of the Tx queue 1657 * 1658 * Read the Tx queue context from the HW registers, then unpack it into the 1659 * ice_tlan_ctx structure for use. 1660 * 1661 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1662 */ 1663 int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1664 u32 txq_index) 1665 { 1666 ice_txq_ctx_buf_full_t buf = {}; 1667 1668 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1669 return -EINVAL; 1670 1671 ice_copy_txq_ctx_from_hw(hw, &buf, txq_index); 1672 ice_unpack_txq_ctx_full(&buf, tlan_ctx); 1673 1674 return 0; 1675 } 1676 1677 /** 1678 * ice_write_txq_ctx - Write Tx queue context to HW 1679 * @hw: pointer to the hardware structure 1680 * @tlan_ctx: pointer to the Tx queue context 1681 * @txq_index: the index of the Tx queue 1682 * 1683 * Pack the Tx queue context into the dense HW layout, then write it into the 1684 * HW registers. 1685 * 1686 * Returns: 0 on success, or -EINVAL on an invalid Tx queue index. 1687 */ 1688 int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx, 1689 u32 txq_index) 1690 { 1691 ice_txq_ctx_buf_full_t buf = {}; 1692 1693 if (txq_index > QTX_COMM_HEAD_MAX_INDEX) 1694 return -EINVAL; 1695 1696 ice_pack_txq_ctx_full(tlan_ctx, &buf); 1697 ice_copy_txq_ctx_to_hw(hw, &buf, txq_index); 1698 1699 return 0; 1700 } 1701 1702 /* Tx time Queue Context */ 1703 static const struct packed_field_u8 ice_txtime_ctx_fields[] = { 1704 /* Field Width LSB */ 1705 ICE_CTX_STORE(ice_txtime_ctx, base, 57, 0), 1706 ICE_CTX_STORE(ice_txtime_ctx, pf_num, 3, 57), 1707 ICE_CTX_STORE(ice_txtime_ctx, vmvf_num, 10, 60), 1708 ICE_CTX_STORE(ice_txtime_ctx, vmvf_type, 2, 70), 1709 ICE_CTX_STORE(ice_txtime_ctx, src_vsi, 10, 72), 1710 ICE_CTX_STORE(ice_txtime_ctx, cpuid, 8, 82), 1711 ICE_CTX_STORE(ice_txtime_ctx, tphrd_desc, 1, 90), 1712 ICE_CTX_STORE(ice_txtime_ctx, qlen, 13, 91), 1713 ICE_CTX_STORE(ice_txtime_ctx, timer_num, 1, 104), 1714 ICE_CTX_STORE(ice_txtime_ctx, txtime_ena_q, 1, 105), 1715 ICE_CTX_STORE(ice_txtime_ctx, drbell_mode_32, 1, 106), 1716 ICE_CTX_STORE(ice_txtime_ctx, ts_res, 4, 107), 1717 ICE_CTX_STORE(ice_txtime_ctx, ts_round_type, 2, 111), 1718 ICE_CTX_STORE(ice_txtime_ctx, ts_pacing_slot, 3, 113), 1719 ICE_CTX_STORE(ice_txtime_ctx, merging_ena, 1, 116), 1720 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_prof_id, 4, 117), 1721 ICE_CTX_STORE(ice_txtime_ctx, ts_fetch_cache_line_aln_thld, 4, 121), 1722 ICE_CTX_STORE(ice_txtime_ctx, tx_pipe_delay_mode, 1, 125), 1723 }; 1724 1725 /** 1726 * ice_pack_txtime_ctx - pack Tx time queue context into a HW buffer 1727 * @ctx: the Tx time queue context to pack 1728 * @buf: the HW buffer to pack into 1729 * 1730 * Pack the Tx time queue context from the CPU-friendly unpacked buffer into 1731 * its bit-packed HW layout. 1732 */ 1733 void ice_pack_txtime_ctx(const struct ice_txtime_ctx *ctx, 1734 ice_txtime_ctx_buf_t *buf) 1735 { 1736 pack_fields(buf, sizeof(*buf), ctx, ice_txtime_ctx_fields, 1737 QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST); 1738 } 1739 1740 /* Sideband Queue command wrappers */ 1741 1742 /** 1743 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1744 * @hw: pointer to the HW struct 1745 * @desc: descriptor describing the command 1746 * @buf: buffer to use for indirect commands (NULL for direct commands) 1747 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1748 * @cd: pointer to command details structure 1749 */ 1750 static int 1751 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1752 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1753 { 1754 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1755 (struct libie_aq_desc *)desc, buf, buf_size, cd); 1756 } 1757 1758 /** 1759 * ice_sbq_rw_reg - Fill Sideband Queue command 1760 * @hw: pointer to the HW struct 1761 * @in: message info to be filled in descriptor 1762 * @flags: control queue descriptor flags 1763 */ 1764 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags) 1765 { 1766 struct ice_sbq_cmd_desc desc = {0}; 1767 struct ice_sbq_msg_req msg = {0}; 1768 u16 msg_len; 1769 int status; 1770 1771 msg_len = sizeof(msg); 1772 1773 msg.dest_dev = in->dest_dev; 1774 msg.opcode = in->opcode; 1775 msg.flags = ICE_SBQ_MSG_FLAGS; 1776 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1777 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1778 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1779 1780 if (in->opcode) 1781 msg.data = cpu_to_le32(in->data); 1782 else 1783 /* data read comes back in completion, so shorten the struct by 1784 * sizeof(msg.data) 1785 */ 1786 msg_len -= sizeof(msg.data); 1787 1788 desc.flags = cpu_to_le16(flags); 1789 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1790 desc.param0.cmd_len = cpu_to_le16(msg_len); 1791 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1792 if (!status && !in->opcode) 1793 in->data = le32_to_cpu 1794 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1795 return status; 1796 } 1797 1798 /* FW Admin Queue command wrappers */ 1799 1800 /* Software lock/mutex that is meant to be held while the Global Config Lock 1801 * in firmware is acquired by the software to prevent most (but not all) types 1802 * of AQ commands from being sent to FW 1803 */ 1804 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1805 1806 /** 1807 * ice_should_retry_sq_send_cmd 1808 * @opcode: AQ opcode 1809 * 1810 * Decide if we should retry the send command routine for the ATQ, depending 1811 * on the opcode. 1812 */ 1813 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1814 { 1815 switch (opcode) { 1816 case ice_aqc_opc_get_link_topo: 1817 case ice_aqc_opc_lldp_stop: 1818 case ice_aqc_opc_lldp_start: 1819 case ice_aqc_opc_lldp_filter_ctrl: 1820 case ice_aqc_opc_sff_eeprom: 1821 return true; 1822 } 1823 1824 return false; 1825 } 1826 1827 /** 1828 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1829 * @hw: pointer to the HW struct 1830 * @cq: pointer to the specific Control queue 1831 * @desc: prefilled descriptor describing the command 1832 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1833 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1834 * @cd: pointer to command details structure 1835 * 1836 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1837 * Queue if the EBUSY AQ error is returned. 1838 */ 1839 static int 1840 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1841 struct libie_aq_desc *desc, void *buf, u16 buf_size, 1842 struct ice_sq_cd *cd) 1843 { 1844 struct libie_aq_desc desc_cpy; 1845 bool is_cmd_for_retry; 1846 u8 *buf_cpy = NULL; 1847 u8 idx = 0; 1848 u16 opcode; 1849 int status; 1850 1851 opcode = le16_to_cpu(desc->opcode); 1852 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1853 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1854 1855 if (is_cmd_for_retry) { 1856 if (buf) { 1857 buf_cpy = kmemdup(buf, buf_size, GFP_KERNEL); 1858 if (!buf_cpy) 1859 return -ENOMEM; 1860 } 1861 1862 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1863 } 1864 1865 do { 1866 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1867 1868 if (!is_cmd_for_retry || !status || 1869 hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) 1870 break; 1871 1872 if (buf_cpy) 1873 memcpy(buf, buf_cpy, buf_size); 1874 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1875 msleep(ICE_SQ_SEND_DELAY_TIME_MS); 1876 1877 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1878 1879 kfree(buf_cpy); 1880 return status; 1881 } 1882 1883 /** 1884 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1885 * @hw: pointer to the HW struct 1886 * @desc: descriptor describing the command 1887 * @buf: buffer to use for indirect commands (NULL for direct commands) 1888 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1889 * @cd: pointer to command details structure 1890 * 1891 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1892 */ 1893 int 1894 ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf, 1895 u16 buf_size, struct ice_sq_cd *cd) 1896 { 1897 struct libie_aqc_req_res *cmd = libie_aq_raw(desc); 1898 bool lock_acquired = false; 1899 int status; 1900 1901 /* When a package download is in process (i.e. when the firmware's 1902 * Global Configuration Lock resource is held), only the Download 1903 * Package, Get Version, Get Package Info List, Upload Section, 1904 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1905 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1906 * Recipes to Profile Association, and Release Resource (with resource 1907 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1908 * must block until the package download completes and the Global Config 1909 * Lock is released. See also ice_acquire_global_cfg_lock(). 1910 */ 1911 switch (le16_to_cpu(desc->opcode)) { 1912 case ice_aqc_opc_download_pkg: 1913 case ice_aqc_opc_get_pkg_info_list: 1914 case ice_aqc_opc_get_ver: 1915 case ice_aqc_opc_upload_section: 1916 case ice_aqc_opc_update_pkg: 1917 case ice_aqc_opc_set_port_params: 1918 case ice_aqc_opc_get_vlan_mode_parameters: 1919 case ice_aqc_opc_set_vlan_mode_parameters: 1920 case ice_aqc_opc_set_tx_topo: 1921 case ice_aqc_opc_get_tx_topo: 1922 case ice_aqc_opc_add_recipe: 1923 case ice_aqc_opc_recipe_to_profile: 1924 case ice_aqc_opc_get_recipe: 1925 case ice_aqc_opc_get_recipe_to_profile: 1926 break; 1927 case ice_aqc_opc_release_res: 1928 if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) 1929 break; 1930 fallthrough; 1931 default: 1932 mutex_lock(&ice_global_cfg_lock_sw); 1933 lock_acquired = true; 1934 break; 1935 } 1936 1937 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1938 if (lock_acquired) 1939 mutex_unlock(&ice_global_cfg_lock_sw); 1940 1941 return status; 1942 } 1943 1944 /** 1945 * ice_aq_get_fw_ver 1946 * @hw: pointer to the HW struct 1947 * @cd: pointer to command details structure or NULL 1948 * 1949 * Get the firmware version (0x0001) from the admin queue commands 1950 */ 1951 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1952 { 1953 struct libie_aqc_get_ver *resp; 1954 struct libie_aq_desc desc; 1955 int status; 1956 1957 resp = &desc.params.get_ver; 1958 1959 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1960 1961 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1962 1963 if (!status) { 1964 hw->fw_branch = resp->fw_branch; 1965 hw->fw_maj_ver = resp->fw_major; 1966 hw->fw_min_ver = resp->fw_minor; 1967 hw->fw_patch = resp->fw_patch; 1968 hw->fw_build = le32_to_cpu(resp->fw_build); 1969 hw->api_branch = resp->api_branch; 1970 hw->api_maj_ver = resp->api_major; 1971 hw->api_min_ver = resp->api_minor; 1972 hw->api_patch = resp->api_patch; 1973 } 1974 1975 return status; 1976 } 1977 1978 /** 1979 * ice_aq_send_driver_ver 1980 * @hw: pointer to the HW struct 1981 * @dv: driver's major, minor version 1982 * @cd: pointer to command details structure or NULL 1983 * 1984 * Send the driver version (0x0002) to the firmware 1985 */ 1986 int 1987 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1988 struct ice_sq_cd *cd) 1989 { 1990 struct libie_aqc_driver_ver *cmd; 1991 struct libie_aq_desc desc; 1992 u16 len; 1993 1994 cmd = &desc.params.driver_ver; 1995 1996 if (!dv) 1997 return -EINVAL; 1998 1999 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 2000 2001 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2002 cmd->major_ver = dv->major_ver; 2003 cmd->minor_ver = dv->minor_ver; 2004 cmd->build_ver = dv->build_ver; 2005 cmd->subbuild_ver = dv->subbuild_ver; 2006 2007 len = 0; 2008 while (len < sizeof(dv->driver_string) && 2009 isascii(dv->driver_string[len]) && dv->driver_string[len]) 2010 len++; 2011 2012 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 2013 } 2014 2015 /** 2016 * ice_aq_q_shutdown 2017 * @hw: pointer to the HW struct 2018 * @unloading: is the driver unloading itself 2019 * 2020 * Tell the Firmware that we're shutting down the AdminQ and whether 2021 * or not the driver is unloading as well (0x0003). 2022 */ 2023 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 2024 { 2025 struct ice_aqc_q_shutdown *cmd; 2026 struct libie_aq_desc desc; 2027 2028 cmd = libie_aq_raw(&desc); 2029 2030 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 2031 2032 if (unloading) 2033 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 2034 2035 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2036 } 2037 2038 /** 2039 * ice_aq_req_res 2040 * @hw: pointer to the HW struct 2041 * @res: resource ID 2042 * @access: access type 2043 * @sdp_number: resource number 2044 * @timeout: the maximum time in ms that the driver may hold the resource 2045 * @cd: pointer to command details structure or NULL 2046 * 2047 * Requests common resource using the admin queue commands (0x0008). 2048 * When attempting to acquire the Global Config Lock, the driver can 2049 * learn of three states: 2050 * 1) 0 - acquired lock, and can perform download package 2051 * 2) -EIO - did not get lock, driver should fail to load 2052 * 3) -EALREADY - did not get lock, but another driver has 2053 * successfully downloaded the package; the driver does 2054 * not have to download the package and can continue 2055 * loading 2056 * 2057 * Note that if the caller is in an acquire lock, perform action, release lock 2058 * phase of operation, it is possible that the FW may detect a timeout and issue 2059 * a CORER. In this case, the driver will receive a CORER interrupt and will 2060 * have to determine its cause. The calling thread that is handling this flow 2061 * will likely get an error propagated back to it indicating the Download 2062 * Package, Update Package or the Release Resource AQ commands timed out. 2063 */ 2064 static int 2065 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2066 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 2067 struct ice_sq_cd *cd) 2068 { 2069 struct libie_aqc_req_res *cmd_resp; 2070 struct libie_aq_desc desc; 2071 int status; 2072 2073 cmd_resp = &desc.params.res_owner; 2074 2075 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 2076 2077 cmd_resp->res_id = cpu_to_le16(res); 2078 cmd_resp->access_type = cpu_to_le16(access); 2079 cmd_resp->res_number = cpu_to_le32(sdp_number); 2080 cmd_resp->timeout = cpu_to_le32(*timeout); 2081 *timeout = 0; 2082 2083 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2084 2085 /* The completion specifies the maximum time in ms that the driver 2086 * may hold the resource in the Timeout field. 2087 */ 2088 2089 /* Global config lock response utilizes an additional status field. 2090 * 2091 * If the Global config lock resource is held by some other driver, the 2092 * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field 2093 * and the timeout field indicates the maximum time the current owner 2094 * of the resource has to free it. 2095 */ 2096 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 2097 if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) { 2098 *timeout = le32_to_cpu(cmd_resp->timeout); 2099 return 0; 2100 } else if (le16_to_cpu(cmd_resp->status) == 2101 LIBIE_AQ_RES_GLBL_IN_PROG) { 2102 *timeout = le32_to_cpu(cmd_resp->timeout); 2103 return -EIO; 2104 } else if (le16_to_cpu(cmd_resp->status) == 2105 LIBIE_AQ_RES_GLBL_DONE) { 2106 return -EALREADY; 2107 } 2108 2109 /* invalid FW response, force a timeout immediately */ 2110 *timeout = 0; 2111 return -EIO; 2112 } 2113 2114 /* If the resource is held by some other driver, the command completes 2115 * with a busy return value and the timeout field indicates the maximum 2116 * time the current owner of the resource has to free it. 2117 */ 2118 if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY) 2119 *timeout = le32_to_cpu(cmd_resp->timeout); 2120 2121 return status; 2122 } 2123 2124 /** 2125 * ice_aq_release_res 2126 * @hw: pointer to the HW struct 2127 * @res: resource ID 2128 * @sdp_number: resource number 2129 * @cd: pointer to command details structure or NULL 2130 * 2131 * release common resource using the admin queue commands (0x0009) 2132 */ 2133 static int 2134 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 2135 struct ice_sq_cd *cd) 2136 { 2137 struct libie_aqc_req_res *cmd; 2138 struct libie_aq_desc desc; 2139 2140 cmd = &desc.params.res_owner; 2141 2142 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 2143 2144 cmd->res_id = cpu_to_le16(res); 2145 cmd->res_number = cpu_to_le32(sdp_number); 2146 2147 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2148 } 2149 2150 /** 2151 * ice_acquire_res 2152 * @hw: pointer to the HW structure 2153 * @res: resource ID 2154 * @access: access type (read or write) 2155 * @timeout: timeout in milliseconds 2156 * 2157 * This function will attempt to acquire the ownership of a resource. 2158 */ 2159 int 2160 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 2161 enum ice_aq_res_access_type access, u32 timeout) 2162 { 2163 #define ICE_RES_POLLING_DELAY_MS 10 2164 u32 delay = ICE_RES_POLLING_DELAY_MS; 2165 u32 time_left = timeout; 2166 int status; 2167 2168 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2169 2170 /* A return code of -EALREADY means that another driver has 2171 * previously acquired the resource and performed any necessary updates; 2172 * in this case the caller does not obtain the resource and has no 2173 * further work to do. 2174 */ 2175 if (status == -EALREADY) 2176 goto ice_acquire_res_exit; 2177 2178 if (status) 2179 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 2180 2181 /* If necessary, poll until the current lock owner timeouts */ 2182 timeout = time_left; 2183 while (status && timeout && time_left) { 2184 mdelay(delay); 2185 timeout = (timeout > delay) ? timeout - delay : 0; 2186 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 2187 2188 if (status == -EALREADY) 2189 /* lock free, but no work to do */ 2190 break; 2191 2192 if (!status) 2193 /* lock acquired */ 2194 break; 2195 } 2196 if (status && status != -EALREADY) 2197 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 2198 2199 ice_acquire_res_exit: 2200 if (status == -EALREADY) { 2201 if (access == ICE_RES_WRITE) 2202 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 2203 else 2204 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 2205 } 2206 return status; 2207 } 2208 2209 /** 2210 * ice_release_res 2211 * @hw: pointer to the HW structure 2212 * @res: resource ID 2213 * 2214 * This function will release a resource using the proper Admin Command. 2215 */ 2216 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 2217 { 2218 unsigned long timeout; 2219 int status; 2220 2221 /* there are some rare cases when trying to release the resource 2222 * results in an admin queue timeout, so handle them correctly 2223 */ 2224 timeout = jiffies + 10 * usecs_to_jiffies(ICE_CTL_Q_SQ_CMD_TIMEOUT); 2225 do { 2226 status = ice_aq_release_res(hw, res, 0, NULL); 2227 if (status != -EIO) 2228 break; 2229 usleep_range(1000, 2000); 2230 } while (time_before(jiffies, timeout)); 2231 } 2232 2233 /** 2234 * ice_aq_alloc_free_res - command to allocate/free resources 2235 * @hw: pointer to the HW struct 2236 * @buf: Indirect buffer to hold data parameters and response 2237 * @buf_size: size of buffer for indirect commands 2238 * @opc: pass in the command opcode 2239 * 2240 * Helper function to allocate/free resources using the admin queue commands 2241 */ 2242 int ice_aq_alloc_free_res(struct ice_hw *hw, 2243 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2244 enum ice_adminq_opc opc) 2245 { 2246 struct ice_aqc_alloc_free_res_cmd *cmd; 2247 struct libie_aq_desc desc; 2248 2249 cmd = libie_aq_raw(&desc); 2250 2251 if (!buf || buf_size < flex_array_size(buf, elem, 1)) 2252 return -EINVAL; 2253 2254 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2255 2256 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 2257 2258 cmd->num_entries = cpu_to_le16(1); 2259 2260 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL); 2261 } 2262 2263 /** 2264 * ice_alloc_hw_res - allocate resource 2265 * @hw: pointer to the HW struct 2266 * @type: type of resource 2267 * @num: number of resources to allocate 2268 * @btm: allocate from bottom 2269 * @res: pointer to array that will receive the resources 2270 */ 2271 int 2272 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2273 { 2274 struct ice_aqc_alloc_free_res_elem *buf; 2275 u16 buf_len; 2276 int status; 2277 2278 buf_len = struct_size(buf, elem, num); 2279 buf = kzalloc(buf_len, GFP_KERNEL); 2280 if (!buf) 2281 return -ENOMEM; 2282 2283 /* Prepare buffer to allocate resource. */ 2284 buf->num_elems = cpu_to_le16(num); 2285 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2286 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2287 if (btm) 2288 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2289 2290 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); 2291 if (status) 2292 goto ice_alloc_res_exit; 2293 2294 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2295 2296 ice_alloc_res_exit: 2297 kfree(buf); 2298 return status; 2299 } 2300 2301 /** 2302 * ice_free_hw_res - free allocated HW resource 2303 * @hw: pointer to the HW struct 2304 * @type: type of resource to free 2305 * @num: number of resources 2306 * @res: pointer to array that contains the resources to free 2307 */ 2308 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2309 { 2310 struct ice_aqc_alloc_free_res_elem *buf; 2311 u16 buf_len; 2312 int status; 2313 2314 buf_len = struct_size(buf, elem, num); 2315 buf = kzalloc(buf_len, GFP_KERNEL); 2316 if (!buf) 2317 return -ENOMEM; 2318 2319 /* Prepare buffer to free resource. */ 2320 buf->num_elems = cpu_to_le16(num); 2321 buf->res_type = cpu_to_le16(type); 2322 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2323 2324 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); 2325 if (status) 2326 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2327 2328 kfree(buf); 2329 return status; 2330 } 2331 2332 /** 2333 * ice_get_num_per_func - determine number of resources per PF 2334 * @hw: pointer to the HW structure 2335 * @max: value to be evenly split between each PF 2336 * 2337 * Determine the number of valid functions by going through the bitmap returned 2338 * from parsing capabilities and use this to calculate the number of resources 2339 * per PF based on the max value passed in. 2340 */ 2341 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2342 { 2343 u8 funcs; 2344 2345 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2346 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2347 ICE_CAPS_VALID_FUNCS_M); 2348 2349 if (!funcs) 2350 return 0; 2351 2352 return max / funcs; 2353 } 2354 2355 /** 2356 * ice_parse_common_caps - parse common device/function capabilities 2357 * @hw: pointer to the HW struct 2358 * @caps: pointer to common capabilities structure 2359 * @elem: the capability element to parse 2360 * @prefix: message prefix for tracing capabilities 2361 * 2362 * Given a capability element, extract relevant details into the common 2363 * capability structure. 2364 * 2365 * Returns: true if the capability matches one of the common capability ids, 2366 * false otherwise. 2367 */ 2368 static bool 2369 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2370 struct libie_aqc_list_caps_elem *elem, const char *prefix) 2371 { 2372 u32 logical_id = le32_to_cpu(elem->logical_id); 2373 u32 phys_id = le32_to_cpu(elem->phys_id); 2374 u32 number = le32_to_cpu(elem->number); 2375 u16 cap = le16_to_cpu(elem->cap); 2376 bool found = true; 2377 2378 switch (cap) { 2379 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2380 caps->valid_functions = number; 2381 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2382 caps->valid_functions); 2383 break; 2384 case LIBIE_AQC_CAPS_SRIOV: 2385 caps->sr_iov_1_1 = (number == 1); 2386 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2387 caps->sr_iov_1_1); 2388 break; 2389 case LIBIE_AQC_CAPS_DCB: 2390 caps->dcb = (number == 1); 2391 caps->active_tc_bitmap = logical_id; 2392 caps->maxtc = phys_id; 2393 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2394 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2395 caps->active_tc_bitmap); 2396 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2397 break; 2398 case LIBIE_AQC_CAPS_RSS: 2399 caps->rss_table_size = number; 2400 caps->rss_table_entry_width = logical_id; 2401 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2402 caps->rss_table_size); 2403 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2404 caps->rss_table_entry_width); 2405 break; 2406 case LIBIE_AQC_CAPS_RXQS: 2407 caps->num_rxq = number; 2408 caps->rxq_first_id = phys_id; 2409 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2410 caps->num_rxq); 2411 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2412 caps->rxq_first_id); 2413 break; 2414 case LIBIE_AQC_CAPS_TXQS: 2415 caps->num_txq = number; 2416 caps->txq_first_id = phys_id; 2417 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2418 caps->num_txq); 2419 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2420 caps->txq_first_id); 2421 break; 2422 case LIBIE_AQC_CAPS_MSIX: 2423 caps->num_msix_vectors = number; 2424 caps->msix_vector_first_id = phys_id; 2425 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2426 caps->num_msix_vectors); 2427 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2428 caps->msix_vector_first_id); 2429 break; 2430 case LIBIE_AQC_CAPS_PENDING_NVM_VER: 2431 caps->nvm_update_pending_nvm = true; 2432 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2433 break; 2434 case LIBIE_AQC_CAPS_PENDING_OROM_VER: 2435 caps->nvm_update_pending_orom = true; 2436 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2437 break; 2438 case LIBIE_AQC_CAPS_PENDING_NET_VER: 2439 caps->nvm_update_pending_netlist = true; 2440 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2441 break; 2442 case LIBIE_AQC_CAPS_NVM_MGMT: 2443 caps->nvm_unified_update = 2444 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2445 true : false; 2446 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2447 caps->nvm_unified_update); 2448 break; 2449 case LIBIE_AQC_CAPS_RDMA: 2450 if (IS_ENABLED(CONFIG_INFINIBAND_IRDMA)) 2451 caps->rdma = (number == 1); 2452 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2453 break; 2454 case LIBIE_AQC_CAPS_MAX_MTU: 2455 caps->max_mtu = number; 2456 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2457 prefix, caps->max_mtu); 2458 break; 2459 case LIBIE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2460 caps->pcie_reset_avoidance = (number > 0); 2461 ice_debug(hw, ICE_DBG_INIT, 2462 "%s: pcie_reset_avoidance = %d\n", prefix, 2463 caps->pcie_reset_avoidance); 2464 break; 2465 case LIBIE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2466 caps->reset_restrict_support = (number == 1); 2467 ice_debug(hw, ICE_DBG_INIT, 2468 "%s: reset_restrict_support = %d\n", prefix, 2469 caps->reset_restrict_support); 2470 break; 2471 case LIBIE_AQC_CAPS_FW_LAG_SUPPORT: 2472 caps->roce_lag = number & LIBIE_AQC_BIT_ROCEV2_LAG; 2473 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n", 2474 prefix, caps->roce_lag); 2475 caps->sriov_lag = number & LIBIE_AQC_BIT_SRIOV_LAG; 2476 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n", 2477 prefix, caps->sriov_lag); 2478 caps->sriov_aa_lag = number & LIBIE_AQC_BIT_SRIOV_AA_LAG; 2479 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_aa_lag = %u\n", 2480 prefix, caps->sriov_aa_lag); 2481 break; 2482 case LIBIE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE: 2483 caps->tx_sched_topo_comp_mode_en = (number == 1); 2484 break; 2485 default: 2486 /* Not one of the recognized common capabilities */ 2487 found = false; 2488 } 2489 2490 return found; 2491 } 2492 2493 /** 2494 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2495 * @hw: pointer to the HW structure 2496 * @caps: pointer to capabilities structure to fix 2497 * 2498 * Re-calculate the capabilities that are dependent on the number of physical 2499 * ports; i.e. some features are not supported or function differently on 2500 * devices with more than 4 ports. 2501 */ 2502 static void 2503 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2504 { 2505 /* This assumes device capabilities are always scanned before function 2506 * capabilities during the initialization flow. 2507 */ 2508 if (hw->dev_caps.num_funcs > 4) { 2509 /* Max 4 TCs per port */ 2510 caps->maxtc = 4; 2511 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2512 caps->maxtc); 2513 if (caps->rdma) { 2514 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2515 caps->rdma = 0; 2516 } 2517 2518 /* print message only when processing device capabilities 2519 * during initialization. 2520 */ 2521 if (caps == &hw->dev_caps.common_cap) 2522 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2523 } 2524 } 2525 2526 /** 2527 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2528 * @hw: pointer to the HW struct 2529 * @func_p: pointer to function capabilities structure 2530 * @cap: pointer to the capability element to parse 2531 * 2532 * Extract function capabilities for ICE_AQC_CAPS_VF. 2533 */ 2534 static void 2535 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2536 struct libie_aqc_list_caps_elem *cap) 2537 { 2538 u32 logical_id = le32_to_cpu(cap->logical_id); 2539 u32 number = le32_to_cpu(cap->number); 2540 2541 func_p->num_allocd_vfs = number; 2542 func_p->vf_base_id = logical_id; 2543 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2544 func_p->num_allocd_vfs); 2545 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2546 func_p->vf_base_id); 2547 } 2548 2549 /** 2550 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2551 * @hw: pointer to the HW struct 2552 * @func_p: pointer to function capabilities structure 2553 * @cap: pointer to the capability element to parse 2554 * 2555 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2556 */ 2557 static void 2558 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2559 struct libie_aqc_list_caps_elem *cap) 2560 { 2561 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2562 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2563 le32_to_cpu(cap->number)); 2564 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2565 func_p->guar_num_vsi); 2566 } 2567 2568 /** 2569 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2570 * @hw: pointer to the HW struct 2571 * @func_p: pointer to function capabilities structure 2572 * @cap: pointer to the capability element to parse 2573 * 2574 * Extract function capabilities for ICE_AQC_CAPS_1588. 2575 */ 2576 static void 2577 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2578 struct libie_aqc_list_caps_elem *cap) 2579 { 2580 struct ice_ts_func_info *info = &func_p->ts_func_info; 2581 u32 number = le32_to_cpu(cap->number); 2582 2583 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2584 func_p->common_cap.ieee_1588 = info->ena; 2585 2586 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2587 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2588 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2589 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2590 2591 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { 2592 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); 2593 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2594 } else { 2595 info->clk_freq = ICE_TSPLL_FREQ_156_250; 2596 info->clk_src = ICE_CLK_SRC_TIME_REF; 2597 } 2598 2599 if (info->clk_freq < NUM_ICE_TSPLL_FREQ) { 2600 info->time_ref = (enum ice_tspll_freq)info->clk_freq; 2601 } else { 2602 /* Unknown clock frequency, so assume a (probably incorrect) 2603 * default to avoid out-of-bounds look ups of frequency 2604 * related information. 2605 */ 2606 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2607 info->clk_freq); 2608 info->time_ref = ICE_TSPLL_FREQ_25_000; 2609 } 2610 2611 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2612 func_p->common_cap.ieee_1588); 2613 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2614 info->src_tmr_owned); 2615 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2616 info->tmr_ena); 2617 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2618 info->tmr_index_owned); 2619 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2620 info->tmr_index_assoc); 2621 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2622 info->clk_freq); 2623 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2624 info->clk_src); 2625 } 2626 2627 /** 2628 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2629 * @hw: pointer to the HW struct 2630 * @func_p: pointer to function capabilities structure 2631 * 2632 * Extract function capabilities for ICE_AQC_CAPS_FD. 2633 */ 2634 static void 2635 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2636 { 2637 u32 reg_val, gsize, bsize; 2638 2639 reg_val = rd32(hw, GLQF_FD_SIZE); 2640 switch (hw->mac_type) { 2641 case ICE_MAC_E830: 2642 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2643 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2644 break; 2645 case ICE_MAC_E810: 2646 default: 2647 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val); 2648 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val); 2649 } 2650 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); 2651 func_p->fd_fltr_best_effort = bsize; 2652 2653 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2654 func_p->fd_fltr_guar); 2655 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2656 func_p->fd_fltr_best_effort); 2657 } 2658 2659 /** 2660 * ice_parse_func_caps - Parse function capabilities 2661 * @hw: pointer to the HW struct 2662 * @func_p: pointer to function capabilities structure 2663 * @buf: buffer containing the function capability records 2664 * @cap_count: the number of capabilities 2665 * 2666 * Helper function to parse function (0x000A) capabilities list. For 2667 * capabilities shared between device and function, this relies on 2668 * ice_parse_common_caps. 2669 * 2670 * Loop through the list of provided capabilities and extract the relevant 2671 * data into the function capabilities structured. 2672 */ 2673 static void 2674 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2675 void *buf, u32 cap_count) 2676 { 2677 struct libie_aqc_list_caps_elem *cap_resp; 2678 u32 i; 2679 2680 cap_resp = buf; 2681 2682 memset(func_p, 0, sizeof(*func_p)); 2683 2684 for (i = 0; i < cap_count; i++) { 2685 u16 cap = le16_to_cpu(cap_resp[i].cap); 2686 bool found; 2687 2688 found = ice_parse_common_caps(hw, &func_p->common_cap, 2689 &cap_resp[i], "func caps"); 2690 2691 switch (cap) { 2692 case LIBIE_AQC_CAPS_VF: 2693 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2694 break; 2695 case LIBIE_AQC_CAPS_VSI: 2696 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2697 break; 2698 case LIBIE_AQC_CAPS_1588: 2699 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2700 break; 2701 case LIBIE_AQC_CAPS_FD: 2702 ice_parse_fdir_func_caps(hw, func_p); 2703 break; 2704 default: 2705 /* Don't list common capabilities as unknown */ 2706 if (!found) 2707 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2708 i, cap); 2709 break; 2710 } 2711 } 2712 2713 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2714 } 2715 2716 /** 2717 * ice_func_id_to_logical_id - map from function id to logical pf id 2718 * @active_function_bitmap: active function bitmap 2719 * @pf_id: function number of device 2720 * 2721 * Return: logical PF ID. 2722 */ 2723 static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id) 2724 { 2725 u8 logical_id = 0; 2726 u8 i; 2727 2728 for (i = 0; i < pf_id; i++) 2729 if (active_function_bitmap & BIT(i)) 2730 logical_id++; 2731 2732 return logical_id; 2733 } 2734 2735 /** 2736 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2737 * @hw: pointer to the HW struct 2738 * @dev_p: pointer to device capabilities structure 2739 * @cap: capability element to parse 2740 * 2741 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2742 */ 2743 static void 2744 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2745 struct libie_aqc_list_caps_elem *cap) 2746 { 2747 u32 number = le32_to_cpu(cap->number); 2748 2749 dev_p->num_funcs = hweight32(number); 2750 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2751 dev_p->num_funcs); 2752 2753 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); 2754 } 2755 2756 /** 2757 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2758 * @hw: pointer to the HW struct 2759 * @dev_p: pointer to device capabilities structure 2760 * @cap: capability element to parse 2761 * 2762 * Parse ICE_AQC_CAPS_VF for device capabilities. 2763 */ 2764 static void 2765 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2766 struct libie_aqc_list_caps_elem *cap) 2767 { 2768 u32 number = le32_to_cpu(cap->number); 2769 2770 dev_p->num_vfs_exposed = number; 2771 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2772 dev_p->num_vfs_exposed); 2773 } 2774 2775 /** 2776 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2777 * @hw: pointer to the HW struct 2778 * @dev_p: pointer to device capabilities structure 2779 * @cap: capability element to parse 2780 * 2781 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2782 */ 2783 static void 2784 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2785 struct libie_aqc_list_caps_elem *cap) 2786 { 2787 u32 number = le32_to_cpu(cap->number); 2788 2789 dev_p->num_vsi_allocd_to_host = number; 2790 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2791 dev_p->num_vsi_allocd_to_host); 2792 } 2793 2794 /** 2795 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2796 * @hw: pointer to the HW struct 2797 * @dev_p: pointer to device capabilities structure 2798 * @cap: capability element to parse 2799 * 2800 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2801 */ 2802 static void 2803 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2804 struct libie_aqc_list_caps_elem *cap) 2805 { 2806 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2807 u32 logical_id = le32_to_cpu(cap->logical_id); 2808 u32 phys_id = le32_to_cpu(cap->phys_id); 2809 u32 number = le32_to_cpu(cap->number); 2810 2811 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2812 dev_p->common_cap.ieee_1588 = info->ena; 2813 2814 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2815 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2816 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2817 2818 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); 2819 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2820 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2821 2822 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2823 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); 2824 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); 2825 2826 info->ena_ports = logical_id; 2827 info->tmr_own_map = phys_id; 2828 2829 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2830 dev_p->common_cap.ieee_1588); 2831 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2832 info->tmr0_owner); 2833 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2834 info->tmr0_owned); 2835 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2836 info->tmr0_ena); 2837 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2838 info->tmr1_owner); 2839 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2840 info->tmr1_owned); 2841 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2842 info->tmr1_ena); 2843 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2844 info->ts_ll_read); 2845 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n", 2846 info->ts_ll_int_read); 2847 ice_debug(hw, ICE_DBG_INIT, "dev caps: ll_phy_tmr_update = %u\n", 2848 info->ll_phy_tmr_update); 2849 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2850 info->ena_ports); 2851 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2852 info->tmr_own_map); 2853 } 2854 2855 /** 2856 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2857 * @hw: pointer to the HW struct 2858 * @dev_p: pointer to device capabilities structure 2859 * @cap: capability element to parse 2860 * 2861 * Parse ICE_AQC_CAPS_FD for device capabilities. 2862 */ 2863 static void 2864 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2865 struct libie_aqc_list_caps_elem *cap) 2866 { 2867 u32 number = le32_to_cpu(cap->number); 2868 2869 dev_p->num_flow_director_fltr = number; 2870 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2871 dev_p->num_flow_director_fltr); 2872 } 2873 2874 /** 2875 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap 2876 * @hw: pointer to the HW struct 2877 * @dev_p: pointer to device capabilities structure 2878 * @cap: capability element to parse 2879 * 2880 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading 2881 * enabled sensors. 2882 */ 2883 static void 2884 ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2885 struct libie_aqc_list_caps_elem *cap) 2886 { 2887 dev_p->supported_sensors = le32_to_cpu(cap->number); 2888 2889 ice_debug(hw, ICE_DBG_INIT, 2890 "dev caps: supported sensors (bitmap) = 0x%x\n", 2891 dev_p->supported_sensors); 2892 } 2893 2894 /** 2895 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap 2896 * @hw: pointer to the HW struct 2897 * @dev_p: pointer to device capabilities structure 2898 * @cap: capability element to parse 2899 * 2900 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. 2901 */ 2902 static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw, 2903 struct ice_hw_dev_caps *dev_p, 2904 struct libie_aqc_list_caps_elem *cap) 2905 { 2906 dev_p->nac_topo.mode = le32_to_cpu(cap->number); 2907 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; 2908 2909 dev_info(ice_hw_to_dev(hw), 2910 "PF is configured in %s mode with IP instance ID %d\n", 2911 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? 2912 "primary" : "secondary", dev_p->nac_topo.id); 2913 2914 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", 2915 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); 2916 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", 2917 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); 2918 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", 2919 dev_p->nac_topo.id); 2920 } 2921 2922 /** 2923 * ice_parse_dev_caps - Parse device capabilities 2924 * @hw: pointer to the HW struct 2925 * @dev_p: pointer to device capabilities structure 2926 * @buf: buffer containing the device capability records 2927 * @cap_count: the number of capabilities 2928 * 2929 * Helper device to parse device (0x000B) capabilities list. For 2930 * capabilities shared between device and function, this relies on 2931 * ice_parse_common_caps. 2932 * 2933 * Loop through the list of provided capabilities and extract the relevant 2934 * data into the device capabilities structured. 2935 */ 2936 static void 2937 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2938 void *buf, u32 cap_count) 2939 { 2940 struct libie_aqc_list_caps_elem *cap_resp; 2941 u32 i; 2942 2943 cap_resp = buf; 2944 2945 memset(dev_p, 0, sizeof(*dev_p)); 2946 2947 for (i = 0; i < cap_count; i++) { 2948 u16 cap = le16_to_cpu(cap_resp[i].cap); 2949 bool found; 2950 2951 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2952 &cap_resp[i], "dev caps"); 2953 2954 switch (cap) { 2955 case LIBIE_AQC_CAPS_VALID_FUNCTIONS: 2956 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2957 break; 2958 case LIBIE_AQC_CAPS_VF: 2959 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2960 break; 2961 case LIBIE_AQC_CAPS_VSI: 2962 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2963 break; 2964 case LIBIE_AQC_CAPS_1588: 2965 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2966 break; 2967 case LIBIE_AQC_CAPS_FD: 2968 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2969 break; 2970 case LIBIE_AQC_CAPS_SENSOR_READING: 2971 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); 2972 break; 2973 case LIBIE_AQC_CAPS_NAC_TOPOLOGY: 2974 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); 2975 break; 2976 default: 2977 /* Don't list common capabilities as unknown */ 2978 if (!found) 2979 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2980 i, cap); 2981 break; 2982 } 2983 } 2984 2985 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2986 } 2987 2988 /** 2989 * ice_is_phy_rclk_in_netlist 2990 * @hw: pointer to the hw struct 2991 * 2992 * Check if the PHY Recovered Clock device is present in the netlist 2993 */ 2994 bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw) 2995 { 2996 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 2997 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 2998 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) && 2999 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY, 3000 ICE_AQC_LINK_TOPO_NODE_CTX_PORT, 3001 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) 3002 return false; 3003 3004 return true; 3005 } 3006 3007 /** 3008 * ice_is_clock_mux_in_netlist 3009 * @hw: pointer to the hw struct 3010 * 3011 * Check if the Clock Multiplexer device is present in the netlist 3012 */ 3013 bool ice_is_clock_mux_in_netlist(struct ice_hw *hw) 3014 { 3015 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX, 3016 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3017 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX, 3018 NULL)) 3019 return false; 3020 3021 return true; 3022 } 3023 3024 /** 3025 * ice_is_cgu_in_netlist - check for CGU presence 3026 * @hw: pointer to the hw struct 3027 * 3028 * Check if the Clock Generation Unit (CGU) device is present in the netlist. 3029 * Save the CGU part number in the hw structure for later use. 3030 * Return: 3031 * * true - cgu is present 3032 * * false - cgu is not present 3033 */ 3034 bool ice_is_cgu_in_netlist(struct ice_hw *hw) 3035 { 3036 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3037 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3038 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032, 3039 NULL)) { 3040 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; 3041 return true; 3042 } else if (!ice_find_netlist_node(hw, 3043 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL, 3044 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3045 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384, 3046 NULL)) { 3047 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; 3048 return true; 3049 } 3050 3051 return false; 3052 } 3053 3054 /** 3055 * ice_is_gps_in_netlist 3056 * @hw: pointer to the hw struct 3057 * 3058 * Check if the GPS generic device is present in the netlist 3059 */ 3060 bool ice_is_gps_in_netlist(struct ice_hw *hw) 3061 { 3062 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS, 3063 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL, 3064 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) 3065 return false; 3066 3067 return true; 3068 } 3069 3070 /** 3071 * ice_aq_list_caps - query function/device capabilities 3072 * @hw: pointer to the HW struct 3073 * @buf: a buffer to hold the capabilities 3074 * @buf_size: size of the buffer 3075 * @cap_count: if not NULL, set to the number of capabilities reported 3076 * @opc: capabilities type to discover, device or function 3077 * @cd: pointer to command details structure or NULL 3078 * 3079 * Get the function (0x000A) or device (0x000B) capabilities description from 3080 * firmware and store it in the buffer. 3081 * 3082 * If the cap_count pointer is not NULL, then it is set to the number of 3083 * capabilities firmware will report. Note that if the buffer size is too 3084 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 3085 * cap_count will still be updated in this case. It is recommended that the 3086 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 3087 * firmware could return) to avoid this. 3088 */ 3089 int 3090 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 3091 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 3092 { 3093 struct libie_aqc_list_caps *cmd; 3094 struct libie_aq_desc desc; 3095 int status; 3096 3097 cmd = &desc.params.get_cap; 3098 3099 if (opc != ice_aqc_opc_list_func_caps && 3100 opc != ice_aqc_opc_list_dev_caps) 3101 return -EINVAL; 3102 3103 ice_fill_dflt_direct_cmd_desc(&desc, opc); 3104 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 3105 3106 if (cap_count) 3107 *cap_count = le32_to_cpu(cmd->count); 3108 3109 return status; 3110 } 3111 3112 /** 3113 * ice_discover_dev_caps - Read and extract device capabilities 3114 * @hw: pointer to the hardware structure 3115 * @dev_caps: pointer to device capabilities structure 3116 * 3117 * Read the device capabilities and extract them into the dev_caps structure 3118 * for later use. 3119 */ 3120 int 3121 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 3122 { 3123 u32 cap_count = 0; 3124 void *cbuf; 3125 int status; 3126 3127 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3128 if (!cbuf) 3129 return -ENOMEM; 3130 3131 /* Although the driver doesn't know the number of capabilities the 3132 * device will return, we can simply send a 4KB buffer, the maximum 3133 * possible size that firmware can return. 3134 */ 3135 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3136 3137 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3138 ice_aqc_opc_list_dev_caps, NULL); 3139 if (!status) 3140 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 3141 kfree(cbuf); 3142 3143 return status; 3144 } 3145 3146 /** 3147 * ice_discover_func_caps - Read and extract function capabilities 3148 * @hw: pointer to the hardware structure 3149 * @func_caps: pointer to function capabilities structure 3150 * 3151 * Read the function capabilities and extract them into the func_caps structure 3152 * for later use. 3153 */ 3154 static int 3155 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 3156 { 3157 u32 cap_count = 0; 3158 void *cbuf; 3159 int status; 3160 3161 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 3162 if (!cbuf) 3163 return -ENOMEM; 3164 3165 /* Although the driver doesn't know the number of capabilities the 3166 * device will return, we can simply send a 4KB buffer, the maximum 3167 * possible size that firmware can return. 3168 */ 3169 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem); 3170 3171 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 3172 ice_aqc_opc_list_func_caps, NULL); 3173 if (!status) 3174 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 3175 kfree(cbuf); 3176 3177 return status; 3178 } 3179 3180 /** 3181 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 3182 * @hw: pointer to the hardware structure 3183 */ 3184 void ice_set_safe_mode_caps(struct ice_hw *hw) 3185 { 3186 struct ice_hw_func_caps *func_caps = &hw->func_caps; 3187 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 3188 struct ice_hw_common_caps cached_caps; 3189 u32 num_funcs; 3190 3191 /* cache some func_caps values that should be restored after memset */ 3192 cached_caps = func_caps->common_cap; 3193 3194 /* unset func capabilities */ 3195 memset(func_caps, 0, sizeof(*func_caps)); 3196 3197 #define ICE_RESTORE_FUNC_CAP(name) \ 3198 func_caps->common_cap.name = cached_caps.name 3199 3200 /* restore cached values */ 3201 ICE_RESTORE_FUNC_CAP(valid_functions); 3202 ICE_RESTORE_FUNC_CAP(txq_first_id); 3203 ICE_RESTORE_FUNC_CAP(rxq_first_id); 3204 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 3205 ICE_RESTORE_FUNC_CAP(max_mtu); 3206 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 3207 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 3208 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 3209 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 3210 3211 /* one Tx and one Rx queue in safe mode */ 3212 func_caps->common_cap.num_rxq = 1; 3213 func_caps->common_cap.num_txq = 1; 3214 3215 /* two MSIX vectors, one for traffic and one for misc causes */ 3216 func_caps->common_cap.num_msix_vectors = 2; 3217 func_caps->guar_num_vsi = 1; 3218 3219 /* cache some dev_caps values that should be restored after memset */ 3220 cached_caps = dev_caps->common_cap; 3221 num_funcs = dev_caps->num_funcs; 3222 3223 /* unset dev capabilities */ 3224 memset(dev_caps, 0, sizeof(*dev_caps)); 3225 3226 #define ICE_RESTORE_DEV_CAP(name) \ 3227 dev_caps->common_cap.name = cached_caps.name 3228 3229 /* restore cached values */ 3230 ICE_RESTORE_DEV_CAP(valid_functions); 3231 ICE_RESTORE_DEV_CAP(txq_first_id); 3232 ICE_RESTORE_DEV_CAP(rxq_first_id); 3233 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 3234 ICE_RESTORE_DEV_CAP(max_mtu); 3235 ICE_RESTORE_DEV_CAP(nvm_unified_update); 3236 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 3237 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 3238 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 3239 dev_caps->num_funcs = num_funcs; 3240 3241 /* one Tx and one Rx queue per function in safe mode */ 3242 dev_caps->common_cap.num_rxq = num_funcs; 3243 dev_caps->common_cap.num_txq = num_funcs; 3244 3245 /* two MSIX vectors per function */ 3246 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 3247 } 3248 3249 /** 3250 * ice_get_caps - get info about the HW 3251 * @hw: pointer to the hardware structure 3252 */ 3253 int ice_get_caps(struct ice_hw *hw) 3254 { 3255 int status; 3256 3257 status = ice_discover_dev_caps(hw, &hw->dev_caps); 3258 if (status) 3259 return status; 3260 3261 return ice_discover_func_caps(hw, &hw->func_caps); 3262 } 3263 3264 /** 3265 * ice_aq_manage_mac_write - manage MAC address write command 3266 * @hw: pointer to the HW struct 3267 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 3268 * @flags: flags to control write behavior 3269 * @cd: pointer to command details structure or NULL 3270 * 3271 * This function is used to write MAC address to the NVM (0x0108). 3272 */ 3273 int 3274 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 3275 struct ice_sq_cd *cd) 3276 { 3277 struct ice_aqc_manage_mac_write *cmd; 3278 struct libie_aq_desc desc; 3279 3280 cmd = libie_aq_raw(&desc); 3281 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 3282 3283 cmd->flags = flags; 3284 ether_addr_copy(cmd->mac_addr, mac_addr); 3285 3286 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3287 } 3288 3289 /** 3290 * ice_aq_clear_pxe_mode 3291 * @hw: pointer to the HW struct 3292 * 3293 * Tell the firmware that the driver is taking over from PXE (0x0110). 3294 */ 3295 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 3296 { 3297 struct ice_aqc_clear_pxe *cmd; 3298 struct libie_aq_desc desc; 3299 3300 cmd = libie_aq_raw(&desc); 3301 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 3302 cmd->rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 3303 3304 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3305 } 3306 3307 /** 3308 * ice_clear_pxe_mode - clear pxe operations mode 3309 * @hw: pointer to the HW struct 3310 * 3311 * Make sure all PXE mode settings are cleared, including things 3312 * like descriptor fetch/write-back mode. 3313 */ 3314 void ice_clear_pxe_mode(struct ice_hw *hw) 3315 { 3316 if (ice_check_sq_alive(hw, &hw->adminq)) 3317 ice_aq_clear_pxe_mode(hw); 3318 } 3319 3320 /** 3321 * ice_aq_set_port_params - set physical port parameters. 3322 * @pi: pointer to the port info struct 3323 * @double_vlan: if set double VLAN is enabled 3324 * @cd: pointer to command details structure or NULL 3325 * 3326 * Set Physical port parameters (0x0203) 3327 */ 3328 int 3329 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 3330 struct ice_sq_cd *cd) 3331 3332 { 3333 struct ice_aqc_set_port_params *cmd; 3334 struct ice_hw *hw = pi->hw; 3335 struct libie_aq_desc desc; 3336 u16 cmd_flags = 0; 3337 3338 cmd = libie_aq_raw(&desc); 3339 3340 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 3341 if (double_vlan) 3342 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 3343 cmd->cmd_flags = cpu_to_le16(cmd_flags); 3344 3345 cmd->local_fwd_mode = pi->local_fwd_mode | 3346 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID; 3347 3348 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3349 } 3350 3351 /** 3352 * ice_is_100m_speed_supported 3353 * @hw: pointer to the HW struct 3354 * 3355 * returns true if 100M speeds are supported by the device, 3356 * false otherwise. 3357 */ 3358 bool ice_is_100m_speed_supported(struct ice_hw *hw) 3359 { 3360 switch (hw->device_id) { 3361 case ICE_DEV_ID_E822C_SGMII: 3362 case ICE_DEV_ID_E822L_SGMII: 3363 case ICE_DEV_ID_E823L_1GBE: 3364 case ICE_DEV_ID_E823C_SGMII: 3365 case ICE_DEV_ID_E825C_SGMII: 3366 return true; 3367 default: 3368 return false; 3369 } 3370 } 3371 3372 /** 3373 * ice_get_link_speed_based_on_phy_type - returns link speed 3374 * @phy_type_low: lower part of phy_type 3375 * @phy_type_high: higher part of phy_type 3376 * 3377 * This helper function will convert an entry in PHY type structure 3378 * [phy_type_low, phy_type_high] to its corresponding link speed. 3379 * Note: In the structure of [phy_type_low, phy_type_high], there should 3380 * be one bit set, as this function will convert one PHY type to its 3381 * speed. 3382 * 3383 * Return: 3384 * * PHY speed for recognized PHY type 3385 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3386 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 3387 */ 3388 u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 3389 { 3390 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3391 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3392 3393 switch (phy_type_low) { 3394 case ICE_PHY_TYPE_LOW_100BASE_TX: 3395 case ICE_PHY_TYPE_LOW_100M_SGMII: 3396 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 3397 break; 3398 case ICE_PHY_TYPE_LOW_1000BASE_T: 3399 case ICE_PHY_TYPE_LOW_1000BASE_SX: 3400 case ICE_PHY_TYPE_LOW_1000BASE_LX: 3401 case ICE_PHY_TYPE_LOW_1000BASE_KX: 3402 case ICE_PHY_TYPE_LOW_1G_SGMII: 3403 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 3404 break; 3405 case ICE_PHY_TYPE_LOW_2500BASE_T: 3406 case ICE_PHY_TYPE_LOW_2500BASE_X: 3407 case ICE_PHY_TYPE_LOW_2500BASE_KX: 3408 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 3409 break; 3410 case ICE_PHY_TYPE_LOW_5GBASE_T: 3411 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3412 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3413 break; 3414 case ICE_PHY_TYPE_LOW_10GBASE_T: 3415 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3416 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3417 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3418 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3419 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3420 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3421 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3422 break; 3423 case ICE_PHY_TYPE_LOW_25GBASE_T: 3424 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3425 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3426 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3427 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3428 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3429 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3430 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3431 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3432 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3433 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3434 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3435 break; 3436 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3437 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3438 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3439 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3440 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3441 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3442 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3443 break; 3444 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3445 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3446 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3447 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3448 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3449 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3450 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3451 case ICE_PHY_TYPE_LOW_50G_AUI2: 3452 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3453 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3454 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3455 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3456 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3457 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3458 case ICE_PHY_TYPE_LOW_50G_AUI1: 3459 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3460 break; 3461 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3462 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3463 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3464 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3465 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3466 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3467 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3468 case ICE_PHY_TYPE_LOW_100G_AUI4: 3469 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3470 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3471 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3472 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3473 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3474 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3475 break; 3476 default: 3477 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3478 break; 3479 } 3480 3481 switch (phy_type_high) { 3482 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3483 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3484 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3485 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3486 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3487 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3488 break; 3489 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: 3490 case ICE_PHY_TYPE_HIGH_200G_SR4: 3491 case ICE_PHY_TYPE_HIGH_200G_FR4: 3492 case ICE_PHY_TYPE_HIGH_200G_LR4: 3493 case ICE_PHY_TYPE_HIGH_200G_DR4: 3494 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: 3495 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: 3496 case ICE_PHY_TYPE_HIGH_200G_AUI4: 3497 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; 3498 break; 3499 default: 3500 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3501 break; 3502 } 3503 3504 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3505 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3506 return ICE_AQ_LINK_SPEED_UNKNOWN; 3507 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3508 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3509 return ICE_AQ_LINK_SPEED_UNKNOWN; 3510 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3511 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3512 return speed_phy_type_low; 3513 else 3514 return speed_phy_type_high; 3515 } 3516 3517 /** 3518 * ice_update_phy_type 3519 * @phy_type_low: pointer to the lower part of phy_type 3520 * @phy_type_high: pointer to the higher part of phy_type 3521 * @link_speeds_bitmap: targeted link speeds bitmap 3522 * 3523 * Note: For the link_speeds_bitmap structure, you can check it at 3524 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3525 * link_speeds_bitmap include multiple speeds. 3526 * 3527 * Each entry in this [phy_type_low, phy_type_high] structure will 3528 * present a certain link speed. This helper function will turn on bits 3529 * in [phy_type_low, phy_type_high] structure based on the value of 3530 * link_speeds_bitmap input parameter. 3531 */ 3532 void 3533 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3534 u16 link_speeds_bitmap) 3535 { 3536 u64 pt_high; 3537 u64 pt_low; 3538 int index; 3539 u16 speed; 3540 3541 /* We first check with low part of phy_type */ 3542 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3543 pt_low = BIT_ULL(index); 3544 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3545 3546 if (link_speeds_bitmap & speed) 3547 *phy_type_low |= BIT_ULL(index); 3548 } 3549 3550 /* We then check with high part of phy_type */ 3551 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3552 pt_high = BIT_ULL(index); 3553 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3554 3555 if (link_speeds_bitmap & speed) 3556 *phy_type_high |= BIT_ULL(index); 3557 } 3558 } 3559 3560 /** 3561 * ice_aq_set_phy_cfg 3562 * @hw: pointer to the HW struct 3563 * @pi: port info structure of the interested logical port 3564 * @cfg: structure with PHY configuration data to be set 3565 * @cd: pointer to command details structure or NULL 3566 * 3567 * Set the various PHY configuration parameters supported on the Port. 3568 * One or more of the Set PHY config parameters may be ignored in an MFP 3569 * mode as the PF may not have the privilege to set some of the PHY Config 3570 * parameters. This status will be indicated by the command response (0x0601). 3571 */ 3572 int 3573 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3574 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3575 { 3576 struct ice_aqc_set_phy_cfg *cmd; 3577 struct libie_aq_desc desc; 3578 int status; 3579 3580 if (!cfg) 3581 return -EINVAL; 3582 3583 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3584 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3585 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3586 cfg->caps); 3587 3588 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3589 } 3590 3591 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3592 cmd = libie_aq_raw(&desc); 3593 cmd->lport_num = pi->lport; 3594 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 3595 3596 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3597 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3598 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3599 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3600 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3601 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3602 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3603 cfg->low_power_ctrl_an); 3604 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3605 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3606 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3607 cfg->link_fec_opt); 3608 3609 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3610 if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE) 3611 status = 0; 3612 3613 if (!status) 3614 pi->phy.curr_user_phy_cfg = *cfg; 3615 3616 return status; 3617 } 3618 3619 /** 3620 * ice_update_link_info - update status of the HW network link 3621 * @pi: port info structure of the interested logical port 3622 */ 3623 int ice_update_link_info(struct ice_port_info *pi) 3624 { 3625 struct ice_link_status *li; 3626 int status; 3627 3628 if (!pi) 3629 return -EINVAL; 3630 3631 li = &pi->phy.link_info; 3632 3633 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3634 if (status) 3635 return status; 3636 3637 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3638 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3639 3640 pcaps = kzalloc_obj(*pcaps); 3641 if (!pcaps) 3642 return -ENOMEM; 3643 3644 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3645 pcaps, NULL); 3646 } 3647 3648 return status; 3649 } 3650 3651 /** 3652 * ice_aq_get_phy_equalization - function to read serdes equaliser 3653 * value from firmware using admin queue command. 3654 * @hw: pointer to the HW struct 3655 * @data_in: represents the serdes equalization parameter requested 3656 * @op_code: represents the serdes number and flag to represent tx or rx 3657 * @serdes_num: represents the serdes number 3658 * @output: pointer to the caller-supplied buffer to return serdes equaliser 3659 * 3660 * Return: non-zero status on error and 0 on success. 3661 */ 3662 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 3663 u8 serdes_num, int *output) 3664 { 3665 struct ice_aqc_dnl_call_command *cmd; 3666 struct ice_aqc_dnl_call buf = {}; 3667 struct libie_aq_desc desc; 3668 int err; 3669 3670 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in); 3671 buf.sto.txrx_equa_reqs.op_code_serdes_sel = 3672 cpu_to_le16(op_code | (serdes_num & 0xF)); 3673 cmd = libie_aq_raw(&desc); 3674 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call); 3675 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_BUF | 3676 LIBIE_AQ_FLAG_RD | 3677 LIBIE_AQ_FLAG_SI); 3678 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call)); 3679 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); 3680 3681 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call), 3682 NULL); 3683 *output = err ? 0 : buf.sto.txrx_equa_resp.val; 3684 3685 return err; 3686 } 3687 3688 #define FEC_REG_PORT(port) { \ 3689 FEC_CORR_LOW_REG_PORT##port, \ 3690 FEC_CORR_HIGH_REG_PORT##port, \ 3691 FEC_UNCORR_LOW_REG_PORT##port, \ 3692 FEC_UNCORR_HIGH_REG_PORT##port, \ 3693 } 3694 3695 static const u32 fec_reg[][ICE_FEC_MAX] = { 3696 FEC_REG_PORT(0), 3697 FEC_REG_PORT(1), 3698 FEC_REG_PORT(2), 3699 FEC_REG_PORT(3) 3700 }; 3701 3702 /** 3703 * ice_aq_get_fec_stats - reads fec stats from phy 3704 * @hw: pointer to the HW struct 3705 * @pcs_quad: represents pcsquad of user input serdes 3706 * @pcs_port: represents the pcs port number part of above pcs quad 3707 * @fec_type: represents FEC stats type 3708 * @output: pointer to the caller-supplied buffer to return requested fec stats 3709 * 3710 * Return: non-zero status on error and 0 on success. 3711 */ 3712 int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, 3713 enum ice_fec_stats_types fec_type, u32 *output) 3714 { 3715 u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); 3716 struct ice_sbq_msg_input msg = {}; 3717 u32 receiver_id, reg_offset; 3718 int err; 3719 3720 if (pcs_port > 3) 3721 return -EINVAL; 3722 3723 reg_offset = fec_reg[pcs_port][fec_type]; 3724 3725 if (pcs_quad == 0) 3726 receiver_id = FEC_RECEIVER_ID_PCS0; 3727 else if (pcs_quad == 1) 3728 receiver_id = FEC_RECEIVER_ID_PCS1; 3729 else 3730 return -EINVAL; 3731 3732 msg.msg_addr_low = lower_16_bits(reg_offset); 3733 msg.msg_addr_high = receiver_id; 3734 msg.opcode = ice_sbq_msg_rd; 3735 msg.dest_dev = ice_sbq_dev_phy_0; 3736 3737 err = ice_sbq_rw_reg(hw, &msg, flag); 3738 if (err) 3739 return err; 3740 3741 *output = msg.data; 3742 return 0; 3743 } 3744 3745 /** 3746 * ice_cache_phy_user_req 3747 * @pi: port information structure 3748 * @cache_data: PHY logging data 3749 * @cache_mode: PHY logging mode 3750 * 3751 * Log the user request on (FC, FEC, SPEED) for later use. 3752 */ 3753 static void 3754 ice_cache_phy_user_req(struct ice_port_info *pi, 3755 struct ice_phy_cache_mode_data cache_data, 3756 enum ice_phy_cache_mode cache_mode) 3757 { 3758 if (!pi) 3759 return; 3760 3761 switch (cache_mode) { 3762 case ICE_FC_MODE: 3763 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3764 break; 3765 case ICE_SPEED_MODE: 3766 pi->phy.curr_user_speed_req = 3767 cache_data.data.curr_user_speed_req; 3768 break; 3769 case ICE_FEC_MODE: 3770 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3771 break; 3772 default: 3773 break; 3774 } 3775 } 3776 3777 /** 3778 * ice_caps_to_fc_mode 3779 * @caps: PHY capabilities 3780 * 3781 * Convert PHY FC capabilities to ice FC mode 3782 */ 3783 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3784 { 3785 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3786 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3787 return ICE_FC_FULL; 3788 3789 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3790 return ICE_FC_TX_PAUSE; 3791 3792 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3793 return ICE_FC_RX_PAUSE; 3794 3795 return ICE_FC_NONE; 3796 } 3797 3798 /** 3799 * ice_caps_to_fec_mode 3800 * @caps: PHY capabilities 3801 * @fec_options: Link FEC options 3802 * 3803 * Convert PHY FEC capabilities to ice FEC mode 3804 */ 3805 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3806 { 3807 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3808 return ICE_FEC_AUTO; 3809 3810 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3811 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3812 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3813 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3814 return ICE_FEC_BASER; 3815 3816 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3817 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3818 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3819 return ICE_FEC_RS; 3820 3821 return ICE_FEC_NONE; 3822 } 3823 3824 /** 3825 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3826 * @pi: port information structure 3827 * @cfg: PHY configuration data to set FC mode 3828 * @req_mode: FC mode to configure 3829 */ 3830 int 3831 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3832 enum ice_fc_mode req_mode) 3833 { 3834 struct ice_phy_cache_mode_data cache_data; 3835 u8 pause_mask = 0x0; 3836 3837 if (!pi || !cfg) 3838 return -EINVAL; 3839 3840 switch (req_mode) { 3841 case ICE_FC_FULL: 3842 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3843 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3844 break; 3845 case ICE_FC_RX_PAUSE: 3846 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3847 break; 3848 case ICE_FC_TX_PAUSE: 3849 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3850 break; 3851 default: 3852 break; 3853 } 3854 3855 /* clear the old pause settings */ 3856 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3857 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3858 3859 /* set the new capabilities */ 3860 cfg->caps |= pause_mask; 3861 3862 /* Cache user FC request */ 3863 cache_data.data.curr_user_fc_req = req_mode; 3864 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3865 3866 return 0; 3867 } 3868 3869 /** 3870 * ice_set_fc 3871 * @pi: port information structure 3872 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3873 * @ena_auto_link_update: enable automatic link update 3874 * 3875 * Set the requested flow control mode. 3876 */ 3877 int 3878 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3879 { 3880 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 3881 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3882 struct ice_hw *hw; 3883 int status; 3884 3885 if (!pi || !aq_failures) 3886 return -EINVAL; 3887 3888 hw = pi->hw; 3889 3890 pcaps = kzalloc_obj(*pcaps); 3891 if (!pcaps) 3892 return -ENOMEM; 3893 3894 /* Get the current PHY config */ 3895 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3896 pcaps, NULL); 3897 if (status) { 3898 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3899 goto out; 3900 } 3901 3902 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3903 3904 /* Configure the set PHY data */ 3905 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3906 if (status) 3907 goto out; 3908 3909 /* If the capabilities have changed, then set the new config */ 3910 if (cfg.caps != pcaps->caps) { 3911 int retry_count, retry_max = 10; 3912 3913 /* Auto restart link so settings take effect */ 3914 if (ena_auto_link_update) 3915 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3916 3917 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3918 if (status) { 3919 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3920 goto out; 3921 } 3922 3923 /* Update the link info 3924 * It sometimes takes a really long time for link to 3925 * come back from the atomic reset. Thus, we wait a 3926 * little bit. 3927 */ 3928 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3929 status = ice_update_link_info(pi); 3930 3931 if (!status) 3932 break; 3933 3934 mdelay(100); 3935 } 3936 3937 if (status) 3938 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3939 } 3940 3941 out: 3942 return status; 3943 } 3944 3945 /** 3946 * ice_phy_caps_equals_cfg 3947 * @phy_caps: PHY capabilities 3948 * @phy_cfg: PHY configuration 3949 * 3950 * Helper function to determine if PHY capabilities matches PHY 3951 * configuration 3952 */ 3953 bool 3954 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3955 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3956 { 3957 u8 caps_mask, cfg_mask; 3958 3959 if (!phy_caps || !phy_cfg) 3960 return false; 3961 3962 /* These bits are not common between capabilities and configuration. 3963 * Do not use them to determine equality. 3964 */ 3965 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3966 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3967 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3968 3969 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3970 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3971 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3972 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3973 phy_caps->eee_cap != phy_cfg->eee_cap || 3974 phy_caps->eeer_value != phy_cfg->eeer_value || 3975 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3976 return false; 3977 3978 return true; 3979 } 3980 3981 /** 3982 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3983 * @pi: port information structure 3984 * @caps: PHY ability structure to copy date from 3985 * @cfg: PHY configuration structure to copy data to 3986 * 3987 * Helper function to copy AQC PHY get ability data to PHY set configuration 3988 * data structure 3989 */ 3990 void 3991 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3992 struct ice_aqc_get_phy_caps_data *caps, 3993 struct ice_aqc_set_phy_cfg_data *cfg) 3994 { 3995 if (!pi || !caps || !cfg) 3996 return; 3997 3998 memset(cfg, 0, sizeof(*cfg)); 3999 cfg->phy_type_low = caps->phy_type_low; 4000 cfg->phy_type_high = caps->phy_type_high; 4001 cfg->caps = caps->caps; 4002 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 4003 cfg->eee_cap = caps->eee_cap; 4004 cfg->eeer_value = caps->eeer_value; 4005 cfg->link_fec_opt = caps->link_fec_options; 4006 cfg->module_compliance_enforcement = 4007 caps->module_compliance_enforcement; 4008 } 4009 4010 /** 4011 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 4012 * @pi: port information structure 4013 * @cfg: PHY configuration data to set FEC mode 4014 * @fec: FEC mode to configure 4015 */ 4016 int 4017 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 4018 enum ice_fec_mode fec) 4019 { 4020 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; 4021 struct ice_hw *hw; 4022 int status; 4023 4024 if (!pi || !cfg) 4025 return -EINVAL; 4026 4027 hw = pi->hw; 4028 4029 pcaps = kzalloc_obj(*pcaps); 4030 if (!pcaps) 4031 return -ENOMEM; 4032 4033 status = ice_aq_get_phy_caps(pi, false, 4034 (ice_fw_supports_report_dflt_cfg(hw) ? 4035 ICE_AQC_REPORT_DFLT_CFG : 4036 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 4037 if (status) 4038 goto out; 4039 4040 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 4041 cfg->link_fec_opt = pcaps->link_fec_options; 4042 4043 switch (fec) { 4044 case ICE_FEC_BASER: 4045 /* Clear RS bits, and AND BASE-R ability 4046 * bits and OR request bits. 4047 */ 4048 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 4049 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 4050 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 4051 ICE_AQC_PHY_FEC_25G_KR_REQ; 4052 break; 4053 case ICE_FEC_RS: 4054 /* Clear BASE-R bits, and AND RS ability 4055 * bits and OR request bits. 4056 */ 4057 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 4058 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 4059 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 4060 break; 4061 case ICE_FEC_NONE: 4062 /* Clear all FEC option bits. */ 4063 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 4064 break; 4065 case ICE_FEC_AUTO: 4066 /* AND auto FEC bit, and all caps bits. */ 4067 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 4068 cfg->link_fec_opt |= pcaps->link_fec_options; 4069 break; 4070 default: 4071 status = -EINVAL; 4072 break; 4073 } 4074 4075 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 4076 !ice_fw_supports_report_dflt_cfg(hw)) { 4077 struct ice_link_default_override_tlv tlv = { 0 }; 4078 4079 status = ice_get_link_default_override(&tlv, pi); 4080 if (status) 4081 goto out; 4082 4083 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 4084 (tlv.options & ICE_LINK_OVERRIDE_EN)) 4085 cfg->link_fec_opt = tlv.fec_options; 4086 } 4087 4088 out: 4089 return status; 4090 } 4091 4092 /** 4093 * ice_get_link_status - get status of the HW network link 4094 * @pi: port information structure 4095 * @link_up: pointer to bool (true/false = linkup/linkdown) 4096 * 4097 * Variable link_up is true if link is up, false if link is down. 4098 * The variable link_up is invalid if status is non zero. As a 4099 * result of this call, link status reporting becomes enabled 4100 */ 4101 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 4102 { 4103 struct ice_phy_info *phy_info; 4104 int status = 0; 4105 4106 if (!pi || !link_up) 4107 return -EINVAL; 4108 4109 phy_info = &pi->phy; 4110 4111 if (phy_info->get_link_info) { 4112 status = ice_update_link_info(pi); 4113 4114 if (status) 4115 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 4116 status); 4117 } 4118 4119 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 4120 4121 return status; 4122 } 4123 4124 /** 4125 * ice_aq_set_link_restart_an 4126 * @pi: pointer to the port information structure 4127 * @ena_link: if true: enable link, if false: disable link 4128 * @cd: pointer to command details structure or NULL 4129 * @refclk: the new TX reference clock, 0 if no change 4130 * 4131 * Sets up the link and restarts the Auto-Negotiation over the link. 4132 */ 4133 int 4134 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 4135 struct ice_sq_cd *cd, u8 refclk) 4136 { 4137 struct ice_aqc_restart_an *cmd; 4138 struct libie_aq_desc desc; 4139 4140 cmd = libie_aq_raw(&desc); 4141 4142 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 4143 4144 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 4145 cmd->lport_num = pi->lport; 4146 if (ena_link) 4147 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 4148 else 4149 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 4150 4151 cmd->cmd_flags |= FIELD_PREP(ICE_AQC_RESTART_AN_REFCLK_M, refclk); 4152 4153 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 4154 } 4155 4156 /** 4157 * ice_aq_set_event_mask 4158 * @hw: pointer to the HW struct 4159 * @port_num: port number of the physical function 4160 * @mask: event mask to be set 4161 * @cd: pointer to command details structure or NULL 4162 * 4163 * Set event mask (0x0613) 4164 */ 4165 int 4166 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 4167 struct ice_sq_cd *cd) 4168 { 4169 struct ice_aqc_set_event_mask *cmd; 4170 struct libie_aq_desc desc; 4171 4172 cmd = libie_aq_raw(&desc); 4173 4174 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 4175 4176 cmd->lport_num = port_num; 4177 4178 cmd->event_mask = cpu_to_le16(mask); 4179 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4180 } 4181 4182 /** 4183 * ice_aq_set_mac_loopback 4184 * @hw: pointer to the HW struct 4185 * @ena_lpbk: Enable or Disable loopback 4186 * @cd: pointer to command details structure or NULL 4187 * 4188 * Enable/disable loopback on a given port 4189 */ 4190 int 4191 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 4192 { 4193 struct ice_aqc_set_mac_lb *cmd; 4194 struct libie_aq_desc desc; 4195 4196 cmd = libie_aq_raw(&desc); 4197 4198 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 4199 if (ena_lpbk) 4200 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 4201 4202 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4203 } 4204 4205 /** 4206 * ice_aq_set_port_id_led 4207 * @pi: pointer to the port information 4208 * @is_orig_mode: is this LED set to original mode (by the net-list) 4209 * @cd: pointer to command details structure or NULL 4210 * 4211 * Set LED value for the given port (0x06e9) 4212 */ 4213 int 4214 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 4215 struct ice_sq_cd *cd) 4216 { 4217 struct ice_aqc_set_port_id_led *cmd; 4218 struct ice_hw *hw = pi->hw; 4219 struct libie_aq_desc desc; 4220 4221 cmd = libie_aq_raw(&desc); 4222 4223 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 4224 4225 if (is_orig_mode) 4226 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 4227 else 4228 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 4229 4230 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4231 } 4232 4233 /** 4234 * ice_aq_get_port_options 4235 * @hw: pointer to the HW struct 4236 * @options: buffer for the resultant port options 4237 * @option_count: input - size of the buffer in port options structures, 4238 * output - number of returned port options 4239 * @lport: logical port to call the command with (optional) 4240 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4241 * when PF owns more than 1 port it must be true 4242 * @active_option_idx: index of active port option in returned buffer 4243 * @active_option_valid: active option in returned buffer is valid 4244 * @pending_option_idx: index of pending port option in returned buffer 4245 * @pending_option_valid: pending option in returned buffer is valid 4246 * 4247 * Calls Get Port Options AQC (0x06ea) and verifies result. 4248 */ 4249 int 4250 ice_aq_get_port_options(struct ice_hw *hw, 4251 struct ice_aqc_get_port_options_elem *options, 4252 u8 *option_count, u8 lport, bool lport_valid, 4253 u8 *active_option_idx, bool *active_option_valid, 4254 u8 *pending_option_idx, bool *pending_option_valid) 4255 { 4256 struct ice_aqc_get_port_options *cmd; 4257 struct libie_aq_desc desc; 4258 int status; 4259 u8 i; 4260 4261 /* options buffer shall be able to hold max returned options */ 4262 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 4263 return -EINVAL; 4264 4265 cmd = libie_aq_raw(&desc); 4266 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 4267 4268 if (lport_valid) 4269 cmd->lport_num = lport; 4270 cmd->lport_num_valid = lport_valid; 4271 4272 status = ice_aq_send_cmd(hw, &desc, options, 4273 *option_count * sizeof(*options), NULL); 4274 if (status) 4275 return status; 4276 4277 /* verify direct FW response & set output parameters */ 4278 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 4279 cmd->port_options_count); 4280 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 4281 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 4282 cmd->port_options); 4283 if (*active_option_valid) { 4284 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 4285 cmd->port_options); 4286 if (*active_option_idx > (*option_count - 1)) 4287 return -EIO; 4288 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 4289 *active_option_idx); 4290 } 4291 4292 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 4293 cmd->pending_port_option_status); 4294 if (*pending_option_valid) { 4295 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 4296 cmd->pending_port_option_status); 4297 if (*pending_option_idx > (*option_count - 1)) 4298 return -EIO; 4299 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 4300 *pending_option_idx); 4301 } 4302 4303 /* mask output options fields */ 4304 for (i = 0; i < *option_count; i++) { 4305 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 4306 options[i].pmd); 4307 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 4308 options[i].max_lane_speed); 4309 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 4310 options[i].pmd, options[i].max_lane_speed); 4311 } 4312 4313 return 0; 4314 } 4315 4316 /** 4317 * ice_aq_set_port_option 4318 * @hw: pointer to the HW struct 4319 * @lport: logical port to call the command with 4320 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 4321 * when PF owns more than 1 port it must be true 4322 * @new_option: new port option to be written 4323 * 4324 * Calls Set Port Options AQC (0x06eb). 4325 */ 4326 int 4327 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 4328 u8 new_option) 4329 { 4330 struct ice_aqc_set_port_option *cmd; 4331 struct libie_aq_desc desc; 4332 4333 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 4334 return -EINVAL; 4335 4336 cmd = libie_aq_raw(&desc); 4337 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 4338 4339 if (lport_valid) 4340 cmd->lport_num = lport; 4341 4342 cmd->lport_num_valid = lport_valid; 4343 cmd->selected_port_option = new_option; 4344 4345 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4346 } 4347 4348 /** 4349 * ice_get_phy_lane_number - Get PHY lane number for current adapter 4350 * @hw: pointer to the hw struct 4351 * 4352 * Return: PHY lane number on success, negative error code otherwise. 4353 */ 4354 int ice_get_phy_lane_number(struct ice_hw *hw) 4355 { 4356 struct ice_aqc_get_port_options_elem *options; 4357 unsigned int lport = 0; 4358 unsigned int lane; 4359 int err; 4360 4361 /* E82X does not have sequential IDs, lane number is PF ID. 4362 * For E825 device, the exception is the variant with external 4363 * PHY (0x579F), in which there is also 1:1 pf_id -> lane_number 4364 * mapping. 4365 */ 4366 if (hw->mac_type == ICE_MAC_GENERIC || 4367 hw->device_id == ICE_DEV_ID_E825C_SGMII) 4368 return hw->pf_id; 4369 4370 options = kzalloc_objs(*options, ICE_AQC_PORT_OPT_MAX); 4371 if (!options) 4372 return -ENOMEM; 4373 4374 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) { 4375 u8 options_count = ICE_AQC_PORT_OPT_MAX; 4376 u8 speed, active_idx, pending_idx; 4377 bool active_valid, pending_valid; 4378 4379 err = ice_aq_get_port_options(hw, options, &options_count, lane, 4380 true, &active_idx, &active_valid, 4381 &pending_idx, &pending_valid); 4382 if (err) 4383 goto err; 4384 4385 if (!active_valid) 4386 continue; 4387 4388 speed = options[active_idx].max_lane_speed; 4389 /* If we don't get speed for this lane, it's unoccupied */ 4390 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) 4391 continue; 4392 4393 if (hw->pf_id == lport) { 4394 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && 4395 ice_is_dual(hw) && !ice_is_primary(hw)) 4396 lane += ICE_PORTS_PER_QUAD; 4397 kfree(options); 4398 return lane; 4399 } 4400 lport++; 4401 } 4402 4403 /* PHY lane not found */ 4404 err = -ENXIO; 4405 err: 4406 kfree(options); 4407 return err; 4408 } 4409 4410 /** 4411 * ice_aq_sff_eeprom 4412 * @hw: pointer to the HW struct 4413 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 4414 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 4415 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 4416 * @page: QSFP page 4417 * @set_page: set or ignore the page 4418 * @data: pointer to data buffer to be read/written to the I2C device. 4419 * @length: 1-16 for read, 1 for write. 4420 * @write: 0 read, 1 for write. 4421 * @cd: pointer to command details structure or NULL 4422 * 4423 * Read/Write SFF EEPROM (0x06EE) 4424 */ 4425 int 4426 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 4427 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 4428 bool write, struct ice_sq_cd *cd) 4429 { 4430 struct ice_aqc_sff_eeprom *cmd; 4431 struct libie_aq_desc desc; 4432 u16 i2c_bus_addr; 4433 int status; 4434 4435 if (!data || (mem_addr & 0xff00)) 4436 return -EINVAL; 4437 4438 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 4439 cmd = libie_aq_raw(&desc); 4440 desc.flags = cpu_to_le16(LIBIE_AQ_FLAG_RD); 4441 cmd->lport_num = (u8)(lport & 0xff); 4442 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 4443 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) | 4444 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page); 4445 if (write) 4446 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE; 4447 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); 4448 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 4449 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); 4450 4451 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 4452 return status; 4453 } 4454 4455 static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type) 4456 { 4457 switch (type) { 4458 case ICE_LUT_VSI: 4459 return ICE_LUT_VSI_SIZE; 4460 case ICE_LUT_GLOBAL: 4461 return ICE_LUT_GLOBAL_SIZE; 4462 case ICE_LUT_PF: 4463 return ICE_LUT_PF_SIZE; 4464 } 4465 WARN_ONCE(1, "incorrect type passed"); 4466 return ICE_LUT_VSI_SIZE; 4467 } 4468 4469 static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size) 4470 { 4471 switch (size) { 4472 case ICE_LUT_VSI_SIZE: 4473 return ICE_AQC_LUT_SIZE_SMALL; 4474 case ICE_LUT_GLOBAL_SIZE: 4475 return ICE_AQC_LUT_SIZE_512; 4476 case ICE_LUT_PF_SIZE: 4477 return ICE_AQC_LUT_SIZE_2K; 4478 } 4479 WARN_ONCE(1, "incorrect size passed"); 4480 return 0; 4481 } 4482 4483 /** 4484 * __ice_aq_get_set_rss_lut 4485 * @hw: pointer to the hardware structure 4486 * @params: RSS LUT parameters 4487 * @set: set true to set the table, false to get the table 4488 * 4489 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 4490 */ 4491 static int 4492 __ice_aq_get_set_rss_lut(struct ice_hw *hw, 4493 struct ice_aq_get_set_rss_lut_params *params, bool set) 4494 { 4495 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; 4496 enum ice_lut_type lut_type = params->lut_type; 4497 struct ice_aqc_get_set_rss_lut *desc_params; 4498 enum ice_aqc_lut_flags flags; 4499 enum ice_lut_size lut_size; 4500 struct libie_aq_desc desc; 4501 u8 *lut = params->lut; 4502 4503 4504 if (!lut || !ice_is_vsi_valid(hw, vsi_handle)) 4505 return -EINVAL; 4506 4507 lut_size = ice_lut_type_to_size(lut_type); 4508 if (lut_size > params->lut_size) 4509 return -EINVAL; 4510 else if (set && lut_size != params->lut_size) 4511 return -EINVAL; 4512 4513 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut; 4514 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 4515 if (set) 4516 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4517 4518 desc_params = libie_aq_raw(&desc); 4519 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 4520 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4521 4522 if (lut_type == ICE_LUT_GLOBAL) 4523 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX, 4524 params->global_lut_id); 4525 4526 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size); 4527 desc_params->flags = cpu_to_le16(flags); 4528 4529 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 4530 } 4531 4532 /** 4533 * ice_aq_get_rss_lut 4534 * @hw: pointer to the hardware structure 4535 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 4536 * 4537 * get the RSS lookup table, PF or VSI type 4538 */ 4539 int 4540 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 4541 { 4542 return __ice_aq_get_set_rss_lut(hw, get_params, false); 4543 } 4544 4545 /** 4546 * ice_aq_set_rss_lut 4547 * @hw: pointer to the hardware structure 4548 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4549 * 4550 * set the RSS lookup table, PF or VSI type 4551 */ 4552 int 4553 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4554 { 4555 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4556 } 4557 4558 /** 4559 * __ice_aq_get_set_rss_key 4560 * @hw: pointer to the HW struct 4561 * @vsi_id: VSI FW index 4562 * @key: pointer to key info struct 4563 * @set: set true to set the key, false to get the key 4564 * 4565 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4566 */ 4567 static int 4568 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4569 struct ice_aqc_get_set_rss_keys *key, bool set) 4570 { 4571 struct ice_aqc_get_set_rss_key *desc_params; 4572 u16 key_size = sizeof(*key); 4573 struct libie_aq_desc desc; 4574 4575 if (set) { 4576 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4577 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4578 } else { 4579 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4580 } 4581 4582 desc_params = libie_aq_raw(&desc); 4583 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); 4584 4585 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4586 } 4587 4588 /** 4589 * ice_aq_get_rss_key 4590 * @hw: pointer to the HW struct 4591 * @vsi_handle: software VSI handle 4592 * @key: pointer to key info struct 4593 * 4594 * get the RSS key per VSI 4595 */ 4596 int 4597 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4598 struct ice_aqc_get_set_rss_keys *key) 4599 { 4600 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4601 return -EINVAL; 4602 4603 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4604 key, false); 4605 } 4606 4607 /** 4608 * ice_aq_set_rss_key 4609 * @hw: pointer to the HW struct 4610 * @vsi_handle: software VSI handle 4611 * @keys: pointer to key info struct 4612 * 4613 * set the RSS key per VSI 4614 */ 4615 int 4616 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4617 struct ice_aqc_get_set_rss_keys *keys) 4618 { 4619 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4620 return -EINVAL; 4621 4622 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4623 keys, true); 4624 } 4625 4626 /** 4627 * ice_aq_add_lan_txq 4628 * @hw: pointer to the hardware structure 4629 * @num_qgrps: Number of added queue groups 4630 * @qg_list: list of queue groups to be added 4631 * @buf_size: size of buffer for indirect command 4632 * @cd: pointer to command details structure or NULL 4633 * 4634 * Add Tx LAN queue (0x0C30) 4635 * 4636 * NOTE: 4637 * Prior to calling add Tx LAN queue: 4638 * Initialize the following as part of the Tx queue context: 4639 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4640 * Cache profile and Packet shaper profile. 4641 * 4642 * After add Tx LAN queue AQ command is completed: 4643 * Interrupts should be associated with specific queues, 4644 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4645 * flow. 4646 */ 4647 static int 4648 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4649 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4650 struct ice_sq_cd *cd) 4651 { 4652 struct ice_aqc_add_tx_qgrp *list; 4653 struct ice_aqc_add_txqs *cmd; 4654 struct libie_aq_desc desc; 4655 u16 i, sum_size = 0; 4656 4657 cmd = libie_aq_raw(&desc); 4658 4659 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4660 4661 if (!qg_list) 4662 return -EINVAL; 4663 4664 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4665 return -EINVAL; 4666 4667 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4668 sum_size += struct_size(list, txqs, list->num_txqs); 4669 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4670 list->num_txqs); 4671 } 4672 4673 if (buf_size != sum_size) 4674 return -EINVAL; 4675 4676 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4677 4678 cmd->num_qgrps = num_qgrps; 4679 4680 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4681 } 4682 4683 /** 4684 * ice_aq_dis_lan_txq 4685 * @hw: pointer to the hardware structure 4686 * @num_qgrps: number of groups in the list 4687 * @qg_list: the list of groups to disable 4688 * @buf_size: the total size of the qg_list buffer in bytes 4689 * @rst_src: if called due to reset, specifies the reset source 4690 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4691 * @cd: pointer to command details structure or NULL 4692 * 4693 * Disable LAN Tx queue (0x0C31) 4694 */ 4695 static int 4696 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4697 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4698 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4699 struct ice_sq_cd *cd) 4700 { 4701 struct ice_aqc_dis_txq_item *item; 4702 struct ice_aqc_dis_txqs *cmd; 4703 struct libie_aq_desc desc; 4704 u16 vmvf_and_timeout; 4705 u16 i, sz = 0; 4706 int status; 4707 4708 cmd = libie_aq_raw(&desc); 4709 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4710 4711 /* qg_list can be NULL only in VM/VF reset flow */ 4712 if (!qg_list && !rst_src) 4713 return -EINVAL; 4714 4715 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4716 return -EINVAL; 4717 4718 cmd->num_entries = num_qgrps; 4719 4720 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5); 4721 4722 switch (rst_src) { 4723 case ICE_VM_RESET: 4724 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4725 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M; 4726 break; 4727 case ICE_VF_RESET: 4728 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4729 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4730 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & 4731 ICE_AQC_Q_DIS_VMVF_NUM_M; 4732 break; 4733 case ICE_NO_RESET: 4734 default: 4735 break; 4736 } 4737 4738 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); 4739 4740 /* flush pipe on time out */ 4741 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4742 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4743 if (!qg_list) 4744 goto do_aq; 4745 4746 /* set RD bit to indicate that command buffer is provided by the driver 4747 * and it needs to be read by the firmware 4748 */ 4749 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4750 4751 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4752 u16 item_size = struct_size(item, q_id, item->num_qs); 4753 4754 /* If the num of queues is even, add 2 bytes of padding */ 4755 if ((item->num_qs % 2) == 0) 4756 item_size += 2; 4757 4758 sz += item_size; 4759 4760 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4761 } 4762 4763 if (buf_size != sz) 4764 return -EINVAL; 4765 4766 do_aq: 4767 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4768 if (status) { 4769 if (!qg_list) 4770 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4771 vmvf_num, hw->adminq.sq_last_status); 4772 else 4773 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4774 le16_to_cpu(qg_list[0].q_id[0]), 4775 hw->adminq.sq_last_status); 4776 } 4777 return status; 4778 } 4779 4780 /** 4781 * ice_aq_cfg_lan_txq - send AQ command 0x0C32 to FW 4782 * @hw: pointer to the hardware structure 4783 * @buf: buffer for command 4784 * @buf_size: size of buffer in bytes 4785 * @num_qs: number of queues being configured 4786 * @oldport: origination lport 4787 * @newport: destination lport 4788 * @mode: cmd_type for move to use 4789 * @cd: pointer to command details structure or NULL 4790 * 4791 * Move/Configure LAN Tx queue (0x0C32) 4792 * 4793 * Return: Zero on success, associated error code on failure. 4794 */ 4795 int 4796 ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf, 4797 u16 buf_size, u16 num_qs, u8 oldport, u8 newport, 4798 u8 mode, struct ice_sq_cd *cd) 4799 { 4800 struct ice_aqc_cfg_txqs *cmd; 4801 struct libie_aq_desc desc; 4802 int status; 4803 4804 cmd = libie_aq_raw(&desc); 4805 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs); 4806 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4807 4808 if (!buf) 4809 return -EINVAL; 4810 4811 cmd->cmd_type = mode; 4812 cmd->num_qs = num_qs; 4813 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); 4814 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); 4815 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_MODE_M, 4816 ICE_AQC_Q_CFG_MODE_KEEP_OWN); 4817 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); 4818 cmd->blocked_cgds = 0; 4819 4820 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4821 if (status) 4822 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n", 4823 hw->adminq.sq_last_status); 4824 return status; 4825 } 4826 4827 /** 4828 * ice_aq_add_rdma_qsets 4829 * @hw: pointer to the hardware structure 4830 * @num_qset_grps: Number of RDMA Qset groups 4831 * @qset_list: list of Qset groups to be added 4832 * @buf_size: size of buffer for indirect command 4833 * @cd: pointer to command details structure or NULL 4834 * 4835 * Add Tx RDMA Qsets (0x0C33) 4836 */ 4837 static int 4838 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4839 struct ice_aqc_add_rdma_qset_data *qset_list, 4840 u16 buf_size, struct ice_sq_cd *cd) 4841 { 4842 struct ice_aqc_add_rdma_qset_data *list; 4843 struct ice_aqc_add_rdma_qset *cmd; 4844 struct libie_aq_desc desc; 4845 u16 i, sum_size = 0; 4846 4847 cmd = libie_aq_raw(&desc); 4848 4849 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4850 4851 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4852 return -EINVAL; 4853 4854 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4855 u16 num_qsets = le16_to_cpu(list->num_qsets); 4856 4857 sum_size += struct_size(list, rdma_qsets, num_qsets); 4858 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4859 num_qsets); 4860 } 4861 4862 if (buf_size != sum_size) 4863 return -EINVAL; 4864 4865 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4866 4867 cmd->num_qset_grps = num_qset_grps; 4868 4869 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4870 } 4871 4872 /** 4873 * ice_aq_set_txtimeq - set Tx time queues 4874 * @hw: pointer to the hardware structure 4875 * @txtimeq: first Tx time queue id to configure 4876 * @q_count: number of queues to configure 4877 * @txtime_qg: queue group to be set 4878 * @buf_size: size of buffer for indirect command 4879 * @cd: pointer to command details structure or NULL 4880 * 4881 * Set Tx Time queue (0x0C35) 4882 * Return: 0 on success or negative value on failure. 4883 */ 4884 int 4885 ice_aq_set_txtimeq(struct ice_hw *hw, u16 txtimeq, u8 q_count, 4886 struct ice_aqc_set_txtime_qgrp *txtime_qg, u16 buf_size, 4887 struct ice_sq_cd *cd) 4888 { 4889 struct ice_aqc_set_txtimeqs *cmd; 4890 struct libie_aq_desc desc; 4891 u16 size; 4892 4893 if (!txtime_qg || txtimeq > ICE_TXTIME_MAX_QUEUE || 4894 q_count < 1 || q_count > ICE_SET_TXTIME_MAX_Q_AMOUNT) 4895 return -EINVAL; 4896 4897 size = struct_size(txtime_qg, txtimeqs, q_count); 4898 if (buf_size != size) 4899 return -EINVAL; 4900 4901 cmd = libie_aq_raw(&desc); 4902 4903 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_txtimeqs); 4904 4905 desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD); 4906 4907 cmd->q_id = cpu_to_le16(txtimeq); 4908 cmd->q_amount = cpu_to_le16(q_count); 4909 return ice_aq_send_cmd(hw, &desc, txtime_qg, buf_size, cd); 4910 } 4911 4912 /* End of FW Admin Queue command wrappers */ 4913 4914 /** 4915 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4916 * @hw: pointer to the HW struct 4917 * @vsi_handle: software VSI handle 4918 * @tc: TC number 4919 * @q_handle: software queue handle 4920 */ 4921 struct ice_q_ctx * 4922 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4923 { 4924 struct ice_vsi_ctx *vsi; 4925 struct ice_q_ctx *q_ctx; 4926 4927 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4928 if (!vsi) 4929 return NULL; 4930 if (q_handle >= vsi->num_lan_q_entries[tc]) 4931 return NULL; 4932 if (!vsi->lan_q_ctx[tc]) 4933 return NULL; 4934 q_ctx = vsi->lan_q_ctx[tc]; 4935 return &q_ctx[q_handle]; 4936 } 4937 4938 /** 4939 * ice_ena_vsi_txq 4940 * @pi: port information structure 4941 * @vsi_handle: software VSI handle 4942 * @tc: TC number 4943 * @q_handle: software queue handle 4944 * @num_qgrps: Number of added queue groups 4945 * @buf: list of queue groups to be added 4946 * @buf_size: size of buffer for indirect command 4947 * @cd: pointer to command details structure or NULL 4948 * 4949 * This function adds one LAN queue 4950 */ 4951 int 4952 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4953 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4954 struct ice_sq_cd *cd) 4955 { 4956 struct ice_aqc_txsched_elem_data node = { 0 }; 4957 struct ice_sched_node *parent; 4958 struct ice_q_ctx *q_ctx; 4959 struct ice_hw *hw; 4960 int status; 4961 4962 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4963 return -EIO; 4964 4965 if (num_qgrps > 1 || buf->num_txqs > 1) 4966 return -ENOSPC; 4967 4968 hw = pi->hw; 4969 4970 if (!ice_is_vsi_valid(hw, vsi_handle)) 4971 return -EINVAL; 4972 4973 mutex_lock(&pi->sched_lock); 4974 4975 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4976 if (!q_ctx) { 4977 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4978 q_handle); 4979 status = -EINVAL; 4980 goto ena_txq_exit; 4981 } 4982 4983 /* find a parent node */ 4984 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4985 ICE_SCHED_NODE_OWNER_LAN); 4986 if (!parent) { 4987 status = -EINVAL; 4988 goto ena_txq_exit; 4989 } 4990 4991 buf->parent_teid = parent->info.node_teid; 4992 node.parent_teid = parent->info.node_teid; 4993 /* Mark that the values in the "generic" section as valid. The default 4994 * value in the "generic" section is zero. This means that : 4995 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4996 * - 0 priority among siblings, indicated by Bit 1-3. 4997 * - WFQ, indicated by Bit 4. 4998 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4999 * Bit 5-6. 5000 * - Bit 7 is reserved. 5001 * Without setting the generic section as valid in valid_sections, the 5002 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 5003 */ 5004 buf->txqs[0].info.valid_sections = 5005 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5006 ICE_AQC_ELEM_VALID_EIR; 5007 buf->txqs[0].info.generic = 0; 5008 buf->txqs[0].info.cir_bw.bw_profile_idx = 5009 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5010 buf->txqs[0].info.cir_bw.bw_alloc = 5011 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5012 buf->txqs[0].info.eir_bw.bw_profile_idx = 5013 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5014 buf->txqs[0].info.eir_bw.bw_alloc = 5015 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5016 5017 /* add the LAN queue */ 5018 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 5019 if (status) { 5020 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 5021 le16_to_cpu(buf->txqs[0].txq_id), 5022 hw->adminq.sq_last_status); 5023 goto ena_txq_exit; 5024 } 5025 5026 node.node_teid = buf->txqs[0].q_teid; 5027 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5028 q_ctx->q_handle = q_handle; 5029 q_ctx->q_teid = le32_to_cpu(node.node_teid); 5030 5031 /* add a leaf node into scheduler tree queue layer */ 5032 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 5033 if (!status) 5034 status = ice_sched_replay_q_bw(pi, q_ctx); 5035 5036 ena_txq_exit: 5037 mutex_unlock(&pi->sched_lock); 5038 return status; 5039 } 5040 5041 /** 5042 * ice_dis_vsi_txq 5043 * @pi: port information structure 5044 * @vsi_handle: software VSI handle 5045 * @tc: TC number 5046 * @num_queues: number of queues 5047 * @q_handles: pointer to software queue handle array 5048 * @q_ids: pointer to the q_id array 5049 * @q_teids: pointer to queue node teids 5050 * @rst_src: if called due to reset, specifies the reset source 5051 * @vmvf_num: the relative VM or VF number that is undergoing the reset 5052 * @cd: pointer to command details structure or NULL 5053 * 5054 * This function removes queues and their corresponding nodes in SW DB 5055 */ 5056 int 5057 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 5058 u16 *q_handles, u16 *q_ids, u32 *q_teids, 5059 enum ice_disq_rst_src rst_src, u16 vmvf_num, 5060 struct ice_sq_cd *cd) 5061 { 5062 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5063 u16 i, buf_size = __struct_size(qg_list); 5064 struct ice_q_ctx *q_ctx; 5065 int status = -ENOENT; 5066 struct ice_hw *hw; 5067 5068 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5069 return -EIO; 5070 5071 hw = pi->hw; 5072 5073 if (!num_queues) { 5074 /* if queue is disabled already yet the disable queue command 5075 * has to be sent to complete the VF reset, then call 5076 * ice_aq_dis_lan_txq without any queue information 5077 */ 5078 if (rst_src) 5079 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 5080 vmvf_num, NULL); 5081 return -EIO; 5082 } 5083 5084 mutex_lock(&pi->sched_lock); 5085 5086 for (i = 0; i < num_queues; i++) { 5087 struct ice_sched_node *node; 5088 5089 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 5090 if (!node) 5091 continue; 5092 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 5093 if (!q_ctx) { 5094 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 5095 q_handles[i]); 5096 continue; 5097 } 5098 if (q_ctx->q_handle != q_handles[i]) { 5099 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 5100 q_ctx->q_handle, q_handles[i]); 5101 continue; 5102 } 5103 qg_list->parent_teid = node->info.parent_teid; 5104 qg_list->num_qs = 1; 5105 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 5106 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 5107 vmvf_num, cd); 5108 5109 if (status) 5110 break; 5111 ice_free_sched_node(pi, node); 5112 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 5113 q_ctx->q_teid = ICE_INVAL_TEID; 5114 } 5115 mutex_unlock(&pi->sched_lock); 5116 return status; 5117 } 5118 5119 /** 5120 * ice_cfg_vsi_qs - configure the new/existing VSI queues 5121 * @pi: port information structure 5122 * @vsi_handle: software VSI handle 5123 * @tc_bitmap: TC bitmap 5124 * @maxqs: max queues array per TC 5125 * @owner: LAN or RDMA 5126 * 5127 * This function adds/updates the VSI queues per TC. 5128 */ 5129 static int 5130 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5131 u16 *maxqs, u8 owner) 5132 { 5133 int status = 0; 5134 u8 i; 5135 5136 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5137 return -EIO; 5138 5139 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5140 return -EINVAL; 5141 5142 mutex_lock(&pi->sched_lock); 5143 5144 ice_for_each_traffic_class(i) { 5145 /* configuration is possible only if TC node is present */ 5146 if (!ice_sched_get_tc_node(pi, i)) 5147 continue; 5148 5149 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 5150 ice_is_tc_ena(tc_bitmap, i)); 5151 if (status) 5152 break; 5153 } 5154 5155 mutex_unlock(&pi->sched_lock); 5156 return status; 5157 } 5158 5159 /** 5160 * ice_cfg_vsi_lan - configure VSI LAN queues 5161 * @pi: port information structure 5162 * @vsi_handle: software VSI handle 5163 * @tc_bitmap: TC bitmap 5164 * @max_lanqs: max LAN queues array per TC 5165 * 5166 * This function adds/updates the VSI LAN queues per TC. 5167 */ 5168 int 5169 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 5170 u16 *max_lanqs) 5171 { 5172 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 5173 ICE_SCHED_NODE_OWNER_LAN); 5174 } 5175 5176 /** 5177 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 5178 * @pi: port information structure 5179 * @vsi_handle: software VSI handle 5180 * @tc_bitmap: TC bitmap 5181 * @max_rdmaqs: max RDMA queues array per TC 5182 * 5183 * This function adds/updates the VSI RDMA queues per TC. 5184 */ 5185 int 5186 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 5187 u16 *max_rdmaqs) 5188 { 5189 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 5190 ICE_SCHED_NODE_OWNER_RDMA); 5191 } 5192 5193 /** 5194 * ice_ena_vsi_rdma_qset 5195 * @pi: port information structure 5196 * @vsi_handle: software VSI handle 5197 * @tc: TC number 5198 * @rdma_qset: pointer to RDMA Qset 5199 * @num_qsets: number of RDMA Qsets 5200 * @qset_teid: pointer to Qset node TEIDs 5201 * 5202 * This function adds RDMA Qset 5203 */ 5204 int 5205 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 5206 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 5207 { 5208 struct ice_aqc_txsched_elem_data node = { 0 }; 5209 struct ice_aqc_add_rdma_qset_data *buf; 5210 struct ice_sched_node *parent; 5211 struct ice_hw *hw; 5212 u16 i, buf_size; 5213 int ret; 5214 5215 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5216 return -EIO; 5217 hw = pi->hw; 5218 5219 if (!ice_is_vsi_valid(hw, vsi_handle)) 5220 return -EINVAL; 5221 5222 buf_size = struct_size(buf, rdma_qsets, num_qsets); 5223 buf = kzalloc(buf_size, GFP_KERNEL); 5224 if (!buf) 5225 return -ENOMEM; 5226 mutex_lock(&pi->sched_lock); 5227 5228 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 5229 ICE_SCHED_NODE_OWNER_RDMA); 5230 if (!parent) { 5231 ret = -EINVAL; 5232 goto rdma_error_exit; 5233 } 5234 buf->parent_teid = parent->info.node_teid; 5235 node.parent_teid = parent->info.node_teid; 5236 5237 buf->num_qsets = cpu_to_le16(num_qsets); 5238 for (i = 0; i < num_qsets; i++) { 5239 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 5240 buf->rdma_qsets[i].info.valid_sections = 5241 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 5242 ICE_AQC_ELEM_VALID_EIR; 5243 buf->rdma_qsets[i].info.generic = 0; 5244 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 5245 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5246 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 5247 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5248 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 5249 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 5250 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 5251 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 5252 } 5253 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 5254 if (ret) { 5255 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 5256 goto rdma_error_exit; 5257 } 5258 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 5259 for (i = 0; i < num_qsets; i++) { 5260 node.node_teid = buf->rdma_qsets[i].qset_teid; 5261 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 5262 &node, NULL); 5263 if (ret) 5264 break; 5265 qset_teid[i] = le32_to_cpu(node.node_teid); 5266 } 5267 rdma_error_exit: 5268 mutex_unlock(&pi->sched_lock); 5269 kfree(buf); 5270 return ret; 5271 } 5272 5273 /** 5274 * ice_dis_vsi_rdma_qset - free RDMA resources 5275 * @pi: port_info struct 5276 * @count: number of RDMA Qsets to free 5277 * @qset_teid: TEID of Qset node 5278 * @q_id: list of queue IDs being disabled 5279 */ 5280 int 5281 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 5282 u16 *q_id) 5283 { 5284 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1); 5285 u16 qg_size = __struct_size(qg_list); 5286 struct ice_hw *hw; 5287 int status = 0; 5288 int i; 5289 5290 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 5291 return -EIO; 5292 5293 hw = pi->hw; 5294 5295 mutex_lock(&pi->sched_lock); 5296 5297 for (i = 0; i < count; i++) { 5298 struct ice_sched_node *node; 5299 5300 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 5301 if (!node) 5302 continue; 5303 5304 qg_list->parent_teid = node->info.parent_teid; 5305 qg_list->num_qs = 1; 5306 qg_list->q_id[0] = 5307 cpu_to_le16(q_id[i] | 5308 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 5309 5310 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 5311 ICE_NO_RESET, 0, NULL); 5312 if (status) 5313 break; 5314 5315 ice_free_sched_node(pi, node); 5316 } 5317 5318 mutex_unlock(&pi->sched_lock); 5319 return status; 5320 } 5321 5322 /** 5323 * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements 5324 * @hw: pointer to the HW struct 5325 * @dpll_idx: index of dpll to be measured 5326 * @meas: array to be filled with results 5327 * @meas_num: max number of results array can hold 5328 * 5329 * Get CGU measurements (0x0C59) of phase and frequency offsets for input 5330 * pins on given dpll. 5331 * 5332 * Return: 0 on success or negative value on failure. 5333 */ 5334 int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, 5335 struct ice_cgu_input_measure *meas, 5336 u16 meas_num) 5337 { 5338 struct ice_aqc_get_cgu_input_measure *cmd; 5339 struct libie_aq_desc desc; 5340 5341 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_measure); 5342 cmd = libie_aq_raw(&desc); 5343 cmd->dpll_idx_opt = dpll_idx & ICE_AQC_GET_CGU_IN_MEAS_DPLL_IDX_M; 5344 5345 return ice_aq_send_cmd(hw, &desc, meas, meas_num * sizeof(*meas), NULL); 5346 } 5347 5348 /** 5349 * ice_aq_get_cgu_abilities - get cgu abilities 5350 * @hw: pointer to the HW struct 5351 * @abilities: CGU abilities 5352 * 5353 * Get CGU abilities (0x0C61) 5354 * Return: 0 on success or negative value on failure. 5355 */ 5356 int 5357 ice_aq_get_cgu_abilities(struct ice_hw *hw, 5358 struct ice_aqc_get_cgu_abilities *abilities) 5359 { 5360 struct libie_aq_desc desc; 5361 5362 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities); 5363 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL); 5364 } 5365 5366 /** 5367 * ice_aq_set_input_pin_cfg - set input pin config 5368 * @hw: pointer to the HW struct 5369 * @input_idx: Input index 5370 * @flags1: Input flags 5371 * @flags2: Input flags 5372 * @freq: Frequency in Hz 5373 * @phase_delay: Delay in ps 5374 * 5375 * Set CGU input config (0x0C62) 5376 * Return: 0 on success or negative value on failure. 5377 */ 5378 int 5379 ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2, 5380 u32 freq, s32 phase_delay) 5381 { 5382 struct ice_aqc_set_cgu_input_config *cmd; 5383 struct libie_aq_desc desc; 5384 5385 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config); 5386 cmd = libie_aq_raw(&desc); 5387 cmd->input_idx = input_idx; 5388 cmd->flags1 = flags1; 5389 cmd->flags2 = flags2; 5390 cmd->freq = cpu_to_le32(freq); 5391 cmd->phase_delay = cpu_to_le32(phase_delay); 5392 5393 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5394 } 5395 5396 /** 5397 * ice_aq_get_input_pin_cfg - get input pin config 5398 * @hw: pointer to the HW struct 5399 * @input_idx: Input index 5400 * @status: Pin status 5401 * @type: Pin type 5402 * @flags1: Input flags 5403 * @flags2: Input flags 5404 * @freq: Frequency in Hz 5405 * @phase_delay: Delay in ps 5406 * 5407 * Get CGU input config (0x0C63) 5408 * Return: 0 on success or negative value on failure. 5409 */ 5410 int 5411 ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type, 5412 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay) 5413 { 5414 struct ice_aqc_get_cgu_input_config *cmd; 5415 struct libie_aq_desc desc; 5416 int ret; 5417 5418 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config); 5419 cmd = libie_aq_raw(&desc); 5420 cmd->input_idx = input_idx; 5421 5422 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5423 if (!ret) { 5424 if (status) 5425 *status = cmd->status; 5426 if (type) 5427 *type = cmd->type; 5428 if (flags1) 5429 *flags1 = cmd->flags1; 5430 if (flags2) 5431 *flags2 = cmd->flags2; 5432 if (freq) 5433 *freq = le32_to_cpu(cmd->freq); 5434 if (phase_delay) 5435 *phase_delay = le32_to_cpu(cmd->phase_delay); 5436 } 5437 5438 return ret; 5439 } 5440 5441 /** 5442 * ice_aq_set_output_pin_cfg - set output pin config 5443 * @hw: pointer to the HW struct 5444 * @output_idx: Output index 5445 * @flags: Output flags 5446 * @src_sel: Index of DPLL block 5447 * @freq: Output frequency 5448 * @phase_delay: Output phase compensation 5449 * 5450 * Set CGU output config (0x0C64) 5451 * Return: 0 on success or negative value on failure. 5452 */ 5453 int 5454 ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags, 5455 u8 src_sel, u32 freq, s32 phase_delay) 5456 { 5457 struct ice_aqc_set_cgu_output_config *cmd; 5458 struct libie_aq_desc desc; 5459 5460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config); 5461 cmd = libie_aq_raw(&desc); 5462 cmd->output_idx = output_idx; 5463 cmd->flags = flags; 5464 cmd->src_sel = src_sel; 5465 cmd->freq = cpu_to_le32(freq); 5466 cmd->phase_delay = cpu_to_le32(phase_delay); 5467 5468 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5469 } 5470 5471 /** 5472 * ice_aq_get_output_pin_cfg - get output pin config 5473 * @hw: pointer to the HW struct 5474 * @output_idx: Output index 5475 * @flags: Output flags 5476 * @src_sel: Internal DPLL source 5477 * @freq: Output frequency 5478 * @src_freq: Source frequency 5479 * 5480 * Get CGU output config (0x0C65) 5481 * Return: 0 on success or negative value on failure. 5482 */ 5483 int 5484 ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags, 5485 u8 *src_sel, u32 *freq, u32 *src_freq) 5486 { 5487 struct ice_aqc_get_cgu_output_config *cmd; 5488 struct libie_aq_desc desc; 5489 int ret; 5490 5491 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config); 5492 cmd = libie_aq_raw(&desc); 5493 cmd->output_idx = output_idx; 5494 5495 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5496 if (!ret) { 5497 if (flags) 5498 *flags = cmd->flags; 5499 if (src_sel) 5500 *src_sel = cmd->src_sel; 5501 if (freq) 5502 *freq = le32_to_cpu(cmd->freq); 5503 if (src_freq) 5504 *src_freq = le32_to_cpu(cmd->src_freq); 5505 } 5506 5507 return ret; 5508 } 5509 5510 /** 5511 * ice_aq_get_cgu_dpll_status - get dpll status 5512 * @hw: pointer to the HW struct 5513 * @dpll_num: DPLL index 5514 * @ref_state: Reference clock state 5515 * @config: current DPLL config 5516 * @dpll_state: current DPLL state 5517 * @phase_offset: Phase offset in ns 5518 * @eec_mode: EEC_mode 5519 * 5520 * Get CGU DPLL status (0x0C66) 5521 * Return: 0 on success or negative value on failure. 5522 */ 5523 int 5524 ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state, 5525 u8 *dpll_state, u8 *config, s64 *phase_offset, 5526 u8 *eec_mode) 5527 { 5528 struct ice_aqc_get_cgu_dpll_status *cmd; 5529 struct libie_aq_desc desc; 5530 int status; 5531 5532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status); 5533 cmd = libie_aq_raw(&desc); 5534 cmd->dpll_num = dpll_num; 5535 5536 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5537 if (!status) { 5538 *ref_state = cmd->ref_state; 5539 *dpll_state = cmd->dpll_state; 5540 *config = cmd->config; 5541 *phase_offset = le32_to_cpu(cmd->phase_offset_h); 5542 *phase_offset <<= 32; 5543 *phase_offset += le32_to_cpu(cmd->phase_offset_l); 5544 *phase_offset = sign_extend64(*phase_offset, 47); 5545 *eec_mode = cmd->eec_mode; 5546 } 5547 5548 return status; 5549 } 5550 5551 /** 5552 * ice_aq_set_cgu_dpll_config - set dpll config 5553 * @hw: pointer to the HW struct 5554 * @dpll_num: DPLL index 5555 * @ref_state: Reference clock state 5556 * @config: DPLL config 5557 * @eec_mode: EEC mode 5558 * 5559 * Set CGU DPLL config (0x0C67) 5560 * Return: 0 on success or negative value on failure. 5561 */ 5562 int 5563 ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state, 5564 u8 config, u8 eec_mode) 5565 { 5566 struct ice_aqc_set_cgu_dpll_config *cmd; 5567 struct libie_aq_desc desc; 5568 5569 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config); 5570 cmd = libie_aq_raw(&desc); 5571 cmd->dpll_num = dpll_num; 5572 cmd->ref_state = ref_state; 5573 cmd->config = config; 5574 cmd->eec_mode = eec_mode; 5575 5576 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5577 } 5578 5579 /** 5580 * ice_aq_set_cgu_ref_prio - set input reference priority 5581 * @hw: pointer to the HW struct 5582 * @dpll_num: DPLL index 5583 * @ref_idx: Reference pin index 5584 * @ref_priority: Reference input priority 5585 * 5586 * Set CGU reference priority (0x0C68) 5587 * Return: 0 on success or negative value on failure. 5588 */ 5589 int 5590 ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5591 u8 ref_priority) 5592 { 5593 struct ice_aqc_set_cgu_ref_prio *cmd; 5594 struct libie_aq_desc desc; 5595 5596 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio); 5597 cmd = libie_aq_raw(&desc); 5598 cmd->dpll_num = dpll_num; 5599 cmd->ref_idx = ref_idx; 5600 cmd->ref_priority = ref_priority; 5601 5602 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5603 } 5604 5605 /** 5606 * ice_aq_get_cgu_ref_prio - get input reference priority 5607 * @hw: pointer to the HW struct 5608 * @dpll_num: DPLL index 5609 * @ref_idx: Reference pin index 5610 * @ref_prio: Reference input priority 5611 * 5612 * Get CGU reference priority (0x0C69) 5613 * Return: 0 on success or negative value on failure. 5614 */ 5615 int 5616 ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx, 5617 u8 *ref_prio) 5618 { 5619 struct ice_aqc_get_cgu_ref_prio *cmd; 5620 struct libie_aq_desc desc; 5621 int status; 5622 5623 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio); 5624 cmd = libie_aq_raw(&desc); 5625 cmd->dpll_num = dpll_num; 5626 cmd->ref_idx = ref_idx; 5627 5628 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5629 if (!status) 5630 *ref_prio = cmd->ref_priority; 5631 5632 return status; 5633 } 5634 5635 /** 5636 * ice_aq_get_cgu_info - get cgu info 5637 * @hw: pointer to the HW struct 5638 * @cgu_id: CGU ID 5639 * @cgu_cfg_ver: CGU config version 5640 * @cgu_fw_ver: CGU firmware version 5641 * 5642 * Get CGU info (0x0C6A) 5643 * Return: 0 on success or negative value on failure. 5644 */ 5645 int 5646 ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver, 5647 u32 *cgu_fw_ver) 5648 { 5649 struct ice_aqc_get_cgu_info *cmd; 5650 struct libie_aq_desc desc; 5651 int status; 5652 5653 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info); 5654 cmd = libie_aq_raw(&desc); 5655 5656 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5657 if (!status) { 5658 *cgu_id = le32_to_cpu(cmd->cgu_id); 5659 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); 5660 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); 5661 } 5662 5663 return status; 5664 } 5665 5666 /** 5667 * ice_aq_set_phy_rec_clk_out - set RCLK phy out 5668 * @hw: pointer to the HW struct 5669 * @phy_output: PHY reference clock output pin 5670 * @enable: GPIO state to be applied 5671 * @freq: PHY output frequency 5672 * 5673 * Set phy recovered clock as reference (0x0630) 5674 * Return: 0 on success or negative value on failure. 5675 */ 5676 int 5677 ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable, 5678 u32 *freq) 5679 { 5680 struct ice_aqc_set_phy_rec_clk_out *cmd; 5681 struct libie_aq_desc desc; 5682 int status; 5683 5684 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out); 5685 cmd = libie_aq_raw(&desc); 5686 cmd->phy_output = phy_output; 5687 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; 5688 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; 5689 cmd->freq = cpu_to_le32(*freq); 5690 5691 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5692 if (!status) 5693 *freq = le32_to_cpu(cmd->freq); 5694 5695 return status; 5696 } 5697 5698 /** 5699 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info 5700 * @hw: pointer to the HW struct 5701 * @phy_output: PHY reference clock output pin 5702 * @port_num: Port number 5703 * @flags: PHY flags 5704 * @node_handle: PHY output frequency 5705 * 5706 * Get PHY recovered clock output info (0x0631) 5707 * Return: 0 on success or negative value on failure. 5708 */ 5709 int 5710 ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num, 5711 u8 *flags, u16 *node_handle) 5712 { 5713 struct ice_aqc_get_phy_rec_clk_out *cmd; 5714 struct libie_aq_desc desc; 5715 int status; 5716 5717 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out); 5718 cmd = libie_aq_raw(&desc); 5719 cmd->phy_output = *phy_output; 5720 5721 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5722 if (!status) { 5723 *phy_output = cmd->phy_output; 5724 if (port_num) 5725 *port_num = cmd->port_num; 5726 if (flags) 5727 *flags = cmd->flags; 5728 if (node_handle) 5729 *node_handle = le16_to_cpu(cmd->node_handle); 5730 } 5731 5732 return status; 5733 } 5734 5735 /** 5736 * ice_aq_get_sensor_reading 5737 * @hw: pointer to the HW struct 5738 * @data: pointer to data to be read from the sensor 5739 * 5740 * Get sensor reading (0x0632) 5741 */ 5742 int ice_aq_get_sensor_reading(struct ice_hw *hw, 5743 struct ice_aqc_get_sensor_reading_resp *data) 5744 { 5745 struct ice_aqc_get_sensor_reading *cmd; 5746 struct libie_aq_desc desc; 5747 int status; 5748 5749 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); 5750 cmd = libie_aq_raw(&desc); 5751 #define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0 5752 #define ICE_INTERNAL_TEMP_SENSOR 0 5753 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; 5754 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; 5755 5756 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5757 if (!status) 5758 memcpy(data, &desc.params.raw, 5759 sizeof(*data)); 5760 5761 return status; 5762 } 5763 5764 /** 5765 * ice_replay_pre_init - replay pre initialization 5766 * @hw: pointer to the HW struct 5767 * 5768 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 5769 */ 5770 static int ice_replay_pre_init(struct ice_hw *hw) 5771 { 5772 struct ice_switch_info *sw = hw->switch_info; 5773 u8 i; 5774 5775 /* Delete old entries from replay filter list head if there is any */ 5776 ice_rm_all_sw_replay_rule_info(hw); 5777 /* In start of replay, move entries into replay_rules list, it 5778 * will allow adding rules entries back to filt_rules list, 5779 * which is operational list. 5780 */ 5781 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 5782 list_replace_init(&sw->recp_list[i].filt_rules, 5783 &sw->recp_list[i].filt_replay_rules); 5784 ice_sched_replay_agg_vsi_preinit(hw); 5785 5786 return 0; 5787 } 5788 5789 /** 5790 * ice_replay_vsi - replay VSI configuration 5791 * @hw: pointer to the HW struct 5792 * @vsi_handle: driver VSI handle 5793 * 5794 * Restore all VSI configuration after reset. It is required to call this 5795 * function with main VSI first. 5796 */ 5797 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 5798 { 5799 int status; 5800 5801 if (!ice_is_vsi_valid(hw, vsi_handle)) 5802 return -EINVAL; 5803 5804 /* Replay pre-initialization if there is any */ 5805 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 5806 status = ice_replay_pre_init(hw); 5807 if (status) 5808 return status; 5809 } 5810 /* Replay per VSI all RSS configurations */ 5811 status = ice_replay_rss_cfg(hw, vsi_handle); 5812 if (status) 5813 return status; 5814 /* Replay per VSI all filters */ 5815 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 5816 if (!status) 5817 status = ice_replay_vsi_agg(hw, vsi_handle); 5818 return status; 5819 } 5820 5821 /** 5822 * ice_replay_post - post replay configuration cleanup 5823 * @hw: pointer to the HW struct 5824 * 5825 * Post replay cleanup. 5826 */ 5827 void ice_replay_post(struct ice_hw *hw) 5828 { 5829 /* Delete old entries from replay filter list head */ 5830 ice_rm_all_sw_replay_rule_info(hw); 5831 ice_sched_replay_agg(hw); 5832 } 5833 5834 /** 5835 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5836 * @hw: ptr to the hardware info 5837 * @reg: offset of 64 bit HW register to read from 5838 * @prev_stat_loaded: bool to specify if previous stats are loaded 5839 * @prev_stat: ptr to previous loaded stat value 5840 * @cur_stat: ptr to current stat value 5841 */ 5842 void 5843 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5844 u64 *prev_stat, u64 *cur_stat) 5845 { 5846 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5847 5848 /* device stats are not reset at PFR, they likely will not be zeroed 5849 * when the driver starts. Thus, save the value from the first read 5850 * without adding to the statistic value so that we report stats which 5851 * count up from zero. 5852 */ 5853 if (!prev_stat_loaded) { 5854 *prev_stat = new_data; 5855 return; 5856 } 5857 5858 /* Calculate the difference between the new and old values, and then 5859 * add it to the software stat value. 5860 */ 5861 if (new_data >= *prev_stat) 5862 *cur_stat += new_data - *prev_stat; 5863 else 5864 /* to manage the potential roll-over */ 5865 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5866 5867 /* Update the previously stored value to prepare for next read */ 5868 *prev_stat = new_data; 5869 } 5870 5871 /** 5872 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5873 * @hw: ptr to the hardware info 5874 * @reg: offset of HW register to read from 5875 * @prev_stat_loaded: bool to specify if previous stats are loaded 5876 * @prev_stat: ptr to previous loaded stat value 5877 * @cur_stat: ptr to current stat value 5878 */ 5879 void 5880 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5881 u64 *prev_stat, u64 *cur_stat) 5882 { 5883 u32 new_data; 5884 5885 new_data = rd32(hw, reg); 5886 5887 /* device stats are not reset at PFR, they likely will not be zeroed 5888 * when the driver starts. Thus, save the value from the first read 5889 * without adding to the statistic value so that we report stats which 5890 * count up from zero. 5891 */ 5892 if (!prev_stat_loaded) { 5893 *prev_stat = new_data; 5894 return; 5895 } 5896 5897 /* Calculate the difference between the new and old values, and then 5898 * add it to the software stat value. 5899 */ 5900 if (new_data >= *prev_stat) 5901 *cur_stat += new_data - *prev_stat; 5902 else 5903 /* to manage the potential roll-over */ 5904 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5905 5906 /* Update the previously stored value to prepare for next read */ 5907 *prev_stat = new_data; 5908 } 5909 5910 /** 5911 * ice_sched_query_elem - query element information from HW 5912 * @hw: pointer to the HW struct 5913 * @node_teid: node TEID to be queried 5914 * @buf: buffer to element information 5915 * 5916 * This function queries HW element information 5917 */ 5918 int 5919 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5920 struct ice_aqc_txsched_elem_data *buf) 5921 { 5922 u16 buf_size, num_elem_ret = 0; 5923 int status; 5924 5925 buf_size = sizeof(*buf); 5926 memset(buf, 0, buf_size); 5927 buf->node_teid = cpu_to_le32(node_teid); 5928 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5929 NULL); 5930 if (status || num_elem_ret != 1) 5931 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5932 return status; 5933 } 5934 5935 /** 5936 * ice_aq_read_i2c 5937 * @hw: pointer to the hw struct 5938 * @topo_addr: topology address for a device to communicate with 5939 * @bus_addr: 7-bit I2C bus address 5940 * @addr: I2C memory address (I2C offset) with up to 16 bits 5941 * @params: I2C parameters: bit [7] - Repeated start, 5942 * bits [6:5] data offset size, 5943 * bit [4] - I2C address type, 5944 * bits [3:0] - data size to read (0-16 bytes) 5945 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5946 * @cd: pointer to command details structure or NULL 5947 * 5948 * Read I2C (0x06E2) 5949 */ 5950 int 5951 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5952 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5953 struct ice_sq_cd *cd) 5954 { 5955 struct libie_aq_desc desc = { 0 }; 5956 struct ice_aqc_i2c *cmd; 5957 u8 data_size; 5958 int status; 5959 5960 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5961 cmd = libie_aq_raw(&desc); 5962 5963 if (!data) 5964 return -EINVAL; 5965 5966 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5967 5968 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5969 cmd->topo_addr = topo_addr; 5970 cmd->i2c_params = params; 5971 cmd->i2c_addr = addr; 5972 5973 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5974 if (!status) { 5975 struct ice_aqc_read_i2c_resp *resp; 5976 u8 i; 5977 5978 resp = libie_aq_raw(&desc); 5979 for (i = 0; i < data_size; i++) { 5980 *data = resp->i2c_data[i]; 5981 data++; 5982 } 5983 } 5984 5985 return status; 5986 } 5987 5988 /** 5989 * ice_aq_write_i2c 5990 * @hw: pointer to the hw struct 5991 * @topo_addr: topology address for a device to communicate with 5992 * @bus_addr: 7-bit I2C bus address 5993 * @addr: I2C memory address (I2C offset) with up to 16 bits 5994 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5995 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5996 * @cd: pointer to command details structure or NULL 5997 * 5998 * Write I2C (0x06E3) 5999 * 6000 * * Return: 6001 * * 0 - Successful write to the i2c device 6002 * * -EINVAL - Data size greater than 4 bytes 6003 * * -EIO - FW error 6004 */ 6005 int 6006 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 6007 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 6008 struct ice_sq_cd *cd) 6009 { 6010 struct libie_aq_desc desc = { 0 }; 6011 struct ice_aqc_i2c *cmd; 6012 u8 data_size; 6013 6014 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 6015 cmd = libie_aq_raw(&desc); 6016 6017 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 6018 6019 /* data_size limited to 4 */ 6020 if (data_size > 4) 6021 return -EINVAL; 6022 6023 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 6024 cmd->topo_addr = topo_addr; 6025 cmd->i2c_params = params; 6026 cmd->i2c_addr = addr; 6027 6028 memcpy(cmd->i2c_data, data, data_size); 6029 6030 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6031 } 6032 6033 /** 6034 * ice_get_pca9575_handle - find and return the PCA9575 controller 6035 * @hw: pointer to the hw struct 6036 * @pca9575_handle: GPIO controller's handle 6037 * 6038 * Find and return the GPIO controller's handle in the netlist. 6039 * When found - the value will be cached in the hw structure and following calls 6040 * will return cached value. 6041 * 6042 * Return: 0 on success, -ENXIO when there's no PCA9575 present. 6043 */ 6044 int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 6045 { 6046 struct ice_aqc_get_link_topo *cmd; 6047 struct libie_aq_desc desc; 6048 int err; 6049 u8 idx; 6050 6051 /* If handle was read previously return cached value */ 6052 if (hw->io_expander_handle) { 6053 *pca9575_handle = hw->io_expander_handle; 6054 return 0; 6055 } 6056 6057 #define SW_PCA9575_SFP_TOPO_IDX 2 6058 #define SW_PCA9575_QSFP_TOPO_IDX 1 6059 6060 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 6061 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 6062 idx = SW_PCA9575_SFP_TOPO_IDX; 6063 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 6064 idx = SW_PCA9575_QSFP_TOPO_IDX; 6065 else 6066 return -ENXIO; 6067 6068 /* If handle was not detected read it from the netlist */ 6069 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 6070 cmd = libie_aq_raw(&desc); 6071 cmd->addr.topo_params.node_type_ctx = 6072 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL; 6073 cmd->addr.topo_params.index = idx; 6074 6075 err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6076 if (err) 6077 return -ENXIO; 6078 6079 /* Verify if we found the right IO expander type */ 6080 if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 6081 return -ENXIO; 6082 6083 /* If present save the handle and return it */ 6084 hw->io_expander_handle = 6085 le16_to_cpu(cmd->addr.handle); 6086 *pca9575_handle = hw->io_expander_handle; 6087 6088 return 0; 6089 } 6090 6091 /** 6092 * ice_read_pca9575_reg - read the register from the PCA9575 controller 6093 * @hw: pointer to the hw struct 6094 * @offset: GPIO controller register offset 6095 * @data: pointer to data to be read from the GPIO controller 6096 * 6097 * Return: 0 on success, negative error code otherwise. 6098 */ 6099 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 6100 { 6101 struct ice_aqc_link_topo_addr link_topo; 6102 __le16 addr; 6103 u16 handle; 6104 int err; 6105 6106 memset(&link_topo, 0, sizeof(link_topo)); 6107 6108 err = ice_get_pca9575_handle(hw, &handle); 6109 if (err) 6110 return err; 6111 6112 link_topo.handle = cpu_to_le16(handle); 6113 link_topo.topo_params.node_type_ctx = 6114 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 6115 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 6116 6117 addr = cpu_to_le16((u16)offset); 6118 6119 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 6120 } 6121 6122 /** 6123 * ice_aq_set_gpio 6124 * @hw: pointer to the hw struct 6125 * @gpio_ctrl_handle: GPIO controller node handle 6126 * @pin_idx: IO Number of the GPIO that needs to be set 6127 * @value: SW provide IO value to set in the LSB 6128 * @cd: pointer to command details structure or NULL 6129 * 6130 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 6131 */ 6132 int 6133 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 6134 struct ice_sq_cd *cd) 6135 { 6136 struct libie_aq_desc desc; 6137 struct ice_aqc_gpio *cmd; 6138 6139 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 6140 cmd = libie_aq_raw(&desc); 6141 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6142 cmd->gpio_num = pin_idx; 6143 cmd->gpio_val = value ? 1 : 0; 6144 6145 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6146 } 6147 6148 /** 6149 * ice_aq_get_gpio 6150 * @hw: pointer to the hw struct 6151 * @gpio_ctrl_handle: GPIO controller node handle 6152 * @pin_idx: IO Number of the GPIO that needs to be set 6153 * @value: IO value read 6154 * @cd: pointer to command details structure or NULL 6155 * 6156 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 6157 * the topology 6158 */ 6159 int 6160 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 6161 bool *value, struct ice_sq_cd *cd) 6162 { 6163 struct libie_aq_desc desc; 6164 struct ice_aqc_gpio *cmd; 6165 int status; 6166 6167 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 6168 cmd = libie_aq_raw(&desc); 6169 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 6170 cmd->gpio_num = pin_idx; 6171 6172 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 6173 if (status) 6174 return status; 6175 6176 *value = !!cmd->gpio_val; 6177 return 0; 6178 } 6179 6180 /** 6181 * ice_is_fw_api_min_ver 6182 * @hw: pointer to the hardware structure 6183 * @maj: major version 6184 * @min: minor version 6185 * @patch: patch version 6186 * 6187 * Checks if the firmware API is minimum version 6188 */ 6189 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 6190 { 6191 if (hw->api_maj_ver == maj) { 6192 if (hw->api_min_ver > min) 6193 return true; 6194 if (hw->api_min_ver == min && hw->api_patch >= patch) 6195 return true; 6196 } else if (hw->api_maj_ver > maj) { 6197 return true; 6198 } 6199 6200 return false; 6201 } 6202 6203 /** 6204 * ice_fw_supports_link_override 6205 * @hw: pointer to the hardware structure 6206 * 6207 * Checks if the firmware supports link override 6208 */ 6209 bool ice_fw_supports_link_override(struct ice_hw *hw) 6210 { 6211 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 6212 ICE_FW_API_LINK_OVERRIDE_MIN, 6213 ICE_FW_API_LINK_OVERRIDE_PATCH); 6214 } 6215 6216 /** 6217 * ice_get_link_default_override 6218 * @ldo: pointer to the link default override struct 6219 * @pi: pointer to the port info struct 6220 * 6221 * Gets the link default override for a port 6222 */ 6223 int 6224 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 6225 struct ice_port_info *pi) 6226 { 6227 u16 i, tlv, tlv_len, tlv_start, buf, offset; 6228 struct ice_hw *hw = pi->hw; 6229 int status; 6230 6231 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 6232 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 6233 if (status) { 6234 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 6235 return status; 6236 } 6237 6238 /* Each port has its own config; calculate for our port */ 6239 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 6240 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 6241 6242 /* link options first */ 6243 status = ice_read_sr_word(hw, tlv_start, &buf); 6244 if (status) { 6245 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6246 return status; 6247 } 6248 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); 6249 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 6250 ICE_LINK_OVERRIDE_PHY_CFG_S; 6251 6252 /* link PHY config */ 6253 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 6254 status = ice_read_sr_word(hw, offset, &buf); 6255 if (status) { 6256 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 6257 return status; 6258 } 6259 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 6260 6261 /* PHY types low */ 6262 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 6263 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6264 status = ice_read_sr_word(hw, (offset + i), &buf); 6265 if (status) { 6266 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6267 return status; 6268 } 6269 /* shift 16 bits at a time to fill 64 bits */ 6270 ldo->phy_type_low |= ((u64)buf << (i * 16)); 6271 } 6272 6273 /* PHY types high */ 6274 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 6275 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 6276 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 6277 status = ice_read_sr_word(hw, (offset + i), &buf); 6278 if (status) { 6279 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 6280 return status; 6281 } 6282 /* shift 16 bits at a time to fill 64 bits */ 6283 ldo->phy_type_high |= ((u64)buf << (i * 16)); 6284 } 6285 6286 return status; 6287 } 6288 6289 /** 6290 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 6291 * @caps: get PHY capability data 6292 */ 6293 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 6294 { 6295 if (caps->caps & ICE_AQC_PHY_AN_MODE || 6296 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 6297 ICE_AQC_PHY_AN_EN_CLAUSE73 | 6298 ICE_AQC_PHY_AN_EN_CLAUSE37)) 6299 return true; 6300 6301 return false; 6302 } 6303 6304 /** 6305 * ice_is_fw_health_report_supported - checks if firmware supports health events 6306 * @hw: pointer to the hardware structure 6307 * 6308 * Return: true if firmware supports health status reports, 6309 * false otherwise 6310 */ 6311 bool ice_is_fw_health_report_supported(struct ice_hw *hw) 6312 { 6313 return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ, 6314 ICE_FW_API_HEALTH_REPORT_MIN, 6315 ICE_FW_API_HEALTH_REPORT_PATCH); 6316 } 6317 6318 /** 6319 * ice_aq_set_health_status_cfg - Configure FW health events 6320 * @hw: pointer to the HW struct 6321 * @event_source: type of diagnostic events to enable 6322 * 6323 * Configure the health status event types that the firmware will send to this 6324 * PF. The supported event types are: PF-specific, all PFs, and global. 6325 * 6326 * Return: 0 on success, negative error code otherwise. 6327 */ 6328 int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source) 6329 { 6330 struct ice_aqc_set_health_status_cfg *cmd; 6331 struct libie_aq_desc desc; 6332 6333 cmd = libie_aq_raw(&desc); 6334 6335 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_health_status_cfg); 6336 6337 cmd->event_source = event_source; 6338 6339 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6340 } 6341 6342 /** 6343 * ice_aq_set_lldp_mib - Set the LLDP MIB 6344 * @hw: pointer to the HW struct 6345 * @mib_type: Local, Remote or both Local and Remote MIBs 6346 * @buf: pointer to the caller-supplied buffer to store the MIB block 6347 * @buf_size: size of the buffer (in bytes) 6348 * @cd: pointer to command details structure or NULL 6349 * 6350 * Set the LLDP MIB. (0x0A08) 6351 */ 6352 int 6353 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 6354 struct ice_sq_cd *cd) 6355 { 6356 struct ice_aqc_lldp_set_local_mib *cmd; 6357 struct libie_aq_desc desc; 6358 6359 cmd = libie_aq_raw(&desc); 6360 6361 if (buf_size == 0 || !buf) 6362 return -EINVAL; 6363 6364 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 6365 6366 desc.flags |= cpu_to_le16((u16)LIBIE_AQ_FLAG_RD); 6367 desc.datalen = cpu_to_le16(buf_size); 6368 6369 cmd->type = mib_type; 6370 cmd->length = cpu_to_le16(buf_size); 6371 6372 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 6373 } 6374 6375 /** 6376 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 6377 * @hw: pointer to HW struct 6378 */ 6379 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 6380 { 6381 if (hw->mac_type != ICE_MAC_E810) 6382 return false; 6383 6384 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 6385 ICE_FW_API_LLDP_FLTR_MIN, 6386 ICE_FW_API_LLDP_FLTR_PATCH); 6387 } 6388 6389 /** 6390 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 6391 * @hw: pointer to HW struct 6392 * @vsi: VSI to add the filter to 6393 * @add: boolean for if adding or removing a filter 6394 * 6395 * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed 6396 * with this HW or VSI, otherwise an error corresponding to 6397 * the AQ transaction result. 6398 */ 6399 int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add) 6400 { 6401 struct ice_aqc_lldp_filter_ctrl *cmd; 6402 struct libie_aq_desc desc; 6403 6404 if (!ice_fw_supports_lldp_fltr_ctrl(hw)) 6405 return -EOPNOTSUPP; 6406 6407 cmd = libie_aq_raw(&desc); 6408 6409 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 6410 6411 if (add) 6412 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 6413 else 6414 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 6415 6416 cmd->vsi_num = cpu_to_le16(vsi->vsi_num); 6417 6418 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6419 } 6420 6421 /** 6422 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 6423 * @hw: pointer to HW struct 6424 */ 6425 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 6426 { 6427 struct libie_aq_desc desc; 6428 6429 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 6430 6431 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 6432 } 6433 6434 /** 6435 * ice_fw_supports_report_dflt_cfg 6436 * @hw: pointer to the hardware structure 6437 * 6438 * Checks if the firmware supports report default configuration 6439 */ 6440 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 6441 { 6442 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 6443 ICE_FW_API_REPORT_DFLT_CFG_MIN, 6444 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 6445 } 6446 6447 /* each of the indexes into the following array match the speed of a return 6448 * value from the list of AQ returned speeds like the range: 6449 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 6450 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 6451 * array. The array is defined as 15 elements long because the link_speed 6452 * returned by the firmware is a 16 bit * value, but is indexed 6453 * by [fls(speed) - 1] 6454 */ 6455 static const u32 ice_aq_to_link_speed[] = { 6456 SPEED_10, /* BIT(0) */ 6457 SPEED_100, 6458 SPEED_1000, 6459 SPEED_2500, 6460 SPEED_5000, 6461 SPEED_10000, 6462 SPEED_20000, 6463 SPEED_25000, 6464 SPEED_40000, 6465 SPEED_50000, 6466 SPEED_100000, /* BIT(10) */ 6467 SPEED_200000, 6468 }; 6469 6470 /** 6471 * ice_get_link_speed - get integer speed from table 6472 * @index: array index from fls(aq speed) - 1 6473 * 6474 * Returns: u32 value containing integer speed 6475 */ 6476 u32 ice_get_link_speed(u16 index) 6477 { 6478 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 6479 return 0; 6480 6481 return ice_aq_to_link_speed[index]; 6482 } 6483 6484 /** 6485 * ice_get_dest_cgu - get destination CGU dev for given HW 6486 * @hw: pointer to the HW struct 6487 * 6488 * Get CGU client id for CGU register read/write operations. 6489 * 6490 * Return: CGU device id to use in SBQ transactions. 6491 */ 6492 static enum ice_sbq_dev_id ice_get_dest_cgu(struct ice_hw *hw) 6493 { 6494 /* On dual complex E825 only complex 0 has functional CGU powering all 6495 * the PHYs. 6496 * SBQ destination device cgu points to CGU on a current complex and to 6497 * access primary CGU from the secondary complex, the driver should use 6498 * cgu_peer as a destination device. 6499 */ 6500 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 && ice_is_dual(hw) && 6501 !ice_is_primary(hw)) 6502 return ice_sbq_dev_cgu_peer; 6503 return ice_sbq_dev_cgu; 6504 } 6505 6506 /** 6507 * ice_read_cgu_reg - Read a CGU register 6508 * @hw: Pointer to the HW struct 6509 * @addr: Register address to read 6510 * @val: Storage for register value read 6511 * 6512 * Read the contents of a register of the Clock Generation Unit. Only 6513 * applicable to E82X devices. 6514 * 6515 * Return: 0 on success, other error codes when failed to read from CGU. 6516 */ 6517 int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val) 6518 { 6519 struct ice_sbq_msg_input cgu_msg = { 6520 .dest_dev = ice_get_dest_cgu(hw), 6521 .opcode = ice_sbq_msg_rd, 6522 .msg_addr_low = addr 6523 }; 6524 int err; 6525 6526 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6527 if (err) { 6528 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 6529 addr, err); 6530 return err; 6531 } 6532 6533 *val = cgu_msg.data; 6534 6535 return 0; 6536 } 6537 6538 /** 6539 * ice_write_cgu_reg - Write a CGU register 6540 * @hw: Pointer to the HW struct 6541 * @addr: Register address to write 6542 * @val: Value to write into the register 6543 * 6544 * Write the specified value to a register of the Clock Generation Unit. Only 6545 * applicable to E82X devices. 6546 * 6547 * Return: 0 on success, other error codes when failed to write to CGU. 6548 */ 6549 int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val) 6550 { 6551 struct ice_sbq_msg_input cgu_msg = { 6552 .dest_dev = ice_get_dest_cgu(hw), 6553 .opcode = ice_sbq_msg_wr, 6554 .msg_addr_low = addr, 6555 .data = val 6556 }; 6557 int err; 6558 6559 err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); 6560 if (err) 6561 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 6562 addr, err); 6563 6564 return err; 6565 } 6566