1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ADIS16475 IMU driver
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/kernel.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/imu/adis.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/irq.h>
20 #include <linux/lcm.h>
21 #include <linux/math.h>
22 #include <linux/module.h>
23 #include <linux/property.h>
24 #include <linux/spi/spi.h>
25
26 #define ADIS16475_REG_DIAG_STAT 0x02
27 #define ADIS16475_REG_X_GYRO_L 0x04
28 #define ADIS16475_REG_Y_GYRO_L 0x08
29 #define ADIS16475_REG_Z_GYRO_L 0x0C
30 #define ADIS16475_REG_X_ACCEL_L 0x10
31 #define ADIS16475_REG_Y_ACCEL_L 0x14
32 #define ADIS16475_REG_Z_ACCEL_L 0x18
33 #define ADIS16475_REG_TEMP_OUT 0x1c
34 #define ADIS16475_REG_X_DELTANG_L 0x24
35 #define ADIS16475_REG_Y_DELTANG_L 0x28
36 #define ADIS16475_REG_Z_DELTANG_L 0x2C
37 #define ADIS16475_REG_X_DELTVEL_L 0x30
38 #define ADIS16475_REG_Y_DELTVEL_L 0x34
39 #define ADIS16475_REG_Z_DELTVEL_L 0x38
40 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40
41 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44
42 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48
43 #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c
44 #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50
45 #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54
46 #define ADIS16475_REG_FILT_CTRL 0x5c
47 #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0)
48 #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x)
49 #define ADIS16475_REG_MSG_CTRL 0x60
50 #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0)
51 #define ADIS16475_MSG_CTRL_DR_POL(x) \
52 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x)
53 #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2)
54 #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x)
55 #define ADIS16575_SYNC_4KHZ_MASK BIT(11)
56 #define ADIS16575_SYNC_4KHZ(x) FIELD_PREP(ADIS16575_SYNC_4KHZ_MASK, x)
57 #define ADIS16475_REG_UP_SCALE 0x62
58 #define ADIS16475_REG_DEC_RATE 0x64
59 #define ADIS16475_REG_GLOB_CMD 0x68
60 #define ADIS16475_REG_FIRM_REV 0x6c
61 #define ADIS16475_REG_FIRM_DM 0x6e
62 #define ADIS16475_REG_FIRM_Y 0x70
63 #define ADIS16475_REG_PROD_ID 0x72
64 #define ADIS16475_REG_SERIAL_NUM 0x74
65 #define ADIS16475_REG_FLASH_CNT 0x7c
66 #define ADIS16500_BURST_DATA_SEL_MASK BIT(8)
67 #define ADIS16500_BURST32_MASK BIT(9)
68 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x)
69 /* number of data elements in burst mode */
70 #define ADIS16475_BURST32_MAX_DATA_NO_TS32 32
71 #define ADIS16575_BURST32_DATA_TS32 34
72 #define ADIS16475_BURST_MAX_DATA 20
73 #define ADIS16475_MAX_SCAN_DATA 20
74 /* spi max speed in brust mode */
75 #define ADIS16475_BURST_MAX_SPEED 1000000
76 #define ADIS16575_BURST_MAX_SPEED 8000000
77 #define ADIS16475_LSB_DEC_MASK 0
78 #define ADIS16475_LSB_FIR_MASK 1
79 #define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0)
80 #define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7)
81 #define ADIS16575_MAX_FIFO_WM 511UL
82 #define ADIS16475_REG_FIFO_CTRL 0x5A
83 #define ADIS16575_WM_LVL_MASK GENMASK(15, 4)
84 #define ADIS16575_WM_LVL(x) FIELD_PREP(ADIS16575_WM_LVL_MASK, x)
85 #define ADIS16575_WM_POL_MASK BIT(3)
86 #define ADIS16575_WM_POL(x) FIELD_PREP(ADIS16575_WM_POL_MASK, x)
87 #define ADIS16575_WM_EN_MASK BIT(2)
88 #define ADIS16575_WM_EN(x) FIELD_PREP(ADIS16575_WM_EN_MASK, x)
89 #define ADIS16575_OVERFLOW_MASK BIT(1)
90 #define ADIS16575_STOP_ENQUEUE FIELD_PREP(ADIS16575_OVERFLOW_MASK, 0)
91 #define ADIS16575_OVERWRITE_OLDEST FIELD_PREP(ADIS16575_OVERFLOW_MASK, 1)
92 #define ADIS16575_FIFO_EN_MASK BIT(0)
93 #define ADIS16575_FIFO_EN(x) FIELD_PREP(ADIS16575_FIFO_EN_MASK, x)
94 #define ADIS16575_FIFO_FLUSH_CMD BIT(5)
95 #define ADIS16575_REG_FIFO_CNT 0x3C
96
97 enum {
98 ADIS16475_SYNC_DIRECT = 1,
99 ADIS16475_SYNC_SCALED,
100 ADIS16475_SYNC_OUTPUT,
101 ADIS16475_SYNC_PULSE = 5,
102 };
103
104 struct adis16475_sync {
105 u16 sync_mode;
106 u16 min_rate;
107 u16 max_rate;
108 };
109
110 struct adis16475_chip_info {
111 const struct iio_chan_spec *channels;
112 const struct adis16475_sync *sync;
113 const struct adis_data adis_data;
114 const char *name;
115 #define ADIS16475_HAS_BURST32 BIT(0)
116 #define ADIS16475_HAS_BURST_DELTA_DATA BIT(1)
117 #define ADIS16475_HAS_TIMESTAMP32 BIT(2)
118 #define ADIS16475_NEEDS_BURST_REQUEST BIT(3)
119 const long flags;
120 u32 num_channels;
121 u32 gyro_max_val;
122 u32 gyro_max_scale;
123 u32 accel_max_val;
124 u32 accel_max_scale;
125 u32 temp_scale;
126 u32 deltang_max_val;
127 u32 deltvel_max_val;
128 u32 int_clk;
129 u16 max_dec;
130 u8 num_sync;
131 };
132
133 struct adis16475 {
134 const struct adis16475_chip_info *info;
135 struct adis adis;
136 u32 clk_freq;
137 bool burst32;
138 unsigned long lsb_flag;
139 u16 sync_mode;
140 u16 fifo_watermark;
141 /* Alignment needed for the timestamp */
142 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8);
143 };
144
145 enum {
146 ADIS16475_SCAN_GYRO_X,
147 ADIS16475_SCAN_GYRO_Y,
148 ADIS16475_SCAN_GYRO_Z,
149 ADIS16475_SCAN_ACCEL_X,
150 ADIS16475_SCAN_ACCEL_Y,
151 ADIS16475_SCAN_ACCEL_Z,
152 ADIS16475_SCAN_TEMP,
153 ADIS16475_SCAN_DELTANG_X,
154 ADIS16475_SCAN_DELTANG_Y,
155 ADIS16475_SCAN_DELTANG_Z,
156 ADIS16475_SCAN_DELTVEL_X,
157 ADIS16475_SCAN_DELTVEL_Y,
158 ADIS16475_SCAN_DELTVEL_Z,
159 };
160
161 static bool low_rate_allow;
162 module_param(low_rate_allow, bool, 0444);
163 MODULE_PARM_DESC(low_rate_allow,
164 "Allow IMU rates below the minimum advisable when external clk is used in SCALED mode (default: N)");
165
adis16475_show_firmware_revision(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)166 static ssize_t adis16475_show_firmware_revision(struct file *file,
167 char __user *userbuf,
168 size_t count, loff_t *ppos)
169 {
170 struct adis16475 *st = file->private_data;
171 char buf[7];
172 size_t len;
173 u16 rev;
174 int ret;
175
176 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev);
177 if (ret)
178 return ret;
179
180 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
181
182 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
183 }
184
185 static const struct file_operations adis16475_firmware_revision_fops = {
186 .open = simple_open,
187 .read = adis16475_show_firmware_revision,
188 .llseek = default_llseek,
189 .owner = THIS_MODULE,
190 };
191
adis16475_show_firmware_date(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)192 static ssize_t adis16475_show_firmware_date(struct file *file,
193 char __user *userbuf,
194 size_t count, loff_t *ppos)
195 {
196 struct adis16475 *st = file->private_data;
197 u16 md, year;
198 char buf[12];
199 size_t len;
200 int ret;
201
202 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year);
203 if (ret)
204 return ret;
205
206 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md);
207 if (ret)
208 return ret;
209
210 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff,
211 year);
212
213 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
214 }
215
216 static const struct file_operations adis16475_firmware_date_fops = {
217 .open = simple_open,
218 .read = adis16475_show_firmware_date,
219 .llseek = default_llseek,
220 .owner = THIS_MODULE,
221 };
222
adis16475_show_serial_number(void * arg,u64 * val)223 static int adis16475_show_serial_number(void *arg, u64 *val)
224 {
225 struct adis16475 *st = arg;
226 u16 serial;
227 int ret;
228
229 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial);
230 if (ret)
231 return ret;
232
233 *val = serial;
234
235 return 0;
236 }
237 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops,
238 adis16475_show_serial_number, NULL, "0x%.4llx\n");
239
adis16475_show_product_id(void * arg,u64 * val)240 static int adis16475_show_product_id(void *arg, u64 *val)
241 {
242 struct adis16475 *st = arg;
243 u16 prod_id;
244 int ret;
245
246 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id);
247 if (ret)
248 return ret;
249
250 *val = prod_id;
251
252 return 0;
253 }
254 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops,
255 adis16475_show_product_id, NULL, "%llu\n");
256
adis16475_show_flash_count(void * arg,u64 * val)257 static int adis16475_show_flash_count(void *arg, u64 *val)
258 {
259 struct adis16475 *st = arg;
260 u32 flash_count;
261 int ret;
262
263 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT,
264 &flash_count);
265 if (ret)
266 return ret;
267
268 *val = flash_count;
269
270 return 0;
271 }
272 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops,
273 adis16475_show_flash_count, NULL, "%lld\n");
274
adis16475_debugfs_init(struct iio_dev * indio_dev)275 static void adis16475_debugfs_init(struct iio_dev *indio_dev)
276 {
277 struct adis16475 *st = iio_priv(indio_dev);
278 struct dentry *d = iio_get_debugfs_dentry(indio_dev);
279
280 if (!IS_ENABLED(CONFIG_DEBUG_FS))
281 return;
282
283 debugfs_create_file_unsafe("serial_number", 0400,
284 d, st, &adis16475_serial_number_fops);
285 debugfs_create_file_unsafe("product_id", 0400,
286 d, st, &adis16475_product_id_fops);
287 debugfs_create_file_unsafe("flash_count", 0400,
288 d, st, &adis16475_flash_count_fops);
289 debugfs_create_file("firmware_revision", 0400,
290 d, st, &adis16475_firmware_revision_fops);
291 debugfs_create_file("firmware_date", 0400, d,
292 st, &adis16475_firmware_date_fops);
293 }
294
adis16475_get_freq(struct adis16475 * st,u32 * freq)295 static int adis16475_get_freq(struct adis16475 *st, u32 *freq)
296 {
297 int ret;
298 u16 dec;
299 u32 sample_rate = st->clk_freq;
300
301 adis_dev_auto_lock(&st->adis);
302
303 if (st->sync_mode == ADIS16475_SYNC_SCALED) {
304 u16 sync_scale;
305
306 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, &sync_scale);
307 if (ret)
308 return ret;
309
310 sample_rate = st->clk_freq * sync_scale;
311 }
312
313 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec);
314 if (ret)
315 return ret;
316
317 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1);
318
319 return 0;
320 }
321
adis16475_set_freq(struct adis16475 * st,const u32 freq)322 static int adis16475_set_freq(struct adis16475 *st, const u32 freq)
323 {
324 u16 dec;
325 int ret;
326 u32 sample_rate = st->clk_freq;
327 /* The optimal sample rate for the supported IMUs is between int_clk - 100 and int_clk + 100. */
328 u32 max_sample_rate = st->info->int_clk * 1000 + 100000;
329 u32 min_sample_rate = st->info->int_clk * 1000 - 100000;
330
331 if (!freq)
332 return -EINVAL;
333
334 adis_dev_auto_lock(&st->adis);
335 /*
336 * When using sync scaled mode, the input clock needs to be scaled so that we have
337 * an IMU sample rate between (optimally) int_clk - 100 and int_clk + 100.
338 * After this, we can use the decimation filter to lower the sampling rate in order
339 * to get what the user wants.
340 * Optimally, the user sample rate is a multiple of both the IMU sample rate and
341 * the input clock. Hence, calculating the sync_scale dynamically gives us better
342 * chances of achieving a perfect/integer value for DEC_RATE. The math here is:
343 * 1. lcm of the input clock and the desired output rate.
344 * 2. get the highest multiple of the previous result lower than the adis max rate.
345 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE
346 * and DEC_RATE (to get the user output rate)
347 */
348 if (st->sync_mode == ADIS16475_SYNC_SCALED) {
349 unsigned long scaled_rate = lcm(st->clk_freq, freq);
350 int sync_scale;
351
352 /*
353 * If lcm is bigger than the IMU maximum sampling rate there's no perfect
354 * solution. In this case, we get the highest multiple of the input clock
355 * lower than the IMU max sample rate.
356 */
357 if (scaled_rate > max_sample_rate)
358 scaled_rate = max_sample_rate / st->clk_freq * st->clk_freq;
359 else
360 scaled_rate = max_sample_rate / scaled_rate * scaled_rate;
361
362 /*
363 * This is not an hard requirement but it's not advised to run the IMU
364 * with a sample rate lower than internal clock frequency, due to possible
365 * undersampling issues. However, there are users that might really want
366 * to take the risk. Hence, we provide a module parameter for them. If set,
367 * we allow sample rates lower than internal clock frequency.
368 * By default, we won't allow this and we just roundup the rate to the next
369 * multiple of the input clock. This is done like this as in some cases
370 * (when DEC_RATE is 0) might give us the closest value to the one desired
371 * by the user...
372 */
373 if (scaled_rate < min_sample_rate && !low_rate_allow)
374 scaled_rate = roundup(min_sample_rate, st->clk_freq);
375
376 sync_scale = scaled_rate / st->clk_freq;
377 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale);
378 if (ret)
379 return ret;
380
381 sample_rate = scaled_rate;
382 }
383
384 dec = DIV_ROUND_CLOSEST(sample_rate, freq);
385
386 if (dec)
387 dec--;
388
389 if (dec > st->info->max_dec)
390 dec = st->info->max_dec;
391
392 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec);
393 if (ret)
394 return ret;
395
396 /*
397 * If decimation is used, then gyro and accel data will have meaningful
398 * bits on the LSB registers. This info is used on the trigger handler.
399 */
400 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec);
401
402 return 0;
403 }
404
405 /* The values are approximated. */
406 static const u32 adis16475_3db_freqs[] = {
407 [0] = 720, /* Filter disabled, full BW (~720Hz) */
408 [1] = 360,
409 [2] = 164,
410 [3] = 80,
411 [4] = 40,
412 [5] = 20,
413 [6] = 10,
414 };
415
adis16475_get_filter(struct adis16475 * st,u32 * filter)416 static int adis16475_get_filter(struct adis16475 *st, u32 *filter)
417 {
418 u16 filter_sz;
419 int ret;
420 const int mask = ADIS16475_FILT_CTRL_MASK;
421
422 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz);
423 if (ret)
424 return ret;
425
426 *filter = adis16475_3db_freqs[filter_sz & mask];
427
428 return 0;
429 }
430
adis16475_set_filter(struct adis16475 * st,const u32 filter)431 static int adis16475_set_filter(struct adis16475 *st, const u32 filter)
432 {
433 int i = ARRAY_SIZE(adis16475_3db_freqs);
434 int ret;
435
436 while (--i) {
437 if (adis16475_3db_freqs[i] >= filter)
438 break;
439 }
440
441 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL,
442 ADIS16475_FILT_CTRL(i));
443 if (ret)
444 return ret;
445
446 /*
447 * If FIR is used, then gyro and accel data will have meaningful
448 * bits on the LSB registers. This info is used on the trigger handler.
449 */
450 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i);
451
452 return 0;
453 }
454
adis16475_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)455 static ssize_t adis16475_get_fifo_enabled(struct device *dev,
456 struct device_attribute *attr,
457 char *buf)
458 {
459 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
460 struct adis16475 *st = iio_priv(indio_dev);
461 int ret;
462 u16 val;
463
464 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val);
465 if (ret)
466 return ret;
467
468 return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_FIFO_EN_MASK, val));
469 }
470
adis16475_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)471 static ssize_t adis16475_get_fifo_watermark(struct device *dev,
472 struct device_attribute *attr,
473 char *buf)
474 {
475 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
476 struct adis16475 *st = iio_priv(indio_dev);
477 int ret;
478 u16 val;
479
480 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val);
481 if (ret)
482 return ret;
483
484 return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_WM_LVL_MASK, val) + 1);
485 }
486
hwfifo_watermark_min_show(struct device * dev,struct device_attribute * attr,char * buf)487 static ssize_t hwfifo_watermark_min_show(struct device *dev,
488 struct device_attribute *attr,
489 char *buf)
490 {
491 return sysfs_emit(buf, "1\n");
492 }
493
hwfifo_watermark_max_show(struct device * dev,struct device_attribute * attr,char * buf)494 static ssize_t hwfifo_watermark_max_show(struct device *dev,
495 struct device_attribute *attr,
496 char *buf)
497 {
498 return sysfs_emit(buf, "%lu\n", ADIS16575_MAX_FIFO_WM);
499 }
500
501 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
502 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
503 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
504 adis16475_get_fifo_watermark, NULL, 0);
505 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
506 adis16475_get_fifo_enabled, NULL, 0);
507
508 static const struct iio_dev_attr *adis16475_fifo_attributes[] = {
509 &iio_dev_attr_hwfifo_watermark_min,
510 &iio_dev_attr_hwfifo_watermark_max,
511 &iio_dev_attr_hwfifo_watermark,
512 &iio_dev_attr_hwfifo_enabled,
513 NULL
514 };
515
adis16475_buffer_postenable(struct iio_dev * indio_dev)516 static int adis16475_buffer_postenable(struct iio_dev *indio_dev)
517 {
518 struct adis16475 *st = iio_priv(indio_dev);
519 struct adis *adis = &st->adis;
520
521 return adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL,
522 ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(1));
523 }
524
adis16475_buffer_postdisable(struct iio_dev * indio_dev)525 static int adis16475_buffer_postdisable(struct iio_dev *indio_dev)
526 {
527 struct adis16475 *st = iio_priv(indio_dev);
528 struct adis *adis = &st->adis;
529 int ret;
530
531 adis_dev_auto_lock(&st->adis);
532
533 ret = __adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL,
534 ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(0));
535 if (ret)
536 return ret;
537
538 return __adis_write_reg_16(adis, ADIS16475_REG_GLOB_CMD,
539 ADIS16575_FIFO_FLUSH_CMD);
540 }
541
542 static const struct iio_buffer_setup_ops adis16475_buffer_ops = {
543 .postenable = adis16475_buffer_postenable,
544 .postdisable = adis16475_buffer_postdisable,
545 };
546
adis16475_set_watermark(struct iio_dev * indio_dev,unsigned int val)547 static int adis16475_set_watermark(struct iio_dev *indio_dev, unsigned int val)
548 {
549 struct adis16475 *st = iio_priv(indio_dev);
550 int ret;
551 u16 wm_lvl;
552
553 adis_dev_auto_lock(&st->adis);
554
555 val = min_t(unsigned int, val, ADIS16575_MAX_FIFO_WM);
556
557 wm_lvl = ADIS16575_WM_LVL(val - 1);
558 ret = __adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16575_WM_LVL_MASK, wm_lvl);
559 if (ret)
560 return ret;
561
562 st->fifo_watermark = val;
563
564 return 0;
565 }
566
567 static const u32 adis16475_calib_regs[] = {
568 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L,
569 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L,
570 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L,
571 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L,
572 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L,
573 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L,
574 };
575
adis16475_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)576 static int adis16475_read_raw(struct iio_dev *indio_dev,
577 const struct iio_chan_spec *chan,
578 int *val, int *val2, long info)
579 {
580 struct adis16475 *st = iio_priv(indio_dev);
581 int ret;
582 u32 tmp;
583
584 switch (info) {
585 case IIO_CHAN_INFO_RAW:
586 return adis_single_conversion(indio_dev, chan, 0, val);
587 case IIO_CHAN_INFO_SCALE:
588 switch (chan->type) {
589 case IIO_ANGL_VEL:
590 *val = st->info->gyro_max_val;
591 *val2 = st->info->gyro_max_scale;
592 return IIO_VAL_FRACTIONAL;
593 case IIO_ACCEL:
594 *val = st->info->accel_max_val;
595 *val2 = st->info->accel_max_scale;
596 return IIO_VAL_FRACTIONAL;
597 case IIO_TEMP:
598 *val = st->info->temp_scale;
599 return IIO_VAL_INT;
600 case IIO_DELTA_ANGL:
601 *val = st->info->deltang_max_val;
602 *val2 = 31;
603 return IIO_VAL_FRACTIONAL_LOG2;
604 case IIO_DELTA_VELOCITY:
605 *val = st->info->deltvel_max_val;
606 *val2 = 31;
607 return IIO_VAL_FRACTIONAL_LOG2;
608 default:
609 return -EINVAL;
610 }
611 case IIO_CHAN_INFO_CALIBBIAS:
612 ret = adis_read_reg_32(&st->adis,
613 adis16475_calib_regs[chan->scan_index],
614 val);
615 if (ret)
616 return ret;
617
618 return IIO_VAL_INT;
619 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
620 ret = adis16475_get_filter(st, val);
621 if (ret)
622 return ret;
623
624 return IIO_VAL_INT;
625 case IIO_CHAN_INFO_SAMP_FREQ:
626 ret = adis16475_get_freq(st, &tmp);
627 if (ret)
628 return ret;
629
630 *val = tmp / 1000;
631 *val2 = (tmp % 1000) * 1000;
632 return IIO_VAL_INT_PLUS_MICRO;
633 default:
634 return -EINVAL;
635 }
636 }
637
adis16475_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long info)638 static int adis16475_write_raw(struct iio_dev *indio_dev,
639 const struct iio_chan_spec *chan,
640 int val, int val2, long info)
641 {
642 struct adis16475 *st = iio_priv(indio_dev);
643 u32 tmp;
644
645 switch (info) {
646 case IIO_CHAN_INFO_SAMP_FREQ:
647 tmp = val * 1000 + val2 / 1000;
648 return adis16475_set_freq(st, tmp);
649 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
650 return adis16475_set_filter(st, val);
651 case IIO_CHAN_INFO_CALIBBIAS:
652 return adis_write_reg_32(&st->adis,
653 adis16475_calib_regs[chan->scan_index],
654 val);
655 default:
656 return -EINVAL;
657 }
658 }
659
660 #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \
661 { \
662 .type = (_type), \
663 .modified = 1, \
664 .channel2 = (_mod), \
665 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
666 BIT(IIO_CHAN_INFO_CALIBBIAS), \
667 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
668 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
669 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
670 .address = (_address), \
671 .scan_index = (_si), \
672 .scan_type = { \
673 .sign = 's', \
674 .realbits = (_r_bits), \
675 .storagebits = (_s_bits), \
676 .endianness = IIO_BE, \
677 }, \
678 }
679
680 #define ADIS16475_GYRO_CHANNEL(_mod) \
681 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
682 ADIS16475_REG_ ## _mod ## _GYRO_L, \
683 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32)
684
685 #define ADIS16475_ACCEL_CHANNEL(_mod) \
686 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \
687 ADIS16475_REG_ ## _mod ## _ACCEL_L, \
688 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32)
689
690 #define ADIS16475_TEMP_CHANNEL() { \
691 .type = IIO_TEMP, \
692 .indexed = 1, \
693 .channel = 0, \
694 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
695 BIT(IIO_CHAN_INFO_SCALE), \
696 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
697 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
698 .address = ADIS16475_REG_TEMP_OUT, \
699 .scan_index = ADIS16475_SCAN_TEMP, \
700 .scan_type = { \
701 .sign = 's', \
702 .realbits = 16, \
703 .storagebits = 16, \
704 .endianness = IIO_BE, \
705 }, \
706 }
707
708 #define ADIS16475_MOD_CHAN_DELTA(_type, _mod, _address, _si, _r_bits, _s_bits) { \
709 .type = (_type), \
710 .modified = 1, \
711 .channel2 = (_mod), \
712 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
713 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
714 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
715 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
716 .address = (_address), \
717 .scan_index = _si, \
718 .scan_type = { \
719 .sign = 's', \
720 .realbits = (_r_bits), \
721 .storagebits = (_s_bits), \
722 .endianness = IIO_BE, \
723 }, \
724 }
725
726 #define ADIS16475_DELTANG_CHAN(_mod) \
727 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
728 ADIS16475_REG_ ## _mod ## _DELTANG_L, ADIS16475_SCAN_DELTANG_ ## _mod, 32, 32)
729
730 #define ADIS16475_DELTVEL_CHAN(_mod) \
731 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
732 ADIS16475_REG_ ## _mod ## _DELTVEL_L, ADIS16475_SCAN_DELTVEL_ ## _mod, 32, 32)
733
734 #define ADIS16475_DELTANG_CHAN_NO_SCAN(_mod) \
735 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \
736 ADIS16475_REG_ ## _mod ## _DELTANG_L, -1, 32, 32)
737
738 #define ADIS16475_DELTVEL_CHAN_NO_SCAN(_mod) \
739 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \
740 ADIS16475_REG_ ## _mod ## _DELTVEL_L, -1, 32, 32)
741
742 static const struct iio_chan_spec adis16477_channels[] = {
743 ADIS16475_GYRO_CHANNEL(X),
744 ADIS16475_GYRO_CHANNEL(Y),
745 ADIS16475_GYRO_CHANNEL(Z),
746 ADIS16475_ACCEL_CHANNEL(X),
747 ADIS16475_ACCEL_CHANNEL(Y),
748 ADIS16475_ACCEL_CHANNEL(Z),
749 ADIS16475_TEMP_CHANNEL(),
750 ADIS16475_DELTANG_CHAN(X),
751 ADIS16475_DELTANG_CHAN(Y),
752 ADIS16475_DELTANG_CHAN(Z),
753 ADIS16475_DELTVEL_CHAN(X),
754 ADIS16475_DELTVEL_CHAN(Y),
755 ADIS16475_DELTVEL_CHAN(Z),
756 IIO_CHAN_SOFT_TIMESTAMP(13)
757 };
758
759 static const struct iio_chan_spec adis16475_channels[] = {
760 ADIS16475_GYRO_CHANNEL(X),
761 ADIS16475_GYRO_CHANNEL(Y),
762 ADIS16475_GYRO_CHANNEL(Z),
763 ADIS16475_ACCEL_CHANNEL(X),
764 ADIS16475_ACCEL_CHANNEL(Y),
765 ADIS16475_ACCEL_CHANNEL(Z),
766 ADIS16475_TEMP_CHANNEL(),
767 ADIS16475_DELTANG_CHAN_NO_SCAN(X),
768 ADIS16475_DELTANG_CHAN_NO_SCAN(Y),
769 ADIS16475_DELTANG_CHAN_NO_SCAN(Z),
770 ADIS16475_DELTVEL_CHAN_NO_SCAN(X),
771 ADIS16475_DELTVEL_CHAN_NO_SCAN(Y),
772 ADIS16475_DELTVEL_CHAN_NO_SCAN(Z),
773 IIO_CHAN_SOFT_TIMESTAMP(7)
774 };
775
776 static const struct iio_chan_spec adis16575_channels[] = {
777 ADIS16475_GYRO_CHANNEL(X),
778 ADIS16475_GYRO_CHANNEL(Y),
779 ADIS16475_GYRO_CHANNEL(Z),
780 ADIS16475_ACCEL_CHANNEL(X),
781 ADIS16475_ACCEL_CHANNEL(Y),
782 ADIS16475_ACCEL_CHANNEL(Z),
783 ADIS16475_TEMP_CHANNEL(),
784 ADIS16475_DELTANG_CHAN(X),
785 ADIS16475_DELTANG_CHAN(Y),
786 ADIS16475_DELTANG_CHAN(Z),
787 ADIS16475_DELTVEL_CHAN(X),
788 ADIS16475_DELTVEL_CHAN(Y),
789 ADIS16475_DELTVEL_CHAN(Z),
790 };
791
792 enum adis16475_variant {
793 ADIS16470,
794 ADIS16475_1,
795 ADIS16475_2,
796 ADIS16475_3,
797 ADIS16477_1,
798 ADIS16477_2,
799 ADIS16477_3,
800 ADIS16465_1,
801 ADIS16465_2,
802 ADIS16465_3,
803 ADIS16467_1,
804 ADIS16467_2,
805 ADIS16467_3,
806 ADIS16500,
807 ADIS16501,
808 ADIS16505_1,
809 ADIS16505_2,
810 ADIS16505_3,
811 ADIS16507_1,
812 ADIS16507_2,
813 ADIS16507_3,
814 ADIS16575_2,
815 ADIS16575_3,
816 ADIS16576_2,
817 ADIS16576_3,
818 ADIS16577_2,
819 ADIS16577_3,
820 };
821
822 enum {
823 ADIS16475_DIAG_STAT_DATA_PATH = 1,
824 ADIS16475_DIAG_STAT_FLASH_MEM,
825 ADIS16475_DIAG_STAT_SPI,
826 ADIS16475_DIAG_STAT_STANDBY,
827 ADIS16475_DIAG_STAT_SENSOR,
828 ADIS16475_DIAG_STAT_MEMORY,
829 ADIS16475_DIAG_STAT_CLK,
830 };
831
832 static const char * const adis16475_status_error_msgs[] = {
833 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun",
834 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure",
835 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error",
836 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode",
837 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure",
838 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure",
839 [ADIS16475_DIAG_STAT_CLK] = "Clock error",
840 };
841
842 #define ADIS16475_DATA(_prod_id, _timeouts, _burst_max_len, _burst_max_speed_hz, _has_fifo) \
843 { \
844 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \
845 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \
846 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \
847 .prod_id_reg = ADIS16475_REG_PROD_ID, \
848 .prod_id = (_prod_id), \
849 .self_test_mask = BIT(2), \
850 .self_test_reg = ADIS16475_REG_GLOB_CMD, \
851 .cs_change_delay = 16, \
852 .read_delay = 5, \
853 .write_delay = 5, \
854 .status_error_msgs = adis16475_status_error_msgs, \
855 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \
856 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \
857 BIT(ADIS16475_DIAG_STAT_SPI) | \
858 BIT(ADIS16475_DIAG_STAT_STANDBY) | \
859 BIT(ADIS16475_DIAG_STAT_SENSOR) | \
860 BIT(ADIS16475_DIAG_STAT_MEMORY) | \
861 BIT(ADIS16475_DIAG_STAT_CLK), \
862 .unmasked_drdy = true, \
863 .has_fifo = _has_fifo, \
864 .timeouts = (_timeouts), \
865 .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \
866 .burst_len = ADIS16475_BURST_MAX_DATA, \
867 .burst_max_len = _burst_max_len, \
868 .burst_max_speed_hz = _burst_max_speed_hz \
869 }
870
871 static const struct adis16475_sync adis16475_sync_mode[] = {
872 { ADIS16475_SYNC_OUTPUT },
873 { ADIS16475_SYNC_DIRECT, 1900, 2100 },
874 { ADIS16475_SYNC_SCALED, 1, 128 },
875 { ADIS16475_SYNC_PULSE, 1000, 2100 },
876 };
877
878 static const struct adis16475_sync adis16575_sync_mode[] = {
879 { ADIS16475_SYNC_OUTPUT },
880 { ADIS16475_SYNC_DIRECT, 1900, 4100 },
881 { ADIS16475_SYNC_SCALED, 1, 400 },
882 };
883
884 static const struct adis_timeout adis16475_timeouts = {
885 .reset_ms = 200,
886 .sw_reset_ms = 200,
887 .self_test_ms = 20,
888 };
889
890 static const struct adis_timeout adis1650x_timeouts = {
891 .reset_ms = 260,
892 .sw_reset_ms = 260,
893 .self_test_ms = 30,
894 };
895
896 static const struct adis16475_chip_info adis16475_chip_info[] = {
897 [ADIS16470] = {
898 .name = "adis16470",
899 .num_channels = ARRAY_SIZE(adis16475_channels),
900 .channels = adis16475_channels,
901 .gyro_max_val = 1,
902 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
903 .accel_max_val = 1,
904 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
905 .temp_scale = 100,
906 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
907 .deltvel_max_val = 400,
908 .int_clk = 2000,
909 .max_dec = 1999,
910 .sync = adis16475_sync_mode,
911 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
912 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts,
913 ADIS16475_BURST32_MAX_DATA_NO_TS32,
914 ADIS16475_BURST_MAX_SPEED, false),
915 },
916 [ADIS16475_1] = {
917 .name = "adis16475-1",
918 .num_channels = ARRAY_SIZE(adis16475_channels),
919 .channels = adis16475_channels,
920 .gyro_max_val = 1,
921 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
922 .accel_max_val = 1,
923 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
924 .temp_scale = 100,
925 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
926 .deltvel_max_val = 100,
927 .int_clk = 2000,
928 .max_dec = 1999,
929 .sync = adis16475_sync_mode,
930 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
931 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts,
932 ADIS16475_BURST32_MAX_DATA_NO_TS32,
933 ADIS16475_BURST_MAX_SPEED, false),
934 },
935 [ADIS16475_2] = {
936 .name = "adis16475-2",
937 .num_channels = ARRAY_SIZE(adis16475_channels),
938 .channels = adis16475_channels,
939 .gyro_max_val = 1,
940 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
941 .accel_max_val = 1,
942 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
943 .temp_scale = 100,
944 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
945 .deltvel_max_val = 100,
946 .int_clk = 2000,
947 .max_dec = 1999,
948 .sync = adis16475_sync_mode,
949 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
950 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts,
951 ADIS16475_BURST32_MAX_DATA_NO_TS32,
952 ADIS16475_BURST_MAX_SPEED, false),
953 },
954 [ADIS16475_3] = {
955 .name = "adis16475-3",
956 .num_channels = ARRAY_SIZE(adis16475_channels),
957 .channels = adis16475_channels,
958 .gyro_max_val = 1,
959 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
960 .accel_max_val = 1,
961 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
962 .temp_scale = 100,
963 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
964 .deltvel_max_val = 100,
965 .int_clk = 2000,
966 .max_dec = 1999,
967 .sync = adis16475_sync_mode,
968 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
969 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts,
970 ADIS16475_BURST32_MAX_DATA_NO_TS32,
971 ADIS16475_BURST_MAX_SPEED, false),
972 },
973 [ADIS16477_1] = {
974 .name = "adis16477-1",
975 .num_channels = ARRAY_SIZE(adis16477_channels),
976 .channels = adis16477_channels,
977 .gyro_max_val = 1,
978 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
979 .accel_max_val = 1,
980 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
981 .temp_scale = 100,
982 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
983 .deltvel_max_val = 400,
984 .int_clk = 2000,
985 .max_dec = 1999,
986 .sync = adis16475_sync_mode,
987 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
988 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
989 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts,
990 ADIS16475_BURST32_MAX_DATA_NO_TS32,
991 ADIS16475_BURST_MAX_SPEED, false),
992 },
993 [ADIS16477_2] = {
994 .name = "adis16477-2",
995 .num_channels = ARRAY_SIZE(adis16477_channels),
996 .channels = adis16477_channels,
997 .gyro_max_val = 1,
998 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
999 .accel_max_val = 1,
1000 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
1001 .temp_scale = 100,
1002 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1003 .deltvel_max_val = 400,
1004 .int_clk = 2000,
1005 .max_dec = 1999,
1006 .sync = adis16475_sync_mode,
1007 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1008 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1009 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts,
1010 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1011 ADIS16475_BURST_MAX_SPEED, false),
1012 },
1013 [ADIS16477_3] = {
1014 .name = "adis16477-3",
1015 .num_channels = ARRAY_SIZE(adis16477_channels),
1016 .channels = adis16477_channels,
1017 .gyro_max_val = 1,
1018 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1019 .accel_max_val = 1,
1020 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
1021 .temp_scale = 100,
1022 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1023 .deltvel_max_val = 400,
1024 .int_clk = 2000,
1025 .max_dec = 1999,
1026 .sync = adis16475_sync_mode,
1027 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1028 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1029 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts,
1030 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1031 ADIS16475_BURST_MAX_SPEED, false),
1032 },
1033 [ADIS16465_1] = {
1034 .name = "adis16465-1",
1035 .num_channels = ARRAY_SIZE(adis16475_channels),
1036 .channels = adis16475_channels,
1037 .gyro_max_val = 1,
1038 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
1039 .accel_max_val = 1,
1040 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
1041 .temp_scale = 100,
1042 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1043 .deltvel_max_val = 100,
1044 .int_clk = 2000,
1045 .max_dec = 1999,
1046 .sync = adis16475_sync_mode,
1047 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1048 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts,
1049 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1050 ADIS16475_BURST_MAX_SPEED, false),
1051 },
1052 [ADIS16465_2] = {
1053 .name = "adis16465-2",
1054 .num_channels = ARRAY_SIZE(adis16475_channels),
1055 .channels = adis16475_channels,
1056 .gyro_max_val = 1,
1057 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1058 .accel_max_val = 1,
1059 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
1060 .temp_scale = 100,
1061 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1062 .deltvel_max_val = 100,
1063 .int_clk = 2000,
1064 .max_dec = 1999,
1065 .sync = adis16475_sync_mode,
1066 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1067 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts,
1068 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1069 ADIS16475_BURST_MAX_SPEED, false),
1070 },
1071 [ADIS16465_3] = {
1072 .name = "adis16465-3",
1073 .num_channels = ARRAY_SIZE(adis16475_channels),
1074 .channels = adis16475_channels,
1075 .gyro_max_val = 1,
1076 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1077 .accel_max_val = 1,
1078 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
1079 .temp_scale = 100,
1080 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1081 .deltvel_max_val = 100,
1082 .int_clk = 2000,
1083 .max_dec = 1999,
1084 .sync = adis16475_sync_mode,
1085 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1086 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts,
1087 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1088 ADIS16475_BURST_MAX_SPEED, false),
1089 },
1090 [ADIS16467_1] = {
1091 .name = "adis16467-1",
1092 .num_channels = ARRAY_SIZE(adis16475_channels),
1093 .channels = adis16475_channels,
1094 .gyro_max_val = 1,
1095 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
1096 .accel_max_val = 1,
1097 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
1098 .temp_scale = 100,
1099 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1100 .deltvel_max_val = 400,
1101 .int_clk = 2000,
1102 .max_dec = 1999,
1103 .sync = adis16475_sync_mode,
1104 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1105 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts,
1106 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1107 ADIS16475_BURST_MAX_SPEED, false),
1108 },
1109 [ADIS16467_2] = {
1110 .name = "adis16467-2",
1111 .num_channels = ARRAY_SIZE(adis16475_channels),
1112 .channels = adis16475_channels,
1113 .gyro_max_val = 1,
1114 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1115 .accel_max_val = 1,
1116 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
1117 .temp_scale = 100,
1118 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1119 .deltvel_max_val = 400,
1120 .int_clk = 2000,
1121 .max_dec = 1999,
1122 .sync = adis16475_sync_mode,
1123 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1124 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts,
1125 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1126 ADIS16475_BURST_MAX_SPEED, false),
1127 },
1128 [ADIS16467_3] = {
1129 .name = "adis16467-3",
1130 .num_channels = ARRAY_SIZE(adis16475_channels),
1131 .channels = adis16475_channels,
1132 .gyro_max_val = 1,
1133 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1134 .accel_max_val = 1,
1135 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
1136 .temp_scale = 100,
1137 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1138 .deltvel_max_val = 400,
1139 .int_clk = 2000,
1140 .max_dec = 1999,
1141 .sync = adis16475_sync_mode,
1142 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
1143 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts,
1144 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1145 ADIS16475_BURST_MAX_SPEED, false),
1146 },
1147 [ADIS16500] = {
1148 .name = "adis16500",
1149 .num_channels = ARRAY_SIZE(adis16477_channels),
1150 .channels = adis16477_channels,
1151 .gyro_max_val = 1,
1152 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1153 .accel_max_val = 392,
1154 .accel_max_scale = 32000 << 16,
1155 .temp_scale = 100,
1156 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1157 .deltvel_max_val = 400,
1158 .int_clk = 2000,
1159 .max_dec = 1999,
1160 .sync = adis16475_sync_mode,
1161 /* pulse sync not supported */
1162 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1163 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1164 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts,
1165 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1166 ADIS16475_BURST_MAX_SPEED, false),
1167 },
1168 [ADIS16501] = {
1169 .name = "adis16501",
1170 .num_channels = ARRAY_SIZE(adis16477_channels),
1171 .channels = adis16477_channels,
1172 .gyro_max_val = 1,
1173 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1174 .accel_max_val = 1,
1175 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
1176 .temp_scale = 100,
1177 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1178 .deltvel_max_val = 125,
1179 .int_clk = 2000,
1180 .max_dec = 1999,
1181 .sync = adis16475_sync_mode,
1182 /* pulse sync not supported */
1183 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1184 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1185 .adis_data = ADIS16475_DATA(16501, &adis1650x_timeouts,
1186 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1187 ADIS16475_BURST_MAX_SPEED, false),
1188 },
1189 [ADIS16505_1] = {
1190 .name = "adis16505-1",
1191 .num_channels = ARRAY_SIZE(adis16477_channels),
1192 .channels = adis16477_channels,
1193 .gyro_max_val = 1,
1194 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
1195 .accel_max_val = 78,
1196 .accel_max_scale = 32000 << 16,
1197 .temp_scale = 100,
1198 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1199 .deltvel_max_val = 100,
1200 .int_clk = 2000,
1201 .max_dec = 1999,
1202 .sync = adis16475_sync_mode,
1203 /* pulse sync not supported */
1204 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1205 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1206 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts,
1207 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1208 ADIS16475_BURST_MAX_SPEED, false),
1209 },
1210 [ADIS16505_2] = {
1211 .name = "adis16505-2",
1212 .num_channels = ARRAY_SIZE(adis16477_channels),
1213 .channels = adis16477_channels,
1214 .gyro_max_val = 1,
1215 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1216 .accel_max_val = 78,
1217 .accel_max_scale = 32000 << 16,
1218 .temp_scale = 100,
1219 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1220 .deltvel_max_val = 100,
1221 .int_clk = 2000,
1222 .max_dec = 1999,
1223 .sync = adis16475_sync_mode,
1224 /* pulse sync not supported */
1225 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1226 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1227 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts,
1228 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1229 ADIS16475_BURST_MAX_SPEED, false),
1230 },
1231 [ADIS16505_3] = {
1232 .name = "adis16505-3",
1233 .num_channels = ARRAY_SIZE(adis16477_channels),
1234 .channels = adis16477_channels,
1235 .gyro_max_val = 1,
1236 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1237 .accel_max_val = 78,
1238 .accel_max_scale = 32000 << 16,
1239 .temp_scale = 100,
1240 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1241 .deltvel_max_val = 100,
1242 .int_clk = 2000,
1243 .max_dec = 1999,
1244 .sync = adis16475_sync_mode,
1245 /* pulse sync not supported */
1246 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1247 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1248 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts,
1249 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1250 ADIS16475_BURST_MAX_SPEED, false),
1251 },
1252 [ADIS16507_1] = {
1253 .name = "adis16507-1",
1254 .num_channels = ARRAY_SIZE(adis16477_channels),
1255 .channels = adis16477_channels,
1256 .gyro_max_val = 1,
1257 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
1258 .accel_max_val = 392,
1259 .accel_max_scale = 32000 << 16,
1260 .temp_scale = 100,
1261 .deltang_max_val = IIO_DEGREE_TO_RAD(360),
1262 .deltvel_max_val = 400,
1263 .int_clk = 2000,
1264 .max_dec = 1999,
1265 .sync = adis16475_sync_mode,
1266 /* pulse sync not supported */
1267 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1268 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1269 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts,
1270 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1271 ADIS16475_BURST_MAX_SPEED, false),
1272 },
1273 [ADIS16507_2] = {
1274 .name = "adis16507-2",
1275 .num_channels = ARRAY_SIZE(adis16477_channels),
1276 .channels = adis16477_channels,
1277 .gyro_max_val = 1,
1278 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1279 .accel_max_val = 392,
1280 .accel_max_scale = 32000 << 16,
1281 .temp_scale = 100,
1282 .deltang_max_val = IIO_DEGREE_TO_RAD(720),
1283 .deltvel_max_val = 400,
1284 .int_clk = 2000,
1285 .max_dec = 1999,
1286 .sync = adis16475_sync_mode,
1287 /* pulse sync not supported */
1288 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1289 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1290 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts,
1291 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1292 ADIS16475_BURST_MAX_SPEED, false),
1293 },
1294 [ADIS16507_3] = {
1295 .name = "adis16507-3",
1296 .num_channels = ARRAY_SIZE(adis16477_channels),
1297 .channels = adis16477_channels,
1298 .gyro_max_val = 1,
1299 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1300 .accel_max_val = 392,
1301 .accel_max_scale = 32000 << 16,
1302 .temp_scale = 100,
1303 .deltang_max_val = IIO_DEGREE_TO_RAD(2160),
1304 .deltvel_max_val = 400,
1305 .int_clk = 2000,
1306 .max_dec = 1999,
1307 .sync = adis16475_sync_mode,
1308 /* pulse sync not supported */
1309 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
1310 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA,
1311 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts,
1312 ADIS16475_BURST32_MAX_DATA_NO_TS32,
1313 ADIS16475_BURST_MAX_SPEED, false),
1314 },
1315 [ADIS16575_2] = {
1316 .name = "adis16575-2",
1317 .num_channels = ARRAY_SIZE(adis16575_channels),
1318 .channels = adis16575_channels,
1319 .gyro_max_val = 1,
1320 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1321 .accel_max_val = 8,
1322 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
1323 .temp_scale = 100,
1324 .deltang_max_val = IIO_DEGREE_TO_RAD(450),
1325 .deltvel_max_val = 100,
1326 .int_clk = 4000,
1327 .max_dec = 3999,
1328 .sync = adis16575_sync_mode,
1329 .num_sync = ARRAY_SIZE(adis16575_sync_mode),
1330 .flags = ADIS16475_HAS_BURST32 |
1331 ADIS16475_HAS_BURST_DELTA_DATA |
1332 ADIS16475_NEEDS_BURST_REQUEST |
1333 ADIS16475_HAS_TIMESTAMP32,
1334 .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts,
1335 ADIS16575_BURST32_DATA_TS32,
1336 ADIS16575_BURST_MAX_SPEED, true),
1337 },
1338 [ADIS16575_3] = {
1339 .name = "adis16575-3",
1340 .num_channels = ARRAY_SIZE(adis16575_channels),
1341 .channels = adis16575_channels,
1342 .gyro_max_val = 1,
1343 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1344 .accel_max_val = 8,
1345 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
1346 .temp_scale = 100,
1347 .deltang_max_val = IIO_DEGREE_TO_RAD(2000),
1348 .deltvel_max_val = 100,
1349 .int_clk = 4000,
1350 .max_dec = 3999,
1351 .sync = adis16575_sync_mode,
1352 .num_sync = ARRAY_SIZE(adis16575_sync_mode),
1353 .flags = ADIS16475_HAS_BURST32 |
1354 ADIS16475_HAS_BURST_DELTA_DATA |
1355 ADIS16475_NEEDS_BURST_REQUEST |
1356 ADIS16475_HAS_TIMESTAMP32,
1357 .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts,
1358 ADIS16575_BURST32_DATA_TS32,
1359 ADIS16575_BURST_MAX_SPEED, true),
1360 },
1361 [ADIS16576_2] = {
1362 .name = "adis16576-2",
1363 .num_channels = ARRAY_SIZE(adis16575_channels),
1364 .channels = adis16575_channels,
1365 .gyro_max_val = 1,
1366 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1367 .accel_max_val = 40,
1368 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
1369 .temp_scale = 100,
1370 .deltang_max_val = IIO_DEGREE_TO_RAD(450),
1371 .deltvel_max_val = 125,
1372 .int_clk = 4000,
1373 .max_dec = 3999,
1374 .sync = adis16575_sync_mode,
1375 .num_sync = ARRAY_SIZE(adis16575_sync_mode),
1376 .flags = ADIS16475_HAS_BURST32 |
1377 ADIS16475_HAS_BURST_DELTA_DATA |
1378 ADIS16475_NEEDS_BURST_REQUEST |
1379 ADIS16475_HAS_TIMESTAMP32,
1380 .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts,
1381 ADIS16575_BURST32_DATA_TS32,
1382 ADIS16575_BURST_MAX_SPEED, true),
1383 },
1384 [ADIS16576_3] = {
1385 .name = "adis16576-3",
1386 .num_channels = ARRAY_SIZE(adis16575_channels),
1387 .channels = adis16575_channels,
1388 .gyro_max_val = 1,
1389 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1390 .accel_max_val = 40,
1391 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
1392 .temp_scale = 100,
1393 .deltang_max_val = IIO_DEGREE_TO_RAD(2000),
1394 .deltvel_max_val = 125,
1395 .int_clk = 4000,
1396 .max_dec = 3999,
1397 .sync = adis16575_sync_mode,
1398 .num_sync = ARRAY_SIZE(adis16575_sync_mode),
1399 .flags = ADIS16475_HAS_BURST32 |
1400 ADIS16475_HAS_BURST_DELTA_DATA |
1401 ADIS16475_NEEDS_BURST_REQUEST |
1402 ADIS16475_HAS_TIMESTAMP32,
1403 .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts,
1404 ADIS16575_BURST32_DATA_TS32,
1405 ADIS16575_BURST_MAX_SPEED, true),
1406 },
1407 [ADIS16577_2] = {
1408 .name = "adis16577-2",
1409 .num_channels = ARRAY_SIZE(adis16575_channels),
1410 .channels = adis16575_channels,
1411 .gyro_max_val = 1,
1412 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
1413 .accel_max_val = 40,
1414 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
1415 .temp_scale = 100,
1416 .deltang_max_val = IIO_DEGREE_TO_RAD(450),
1417 .deltvel_max_val = 400,
1418 .int_clk = 4000,
1419 .max_dec = 3999,
1420 .sync = adis16575_sync_mode,
1421 .num_sync = ARRAY_SIZE(adis16575_sync_mode),
1422 .flags = ADIS16475_HAS_BURST32 |
1423 ADIS16475_HAS_BURST_DELTA_DATA |
1424 ADIS16475_NEEDS_BURST_REQUEST |
1425 ADIS16475_HAS_TIMESTAMP32,
1426 .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts,
1427 ADIS16575_BURST32_DATA_TS32,
1428 ADIS16575_BURST_MAX_SPEED, true),
1429 },
1430 [ADIS16577_3] = {
1431 .name = "adis16577-3",
1432 .num_channels = ARRAY_SIZE(adis16575_channels),
1433 .channels = adis16575_channels,
1434 .gyro_max_val = 1,
1435 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
1436 .accel_max_val = 40,
1437 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16),
1438 .temp_scale = 100,
1439 .deltang_max_val = IIO_DEGREE_TO_RAD(2000),
1440 .deltvel_max_val = 400,
1441 .int_clk = 4000,
1442 .max_dec = 3999,
1443 .sync = adis16575_sync_mode,
1444 .num_sync = ARRAY_SIZE(adis16575_sync_mode),
1445 .flags = ADIS16475_HAS_BURST32 |
1446 ADIS16475_HAS_BURST_DELTA_DATA |
1447 ADIS16475_NEEDS_BURST_REQUEST |
1448 ADIS16475_HAS_TIMESTAMP32,
1449 .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts,
1450 ADIS16575_BURST32_DATA_TS32,
1451 ADIS16575_BURST_MAX_SPEED, true),
1452 },
1453 };
1454
adis16475_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1455 static int adis16475_update_scan_mode(struct iio_dev *indio_dev,
1456 const unsigned long *scan_mask)
1457 {
1458 u16 en;
1459 int ret;
1460 struct adis16475 *st = iio_priv(indio_dev);
1461
1462 if (st->info->flags & ADIS16475_HAS_BURST_DELTA_DATA) {
1463 if ((*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) &&
1464 (*scan_mask & ADIS16500_BURST_DATA_SEL_1_CHN_MASK))
1465 return -EINVAL;
1466 if (*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK)
1467 en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 0);
1468 else
1469 en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 1);
1470
1471 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1472 ADIS16500_BURST_DATA_SEL_MASK, en);
1473 if (ret)
1474 return ret;
1475 }
1476
1477 return adis_update_scan_mode(indio_dev, scan_mask);
1478 }
1479
1480 static const struct iio_info adis16475_info = {
1481 .read_raw = &adis16475_read_raw,
1482 .write_raw = &adis16475_write_raw,
1483 .update_scan_mode = adis16475_update_scan_mode,
1484 .debugfs_reg_access = adis_debugfs_reg_access,
1485 };
1486
1487 static const struct iio_info adis16575_info = {
1488 .read_raw = &adis16475_read_raw,
1489 .write_raw = &adis16475_write_raw,
1490 .update_scan_mode = adis16475_update_scan_mode,
1491 .debugfs_reg_access = adis_debugfs_reg_access,
1492 .hwfifo_set_watermark = adis16475_set_watermark,
1493 };
1494
adis16475_validate_crc(const u8 * buffer,u16 crc,u16 burst_size,u16 start_idx)1495 static bool adis16475_validate_crc(const u8 *buffer, u16 crc,
1496 u16 burst_size, u16 start_idx)
1497 {
1498 int i;
1499
1500 for (i = start_idx; i < burst_size - 2; i++)
1501 crc -= buffer[i];
1502
1503 return crc == 0;
1504 }
1505
adis16475_burst32_check(struct adis16475 * st)1506 static void adis16475_burst32_check(struct adis16475 *st)
1507 {
1508 int ret;
1509 struct adis *adis = &st->adis;
1510 u8 timestamp32 = 0;
1511
1512 if (!(st->info->flags & ADIS16475_HAS_BURST32))
1513 return;
1514
1515 if (st->info->flags & ADIS16475_HAS_TIMESTAMP32)
1516 timestamp32 = 1;
1517
1518 if (st->lsb_flag && !st->burst32) {
1519 const u16 en = ADIS16500_BURST32(1);
1520
1521 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1522 ADIS16500_BURST32_MASK, en);
1523 if (ret)
1524 return;
1525
1526 st->burst32 = true;
1527
1528 /*
1529 * In 32-bit mode we need extra 2 bytes for all gyro
1530 * and accel channels.
1531 * If the device has 32-bit timestamp value we need 2 extra
1532 * bytes for it.
1533 */
1534 adis->burst_extra_len = (6 + timestamp32) * sizeof(u16);
1535 adis->xfer[1].len += (6 + timestamp32) * sizeof(u16);
1536
1537 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d",
1538 adis->xfer[1].len);
1539
1540 } else if (!st->lsb_flag && st->burst32) {
1541 const u16 en = ADIS16500_BURST32(0);
1542
1543 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1544 ADIS16500_BURST32_MASK, en);
1545 if (ret)
1546 return;
1547
1548 st->burst32 = false;
1549
1550 /* Remove the extra bits */
1551 adis->burst_extra_len = 0;
1552 adis->xfer[1].len -= (6 + timestamp32) * sizeof(u16);
1553 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n",
1554 adis->xfer[1].len);
1555 }
1556 }
1557
adis16475_push_single_sample(struct iio_poll_func * pf)1558 static int adis16475_push_single_sample(struct iio_poll_func *pf)
1559 {
1560 struct iio_dev *indio_dev = pf->indio_dev;
1561 struct adis16475 *st = iio_priv(indio_dev);
1562 struct adis *adis = &st->adis;
1563 int ret, bit, buff_offset = 0, i = 0;
1564 __be16 *buffer;
1565 u16 crc;
1566 bool valid;
1567 u8 crc_offset = 9;
1568 u16 burst_size = ADIS16475_BURST_MAX_DATA;
1569 u16 start_idx = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 2 : 0;
1570
1571 /* offset until the first element after gyro and accel */
1572 const u8 offset = st->burst32 ? 13 : 7;
1573
1574 if (st->burst32) {
1575 crc_offset = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 16 : 15;
1576 burst_size = adis->data->burst_max_len;
1577 }
1578
1579 ret = spi_sync(adis->spi, &adis->msg);
1580 if (ret)
1581 return ret;
1582
1583 buffer = adis->buffer;
1584
1585 crc = be16_to_cpu(buffer[crc_offset]);
1586 valid = adis16475_validate_crc(adis->buffer, crc, burst_size, start_idx);
1587 if (!valid) {
1588 dev_err(&adis->spi->dev, "Invalid crc\n");
1589 return -EINVAL;
1590 }
1591
1592 iio_for_each_active_channel(indio_dev, bit) {
1593 /*
1594 * When burst mode is used, system flags is the first data
1595 * channel in the sequence, but the scan index is 7.
1596 */
1597 switch (bit) {
1598 case ADIS16475_SCAN_TEMP:
1599 st->data[i++] = buffer[offset];
1600 /*
1601 * The temperature channel has 16-bit storage size.
1602 * We need to perform the padding to have the buffer
1603 * elements naturally aligned in case there are any
1604 * 32-bit storage size channels enabled which have a
1605 * scan index higher than the temperature channel scan
1606 * index.
1607 */
1608 if (*indio_dev->active_scan_mask & GENMASK(ADIS16475_SCAN_DELTVEL_Z, ADIS16475_SCAN_DELTANG_X))
1609 st->data[i++] = 0;
1610 break;
1611 case ADIS16475_SCAN_DELTANG_X ... ADIS16475_SCAN_DELTVEL_Z:
1612 buff_offset = ADIS16475_SCAN_DELTANG_X;
1613 fallthrough;
1614 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z:
1615 /*
1616 * The first 2 bytes on the received data are the
1617 * DIAG_STAT reg, hence the +1 offset here...
1618 */
1619 if (st->burst32) {
1620 /* upper 16 */
1621 st->data[i++] = buffer[(bit - buff_offset) * 2 + 2];
1622 /* lower 16 */
1623 st->data[i++] = buffer[(bit - buff_offset) * 2 + 1];
1624 } else {
1625 st->data[i++] = buffer[(bit - buff_offset) + 1];
1626 /*
1627 * Don't bother in doing the manual read if the
1628 * device supports burst32. burst32 will be
1629 * enabled in the next call to
1630 * adis16475_burst32_check()...
1631 */
1632 if (st->lsb_flag && !(st->info->flags & ADIS16475_HAS_BURST32)) {
1633 u16 val = 0;
1634 const u32 reg = ADIS16475_REG_X_GYRO_L +
1635 bit * 4;
1636
1637 adis_read_reg_16(adis, reg, &val);
1638 st->data[i++] = cpu_to_be16(val);
1639 } else {
1640 /* lower not used */
1641 st->data[i++] = 0;
1642 }
1643 }
1644 break;
1645 }
1646 }
1647
1648 /* There might not be a timestamp option for some devices. */
1649 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
1650
1651 return 0;
1652 }
1653
adis16475_trigger_handler(int irq,void * p)1654 static irqreturn_t adis16475_trigger_handler(int irq, void *p)
1655 {
1656 struct iio_poll_func *pf = p;
1657 struct iio_dev *indio_dev = pf->indio_dev;
1658 struct adis16475 *st = iio_priv(indio_dev);
1659
1660 adis16475_push_single_sample(pf);
1661 /*
1662 * We only check the burst mode at the end of the current capture since
1663 * it takes a full data ready cycle for the device to update the burst
1664 * array.
1665 */
1666 adis16475_burst32_check(st);
1667
1668 iio_trigger_notify_done(indio_dev->trig);
1669
1670 return IRQ_HANDLED;
1671 }
1672
1673 /*
1674 * This function updates the first tx byte from the adis message based on the
1675 * given burst request.
1676 */
adis16575_update_msg_for_burst(struct adis * adis,u8 burst_req)1677 static void adis16575_update_msg_for_burst(struct adis *adis, u8 burst_req)
1678 {
1679 unsigned int burst_max_length;
1680 u8 *tx;
1681
1682 if (adis->data->burst_max_len)
1683 burst_max_length = adis->data->burst_max_len;
1684 else
1685 burst_max_length = adis->data->burst_len + adis->burst_extra_len;
1686
1687 tx = adis->buffer + burst_max_length;
1688 tx[0] = ADIS_READ_REG(burst_req);
1689 }
1690
adis16575_custom_burst_read(struct iio_poll_func * pf,u8 burst_req)1691 static int adis16575_custom_burst_read(struct iio_poll_func *pf, u8 burst_req)
1692 {
1693 struct iio_dev *indio_dev = pf->indio_dev;
1694 struct adis16475 *st = iio_priv(indio_dev);
1695 struct adis *adis = &st->adis;
1696
1697 adis16575_update_msg_for_burst(adis, burst_req);
1698
1699 if (burst_req)
1700 return spi_sync(adis->spi, &adis->msg);
1701
1702 return adis16475_push_single_sample(pf);
1703 }
1704
1705 /*
1706 * This handler is meant to be used for devices which support burst readings
1707 * from FIFO (namely devices from adis1657x family).
1708 * In order to pop the FIFO the 0x68 0x00 FIFO pop burst request has to be sent.
1709 * If the previous device command was not a FIFO pop burst request, the FIFO pop
1710 * burst request will simply pop the FIFO without returning valid data.
1711 * For the nth consecutive burst request, thedevice will send the data popped
1712 * with the (n-1)th consecutive burst request.
1713 * In order to read the data which was popped previously, without popping the
1714 * FIFO, the 0x00 0x00 burst request has to be sent.
1715 * If after a 0x68 0x00 FIFO pop burst request, there is any other device access
1716 * different from a 0x68 0x00 or a 0x00 0x00 burst request, the FIFO data popped
1717 * previously will be lost.
1718 */
adis16475_trigger_handler_with_fifo(int irq,void * p)1719 static irqreturn_t adis16475_trigger_handler_with_fifo(int irq, void *p)
1720 {
1721 struct iio_poll_func *pf = p;
1722 struct iio_dev *indio_dev = pf->indio_dev;
1723 struct adis16475 *st = iio_priv(indio_dev);
1724 struct adis *adis = &st->adis;
1725 int ret;
1726 u16 fifo_cnt, i;
1727
1728 adis_dev_auto_lock(&st->adis);
1729
1730 ret = __adis_read_reg_16(adis, ADIS16575_REG_FIFO_CNT, &fifo_cnt);
1731 if (ret)
1732 goto unlock;
1733
1734 /*
1735 * If no sample is available, nothing can be read. This can happen if
1736 * a the used trigger has a higher frequency than the selected sample rate.
1737 */
1738 if (!fifo_cnt)
1739 goto unlock;
1740
1741 /*
1742 * First burst request - FIFO pop: popped data will be returned in the
1743 * next burst request.
1744 */
1745 ret = adis16575_custom_burst_read(pf, adis->data->burst_reg_cmd);
1746 if (ret)
1747 goto unlock;
1748
1749 for (i = 0; i < fifo_cnt - 1; i++) {
1750 ret = adis16475_push_single_sample(pf);
1751 if (ret)
1752 goto unlock;
1753 }
1754
1755 /* FIFO read without popping */
1756 ret = adis16575_custom_burst_read(pf, 0);
1757
1758 unlock:
1759 /*
1760 * We only check the burst mode at the end of the current capture since
1761 * reading data from registers will impact the FIFO reading.
1762 */
1763 adis16475_burst32_check(st);
1764 iio_trigger_notify_done(indio_dev->trig);
1765
1766 return IRQ_HANDLED;
1767 }
1768
adis16475_config_sync_mode(struct adis16475 * st)1769 static int adis16475_config_sync_mode(struct adis16475 *st)
1770 {
1771 int ret;
1772 struct device *dev = &st->adis.spi->dev;
1773 const struct adis16475_sync *sync;
1774 u32 sync_mode;
1775 u16 max_sample_rate = st->info->int_clk + 100;
1776 u16 val;
1777
1778 /* if available, enable 4khz internal clock */
1779 if (st->info->int_clk == 4000) {
1780 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1781 ADIS16575_SYNC_4KHZ_MASK,
1782 (u16)ADIS16575_SYNC_4KHZ(1));
1783 if (ret)
1784 return ret;
1785 }
1786
1787 /* default to internal clk */
1788 st->clk_freq = st->info->int_clk * 1000;
1789
1790 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode);
1791 if (ret)
1792 return 0;
1793
1794 if (sync_mode >= st->info->num_sync) {
1795 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode,
1796 st->info->name);
1797 return -EINVAL;
1798 }
1799
1800 sync = &st->info->sync[sync_mode];
1801 st->sync_mode = sync->sync_mode;
1802
1803 /* All the other modes require external input signal */
1804 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) {
1805 struct clk *clk = devm_clk_get_enabled(dev, NULL);
1806
1807 if (IS_ERR(clk))
1808 return PTR_ERR(clk);
1809
1810 st->clk_freq = clk_get_rate(clk);
1811 if (st->clk_freq < sync->min_rate ||
1812 st->clk_freq > sync->max_rate) {
1813 dev_err(dev,
1814 "Clk rate:%u not in a valid range:[%u %u]\n",
1815 st->clk_freq, sync->min_rate, sync->max_rate);
1816 return -EINVAL;
1817 }
1818
1819 if (sync->sync_mode == ADIS16475_SYNC_SCALED) {
1820 u16 up_scale;
1821
1822 /*
1823 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale.
1824 * Hence, default the IMU sample rate to the highest multiple of the input
1825 * clock lower than the IMU max sample rate.
1826 */
1827 up_scale = max_sample_rate / st->clk_freq;
1828
1829 ret = __adis_write_reg_16(&st->adis,
1830 ADIS16475_REG_UP_SCALE,
1831 up_scale);
1832 if (ret)
1833 return ret;
1834 }
1835
1836 st->clk_freq *= 1000;
1837 }
1838 /*
1839 * Keep in mind that the mask for the clk modes in adis1650*
1840 * chips is different (1100 instead of 11100). However, we
1841 * are not configuring BIT(4) in these chips and the default
1842 * value is 0, so we are fine in doing the below operations.
1843 * I'm keeping this for simplicity and avoiding extra variables
1844 * in chip_info.
1845 */
1846 val = ADIS16475_SYNC_MODE(sync->sync_mode);
1847 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1848 ADIS16475_SYNC_MODE_MASK, val);
1849 if (ret)
1850 return ret;
1851
1852 usleep_range(250, 260);
1853
1854 return 0;
1855 }
1856
adis16475_config_irq_pin(struct adis16475 * st)1857 static int adis16475_config_irq_pin(struct adis16475 *st)
1858 {
1859 int ret;
1860 u32 irq_type;
1861 u16 val = 0;
1862 u8 polarity;
1863 struct spi_device *spi = st->adis.spi;
1864
1865 irq_type = irq_get_trigger_type(spi->irq);
1866
1867 if (st->adis.data->has_fifo) {
1868 /*
1869 * It is possible to configure the fifo watermark pin polarity.
1870 * Furthermore, we need to update the adis struct if we want the
1871 * watermark pin active low.
1872 */
1873 if (irq_type == IRQ_TYPE_LEVEL_HIGH) {
1874 polarity = 1;
1875 st->adis.irq_flag = IRQF_TRIGGER_HIGH;
1876 } else if (irq_type == IRQ_TYPE_LEVEL_LOW) {
1877 polarity = 0;
1878 st->adis.irq_flag = IRQF_TRIGGER_LOW;
1879 } else {
1880 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
1881 irq_type);
1882 return -EINVAL;
1883 }
1884
1885 /* Configure the watermark pin polarity. */
1886 val = ADIS16575_WM_POL(polarity);
1887 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL,
1888 ADIS16575_WM_POL_MASK, val);
1889 if (ret)
1890 return ret;
1891
1892 /* Enable watermark interrupt pin. */
1893 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL,
1894 ADIS16575_WM_EN_MASK,
1895 (u16)ADIS16575_WM_EN(1));
1896 if (ret)
1897 return ret;
1898
1899 } else {
1900 /*
1901 * It is possible to configure the data ready polarity. Furthermore, we
1902 * need to update the adis struct if we want data ready as active low.
1903 */
1904 if (irq_type == IRQ_TYPE_EDGE_RISING) {
1905 polarity = 1;
1906 st->adis.irq_flag = IRQF_TRIGGER_RISING;
1907 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
1908 polarity = 0;
1909 st->adis.irq_flag = IRQF_TRIGGER_FALLING;
1910 } else {
1911 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
1912 irq_type);
1913 return -EINVAL;
1914 }
1915
1916 val = ADIS16475_MSG_CTRL_DR_POL(polarity);
1917 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1918 ADIS16475_MSG_CTRL_DR_POL_MASK, val);
1919 if (ret)
1920 return ret;
1921 /*
1922 * There is a delay writing to any bits written to the MSC_CTRL
1923 * register. It should not be bigger than 200us, so 250 should be more
1924 * than enough!
1925 */
1926 usleep_range(250, 260);
1927 }
1928
1929 return 0;
1930 }
1931
adis16475_probe(struct spi_device * spi)1932 static int adis16475_probe(struct spi_device *spi)
1933 {
1934 struct iio_dev *indio_dev;
1935 struct adis16475 *st;
1936 int ret;
1937 u16 val;
1938
1939 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1940 if (!indio_dev)
1941 return -ENOMEM;
1942
1943 st = iio_priv(indio_dev);
1944
1945 st->info = spi_get_device_match_data(spi);
1946 if (!st->info)
1947 return -EINVAL;
1948
1949 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data);
1950 if (ret)
1951 return ret;
1952
1953 indio_dev->name = st->info->name;
1954 indio_dev->channels = st->info->channels;
1955 indio_dev->num_channels = st->info->num_channels;
1956 if (st->adis.data->has_fifo)
1957 indio_dev->info = &adis16575_info;
1958 else
1959 indio_dev->info = &adis16475_info;
1960 indio_dev->modes = INDIO_DIRECT_MODE;
1961
1962 ret = __adis_initial_startup(&st->adis);
1963 if (ret)
1964 return ret;
1965
1966 ret = adis16475_config_irq_pin(st);
1967 if (ret)
1968 return ret;
1969
1970 ret = adis16475_config_sync_mode(st);
1971 if (ret)
1972 return ret;
1973
1974 if (st->adis.data->has_fifo) {
1975 ret = devm_adis_setup_buffer_and_trigger_with_attrs(&st->adis, indio_dev,
1976 adis16475_trigger_handler_with_fifo,
1977 &adis16475_buffer_ops,
1978 adis16475_fifo_attributes);
1979 if (ret)
1980 return ret;
1981
1982 /* Update overflow behavior to always overwrite the oldest sample. */
1983 val = ADIS16575_OVERWRITE_OLDEST;
1984 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL,
1985 ADIS16575_OVERFLOW_MASK, val);
1986 if (ret)
1987 return ret;
1988 } else {
1989 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1990 adis16475_trigger_handler);
1991 if (ret)
1992 return ret;
1993 }
1994
1995 ret = devm_iio_device_register(&spi->dev, indio_dev);
1996 if (ret)
1997 return ret;
1998
1999 adis16475_debugfs_init(indio_dev);
2000
2001 return 0;
2002 }
2003
2004 static const struct of_device_id adis16475_of_match[] = {
2005 { .compatible = "adi,adis16470",
2006 .data = &adis16475_chip_info[ADIS16470] },
2007 { .compatible = "adi,adis16475-1",
2008 .data = &adis16475_chip_info[ADIS16475_1] },
2009 { .compatible = "adi,adis16475-2",
2010 .data = &adis16475_chip_info[ADIS16475_2] },
2011 { .compatible = "adi,adis16475-3",
2012 .data = &adis16475_chip_info[ADIS16475_3] },
2013 { .compatible = "adi,adis16477-1",
2014 .data = &adis16475_chip_info[ADIS16477_1] },
2015 { .compatible = "adi,adis16477-2",
2016 .data = &adis16475_chip_info[ADIS16477_2] },
2017 { .compatible = "adi,adis16477-3",
2018 .data = &adis16475_chip_info[ADIS16477_3] },
2019 { .compatible = "adi,adis16465-1",
2020 .data = &adis16475_chip_info[ADIS16465_1] },
2021 { .compatible = "adi,adis16465-2",
2022 .data = &adis16475_chip_info[ADIS16465_2] },
2023 { .compatible = "adi,adis16465-3",
2024 .data = &adis16475_chip_info[ADIS16465_3] },
2025 { .compatible = "adi,adis16467-1",
2026 .data = &adis16475_chip_info[ADIS16467_1] },
2027 { .compatible = "adi,adis16467-2",
2028 .data = &adis16475_chip_info[ADIS16467_2] },
2029 { .compatible = "adi,adis16467-3",
2030 .data = &adis16475_chip_info[ADIS16467_3] },
2031 { .compatible = "adi,adis16500",
2032 .data = &adis16475_chip_info[ADIS16500] },
2033 { .compatible = "adi,adis16501",
2034 .data = &adis16475_chip_info[ADIS16501] },
2035 { .compatible = "adi,adis16505-1",
2036 .data = &adis16475_chip_info[ADIS16505_1] },
2037 { .compatible = "adi,adis16505-2",
2038 .data = &adis16475_chip_info[ADIS16505_2] },
2039 { .compatible = "adi,adis16505-3",
2040 .data = &adis16475_chip_info[ADIS16505_3] },
2041 { .compatible = "adi,adis16507-1",
2042 .data = &adis16475_chip_info[ADIS16507_1] },
2043 { .compatible = "adi,adis16507-2",
2044 .data = &adis16475_chip_info[ADIS16507_2] },
2045 { .compatible = "adi,adis16507-3",
2046 .data = &adis16475_chip_info[ADIS16507_3] },
2047 { .compatible = "adi,adis16575-2",
2048 .data = &adis16475_chip_info[ADIS16575_2] },
2049 { .compatible = "adi,adis16575-3",
2050 .data = &adis16475_chip_info[ADIS16575_3] },
2051 { .compatible = "adi,adis16576-2",
2052 .data = &adis16475_chip_info[ADIS16576_2] },
2053 { .compatible = "adi,adis16576-3",
2054 .data = &adis16475_chip_info[ADIS16576_3] },
2055 { .compatible = "adi,adis16577-2",
2056 .data = &adis16475_chip_info[ADIS16577_2] },
2057 { .compatible = "adi,adis16577-3",
2058 .data = &adis16475_chip_info[ADIS16577_3] },
2059 { }
2060 };
2061 MODULE_DEVICE_TABLE(of, adis16475_of_match);
2062
2063 static const struct spi_device_id adis16475_ids[] = {
2064 { .name = "adis16470", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16470] },
2065 { .name = "adis16475-1", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16475_1] },
2066 { .name = "adis16475-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16475_2] },
2067 { .name = "adis16475-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16475_3] },
2068 { .name = "adis16477-1", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16477_1] },
2069 { .name = "adis16477-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16477_2] },
2070 { .name = "adis16477-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16477_3] },
2071 { .name = "adis16465-1", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16465_1] },
2072 { .name = "adis16465-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16465_2] },
2073 { .name = "adis16465-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16465_3] },
2074 { .name = "adis16467-1", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16467_1] },
2075 { .name = "adis16467-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16467_2] },
2076 { .name = "adis16467-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16467_3] },
2077 { .name = "adis16500", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16500] },
2078 { .name = "adis16501", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16501] },
2079 { .name = "adis16505-1", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16505_1] },
2080 { .name = "adis16505-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16505_2] },
2081 { .name = "adis16505-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16505_3] },
2082 { .name = "adis16507-1", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16507_1] },
2083 { .name = "adis16507-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16507_2] },
2084 { .name = "adis16507-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16507_3] },
2085 { .name = "adis16575-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16575_2] },
2086 { .name = "adis16575-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16575_3] },
2087 { .name = "adis16576-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16576_2] },
2088 { .name = "adis16576-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16576_3] },
2089 { .name = "adis16577-2", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16577_2] },
2090 { .name = "adis16577-3", .driver_data = (kernel_ulong_t)&adis16475_chip_info[ADIS16577_3] },
2091 { }
2092 };
2093 MODULE_DEVICE_TABLE(spi, adis16475_ids);
2094
2095 static struct spi_driver adis16475_driver = {
2096 .driver = {
2097 .name = "adis16475",
2098 .of_match_table = adis16475_of_match,
2099 },
2100 .probe = adis16475_probe,
2101 .id_table = adis16475_ids,
2102 };
2103 module_spi_driver(adis16475_driver);
2104
2105 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
2106 MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver");
2107 MODULE_LICENSE("GPL");
2108 MODULE_IMPORT_NS("IIO_ADISLIB");
2109