1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/mlx5/driver.h>
34 #include <linux/mlx5/eswitch.h>
35 #include "mlx5_core.h"
36 #include "../../mlxfw/mlxfw.h"
37 #include "lib/tout.h"
38
39 enum {
40 MCQS_IDENTIFIER_BOOT_IMG = 0x1,
41 MCQS_IDENTIFIER_OEM_NVCONFIG = 0x4,
42 MCQS_IDENTIFIER_MLNX_NVCONFIG = 0x5,
43 MCQS_IDENTIFIER_CS_TOKEN = 0x6,
44 MCQS_IDENTIFIER_DBG_TOKEN = 0x7,
45 MCQS_IDENTIFIER_GEARBOX = 0xA,
46 };
47
48 enum {
49 MCQS_UPDATE_STATE_IDLE,
50 MCQS_UPDATE_STATE_IN_PROGRESS,
51 MCQS_UPDATE_STATE_APPLIED,
52 MCQS_UPDATE_STATE_ACTIVE,
53 MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
54 MCQS_UPDATE_STATE_FAILED,
55 MCQS_UPDATE_STATE_CANCELED,
56 MCQS_UPDATE_STATE_BUSY,
57 };
58
59 enum {
60 MCQI_INFO_TYPE_CAPABILITIES = 0x0,
61 MCQI_INFO_TYPE_VERSION = 0x1,
62 MCQI_INFO_TYPE_ACTIVATION_METHOD = 0x5,
63 };
64
65 enum {
66 MCQI_FW_RUNNING_VERSION = 0,
67 MCQI_FW_STORED_VERSION = 1,
68 };
69
mlx5_query_board_id(struct mlx5_core_dev * dev)70 int mlx5_query_board_id(struct mlx5_core_dev *dev)
71 {
72 u32 *out;
73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
75 int err;
76
77 out = kzalloc(outlen, GFP_KERNEL);
78 if (!out)
79 return -ENOMEM;
80
81 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
82 err = mlx5_cmd_exec_inout(dev, query_adapter, in, out);
83 if (err)
84 goto out;
85
86 memcpy(dev->board_id,
87 MLX5_ADDR_OF(query_adapter_out, out,
88 query_adapter_struct.vsd_contd_psid),
89 MLX5_FLD_SZ_BYTES(query_adapter_out,
90 query_adapter_struct.vsd_contd_psid));
91
92 out:
93 kfree(out);
94 return err;
95 }
96
mlx5_core_query_vendor_id(struct mlx5_core_dev * mdev,u32 * vendor_id)97 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
98 {
99 u32 *out;
100 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {};
102 int err;
103
104 out = kzalloc(outlen, GFP_KERNEL);
105 if (!out)
106 return -ENOMEM;
107
108 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
109 err = mlx5_cmd_exec_inout(mdev, query_adapter, in, out);
110 if (err)
111 goto out;
112
113 *vendor_id = MLX5_GET(query_adapter_out, out,
114 query_adapter_struct.ieee_vendor_id);
115 out:
116 kfree(out);
117 return err;
118 }
119 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
120
mlx5_get_pcam_reg(struct mlx5_core_dev * dev)121 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
122 {
123 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
124 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
125 MLX5_PCAM_REGS_5000_TO_507F);
126 }
127
mlx5_get_mcam_access_reg_group(struct mlx5_core_dev * dev,enum mlx5_mcam_reg_groups group)128 static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
129 enum mlx5_mcam_reg_groups group)
130 {
131 return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
132 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
133 }
134
mlx5_get_qcam_reg(struct mlx5_core_dev * dev)135 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
136 {
137 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
138 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
139 MLX5_QCAM_REGS_FIRST_128);
140 }
141
mlx5_query_hca_caps(struct mlx5_core_dev * dev)142 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
143 {
144 int err;
145
146 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
147 if (err)
148 return err;
149
150 if (MLX5_CAP_GEN(dev, port_selection_cap)) {
151 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_PORT_SELECTION, HCA_CAP_OPMOD_GET_CUR);
152 if (err)
153 return err;
154 }
155
156 if (MLX5_CAP_GEN(dev, hca_cap_2)) {
157 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_GENERAL_2, HCA_CAP_OPMOD_GET_CUR);
158 if (err)
159 return err;
160 }
161
162 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
163 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ETHERNET_OFFLOADS,
164 HCA_CAP_OPMOD_GET_CUR);
165 if (err)
166 return err;
167 }
168
169 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
170 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
171 HCA_CAP_OPMOD_GET_CUR);
172 if (err)
173 return err;
174 }
175
176 if (MLX5_CAP_GEN(dev, pg)) {
177 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ODP, HCA_CAP_OPMOD_GET_CUR);
178 if (err)
179 return err;
180 }
181
182 if (MLX5_CAP_GEN(dev, atomic)) {
183 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ATOMIC, HCA_CAP_OPMOD_GET_CUR);
184 if (err)
185 return err;
186 }
187
188 if (MLX5_CAP_GEN(dev, roce)) {
189 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ROCE, HCA_CAP_OPMOD_GET_CUR);
190 if (err)
191 return err;
192 }
193
194 if (MLX5_CAP_GEN(dev, nic_flow_table) ||
195 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
196 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_FLOW_TABLE, HCA_CAP_OPMOD_GET_CUR);
197 if (err)
198 return err;
199 }
200
201 if (MLX5_ESWITCH_MANAGER(dev)) {
202 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH_FLOW_TABLE,
203 HCA_CAP_OPMOD_GET_CUR);
204 if (err)
205 return err;
206
207 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ESWITCH, HCA_CAP_OPMOD_GET_CUR);
208 if (err)
209 return err;
210 }
211
212 if (MLX5_CAP_GEN(dev, qos)) {
213 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_QOS, HCA_CAP_OPMOD_GET_CUR);
214 if (err)
215 return err;
216 }
217
218 if (MLX5_CAP_GEN(dev, debug))
219 mlx5_core_get_caps_mode(dev, MLX5_CAP_DEBUG, HCA_CAP_OPMOD_GET_CUR);
220
221 if (MLX5_CAP_GEN(dev, pcam_reg))
222 mlx5_get_pcam_reg(dev);
223
224 if (MLX5_CAP_GEN(dev, mcam_reg)) {
225 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
226 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
227 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9180_0x91FF);
228 }
229
230 if (MLX5_CAP_GEN(dev, qcam_reg))
231 mlx5_get_qcam_reg(dev);
232
233 if (MLX5_CAP_GEN(dev, device_memory)) {
234 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_MEM, HCA_CAP_OPMOD_GET_CUR);
235 if (err)
236 return err;
237 }
238
239 if (MLX5_CAP_GEN(dev, event_cap)) {
240 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_DEV_EVENT, HCA_CAP_OPMOD_GET_CUR);
241 if (err)
242 return err;
243 }
244
245 if (MLX5_CAP_GEN(dev, tls_tx) || MLX5_CAP_GEN(dev, tls_rx)) {
246 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_TLS, HCA_CAP_OPMOD_GET_CUR);
247 if (err)
248 return err;
249 }
250
251 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
252 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
253 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_VDPA_EMULATION, HCA_CAP_OPMOD_GET_CUR);
254 if (err)
255 return err;
256 }
257
258 if (MLX5_CAP_GEN(dev, tlp_device_emulation_manager)) {
259 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_TLP_EMULATION, HCA_CAP_OPMOD_GET_CUR);
260 if (err)
261 return err;
262 }
263
264 if (MLX5_CAP_GEN(dev, ipsec_offload)) {
265 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_IPSEC, HCA_CAP_OPMOD_GET_CUR);
266 if (err)
267 return err;
268 }
269
270 if (MLX5_CAP_GEN(dev, crypto)) {
271 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_CRYPTO, HCA_CAP_OPMOD_GET_CUR);
272 if (err)
273 return err;
274 }
275
276 if (MLX5_CAP_GEN_64(dev, general_obj_types) &
277 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD) {
278 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_MACSEC, HCA_CAP_OPMOD_GET_CUR);
279 if (err)
280 return err;
281 }
282
283 if (MLX5_CAP_GEN(dev, adv_virtualization)) {
284 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ADV_VIRTUALIZATION,
285 HCA_CAP_OPMOD_GET_CUR);
286 if (err)
287 return err;
288 }
289
290 if (MLX5_CAP_GEN(dev, shampo)) {
291 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_SHAMPO, HCA_CAP_OPMOD_GET_CUR);
292 if (err)
293 return err;
294 }
295
296 if (MLX5_CAP_GEN(dev, adv_rdma)) {
297 err = mlx5_core_get_caps_mode(dev, MLX5_CAP_ADV_RDMA,
298 HCA_CAP_OPMOD_GET_CUR);
299 if (err)
300 return err;
301 }
302
303 if (MLX5_CAP_GEN(dev, psp)) {
304 err = mlx5_core_get_caps(dev, MLX5_CAP_PSP);
305 if (err)
306 return err;
307 }
308
309 return 0;
310 }
311
mlx5_cmd_init_hca(struct mlx5_core_dev * dev,u32 * sw_owner_id)312 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, u32 *sw_owner_id)
313 {
314 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {};
315 int i;
316
317 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
318
319 if (MLX5_CAP_GEN(dev, sw_owner_id)) {
320 for (i = 0; i < 4; i++)
321 MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
322 sw_owner_id[i]);
323 }
324
325 if (MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) &&
326 dev->priv.sw_vhca_id > 0)
327 MLX5_SET(init_hca_in, in, sw_vhca_id, dev->priv.sw_vhca_id);
328
329 return mlx5_cmd_exec_in(dev, init_hca, in);
330 }
331
mlx5_cmd_teardown_hca(struct mlx5_core_dev * dev)332 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
333 {
334 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
335
336 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
337 return mlx5_cmd_exec_in(dev, teardown_hca, in);
338 }
339
mlx5_cmd_force_teardown_hca(struct mlx5_core_dev * dev)340 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
341 {
342 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
343 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
344 int force_state;
345 int ret;
346
347 if (!MLX5_CAP_GEN(dev, force_teardown)) {
348 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
349 return -EOPNOTSUPP;
350 }
351
352 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
353 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
354
355 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
356 if (ret)
357 return ret;
358
359 force_state = MLX5_GET(teardown_hca_out, out, state);
360 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
361 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
362 return -EIO;
363 }
364
365 return 0;
366 }
367
mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev * dev)368 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
369 {
370 unsigned long end, delay_ms = mlx5_tout_ms(dev, TEARDOWN);
371 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
372 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
373 int state;
374 int ret;
375
376 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
377 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
378 return -EOPNOTSUPP;
379 }
380
381 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
382 MLX5_SET(teardown_hca_in, in, profile,
383 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
384
385 ret = mlx5_cmd_exec_inout(dev, teardown_hca, in, out);
386 if (ret)
387 return ret;
388
389 state = MLX5_GET(teardown_hca_out, out, state);
390 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
391 mlx5_core_warn(dev, "teardown with fast mode failed\n");
392 return -EIO;
393 }
394
395 mlx5_set_nic_state(dev, MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED);
396
397 /* Loop until device state turns to disable */
398 end = jiffies + msecs_to_jiffies(delay_ms);
399 do {
400 if (mlx5_get_nic_state(dev) == MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED)
401 break;
402 if (pci_channel_offline(dev->pdev)) {
403 mlx5_core_err(dev, "PCI channel offline, stop waiting for NIC IFC\n");
404 return -EACCES;
405 }
406
407 cond_resched();
408 } while (!time_after(jiffies, end));
409
410 if (mlx5_get_nic_state(dev) != MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED) {
411 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
412 mlx5_get_nic_state(dev), delay_ms);
413 return -EIO;
414 }
415
416 return 0;
417 }
418
419 enum mlxsw_reg_mcc_instruction {
420 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
421 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
422 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
423 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
424 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
425 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
426 };
427
mlx5_reg_mcc_set(struct mlx5_core_dev * dev,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)428 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
429 enum mlxsw_reg_mcc_instruction instr,
430 u16 component_index, u32 update_handle,
431 u32 component_size)
432 {
433 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
434 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
435
436 memset(in, 0, sizeof(in));
437
438 MLX5_SET(mcc_reg, in, instruction, instr);
439 MLX5_SET(mcc_reg, in, component_index, component_index);
440 MLX5_SET(mcc_reg, in, update_handle, update_handle);
441 MLX5_SET(mcc_reg, in, component_size, component_size);
442
443 return mlx5_core_access_reg(dev, in, sizeof(in), out,
444 sizeof(out), MLX5_REG_MCC, 0, 1);
445 }
446
mlx5_reg_mcc_query(struct mlx5_core_dev * dev,u32 * update_handle,u8 * error_code,u8 * control_state)447 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
448 u32 *update_handle, u8 *error_code,
449 u8 *control_state)
450 {
451 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
452 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
453 int err;
454
455 memset(in, 0, sizeof(in));
456 memset(out, 0, sizeof(out));
457 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
458
459 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
460 sizeof(out), MLX5_REG_MCC, 0, 0);
461 if (err)
462 goto out;
463
464 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
465 *error_code = MLX5_GET(mcc_reg, out, error_code);
466 *control_state = MLX5_GET(mcc_reg, out, control_state);
467
468 out:
469 return err;
470 }
471
mlx5_reg_mcda_set(struct mlx5_core_dev * dev,u32 update_handle,u32 offset,u16 size,u8 * data)472 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
473 u32 update_handle,
474 u32 offset, u16 size,
475 u8 *data)
476 {
477 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
478 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
479 int i, j, dw_size = size >> 2;
480 __be32 data_element;
481 u32 *in;
482
483 in = kzalloc(in_size, GFP_KERNEL);
484 if (!in)
485 return -ENOMEM;
486
487 MLX5_SET(mcda_reg, in, update_handle, update_handle);
488 MLX5_SET(mcda_reg, in, offset, offset);
489 MLX5_SET(mcda_reg, in, size, size);
490
491 for (i = 0; i < dw_size; i++) {
492 j = i * 4;
493 data_element = htonl(*(u32 *)&data[j]);
494 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
495 }
496
497 err = mlx5_core_access_reg(dev, in, in_size, out,
498 sizeof(out), MLX5_REG_MCDA, 0, 1);
499 kfree(in);
500 return err;
501 }
502
mlx5_reg_mcqi_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u8 info_type,u16 data_size,void * mcqi_data)503 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
504 u16 component_index, bool read_pending,
505 u8 info_type, u16 data_size, void *mcqi_data)
506 {
507 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
508 u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
509 void *data;
510 int err;
511
512 MLX5_SET(mcqi_reg, in, component_index, component_index);
513 MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
514 MLX5_SET(mcqi_reg, in, info_type, info_type);
515 MLX5_SET(mcqi_reg, in, data_size, data_size);
516
517 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
518 MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
519 MLX5_REG_MCQI, 0, 0);
520 if (err)
521 return err;
522
523 data = MLX5_ADDR_OF(mcqi_reg, out, data);
524 memcpy(mcqi_data, data, data_size);
525
526 return 0;
527 }
528
mlx5_reg_mcqi_caps_query(struct mlx5_core_dev * dev,u16 component_index,u32 * max_component_size,u8 * log_mcda_word_size,u16 * mcda_max_write_size)529 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
530 u32 *max_component_size, u8 *log_mcda_word_size,
531 u16 *mcda_max_write_size)
532 {
533 u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
534 int err;
535
536 err = mlx5_reg_mcqi_query(dev, component_index, 0,
537 MCQI_INFO_TYPE_CAPABILITIES,
538 MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
539 if (err)
540 return err;
541
542 *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
543 *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
544 *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
545
546 return 0;
547 }
548
549 struct mlx5_mlxfw_dev {
550 struct mlxfw_dev mlxfw_dev;
551 struct mlx5_core_dev *mlx5_core_dev;
552 };
553
mlx5_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)554 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
555 u16 component_index, u32 *p_max_size,
556 u8 *p_align_bits, u16 *p_max_write_size)
557 {
558 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
559 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
560 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
561
562 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
563 mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
564 return -EOPNOTSUPP;
565 }
566
567 return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
568 p_align_bits, p_max_write_size);
569 }
570
mlx5_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)571 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
572 {
573 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
574 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
575 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
576 u8 control_state, error_code;
577 int err;
578
579 *fwhandle = 0;
580 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
581 if (err)
582 return err;
583
584 if (control_state != MLXFW_FSM_STATE_IDLE)
585 return -EBUSY;
586
587 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
588 0, *fwhandle, 0);
589 }
590
mlx5_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)591 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
592 u16 component_index, u32 component_size)
593 {
594 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
595 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
596 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
597
598 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
599 component_index, fwhandle, component_size);
600 }
601
mlx5_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)602 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
603 u8 *data, u16 size, u32 offset)
604 {
605 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
606 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
607 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
608
609 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
610 }
611
mlx5_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)612 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
613 u16 component_index)
614 {
615 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
616 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
617 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
618
619 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
620 component_index, fwhandle, 0);
621 }
622
mlx5_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)623 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
624 {
625 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
626 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
627 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
628
629 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
630 fwhandle, 0);
631 }
632
mlx5_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)633 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
634 enum mlxfw_fsm_state *fsm_state,
635 enum mlxfw_fsm_state_err *fsm_state_err)
636 {
637 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
638 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
639 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
640 u8 control_state, error_code;
641 int err;
642
643 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
644 if (err)
645 return err;
646
647 *fsm_state = control_state;
648 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
649 MLXFW_FSM_STATE_ERR_MAX);
650 return 0;
651 }
652
mlx5_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)653 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
654 {
655 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
656 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
657 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
658
659 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
660 }
661
mlx5_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)662 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
663 {
664 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
665 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
666 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
667
668 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
669 fwhandle, 0);
670 }
671
mlx5_fsm_reactivate(struct mlxfw_dev * mlxfw_dev,u8 * status)672 static int mlx5_fsm_reactivate(struct mlxfw_dev *mlxfw_dev, u8 *status)
673 {
674 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
675 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
676 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
677 u32 out[MLX5_ST_SZ_DW(mirc_reg)];
678 u32 in[MLX5_ST_SZ_DW(mirc_reg)];
679 unsigned long exp_time;
680 int err;
681
682 exp_time = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, FSM_REACTIVATE));
683
684 if (!MLX5_CAP_MCAM_REG2(dev, mirc))
685 return -EOPNOTSUPP;
686
687 memset(in, 0, sizeof(in));
688
689 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
690 sizeof(out), MLX5_REG_MIRC, 0, 1);
691 if (err)
692 return err;
693
694 do {
695 memset(out, 0, sizeof(out));
696 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
697 sizeof(out), MLX5_REG_MIRC, 0, 0);
698 if (err)
699 return err;
700
701 *status = MLX5_GET(mirc_reg, out, status_code);
702 if (*status != MLXFW_FSM_REACTIVATE_STATUS_BUSY)
703 return 0;
704
705 msleep(20);
706 } while (time_before(jiffies, exp_time));
707
708 return 0;
709 }
710
711 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
712 .component_query = mlx5_component_query,
713 .fsm_lock = mlx5_fsm_lock,
714 .fsm_component_update = mlx5_fsm_component_update,
715 .fsm_block_download = mlx5_fsm_block_download,
716 .fsm_component_verify = mlx5_fsm_component_verify,
717 .fsm_activate = mlx5_fsm_activate,
718 .fsm_reactivate = mlx5_fsm_reactivate,
719 .fsm_query_state = mlx5_fsm_query_state,
720 .fsm_cancel = mlx5_fsm_cancel,
721 .fsm_release = mlx5_fsm_release
722 };
723
mlx5_firmware_flash(struct mlx5_core_dev * dev,const struct firmware * firmware,struct netlink_ext_ack * extack)724 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
725 const struct firmware *firmware,
726 struct netlink_ext_ack *extack)
727 {
728 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
729 .mlxfw_dev = {
730 .ops = &mlx5_mlxfw_dev_ops,
731 .psid = dev->board_id,
732 .psid_size = strlen(dev->board_id),
733 .devlink = priv_to_devlink(dev),
734 },
735 .mlx5_core_dev = dev
736 };
737
738 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
739 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
740 !MLX5_CAP_MCAM_REG(dev, mcc) ||
741 !MLX5_CAP_MCAM_REG(dev, mcda)) {
742 pr_info("%s flashing isn't supported by the running FW\n", __func__);
743 return -EOPNOTSUPP;
744 }
745
746 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
747 firmware, extack);
748 }
749
mlx5_reg_mcqi_version_query(struct mlx5_core_dev * dev,u16 component_index,bool read_pending,u32 * mcqi_version_out)750 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
751 u16 component_index, bool read_pending,
752 u32 *mcqi_version_out)
753 {
754 return mlx5_reg_mcqi_query(dev, component_index, read_pending,
755 MCQI_INFO_TYPE_VERSION,
756 MLX5_ST_SZ_BYTES(mcqi_version),
757 mcqi_version_out);
758 }
759
mlx5_reg_mcqs_query(struct mlx5_core_dev * dev,u32 * out,u16 component_index)760 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
761 u16 component_index)
762 {
763 u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
764 u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
765 int err;
766
767 memset(out, 0, out_sz);
768
769 MLX5_SET(mcqs_reg, in, component_index, component_index);
770
771 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
772 out_sz, MLX5_REG_MCQS, 0, 0);
773 return err;
774 }
775
776 /* scans component index sequentially, to find the boot img index */
mlx5_get_boot_img_component_index(struct mlx5_core_dev * dev)777 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
778 {
779 u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
780 u16 identifier, component_idx = 0;
781 bool quit;
782 int err;
783
784 do {
785 err = mlx5_reg_mcqs_query(dev, out, component_idx);
786 if (err)
787 return err;
788
789 identifier = MLX5_GET(mcqs_reg, out, identifier);
790 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
791 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
792 } while (!quit && ++component_idx);
793
794 if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
795 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
796 component_idx);
797 return -EOPNOTSUPP;
798 }
799
800 return component_idx;
801 }
802
803 static int
mlx5_fw_image_pending(struct mlx5_core_dev * dev,int component_index,bool * pending_version_exists)804 mlx5_fw_image_pending(struct mlx5_core_dev *dev,
805 int component_index,
806 bool *pending_version_exists)
807 {
808 u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
809 u8 component_update_state;
810 int err;
811
812 err = mlx5_reg_mcqs_query(dev, out, component_index);
813 if (err)
814 return err;
815
816 component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
817
818 if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
819 *pending_version_exists = false;
820 } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
821 *pending_version_exists = true;
822 } else {
823 mlx5_core_warn(dev,
824 "mcqs: can't read pending fw version while fw state is %d\n",
825 component_update_state);
826 return -ENODATA;
827 }
828 return 0;
829 }
830
mlx5_fw_version_query(struct mlx5_core_dev * dev,u32 * running_ver,u32 * pending_ver)831 void mlx5_fw_version_query(struct mlx5_core_dev *dev,
832 u32 *running_ver, u32 *pending_ver)
833 {
834 u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
835 bool pending_version_exists;
836 int component_index;
837 int err;
838
839 *running_ver = 0;
840 *pending_ver = 0;
841
842 if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
843 !MLX5_CAP_MCAM_REG(dev, mcqs)) {
844 mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
845 return;
846 }
847
848 component_index = mlx5_get_boot_img_component_index(dev);
849 if (component_index < 0) {
850 mlx5_core_warn(dev, "fw query failed to find boot img component index, err %d\n",
851 component_index);
852 return;
853 }
854
855 *running_ver = U32_MAX; /* indicate failure */
856 err = mlx5_reg_mcqi_version_query(dev, component_index,
857 MCQI_FW_RUNNING_VERSION,
858 reg_mcqi_version);
859 if (!err)
860 *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version,
861 version);
862 else
863 mlx5_core_warn(dev, "failed to query running version, err %d\n",
864 err);
865
866 *pending_ver = U32_MAX; /* indicate failure */
867 err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
868 if (err) {
869 mlx5_core_warn(dev, "failed to query pending image, err %d\n",
870 err);
871 return;
872 }
873
874 if (!pending_version_exists) {
875 *pending_ver = 0;
876 return;
877 }
878
879 err = mlx5_reg_mcqi_version_query(dev, component_index,
880 MCQI_FW_STORED_VERSION,
881 reg_mcqi_version);
882 if (!err)
883 *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version,
884 version);
885 else
886 mlx5_core_warn(dev, "failed to query pending version, err %d\n",
887 err);
888
889 return;
890 }
891