1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // IDT821034 ALSA SoC driver 4 // 5 // Copyright 2022 CS GROUP France 6 // 7 // Author: Herve Codina <herve.codina@bootlin.com> 8 9 #include <linux/bitrev.h> 10 #include <linux/cleanup.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/spi/spi.h> 15 #include <sound/pcm_params.h> 16 #include <sound/soc.h> 17 #include <sound/tlv.h> 18 19 #define IDT821034_NB_CHANNEL 4 20 21 struct idt821034_amp { 22 u16 gain; 23 bool is_muted; 24 }; 25 26 struct idt821034 { 27 struct spi_device *spi; 28 struct mutex mutex; 29 u8 spi_tx_buf; /* Cannot use stack area for SPI (dma-safe memory) */ 30 u8 spi_rx_buf; /* Cannot use stack area for SPI (dma-safe memory) */ 31 struct { 32 u8 codec_conf; 33 struct { 34 u8 power; 35 u8 tx_slot; 36 u8 rx_slot; 37 u8 slic_conf; 38 u8 slic_control; 39 } ch[IDT821034_NB_CHANNEL]; 40 } cache; 41 struct { 42 struct { 43 struct idt821034_amp amp_out; 44 struct idt821034_amp amp_in; 45 } ch[IDT821034_NB_CHANNEL]; 46 } amps; 47 int max_ch_playback; 48 int max_ch_capture; 49 struct gpio_chip gpio_chip; 50 }; 51 52 static int idt821034_8bit_write(struct idt821034 *idt821034, u8 val) 53 { 54 struct spi_transfer xfer[] = { 55 { 56 .tx_buf = &idt821034->spi_tx_buf, 57 .len = 1, 58 }, { 59 .cs_off = 1, 60 .tx_buf = &idt821034->spi_tx_buf, 61 .len = 1, 62 } 63 }; 64 65 idt821034->spi_tx_buf = val; 66 67 dev_vdbg(&idt821034->spi->dev, "spi xfer wr 0x%x\n", val); 68 69 return spi_sync_transfer(idt821034->spi, xfer, 2); 70 } 71 72 static int idt821034_2x8bit_write(struct idt821034 *idt821034, u8 val1, u8 val2) 73 { 74 int ret; 75 76 ret = idt821034_8bit_write(idt821034, val1); 77 if (ret) 78 return ret; 79 return idt821034_8bit_write(idt821034, val2); 80 } 81 82 static int idt821034_8bit_read(struct idt821034 *idt821034, u8 valw, u8 *valr) 83 { 84 struct spi_transfer xfer[] = { 85 { 86 .tx_buf = &idt821034->spi_tx_buf, 87 .rx_buf = &idt821034->spi_rx_buf, 88 .len = 1, 89 }, { 90 .cs_off = 1, 91 .tx_buf = &idt821034->spi_tx_buf, 92 .len = 1, 93 } 94 }; 95 int ret; 96 97 idt821034->spi_tx_buf = valw; 98 99 ret = spi_sync_transfer(idt821034->spi, xfer, 2); 100 if (ret) 101 return ret; 102 103 *valr = idt821034->spi_rx_buf; 104 105 dev_vdbg(&idt821034->spi->dev, "spi xfer wr 0x%x, rd 0x%x\n", 106 valw, *valr); 107 108 return 0; 109 } 110 111 /* Available mode for the programming sequence */ 112 #define IDT821034_MODE_CODEC(_ch) (0x80 | ((_ch) << 2)) 113 #define IDT821034_MODE_SLIC(_ch) (0xD0 | ((_ch) << 2)) 114 #define IDT821034_MODE_GAIN(_ch) (0xC0 | ((_ch) << 2)) 115 116 /* Power values that can be used in 'power' (can be ORed) */ 117 #define IDT821034_CONF_PWRUP_TX BIT(1) /* from analog input to PCM */ 118 #define IDT821034_CONF_PWRUP_RX BIT(0) /* from PCM to analog output */ 119 120 static int idt821034_set_channel_power(struct idt821034 *idt821034, u8 ch, u8 power) 121 { 122 u8 conf; 123 int ret; 124 125 dev_dbg(&idt821034->spi->dev, "set_channel_power(%u, 0x%x)\n", ch, power); 126 127 conf = IDT821034_MODE_CODEC(ch) | idt821034->cache.codec_conf; 128 129 if (power & IDT821034_CONF_PWRUP_RX) { 130 ret = idt821034_2x8bit_write(idt821034, 131 conf | IDT821034_CONF_PWRUP_RX, 132 idt821034->cache.ch[ch].rx_slot); 133 if (ret) 134 return ret; 135 } 136 if (power & IDT821034_CONF_PWRUP_TX) { 137 ret = idt821034_2x8bit_write(idt821034, 138 conf | IDT821034_CONF_PWRUP_TX, 139 idt821034->cache.ch[ch].tx_slot); 140 if (ret) 141 return ret; 142 } 143 if (!(power & (IDT821034_CONF_PWRUP_TX | IDT821034_CONF_PWRUP_RX))) { 144 ret = idt821034_2x8bit_write(idt821034, conf, 0); 145 if (ret) 146 return ret; 147 } 148 149 idt821034->cache.ch[ch].power = power; 150 151 return 0; 152 } 153 154 static u8 idt821034_get_channel_power(struct idt821034 *idt821034, u8 ch) 155 { 156 return idt821034->cache.ch[ch].power; 157 } 158 159 /* Codec configuration values that can be used in 'codec_conf' (can be ORed) */ 160 #define IDT821034_CONF_ALAW_MODE BIT(5) 161 #define IDT821034_CONF_DELAY_MODE BIT(4) 162 163 static int idt821034_set_codec_conf(struct idt821034 *idt821034, u8 codec_conf) 164 { 165 u8 conf; 166 u8 ts; 167 int ret; 168 169 dev_dbg(&idt821034->spi->dev, "set_codec_conf(0x%x)\n", codec_conf); 170 171 /* codec conf fields are common to all channel. 172 * Arbitrary use of channel 0 for this configuration. 173 */ 174 175 /* Set Configuration Register */ 176 conf = IDT821034_MODE_CODEC(0) | codec_conf; 177 178 /* Update conf value and timeslot register value according 179 * to cache values 180 */ 181 if (idt821034->cache.ch[0].power & IDT821034_CONF_PWRUP_RX) { 182 conf |= IDT821034_CONF_PWRUP_RX; 183 ts = idt821034->cache.ch[0].rx_slot; 184 } else if (idt821034->cache.ch[0].power & IDT821034_CONF_PWRUP_TX) { 185 conf |= IDT821034_CONF_PWRUP_TX; 186 ts = idt821034->cache.ch[0].tx_slot; 187 } else { 188 ts = 0x00; 189 } 190 191 /* Write configuration register and time-slot register */ 192 ret = idt821034_2x8bit_write(idt821034, conf, ts); 193 if (ret) 194 return ret; 195 196 idt821034->cache.codec_conf = codec_conf; 197 return 0; 198 } 199 200 static u8 idt821034_get_codec_conf(struct idt821034 *idt821034) 201 { 202 return idt821034->cache.codec_conf; 203 } 204 205 /* Channel direction values that can be used in 'ch_dir' (can be ORed) */ 206 #define IDT821034_CH_RX BIT(0) /* from PCM to analog output */ 207 #define IDT821034_CH_TX BIT(1) /* from analog input to PCM */ 208 209 static int idt821034_set_channel_ts(struct idt821034 *idt821034, u8 ch, u8 ch_dir, u8 ts_num) 210 { 211 u8 conf; 212 int ret; 213 214 dev_dbg(&idt821034->spi->dev, "set_channel_ts(%u, 0x%x, %d)\n", ch, ch_dir, ts_num); 215 216 conf = IDT821034_MODE_CODEC(ch) | idt821034->cache.codec_conf; 217 218 if (ch_dir & IDT821034_CH_RX) { 219 if (idt821034->cache.ch[ch].power & IDT821034_CONF_PWRUP_RX) { 220 ret = idt821034_2x8bit_write(idt821034, 221 conf | IDT821034_CONF_PWRUP_RX, 222 ts_num); 223 if (ret) 224 return ret; 225 } 226 idt821034->cache.ch[ch].rx_slot = ts_num; 227 } 228 if (ch_dir & IDT821034_CH_TX) { 229 if (idt821034->cache.ch[ch].power & IDT821034_CONF_PWRUP_TX) { 230 ret = idt821034_2x8bit_write(idt821034, 231 conf | IDT821034_CONF_PWRUP_TX, 232 ts_num); 233 if (ret) 234 return ret; 235 } 236 idt821034->cache.ch[ch].tx_slot = ts_num; 237 } 238 239 return 0; 240 } 241 242 /* SLIC direction values that can be used in 'slic_dir' (can be ORed) */ 243 #define IDT821034_SLIC_IO1_IN BIT(1) 244 #define IDT821034_SLIC_IO0_IN BIT(0) 245 246 static int idt821034_set_slic_conf(struct idt821034 *idt821034, u8 ch, u8 slic_dir) 247 { 248 u8 conf; 249 int ret; 250 251 dev_dbg(&idt821034->spi->dev, "set_slic_conf(%u, 0x%x)\n", ch, slic_dir); 252 253 conf = IDT821034_MODE_SLIC(ch) | slic_dir; 254 ret = idt821034_2x8bit_write(idt821034, conf, idt821034->cache.ch[ch].slic_control); 255 if (ret) 256 return ret; 257 258 idt821034->cache.ch[ch].slic_conf = slic_dir; 259 260 return 0; 261 } 262 263 static u8 idt821034_get_slic_conf(struct idt821034 *idt821034, u8 ch) 264 { 265 return idt821034->cache.ch[ch].slic_conf; 266 } 267 268 static int idt821034_write_slic_raw(struct idt821034 *idt821034, u8 ch, u8 slic_raw) 269 { 270 u8 conf; 271 int ret; 272 273 dev_dbg(&idt821034->spi->dev, "write_slic_raw(%u, 0x%x)\n", ch, slic_raw); 274 275 /* 276 * On write, slic_raw is mapped as follow : 277 * b4: O_4 278 * b3: O_3 279 * b2: O_2 280 * b1: I/O_1 281 * b0: I/O_0 282 */ 283 284 conf = IDT821034_MODE_SLIC(ch) | idt821034->cache.ch[ch].slic_conf; 285 ret = idt821034_2x8bit_write(idt821034, conf, slic_raw); 286 if (ret) 287 return ret; 288 289 idt821034->cache.ch[ch].slic_control = slic_raw; 290 return 0; 291 } 292 293 static u8 idt821034_get_written_slic_raw(struct idt821034 *idt821034, u8 ch) 294 { 295 return idt821034->cache.ch[ch].slic_control; 296 } 297 298 static int idt821034_read_slic_raw(struct idt821034 *idt821034, u8 ch, u8 *slic_raw) 299 { 300 u8 val; 301 int ret; 302 303 /* 304 * On read, slic_raw is mapped as follow : 305 * b7: I/O_0 306 * b6: I/O_1 307 * b5: O_2 308 * b4: O_3 309 * b3: O_4 310 * b2: I/O1_0, I/O_0 from channel 1 (no matter ch value) 311 * b1: I/O2_0, I/O_0 from channel 2 (no matter ch value) 312 * b2: I/O3_0, I/O_0 from channel 3 (no matter ch value) 313 */ 314 315 val = IDT821034_MODE_SLIC(ch) | idt821034->cache.ch[ch].slic_conf; 316 ret = idt821034_8bit_write(idt821034, val); 317 if (ret) 318 return ret; 319 320 ret = idt821034_8bit_read(idt821034, idt821034->cache.ch[ch].slic_control, slic_raw); 321 if (ret) 322 return ret; 323 324 dev_dbg(&idt821034->spi->dev, "read_slic_raw(%i) 0x%x\n", ch, *slic_raw); 325 326 return 0; 327 } 328 329 /* Gain type values that can be used in 'gain_type' (cannot be ORed) */ 330 #define IDT821034_GAIN_RX (0 << 1) /* from PCM to analog output */ 331 #define IDT821034_GAIN_TX (1 << 1) /* from analog input to PCM */ 332 333 static int idt821034_set_gain_channel(struct idt821034 *idt821034, u8 ch, 334 u8 gain_type, u16 gain_val) 335 { 336 u8 conf; 337 int ret; 338 339 dev_dbg(&idt821034->spi->dev, "set_gain_channel(%u, 0x%x, 0x%x-%d)\n", 340 ch, gain_type, gain_val, gain_val); 341 342 /* 343 * The gain programming coefficients should be calculated as: 344 * Transmit : Coeff_X = round [ gain_X0dB × gain_X ] 345 * Receive: Coeff_R = round [ gain_R0dB × gain_R ] 346 * where: 347 * gain_X0dB = 1820; 348 * gain_X is the target gain; 349 * Coeff_X should be in the range of 0 to 8192. 350 * gain_R0dB = 2506; 351 * gain_R is the target gain; 352 * Coeff_R should be in the range of 0 to 8192. 353 * 354 * A gain programming coefficient is 14-bit wide and in binary format. 355 * The 7 Most Significant Bits of the coefficient is called 356 * GA_MSB_Transmit for transmit path, or is called GA_MSB_Receive for 357 * receive path; The 7 Least Significant Bits of the coefficient is 358 * called GA_LSB_ Transmit for transmit path, or is called 359 * GA_LSB_Receive for receive path. 360 * 361 * An example is given below to clarify the calculation of the 362 * coefficient. To program a +3 dB gain in transmit path and a -3.5 dB 363 * gain in receive path: 364 * 365 * Linear Code of +3dB = 10^(3/20)= 1.412537545 366 * Coeff_X = round (1820 × 1.412537545) = 2571 367 * = 0b001010_00001011 368 * GA_MSB_Transmit = 0b0010100 369 * GA_LSB_Transmit = 0b0001011 370 * 371 * Linear Code of -3.5dB = 10^(-3.5/20) = 0.668343917 372 * Coeff_R= round (2506 × 0.668343917) = 1675 373 * = 0b0001101_0001011 374 * GA_MSB_Receive = 0b0001101 375 * GA_LSB_Receive = 0b0001011 376 */ 377 378 conf = IDT821034_MODE_GAIN(ch) | gain_type; 379 380 ret = idt821034_2x8bit_write(idt821034, conf | 0x00, gain_val & 0x007F); 381 if (ret) 382 return ret; 383 384 ret = idt821034_2x8bit_write(idt821034, conf | 0x01, (gain_val >> 7) & 0x7F); 385 if (ret) 386 return ret; 387 388 return 0; 389 } 390 391 /* Id helpers used in controls and dapm */ 392 #define IDT821034_DIR_OUT (1 << 3) 393 #define IDT821034_DIR_IN (0 << 3) 394 #define IDT821034_ID(_ch, _dir) (((_ch) & 0x03) | (_dir)) 395 #define IDT821034_ID_OUT(_ch) IDT821034_ID(_ch, IDT821034_DIR_OUT) 396 #define IDT821034_ID_IN(_ch) IDT821034_ID(_ch, IDT821034_DIR_IN) 397 398 #define IDT821034_ID_GET_CHAN(_id) ((_id) & 0x03) 399 #define IDT821034_ID_GET_DIR(_id) ((_id) & (1 << 3)) 400 #define IDT821034_ID_IS_OUT(_id) (IDT821034_ID_GET_DIR(_id) == IDT821034_DIR_OUT) 401 402 static int idt821034_kctrl_gain_get(struct snd_kcontrol *kcontrol, 403 struct snd_ctl_elem_value *ucontrol) 404 { 405 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 406 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 407 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component); 408 int min = mc->min; 409 int max = mc->max; 410 unsigned int mask = (1 << fls(max)) - 1; 411 unsigned int invert = mc->invert; 412 int val; 413 u8 ch; 414 415 ch = IDT821034_ID_GET_CHAN(mc->reg); 416 417 scoped_guard(mutex, &idt821034->mutex) { 418 if (IDT821034_ID_IS_OUT(mc->reg)) 419 val = idt821034->amps.ch[ch].amp_out.gain; 420 else 421 val = idt821034->amps.ch[ch].amp_in.gain; 422 } 423 424 ucontrol->value.integer.value[0] = val & mask; 425 if (invert) 426 ucontrol->value.integer.value[0] = max - ucontrol->value.integer.value[0]; 427 else 428 ucontrol->value.integer.value[0] = ucontrol->value.integer.value[0] - min; 429 430 return 0; 431 } 432 433 static int idt821034_kctrl_gain_put(struct snd_kcontrol *kcontrol, 434 struct snd_ctl_elem_value *ucontrol) 435 { 436 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 437 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 438 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component); 439 struct idt821034_amp *amp; 440 int min = mc->min; 441 int max = mc->max; 442 unsigned int mask = (1 << fls(max)) - 1; 443 unsigned int invert = mc->invert; 444 unsigned int val; 445 int ret; 446 u8 gain_type; 447 u8 ch; 448 449 val = ucontrol->value.integer.value[0]; 450 if (val > max - min) 451 return -EINVAL; 452 453 if (invert) 454 val = (max - val) & mask; 455 else 456 val = (val + min) & mask; 457 458 ch = IDT821034_ID_GET_CHAN(mc->reg); 459 460 guard(mutex)(&idt821034->mutex); 461 462 if (IDT821034_ID_IS_OUT(mc->reg)) { 463 amp = &idt821034->amps.ch[ch].amp_out; 464 gain_type = IDT821034_GAIN_RX; 465 } else { 466 amp = &idt821034->amps.ch[ch].amp_in; 467 gain_type = IDT821034_GAIN_TX; 468 } 469 470 if (amp->gain == val) 471 return 0; 472 473 if (!amp->is_muted) { 474 ret = idt821034_set_gain_channel(idt821034, ch, gain_type, val); 475 if (ret) 476 return ret; 477 } 478 479 amp->gain = val; 480 481 return 1; 482 } 483 484 static int idt821034_kctrl_mute_get(struct snd_kcontrol *kcontrol, 485 struct snd_ctl_elem_value *ucontrol) 486 { 487 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 488 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component); 489 int id = kcontrol->private_value; 490 bool is_muted; 491 u8 ch; 492 493 ch = IDT821034_ID_GET_CHAN(id); 494 495 scoped_guard(mutex, &idt821034->mutex) { 496 is_muted = IDT821034_ID_IS_OUT(id) ? 497 idt821034->amps.ch[ch].amp_out.is_muted : 498 idt821034->amps.ch[ch].amp_in.is_muted; 499 } 500 501 ucontrol->value.integer.value[0] = !is_muted; 502 503 return 0; 504 } 505 506 static int idt821034_kctrl_mute_put(struct snd_kcontrol *kcontrol, 507 struct snd_ctl_elem_value *ucontrol) 508 { 509 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 510 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component); 511 int id = kcontrol->private_value; 512 struct idt821034_amp *amp; 513 bool is_mute; 514 u8 gain_type; 515 int ret; 516 u8 ch; 517 518 ch = IDT821034_ID_GET_CHAN(id); 519 is_mute = !ucontrol->value.integer.value[0]; 520 521 guard(mutex)(&idt821034->mutex); 522 523 if (IDT821034_ID_IS_OUT(id)) { 524 amp = &idt821034->amps.ch[ch].amp_out; 525 gain_type = IDT821034_GAIN_RX; 526 } else { 527 amp = &idt821034->amps.ch[ch].amp_in; 528 gain_type = IDT821034_GAIN_TX; 529 } 530 531 if (amp->is_muted == is_mute) 532 return 0; 533 534 ret = idt821034_set_gain_channel(idt821034, ch, gain_type, 535 is_mute ? 0 : amp->gain); 536 if (ret) 537 return ret; 538 539 amp->is_muted = is_mute; 540 541 return 1; 542 } 543 544 static const DECLARE_TLV_DB_LINEAR(idt821034_gain_in, -300, 1300); 545 #define IDT821034_GAIN_IN_MIN_RAW 1288 /* -3.0 dB -> 10^(-3.0/20.0) * 1820 = 1288 */ 546 #define IDT821034_GAIN_IN_MAX_RAW 8130 /* 13.0 dB -> 10^(13.0/20.0) * 1820 = 8130 */ 547 #define IDT821034_GAIN_IN_INIT_RAW 1820 /* 0dB -> 10^(0/20) * 1820 = 1820 */ 548 549 static const DECLARE_TLV_DB_LINEAR(idt821034_gain_out, -1300, 300); 550 #define IDT821034_GAIN_OUT_MIN_RAW 561 /* -13.0 dB -> 10^(-13.0/20.0) * 2506 = 561 */ 551 #define IDT821034_GAIN_OUT_MAX_RAW 3540 /* 3.0 dB -> 10^(3.0/20.0) * 2506 = 3540 */ 552 #define IDT821034_GAIN_OUT_INIT_RAW 2506 /* 0dB -> 10^(0/20) * 2506 = 2506 */ 553 554 static const struct snd_kcontrol_new idt821034_controls[] = { 555 /* DAC volume control */ 556 SOC_SINGLE_RANGE_EXT_TLV("DAC0 Playback Volume", IDT821034_ID_OUT(0), 0, 557 IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW, 558 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 559 idt821034_gain_out), 560 SOC_SINGLE_RANGE_EXT_TLV("DAC1 Playback Volume", IDT821034_ID_OUT(1), 0, 561 IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW, 562 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 563 idt821034_gain_out), 564 SOC_SINGLE_RANGE_EXT_TLV("DAC2 Playback Volume", IDT821034_ID_OUT(2), 0, 565 IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW, 566 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 567 idt821034_gain_out), 568 SOC_SINGLE_RANGE_EXT_TLV("DAC3 Playback Volume", IDT821034_ID_OUT(3), 0, 569 IDT821034_GAIN_OUT_MIN_RAW, IDT821034_GAIN_OUT_MAX_RAW, 570 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 571 idt821034_gain_out), 572 573 /* DAC mute control */ 574 SOC_SINGLE_BOOL_EXT("DAC0 Playback Switch", IDT821034_ID_OUT(0), 575 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 576 SOC_SINGLE_BOOL_EXT("DAC1 Playback Switch", IDT821034_ID_OUT(1), 577 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 578 SOC_SINGLE_BOOL_EXT("DAC2 Playback Switch", IDT821034_ID_OUT(2), 579 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 580 SOC_SINGLE_BOOL_EXT("DAC3 Playback Switch", IDT821034_ID_OUT(3), 581 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 582 583 /* ADC volume control */ 584 SOC_SINGLE_RANGE_EXT_TLV("ADC0 Capture Volume", IDT821034_ID_IN(0), 0, 585 IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW, 586 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 587 idt821034_gain_in), 588 SOC_SINGLE_RANGE_EXT_TLV("ADC1 Capture Volume", IDT821034_ID_IN(1), 0, 589 IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW, 590 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 591 idt821034_gain_in), 592 SOC_SINGLE_RANGE_EXT_TLV("ADC2 Capture Volume", IDT821034_ID_IN(2), 0, 593 IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW, 594 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 595 idt821034_gain_in), 596 SOC_SINGLE_RANGE_EXT_TLV("ADC3 Capture Volume", IDT821034_ID_IN(3), 0, 597 IDT821034_GAIN_IN_MIN_RAW, IDT821034_GAIN_IN_MAX_RAW, 598 0, idt821034_kctrl_gain_get, idt821034_kctrl_gain_put, 599 idt821034_gain_in), 600 601 /* ADC mute control */ 602 SOC_SINGLE_BOOL_EXT("ADC0 Capture Switch", IDT821034_ID_IN(0), 603 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 604 SOC_SINGLE_BOOL_EXT("ADC1 Capture Switch", IDT821034_ID_IN(1), 605 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 606 SOC_SINGLE_BOOL_EXT("ADC2 Capture Switch", IDT821034_ID_IN(2), 607 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 608 SOC_SINGLE_BOOL_EXT("ADC3 Capture Switch", IDT821034_ID_IN(3), 609 idt821034_kctrl_mute_get, idt821034_kctrl_mute_put), 610 }; 611 612 static int idt821034_power_event(struct snd_soc_dapm_widget *w, 613 struct snd_kcontrol *kcontrol, int event) 614 { 615 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 616 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component); 617 unsigned int id = w->shift; 618 u8 power, mask; 619 u8 ch; 620 621 ch = IDT821034_ID_GET_CHAN(id); 622 mask = IDT821034_ID_IS_OUT(id) ? IDT821034_CONF_PWRUP_RX : IDT821034_CONF_PWRUP_TX; 623 624 guard(mutex)(&idt821034->mutex); 625 626 power = idt821034_get_channel_power(idt821034, ch); 627 if (SND_SOC_DAPM_EVENT_ON(event)) 628 power |= mask; 629 else 630 power &= ~mask; 631 632 return idt821034_set_channel_power(idt821034, ch, power); 633 } 634 635 static const struct snd_soc_dapm_widget idt821034_dapm_widgets[] = { 636 SND_SOC_DAPM_DAC_E("DAC0", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(0), 0, 637 idt821034_power_event, 638 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 639 SND_SOC_DAPM_DAC_E("DAC1", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(1), 0, 640 idt821034_power_event, 641 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 642 SND_SOC_DAPM_DAC_E("DAC2", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(2), 0, 643 idt821034_power_event, 644 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 645 SND_SOC_DAPM_DAC_E("DAC3", "Playback", SND_SOC_NOPM, IDT821034_ID_OUT(3), 0, 646 idt821034_power_event, 647 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 648 649 SND_SOC_DAPM_OUTPUT("OUT0"), 650 SND_SOC_DAPM_OUTPUT("OUT1"), 651 SND_SOC_DAPM_OUTPUT("OUT2"), 652 SND_SOC_DAPM_OUTPUT("OUT3"), 653 654 SND_SOC_DAPM_DAC_E("ADC0", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(0), 0, 655 idt821034_power_event, 656 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 657 SND_SOC_DAPM_DAC_E("ADC1", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(1), 0, 658 idt821034_power_event, 659 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 660 SND_SOC_DAPM_DAC_E("ADC2", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(2), 0, 661 idt821034_power_event, 662 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 663 SND_SOC_DAPM_DAC_E("ADC3", "Capture", SND_SOC_NOPM, IDT821034_ID_IN(3), 0, 664 idt821034_power_event, 665 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 666 667 SND_SOC_DAPM_INPUT("IN0"), 668 SND_SOC_DAPM_INPUT("IN1"), 669 SND_SOC_DAPM_INPUT("IN2"), 670 SND_SOC_DAPM_INPUT("IN3"), 671 }; 672 673 static const struct snd_soc_dapm_route idt821034_dapm_routes[] = { 674 { "OUT0", NULL, "DAC0" }, 675 { "OUT1", NULL, "DAC1" }, 676 { "OUT2", NULL, "DAC2" }, 677 { "OUT3", NULL, "DAC3" }, 678 679 { "ADC0", NULL, "IN0" }, 680 { "ADC1", NULL, "IN1" }, 681 { "ADC2", NULL, "IN2" }, 682 { "ADC3", NULL, "IN3" }, 683 }; 684 685 static int idt821034_dai_set_tdm_slot(struct snd_soc_dai *dai, 686 unsigned int tx_mask, unsigned int rx_mask, 687 int slots, int width) 688 { 689 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component); 690 unsigned int mask; 691 u8 slot; 692 int ret; 693 u8 ch; 694 695 switch (width) { 696 case 0: /* Not set -> default 8 */ 697 case 8: 698 break; 699 default: 700 dev_err(dai->dev, "tdm slot width %d not supported\n", width); 701 return -EINVAL; 702 } 703 704 mask = tx_mask; 705 slot = 0; 706 ch = 0; 707 while (mask && ch < IDT821034_NB_CHANNEL) { 708 if (mask & 0x1) { 709 scoped_guard(mutex, &idt821034->mutex) 710 ret = idt821034_set_channel_ts(idt821034, ch, 711 IDT821034_CH_RX, slot); 712 if (ret) { 713 dev_err(dai->dev, "ch%u set tx tdm slot failed (%d)\n", 714 ch, ret); 715 return ret; 716 } 717 ch++; 718 } 719 mask >>= 1; 720 slot++; 721 } 722 if (mask) { 723 dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n", 724 tx_mask, IDT821034_NB_CHANNEL); 725 return -EINVAL; 726 } 727 idt821034->max_ch_playback = ch; 728 729 mask = rx_mask; 730 slot = 0; 731 ch = 0; 732 while (mask && ch < IDT821034_NB_CHANNEL) { 733 if (mask & 0x1) { 734 scoped_guard(mutex, &idt821034->mutex) 735 ret = idt821034_set_channel_ts(idt821034, ch, 736 IDT821034_CH_TX, slot); 737 if (ret) { 738 dev_err(dai->dev, "ch%u set rx tdm slot failed (%d)\n", 739 ch, ret); 740 return ret; 741 } 742 ch++; 743 } 744 mask >>= 1; 745 slot++; 746 } 747 if (mask) { 748 dev_err(dai->dev, "too much rx slots defined (mask = 0x%x) support max %d\n", 749 rx_mask, IDT821034_NB_CHANNEL); 750 return -EINVAL; 751 } 752 idt821034->max_ch_capture = ch; 753 754 return 0; 755 } 756 757 static int idt821034_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 758 { 759 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component); 760 u8 conf; 761 762 guard(mutex)(&idt821034->mutex); 763 764 conf = idt821034_get_codec_conf(idt821034); 765 766 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 767 case SND_SOC_DAIFMT_DSP_A: 768 conf |= IDT821034_CONF_DELAY_MODE; 769 break; 770 case SND_SOC_DAIFMT_DSP_B: 771 conf &= ~IDT821034_CONF_DELAY_MODE; 772 break; 773 default: 774 dev_err(dai->dev, "Unsupported DAI format 0x%x\n", 775 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 776 return -EINVAL; 777 } 778 779 return idt821034_set_codec_conf(idt821034, conf); 780 } 781 782 static int idt821034_dai_hw_params(struct snd_pcm_substream *substream, 783 struct snd_pcm_hw_params *params, 784 struct snd_soc_dai *dai) 785 { 786 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component); 787 u8 conf; 788 789 guard(mutex)(&idt821034->mutex); 790 791 conf = idt821034_get_codec_conf(idt821034); 792 793 switch (params_format(params)) { 794 case SNDRV_PCM_FORMAT_A_LAW: 795 conf |= IDT821034_CONF_ALAW_MODE; 796 break; 797 case SNDRV_PCM_FORMAT_MU_LAW: 798 conf &= ~IDT821034_CONF_ALAW_MODE; 799 break; 800 default: 801 dev_err(dai->dev, "Unsupported PCM format 0x%x\n", 802 params_format(params)); 803 return -EINVAL; 804 } 805 806 return idt821034_set_codec_conf(idt821034, conf); 807 } 808 809 static const unsigned int idt821034_sample_bits[] = {8}; 810 811 static struct snd_pcm_hw_constraint_list idt821034_sample_bits_constr = { 812 .list = idt821034_sample_bits, 813 .count = ARRAY_SIZE(idt821034_sample_bits), 814 }; 815 816 static int idt821034_dai_startup(struct snd_pcm_substream *substream, 817 struct snd_soc_dai *dai) 818 { 819 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(dai->component); 820 unsigned int max_ch = 0; 821 int ret; 822 823 max_ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 824 idt821034->max_ch_playback : idt821034->max_ch_capture; 825 826 /* 827 * Disable stream support (min = 0, max = 0) if no timeslots were 828 * configured otherwise, limit the number of channels to those 829 * configured. 830 */ 831 ret = snd_pcm_hw_constraint_minmax(substream->runtime, SNDRV_PCM_HW_PARAM_CHANNELS, 832 max_ch ? 1 : 0, max_ch); 833 if (ret < 0) 834 return ret; 835 836 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 837 &idt821034_sample_bits_constr); 838 if (ret) 839 return ret; 840 841 return 0; 842 } 843 844 static const u64 idt821034_dai_formats = 845 SND_SOC_POSSIBLE_DAIFMT_DSP_A | 846 SND_SOC_POSSIBLE_DAIFMT_DSP_B; 847 848 static const struct snd_soc_dai_ops idt821034_dai_ops = { 849 .startup = idt821034_dai_startup, 850 .hw_params = idt821034_dai_hw_params, 851 .set_tdm_slot = idt821034_dai_set_tdm_slot, 852 .set_fmt = idt821034_dai_set_fmt, 853 .auto_selectable_formats = &idt821034_dai_formats, 854 .num_auto_selectable_formats = 1, 855 }; 856 857 static struct snd_soc_dai_driver idt821034_dai_driver = { 858 .name = "idt821034", 859 .playback = { 860 .stream_name = "Playback", 861 .channels_min = 1, 862 .channels_max = IDT821034_NB_CHANNEL, 863 .rates = SNDRV_PCM_RATE_8000, 864 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, 865 }, 866 .capture = { 867 .stream_name = "Capture", 868 .channels_min = 1, 869 .channels_max = IDT821034_NB_CHANNEL, 870 .rates = SNDRV_PCM_RATE_8000, 871 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, 872 }, 873 .ops = &idt821034_dai_ops, 874 }; 875 876 static int idt821034_reset_audio(struct idt821034 *idt821034) 877 { 878 int ret; 879 u8 i; 880 881 guard(mutex)(&idt821034->mutex); 882 883 ret = idt821034_set_codec_conf(idt821034, 0); 884 if (ret) 885 return ret; 886 887 for (i = 0; i < IDT821034_NB_CHANNEL; i++) { 888 idt821034->amps.ch[i].amp_out.gain = IDT821034_GAIN_OUT_INIT_RAW; 889 idt821034->amps.ch[i].amp_out.is_muted = false; 890 ret = idt821034_set_gain_channel(idt821034, i, IDT821034_GAIN_RX, 891 idt821034->amps.ch[i].amp_out.gain); 892 if (ret) 893 return ret; 894 895 idt821034->amps.ch[i].amp_in.gain = IDT821034_GAIN_IN_INIT_RAW; 896 idt821034->amps.ch[i].amp_in.is_muted = false; 897 ret = idt821034_set_gain_channel(idt821034, i, IDT821034_GAIN_TX, 898 idt821034->amps.ch[i].amp_in.gain); 899 if (ret) 900 return ret; 901 902 ret = idt821034_set_channel_power(idt821034, i, 0); 903 if (ret) 904 return ret; 905 } 906 907 return 0; 908 } 909 910 static int idt821034_component_probe(struct snd_soc_component *component) 911 { 912 struct idt821034 *idt821034 = snd_soc_component_get_drvdata(component); 913 int ret; 914 915 /* reset idt821034 audio part*/ 916 ret = idt821034_reset_audio(idt821034); 917 if (ret) 918 return ret; 919 920 return 0; 921 } 922 923 static const struct snd_soc_component_driver idt821034_component_driver = { 924 .probe = idt821034_component_probe, 925 .controls = idt821034_controls, 926 .num_controls = ARRAY_SIZE(idt821034_controls), 927 .dapm_widgets = idt821034_dapm_widgets, 928 .num_dapm_widgets = ARRAY_SIZE(idt821034_dapm_widgets), 929 .dapm_routes = idt821034_dapm_routes, 930 .num_dapm_routes = ARRAY_SIZE(idt821034_dapm_routes), 931 .endianness = 1, 932 }; 933 934 #define IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(_offset) (((_offset) / 5) % 4) 935 #define IDT821034_GPIO_OFFSET_TO_SLIC_MASK(_offset) BIT((_offset) % 5) 936 937 static int idt821034_chip_gpio_set(struct gpio_chip *c, unsigned int offset, 938 int val) 939 { 940 u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset); 941 u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset); 942 struct idt821034 *idt821034 = gpiochip_get_data(c); 943 u8 slic_raw; 944 int ret; 945 946 guard(mutex)(&idt821034->mutex); 947 948 slic_raw = idt821034_get_written_slic_raw(idt821034, ch); 949 if (val) 950 slic_raw |= mask; 951 else 952 slic_raw &= ~mask; 953 ret = idt821034_write_slic_raw(idt821034, ch, slic_raw); 954 955 if (ret) 956 dev_err(&idt821034->spi->dev, "set gpio %d (%u, 0x%x) failed (%d)\n", 957 offset, ch, mask, ret); 958 959 return ret; 960 } 961 962 static int idt821034_chip_gpio_get(struct gpio_chip *c, unsigned int offset) 963 { 964 u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset); 965 u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset); 966 struct idt821034 *idt821034 = gpiochip_get_data(c); 967 u8 slic_raw; 968 int ret; 969 970 scoped_guard(mutex, &idt821034->mutex) 971 ret = idt821034_read_slic_raw(idt821034, ch, &slic_raw); 972 if (ret) { 973 dev_err(&idt821034->spi->dev, "get gpio %d (%u, 0x%x) failed (%d)\n", 974 offset, ch, mask, ret); 975 return ret; 976 } 977 978 /* 979 * SLIC IOs are read in reverse order compared to write. 980 * Reverse the read value here in order to have IO0 at lsb (ie same 981 * order as write) 982 */ 983 return !!(bitrev8(slic_raw) & mask); 984 } 985 986 static int idt821034_chip_get_direction(struct gpio_chip *c, unsigned int offset) 987 { 988 u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset); 989 u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset); 990 struct idt821034 *idt821034 = gpiochip_get_data(c); 991 u8 slic_dir; 992 993 guard(mutex)(&idt821034->mutex); 994 slic_dir = idt821034_get_slic_conf(idt821034, ch); 995 996 return slic_dir & mask ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 997 } 998 999 static int idt821034_chip_direction_input(struct gpio_chip *c, unsigned int offset) 1000 { 1001 u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset); 1002 u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset); 1003 struct idt821034 *idt821034 = gpiochip_get_data(c); 1004 u8 slic_conf; 1005 int ret; 1006 1007 /* Only IO0 and IO1 can be set as input */ 1008 if (mask & ~(IDT821034_SLIC_IO1_IN | IDT821034_SLIC_IO0_IN)) 1009 return -EPERM; 1010 1011 guard(mutex)(&idt821034->mutex); 1012 1013 slic_conf = idt821034_get_slic_conf(idt821034, ch) | mask; 1014 1015 ret = idt821034_set_slic_conf(idt821034, ch, slic_conf); 1016 if (ret) { 1017 dev_err(&idt821034->spi->dev, "dir in gpio %d (%u, 0x%x) failed (%d)\n", 1018 offset, ch, mask, ret); 1019 } 1020 1021 return ret; 1022 } 1023 1024 static int idt821034_chip_direction_output(struct gpio_chip *c, unsigned int offset, int val) 1025 { 1026 u8 ch = IDT821034_GPIO_OFFSET_TO_SLIC_CHANNEL(offset); 1027 u8 mask = IDT821034_GPIO_OFFSET_TO_SLIC_MASK(offset); 1028 struct idt821034 *idt821034 = gpiochip_get_data(c); 1029 u8 slic_conf; 1030 int ret; 1031 1032 ret = idt821034_chip_gpio_set(c, offset, val); 1033 if (ret) 1034 return ret; 1035 1036 guard(mutex)(&idt821034->mutex); 1037 1038 slic_conf = idt821034_get_slic_conf(idt821034, ch) & ~mask; 1039 1040 ret = idt821034_set_slic_conf(idt821034, ch, slic_conf); 1041 if (ret) { 1042 dev_err(&idt821034->spi->dev, "dir out gpio %d (%u, 0x%x) failed (%d)\n", 1043 offset, ch, mask, ret); 1044 } 1045 1046 return ret; 1047 } 1048 1049 static int idt821034_reset_gpio(struct idt821034 *idt821034) 1050 { 1051 int ret; 1052 u8 i; 1053 1054 guard(mutex)(&idt821034->mutex); 1055 1056 /* IO0 and IO1 as input for all channels and output IO set to 0 */ 1057 for (i = 0; i < IDT821034_NB_CHANNEL; i++) { 1058 ret = idt821034_set_slic_conf(idt821034, i, 1059 IDT821034_SLIC_IO1_IN | IDT821034_SLIC_IO0_IN); 1060 if (ret) 1061 return ret; 1062 1063 ret = idt821034_write_slic_raw(idt821034, i, 0); 1064 if (ret) 1065 return ret; 1066 1067 } 1068 1069 return 0; 1070 } 1071 1072 static int idt821034_gpio_init(struct idt821034 *idt821034) 1073 { 1074 int ret; 1075 1076 ret = idt821034_reset_gpio(idt821034); 1077 if (ret) 1078 return ret; 1079 1080 idt821034->gpio_chip.owner = THIS_MODULE; 1081 idt821034->gpio_chip.label = dev_name(&idt821034->spi->dev); 1082 idt821034->gpio_chip.parent = &idt821034->spi->dev; 1083 idt821034->gpio_chip.base = -1; 1084 idt821034->gpio_chip.ngpio = 5 * 4; /* 5 GPIOs on 4 channels */ 1085 idt821034->gpio_chip.get_direction = idt821034_chip_get_direction; 1086 idt821034->gpio_chip.direction_input = idt821034_chip_direction_input; 1087 idt821034->gpio_chip.direction_output = idt821034_chip_direction_output; 1088 idt821034->gpio_chip.get = idt821034_chip_gpio_get; 1089 idt821034->gpio_chip.set = idt821034_chip_gpio_set; 1090 idt821034->gpio_chip.can_sleep = true; 1091 1092 return devm_gpiochip_add_data(&idt821034->spi->dev, &idt821034->gpio_chip, 1093 idt821034); 1094 } 1095 1096 static int idt821034_spi_probe(struct spi_device *spi) 1097 { 1098 struct idt821034 *idt821034; 1099 int ret; 1100 1101 spi->bits_per_word = 8; 1102 ret = spi_setup(spi); 1103 if (ret < 0) 1104 return ret; 1105 1106 idt821034 = devm_kzalloc(&spi->dev, sizeof(*idt821034), GFP_KERNEL); 1107 if (!idt821034) 1108 return -ENOMEM; 1109 1110 idt821034->spi = spi; 1111 1112 mutex_init(&idt821034->mutex); 1113 1114 spi_set_drvdata(spi, idt821034); 1115 1116 ret = devm_snd_soc_register_component(&spi->dev, &idt821034_component_driver, 1117 &idt821034_dai_driver, 1); 1118 if (ret) 1119 return ret; 1120 1121 if (IS_ENABLED(CONFIG_GPIOLIB)) 1122 return idt821034_gpio_init(idt821034); 1123 1124 return 0; 1125 } 1126 1127 static const struct of_device_id idt821034_of_match[] = { 1128 { .compatible = "renesas,idt821034", }, 1129 { } 1130 }; 1131 MODULE_DEVICE_TABLE(of, idt821034_of_match); 1132 1133 static const struct spi_device_id idt821034_id_table[] = { 1134 { "idt821034", 0 }, 1135 { } 1136 }; 1137 MODULE_DEVICE_TABLE(spi, idt821034_id_table); 1138 1139 static struct spi_driver idt821034_spi_driver = { 1140 .driver = { 1141 .name = "idt821034", 1142 .of_match_table = idt821034_of_match, 1143 }, 1144 .id_table = idt821034_id_table, 1145 .probe = idt821034_spi_probe, 1146 }; 1147 1148 module_spi_driver(idt821034_spi_driver); 1149 1150 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>"); 1151 MODULE_DESCRIPTION("IDT821034 ALSA SoC driver"); 1152 MODULE_LICENSE("GPL"); 1153