1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _DP_PANEL_H_ 7 #define _DP_PANEL_H_ 8 9 #include <drm/drm_modes.h> 10 #include <drm/msm_drm.h> 11 12 #include "dp_aux.h" 13 #include "dp_link.h" 14 15 struct edid; 16 17 struct msm_dp_display_mode { 18 struct drm_display_mode drm_mode; 19 u32 bpp; 20 u32 h_active_low; 21 u32 v_active_low; 22 bool out_fmt_is_yuv_420; 23 }; 24 25 struct msm_dp_panel_psr { 26 u8 version; 27 u8 capabilities; 28 }; 29 30 /* stream id */ 31 enum msm_dp_stream_id { 32 DP_STREAM_0, 33 DP_STREAM_1, 34 DP_STREAM_2, 35 DP_STREAM_3, 36 DP_STREAM_MAX, 37 }; 38 39 struct msm_dp_panel { 40 /* dpcd raw data */ 41 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 42 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 43 44 struct msm_dp_link_info link_info; 45 struct drm_connector *connector; 46 struct msm_dp_display_mode msm_dp_mode; 47 struct msm_dp_panel_psr psr_cap; 48 bool video_test; 49 bool vsc_sdp_supported; 50 u32 hw_revision; 51 52 enum msm_dp_stream_id stream_id; 53 54 u32 max_bw_code; 55 }; 56 57 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel, 58 const struct drm_display_mode *adjusted_mode, 59 u32 bpp); 60 int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); 61 int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en); 62 int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, 63 struct drm_connector *connector); 64 u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_max_bpp, 65 u32 mode_pclk_khz); 66 void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, 67 const struct drm_edid *drm_edid); 68 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable); 69 70 void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel); 71 72 void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp); 73 void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); 74 75 /** 76 * is_link_rate_valid() - validates the link rate 77 * @bw_code: link rate requested by the sink 78 * 79 * Returns: true if the requested link rate is supported. 80 */ 81 static inline bool is_link_rate_valid(u32 bw_code) 82 { 83 return (bw_code == DP_LINK_BW_1_62 || 84 bw_code == DP_LINK_BW_2_7 || 85 bw_code == DP_LINK_BW_5_4 || 86 bw_code == DP_LINK_BW_8_1); 87 } 88 89 /** 90 * is_lane_count_valid() - validates the lane count 91 * @lane_count: lane count requested by the sink 92 * 93 * Returns: true if the requested lane count is supported. 94 */ 95 static inline bool is_lane_count_valid(u32 lane_count) 96 { 97 return (lane_count == 1 || 98 lane_count == 2 || 99 lane_count == 4); 100 } 101 102 u32 msm_dp_stream_reg(enum msm_dp_stream_id id, u32 reg); 103 104 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, 105 struct msm_dp_link *link, 106 void __iomem *link_base, 107 void __iomem *mst2link_base, 108 void __iomem *mst3link_base, 109 void __iomem *pixel_base); 110 #endif /* _DP_PANEL_H_ */ 111