1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bitmap.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/spmi.h> 23 24 /* PMIC Arbiter configuration registers */ 25 #define PMIC_ARB_VERSION 0x0000 26 #define PMIC_ARB_VERSION_V2_MIN 0x20010000 27 #define PMIC_ARB_VERSION_V3_MIN 0x30000000 28 #define PMIC_ARB_VERSION_V5_MIN 0x50000000 29 #define PMIC_ARB_VERSION_V7_MIN 0x70000000 30 #define PMIC_ARB_VERSION_V8_MIN 0x80000000 31 #define PMIC_ARB_VERSION_V8P5_MIN 0x80050000 32 #define PMIC_ARB_INT_EN 0x0004 33 34 #define PMIC_ARB_FEATURES 0x0004 35 #define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0) 36 #define PMIC_ARB_FEATURES_V8_PERIPH_MASK GENMASK(12, 0) 37 38 /* PMIC Arbiter channel registers offsets */ 39 #define PMIC_ARB_CMD 0x00 40 #define PMIC_ARB_CONFIG 0x04 41 #define PMIC_ARB_STATUS 0x08 42 #define PMIC_ARB_WDATA0 0x10 43 #define PMIC_ARB_WDATA1 0x14 44 #define PMIC_ARB_RDATA0 0x18 45 #define PMIC_ARB_RDATA1 0x1C 46 47 /* Mapping Table */ 48 #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N))) 49 #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF) 50 #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1) 51 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF) 52 #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1) 53 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF) 54 55 #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */ 56 #define PMIC_ARB_MAX_PPID BIT(13) 57 #define PMIC_ARB_APID_VALID BIT(15) 58 #define PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK BIT(24) 59 #define PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK BIT(31) 60 61 #define INVALID_EE 0xFF 62 63 /* Ownership Table */ 64 #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7) 65 66 /* Command register fields */ 67 #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8 68 69 /* Command Opcodes */ 70 enum pmic_arb_cmd_op_code { 71 PMIC_ARB_OP_EXT_WRITEL = 0, 72 PMIC_ARB_OP_EXT_READL = 1, 73 PMIC_ARB_OP_EXT_WRITE = 2, 74 PMIC_ARB_OP_RESET = 3, 75 PMIC_ARB_OP_SLEEP = 4, 76 PMIC_ARB_OP_SHUTDOWN = 5, 77 PMIC_ARB_OP_WAKEUP = 6, 78 PMIC_ARB_OP_AUTHENTICATE = 7, 79 PMIC_ARB_OP_MSTR_READ = 8, 80 PMIC_ARB_OP_MSTR_WRITE = 9, 81 PMIC_ARB_OP_EXT_READ = 13, 82 PMIC_ARB_OP_WRITE = 14, 83 PMIC_ARB_OP_READ = 15, 84 PMIC_ARB_OP_ZERO_WRITE = 16, 85 }; 86 87 /* 88 * PMIC arbiter version 5 uses different register offsets for read/write vs 89 * observer channels. 90 */ 91 enum pmic_arb_channel { 92 PMIC_ARB_CHANNEL_RW, 93 PMIC_ARB_CHANNEL_OBS, 94 }; 95 96 #define PMIC_ARB_MAX_BUSES 4 97 98 /* Maximum number of support PMIC peripherals */ 99 #define PMIC_ARB_MAX_PERIPHS 512 100 #define PMIC_ARB_MAX_PERIPHS_V7 1024 101 #define PMIC_ARB_MAX_PERIPHS_V8 8192 102 #define PMIC_ARB_TIMEOUT_US 1000 103 #define PMIC_ARB_MAX_TRANS_BYTES (8) 104 105 #define PMIC_ARB_APID_MASK 0xFF 106 #define PMIC_ARB_PPID_MASK GENMASK(11, 0) 107 #define PMIC_ARB_V8_PPID_MASK GENMASK(12, 0) 108 109 /* interrupt enable bit */ 110 #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) 111 112 #define HWIRQ_SID_MASK GENMASK(28, 24) 113 #define HWIRQ_PID_MASK GENMASK(23, 16) 114 #define HWIRQ_IRQID_MASK GENMASK(15, 13) 115 #define HWIRQ_APID_MASK GENMASK(12, 0) 116 117 #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \ 118 (FIELD_PREP(HWIRQ_SID_MASK, (slave_id)) | \ 119 FIELD_PREP(HWIRQ_PID_MASK, (periph_id)) | \ 120 FIELD_PREP(HWIRQ_IRQID_MASK, (irq_id)) | \ 121 FIELD_PREP(HWIRQ_APID_MASK, (apid))) 122 123 #define hwirq_to_sid(hwirq) FIELD_GET(HWIRQ_SID_MASK, (hwirq)) 124 #define hwirq_to_per(hwirq) FIELD_GET(HWIRQ_PID_MASK, (hwirq)) 125 #define hwirq_to_irq(hwirq) FIELD_GET(HWIRQ_IRQID_MASK, (hwirq)) 126 #define hwirq_to_apid(hwirq) FIELD_GET(HWIRQ_APID_MASK, (hwirq)) 127 128 struct pmic_arb_ver_ops; 129 130 struct apid_data { 131 u16 ppid; 132 u8 write_ee; 133 u8 irq_ee; 134 }; 135 136 struct spmi_pmic_arb; 137 138 /** 139 * struct spmi_pmic_arb_bus - SPMI PMIC Arbiter Bus object 140 * 141 * @pmic_arb: the SPMI PMIC Arbiter the bus belongs to. 142 * @domain: irq domain object for PMIC IRQ domain 143 * @intr: address of the SPMI interrupt control registers. 144 * @cnfg: address of the PMIC Arbiter configuration registers. 145 * @apid_owner: on v8: address of APID owner mapping table registers 146 * @spmic: spmi controller registered for this bus 147 * @lock: lock to synchronize accesses. 148 * @base_apid: on v7 and v8: minimum APID associated with the 149 * particular SPMI bus instance 150 * @apid_count: on v5, v7 and v8: number of APIDs associated with the 151 * particular SPMI bus instance 152 * @mapping_table: in-memory copy of PPID -> APID mapping table. 153 * @mapping_table_valid:bitmap containing valid-only periphs 154 * @ppid_to_apid: in-memory copy of PPID -> APID mapping table. 155 * @last_apid: Highest value APID in use 156 * @apid_data: Table of data for all APIDs 157 * @min_apid: minimum APID (used for bounding IRQ search) 158 * @max_apid: maximum APID 159 * @irq: PMIC ARB interrupt. 160 * @id: unique ID of the bus 161 */ 162 struct spmi_pmic_arb_bus { 163 struct spmi_pmic_arb *pmic_arb; 164 struct irq_domain *domain; 165 void __iomem *intr; 166 void __iomem *cnfg; 167 void __iomem *apid_owner; 168 struct spmi_controller *spmic; 169 raw_spinlock_t lock; 170 u16 base_apid; 171 int apid_count; 172 u32 *mapping_table; 173 DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); 174 u16 *ppid_to_apid; 175 u16 last_apid; 176 struct apid_data *apid_data; 177 u16 min_apid; 178 u16 max_apid; 179 int irq; 180 u8 id; 181 }; 182 183 /** 184 * struct spmi_pmic_arb - SPMI PMIC Arbiter object 185 * 186 * @rd_base: on v1 "core", on v2 "observer" register base off DT. 187 * @wr_base: on v1 "core", on v2 "chnls" register base off DT. 188 * @core: core register base for v2 and above only (see above) 189 * @core_size: core register base size 190 * @apid_map: on v8, APID mapping table register base 191 * @channel: execution environment channel to use for accesses. 192 * @ee: the current Execution Environment 193 * @ver_ops: version dependent operations. 194 * @max_periphs: Number of elements in apid_data[] 195 * @buses: per arbiter buses instances 196 * @buses_available: number of buses registered 197 */ 198 struct spmi_pmic_arb { 199 void __iomem *rd_base; 200 void __iomem *wr_base; 201 void __iomem *core; 202 resource_size_t core_size; 203 void __iomem *apid_map; 204 u8 channel; 205 u8 ee; 206 const struct pmic_arb_ver_ops *ver_ops; 207 int max_periphs; 208 struct spmi_pmic_arb_bus *buses[PMIC_ARB_MAX_BUSES]; 209 int buses_available; 210 }; 211 212 /** 213 * struct pmic_arb_ver_ops - version dependent functionality. 214 * 215 * @ver_str: version string. 216 * @get_core_resources: initializes the core, observer and channels 217 * @get_bus_resources: requests per-SPMI bus register resources 218 * @init_apid: finds the apid base and count 219 * @ppid_to_apid: finds the apid for a given ppid. 220 * @non_data_cmd: on v1 issues an spmi non-data command. 221 * on v2 no HW support, returns -EOPNOTSUPP. 222 * @offset: on v1 offset of per-ee channel. 223 * on v2 offset of per-ee and per-ppid channel. 224 * @fmt_cmd: formats a GENI/SPMI command. 225 * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn 226 * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn. 227 * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn 228 * on v2 address of SPMI_PIC_ACC_ENABLEn. 229 * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn 230 * on v2 address of SPMI_PIC_IRQ_STATUSn. 231 * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn 232 * on v2 address of SPMI_PIC_IRQ_CLEARn. 233 * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn 234 * @apid_owner: on v2 and later address of SPMI_PERIPHn_2OWNER_TABLE_REG 235 * @check_chnl_status: checks channel status and returns error code if any 236 */ 237 struct pmic_arb_ver_ops { 238 const char *ver_str; 239 int (*get_core_resources)(struct platform_device *pdev, void __iomem *core); 240 int (*get_bus_resources)(struct platform_device *pdev, 241 struct device_node *node, 242 struct spmi_pmic_arb_bus *bus); 243 int (*init_apid)(struct spmi_pmic_arb_bus *bus, int index); 244 int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid); 245 /* spmi commands (read_cmd, write_cmd, cmd) functionality */ 246 int (*offset)(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 247 enum pmic_arb_channel ch_type); 248 u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); 249 int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); 250 /* Interrupts controller functionality (offset of PIC registers) */ 251 void __iomem *(*owner_acc_status)(struct spmi_pmic_arb_bus *bus, u8 m, 252 u16 n); 253 void __iomem *(*acc_enable)(struct spmi_pmic_arb_bus *bus, u16 n); 254 void __iomem *(*irq_status)(struct spmi_pmic_arb_bus *bus, u16 n); 255 void __iomem *(*irq_clear)(struct spmi_pmic_arb_bus *bus, u16 n); 256 u32 (*apid_map_offset)(u16 n); 257 void __iomem *(*apid_owner)(struct spmi_pmic_arb_bus *bus, u16 n); 258 int (*check_chnl_status)(struct spmi_controller *ctrl, u32 status, 259 u8 sid, u16 addr, u32 offset); 260 }; 261 262 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb, 263 u32 offset, u32 val) 264 { 265 writel_relaxed(val, pmic_arb->wr_base + offset); 266 } 267 268 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb, 269 u32 offset, u32 val) 270 { 271 writel_relaxed(val, pmic_arb->rd_base + offset); 272 } 273 274 /** 275 * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf 276 * @pmic_arb: the SPMI PMIC arbiter 277 * @bc: byte count -1. range: 0..3 278 * @reg: register's address 279 * @buf: output parameter, length must be bc + 1 280 */ 281 static void 282 pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc) 283 { 284 u32 data = __raw_readl(pmic_arb->rd_base + reg); 285 286 memcpy(buf, &data, (bc & 3) + 1); 287 } 288 289 /** 290 * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register 291 * @pmic_arb: the SPMI PMIC arbiter 292 * @bc: byte-count -1. range: 0..3. 293 * @reg: register's address. 294 * @buf: buffer to write. length must be bc + 1. 295 */ 296 static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf, 297 u32 reg, u8 bc) 298 { 299 u32 data = 0; 300 301 memcpy(&data, buf, (bc & 3) + 1); 302 __raw_writel(data, pmic_arb->wr_base + reg); 303 } 304 305 static int pmic_arb_check_chnl_status_v1(struct spmi_controller *ctrl, 306 u32 status, u8 sid, u16 addr, 307 u32 offset) 308 { 309 /* Check if DONE bit is set */ 310 if (!(status & BIT(0))) 311 return -EAGAIN; 312 313 if (status & BIT(1)) { 314 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x) reg: 0x%x\n", 315 __func__, sid, addr, status, offset); 316 WARN_ON(1); 317 return -EIO; 318 } 319 320 if (status & BIT(2)) { 321 dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n", 322 __func__, sid, addr, status); 323 return -EPERM; 324 } 325 326 if (status & BIT(3)) { 327 dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n", 328 __func__, sid, addr, status); 329 return -EIO; 330 } 331 332 return 0; 333 } 334 335 static int pmic_arb_check_chnl_status_v8p5(struct spmi_controller *ctrl, 336 u32 status, u8 sid, u16 addr, 337 u32 offset) 338 { 339 /* Check if DONE bit is set */ 340 if (!(status & BIT(0))) 341 return -EAGAIN; 342 343 if (status & BIT(1)) { 344 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x) reg: 0x%x\n", 345 __func__, sid, addr, status, offset); 346 WARN_ON(1); 347 return -EIO; 348 } 349 350 if (status & BIT(2)) { 351 dev_err(&ctrl->dev, "%s: %#x %#x: CRC error (%#x)\n", 352 __func__, sid, addr, status); 353 return -EIO; 354 } 355 356 if (status & BIT(3)) { 357 dev_err(&ctrl->dev, "%s: %#x %#x: parity error (%#x)\n", 358 __func__, sid, addr, status); 359 return -EIO; 360 } 361 362 if (status & BIT(4)) { 363 dev_err(&ctrl->dev, "%s: %#x %#x: NACK error (%#x)\n", 364 __func__, sid, addr, status); 365 return -EIO; 366 } 367 368 if (status & BIT(5)) { 369 dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n", 370 __func__, sid, addr, status); 371 return -EPERM; 372 } 373 374 if (status & BIT(6)) { 375 dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n", 376 __func__, sid, addr, status); 377 return -EIO; 378 } 379 380 return 0; 381 } 382 383 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, 384 void __iomem *base, u8 sid, u16 addr, 385 enum pmic_arb_channel ch_type) 386 { 387 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 388 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 389 u32 status = 0; 390 u32 timeout = PMIC_ARB_TIMEOUT_US; 391 u32 offset; 392 int rc; 393 394 rc = pmic_arb->ver_ops->offset(bus, sid, addr, ch_type); 395 if (rc < 0) 396 return rc; 397 398 offset = rc; 399 offset += PMIC_ARB_STATUS; 400 401 while (timeout--) { 402 status = readl_relaxed(base + offset); 403 404 rc = pmic_arb->ver_ops->check_chnl_status(ctrl, status, sid, addr, offset); 405 if (rc != -EAGAIN) 406 return rc; 407 408 udelay(1); 409 } 410 411 dev_err(&ctrl->dev, "%s: %#x %#x %#x: timeout, status %#x\n", 412 __func__, bus->id, sid, addr, status); 413 return -ETIMEDOUT; 414 } 415 416 static int 417 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) 418 { 419 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 420 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 421 unsigned long flags; 422 u32 cmd; 423 int rc; 424 u32 offset; 425 426 rc = pmic_arb->ver_ops->offset(bus, sid, 0, PMIC_ARB_CHANNEL_RW); 427 if (rc < 0) 428 return rc; 429 430 offset = rc; 431 cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); 432 433 raw_spin_lock_irqsave(&bus->lock, flags); 434 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); 435 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0, 436 PMIC_ARB_CHANNEL_RW); 437 raw_spin_unlock_irqrestore(&bus->lock, flags); 438 439 return rc; 440 } 441 442 static int 443 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) 444 { 445 return -EOPNOTSUPP; 446 } 447 448 /* Non-data command */ 449 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) 450 { 451 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); 452 453 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); 454 455 /* Check for valid non-data command */ 456 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) 457 return -EINVAL; 458 459 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); 460 } 461 462 static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, u8 sid, 463 u16 addr, size_t len, u32 *cmd, u32 *offset) 464 { 465 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 466 u8 bc = len - 1; 467 int rc; 468 469 rc = pmic_arb->ver_ops->offset(bus, sid, addr, 470 PMIC_ARB_CHANNEL_OBS); 471 if (rc < 0) 472 return rc; 473 474 *offset = rc; 475 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { 476 dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested\n", 477 PMIC_ARB_MAX_TRANS_BYTES, len); 478 return -EINVAL; 479 } 480 481 /* Check the opcode */ 482 if (opc >= 0x60 && opc <= 0x7F) 483 opc = PMIC_ARB_OP_READ; 484 else if (opc >= 0x20 && opc <= 0x2F) 485 opc = PMIC_ARB_OP_EXT_READ; 486 else if (opc >= 0x38 && opc <= 0x3F) 487 opc = PMIC_ARB_OP_EXT_READL; 488 else 489 return -EINVAL; 490 491 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); 492 493 return 0; 494 } 495 496 static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd, 497 u32 offset, u8 sid, u16 addr, u8 *buf, 498 size_t len) 499 { 500 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 501 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 502 u8 bc = len - 1; 503 int rc; 504 505 pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd); 506 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr, 507 PMIC_ARB_CHANNEL_OBS); 508 if (rc) 509 return rc; 510 511 pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0, 512 min_t(u8, bc, 3)); 513 514 if (bc > 3) 515 pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1, 516 bc - 4); 517 return 0; 518 } 519 520 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 521 u16 addr, u8 *buf, size_t len) 522 { 523 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 524 unsigned long flags; 525 u32 cmd, offset; 526 int rc; 527 528 rc = pmic_arb_fmt_read_cmd(bus, opc, sid, addr, len, &cmd, 529 &offset); 530 if (rc) 531 return rc; 532 533 raw_spin_lock_irqsave(&bus->lock, flags); 534 rc = pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len); 535 raw_spin_unlock_irqrestore(&bus->lock, flags); 536 537 return rc; 538 } 539 540 static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, 541 u8 sid, u16 addr, size_t len, u32 *cmd, 542 u32 *offset) 543 { 544 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 545 u8 bc = len - 1; 546 int rc; 547 548 rc = pmic_arb->ver_ops->offset(bus, sid, addr, 549 PMIC_ARB_CHANNEL_RW); 550 if (rc < 0) 551 return rc; 552 553 *offset = rc; 554 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { 555 dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested\n", 556 PMIC_ARB_MAX_TRANS_BYTES, len); 557 return -EINVAL; 558 } 559 560 /* Check the opcode */ 561 if (opc >= 0x40 && opc <= 0x5F) 562 opc = PMIC_ARB_OP_WRITE; 563 else if (opc <= 0x0F) 564 opc = PMIC_ARB_OP_EXT_WRITE; 565 else if (opc >= 0x30 && opc <= 0x37) 566 opc = PMIC_ARB_OP_EXT_WRITEL; 567 else if (opc >= 0x80) 568 opc = PMIC_ARB_OP_ZERO_WRITE; 569 else 570 return -EINVAL; 571 572 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); 573 574 return 0; 575 } 576 577 static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd, 578 u32 offset, u8 sid, u16 addr, 579 const u8 *buf, size_t len) 580 { 581 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 582 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 583 u8 bc = len - 1; 584 585 /* Write data to FIFOs */ 586 pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0, 587 min_t(u8, bc, 3)); 588 if (bc > 3) 589 pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1, 590 bc - 4); 591 592 /* Start the transaction */ 593 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); 594 return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr, 595 PMIC_ARB_CHANNEL_RW); 596 } 597 598 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 599 u16 addr, const u8 *buf, size_t len) 600 { 601 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 602 unsigned long flags; 603 u32 cmd, offset; 604 int rc; 605 606 rc = pmic_arb_fmt_write_cmd(bus, opc, sid, addr, len, &cmd, 607 &offset); 608 if (rc) 609 return rc; 610 611 raw_spin_lock_irqsave(&bus->lock, flags); 612 rc = pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, 613 len); 614 raw_spin_unlock_irqrestore(&bus->lock, flags); 615 616 return rc; 617 } 618 619 static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr, 620 const u8 *buf, const u8 *mask, size_t len) 621 { 622 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 623 u32 read_cmd, read_offset, write_cmd, write_offset; 624 u8 temp[PMIC_ARB_MAX_TRANS_BYTES]; 625 unsigned long flags; 626 int rc, i; 627 628 rc = pmic_arb_fmt_read_cmd(bus, SPMI_CMD_EXT_READL, sid, addr, len, 629 &read_cmd, &read_offset); 630 if (rc) 631 return rc; 632 633 rc = pmic_arb_fmt_write_cmd(bus, SPMI_CMD_EXT_WRITEL, sid, addr, 634 len, &write_cmd, &write_offset); 635 if (rc) 636 return rc; 637 638 raw_spin_lock_irqsave(&bus->lock, flags); 639 rc = pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr, 640 temp, len); 641 if (rc) 642 goto done; 643 644 for (i = 0; i < len; i++) 645 temp[i] = (temp[i] & ~mask[i]) | (buf[i] & mask[i]); 646 647 rc = pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid, 648 addr, temp, len); 649 done: 650 raw_spin_unlock_irqrestore(&bus->lock, flags); 651 652 return rc; 653 } 654 655 enum qpnpint_regs { 656 QPNPINT_REG_RT_STS = 0x10, 657 QPNPINT_REG_SET_TYPE = 0x11, 658 QPNPINT_REG_POLARITY_HIGH = 0x12, 659 QPNPINT_REG_POLARITY_LOW = 0x13, 660 QPNPINT_REG_LATCHED_CLR = 0x14, 661 QPNPINT_REG_EN_SET = 0x15, 662 QPNPINT_REG_EN_CLR = 0x16, 663 QPNPINT_REG_LATCHED_STS = 0x18, 664 }; 665 666 struct spmi_pmic_arb_qpnpint_type { 667 u8 type; /* 1 -> edge */ 668 u8 polarity_high; 669 u8 polarity_low; 670 } __packed; 671 672 /* Simplified accessor functions for irqchip callbacks */ 673 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, 674 size_t len) 675 { 676 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 677 u8 sid = hwirq_to_sid(d->hwirq); 678 u8 per = hwirq_to_per(d->hwirq); 679 680 if (pmic_arb_write_cmd(bus->spmic, SPMI_CMD_EXT_WRITEL, sid, 681 (per << 8) + reg, buf, len)) 682 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n", 683 d->irq); 684 } 685 686 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) 687 { 688 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 689 u8 sid = hwirq_to_sid(d->hwirq); 690 u8 per = hwirq_to_per(d->hwirq); 691 692 if (pmic_arb_read_cmd(bus->spmic, SPMI_CMD_EXT_READL, sid, 693 (per << 8) + reg, buf, len)) 694 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n", 695 d->irq); 696 } 697 698 static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg, 699 const void *buf, const void *mask, 700 size_t len) 701 { 702 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 703 u8 sid = hwirq_to_sid(d->hwirq); 704 u8 per = hwirq_to_per(d->hwirq); 705 int rc; 706 707 rc = pmic_arb_masked_write(bus->spmic, sid, (per << 8) + reg, buf, 708 mask, len); 709 if (rc) 710 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x rc=%d\n", 711 d->irq, rc); 712 return rc; 713 } 714 715 static void cleanup_irq(struct spmi_pmic_arb_bus *bus, u16 apid, int id) 716 { 717 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 718 u16 ppid = bus->apid_data[apid].ppid; 719 u8 sid = ppid >> 8; 720 u8 per = ppid & 0xFF; 721 u8 irq_mask = BIT(id); 722 723 dev_err_ratelimited(&bus->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", 724 __func__, apid, sid, per, id); 725 writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(bus, apid)); 726 } 727 728 static int periph_interrupt(struct spmi_pmic_arb_bus *bus, u16 apid) 729 { 730 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 731 unsigned int irq; 732 u32 status, id; 733 int handled = 0; 734 u8 sid = (bus->apid_data[apid].ppid >> 8) & 0x1F; 735 u8 per = bus->apid_data[apid].ppid & 0xFF; 736 737 status = readl_relaxed(pmic_arb->ver_ops->irq_status(bus, apid)); 738 while (status) { 739 id = ffs(status) - 1; 740 status &= ~BIT(id); 741 irq = irq_find_mapping(bus->domain, 742 spec_to_hwirq(sid, per, id, apid)); 743 if (irq == 0) { 744 cleanup_irq(bus, apid, id); 745 continue; 746 } 747 generic_handle_irq(irq); 748 handled++; 749 } 750 751 return handled; 752 } 753 754 static void pmic_arb_chained_irq(struct irq_desc *desc) 755 { 756 struct spmi_pmic_arb_bus *bus = irq_desc_get_handler_data(desc); 757 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 758 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; 759 struct irq_chip *chip = irq_desc_get_chip(desc); 760 int first = bus->min_apid; 761 int last = bus->max_apid; 762 /* 763 * acc_offset will be non-zero for the secondary SPMI bus instance on 764 * v7 and v8 controllers. 765 */ 766 int acc_offset = bus->base_apid >> 5; 767 u8 ee = pmic_arb->ee; 768 u32 status, enable, handled = 0; 769 int i, id, apid; 770 /* status based dispatch */ 771 bool acc_valid = false; 772 u32 irq_status = 0; 773 774 chained_irq_enter(chip, desc); 775 776 for (i = first >> 5; i <= last >> 5; ++i) { 777 status = readl_relaxed(ver_ops->owner_acc_status(bus, ee, i - acc_offset)); 778 if (status) 779 acc_valid = true; 780 781 while (status) { 782 id = ffs(status) - 1; 783 status &= ~BIT(id); 784 apid = id + i * 32; 785 if (apid < first || apid > last) { 786 WARN_ONCE(true, "spurious spmi irq received for apid=%d\n", 787 apid); 788 continue; 789 } 790 enable = readl_relaxed( 791 ver_ops->acc_enable(bus, apid)); 792 if (enable & SPMI_PIC_ACC_ENABLE_BIT) 793 if (periph_interrupt(bus, apid) != 0) 794 handled++; 795 } 796 } 797 798 /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ 799 if (!acc_valid) { 800 for (i = first; i <= last; i++) { 801 /* skip if APPS is not irq owner */ 802 if (bus->apid_data[i].irq_ee != pmic_arb->ee) 803 continue; 804 805 irq_status = readl_relaxed( 806 ver_ops->irq_status(bus, i)); 807 if (irq_status) { 808 enable = readl_relaxed( 809 ver_ops->acc_enable(bus, i)); 810 if (enable & SPMI_PIC_ACC_ENABLE_BIT) { 811 dev_dbg(&bus->spmic->dev, 812 "Dispatching IRQ for apid=%d status=%x\n", 813 i, irq_status); 814 if (periph_interrupt(bus, i) != 0) 815 handled++; 816 } 817 } 818 } 819 } 820 821 if (handled == 0) 822 handle_bad_irq(desc); 823 824 chained_irq_exit(chip, desc); 825 } 826 827 static void qpnpint_irq_ack(struct irq_data *d) 828 { 829 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 830 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 831 u8 irq = hwirq_to_irq(d->hwirq); 832 u16 apid = hwirq_to_apid(d->hwirq); 833 u8 data; 834 835 writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(bus, apid)); 836 837 data = BIT(irq); 838 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); 839 } 840 841 static void qpnpint_irq_mask(struct irq_data *d) 842 { 843 u8 irq = hwirq_to_irq(d->hwirq); 844 u8 data = BIT(irq); 845 846 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); 847 } 848 849 static void qpnpint_irq_unmask(struct irq_data *d) 850 { 851 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 852 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 853 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; 854 u8 irq = hwirq_to_irq(d->hwirq); 855 u16 apid = hwirq_to_apid(d->hwirq); 856 u8 buf[2]; 857 858 writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, 859 ver_ops->acc_enable(bus, apid)); 860 861 qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); 862 if (!(buf[0] & BIT(irq))) { 863 /* 864 * Since the interrupt is currently disabled, write to both the 865 * LATCHED_CLR and EN_SET registers so that a spurious interrupt 866 * cannot be triggered when the interrupt is enabled 867 */ 868 buf[0] = BIT(irq); 869 buf[1] = BIT(irq); 870 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2); 871 } 872 } 873 874 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) 875 { 876 struct spmi_pmic_arb_qpnpint_type type = {0}; 877 struct spmi_pmic_arb_qpnpint_type mask; 878 irq_flow_handler_t flow_handler; 879 u8 irq_bit = BIT(hwirq_to_irq(d->hwirq)); 880 int rc; 881 882 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 883 type.type = irq_bit; 884 if (flow_type & IRQF_TRIGGER_RISING) 885 type.polarity_high = irq_bit; 886 if (flow_type & IRQF_TRIGGER_FALLING) 887 type.polarity_low = irq_bit; 888 889 flow_handler = handle_edge_irq; 890 } else { 891 if ((flow_type & (IRQF_TRIGGER_HIGH)) && 892 (flow_type & (IRQF_TRIGGER_LOW))) 893 return -EINVAL; 894 895 if (flow_type & IRQF_TRIGGER_HIGH) 896 type.polarity_high = irq_bit; 897 else 898 type.polarity_low = irq_bit; 899 900 flow_handler = handle_level_irq; 901 } 902 903 mask.type = irq_bit; 904 mask.polarity_high = irq_bit; 905 mask.polarity_low = irq_bit; 906 907 rc = qpnpint_spmi_masked_write(d, QPNPINT_REG_SET_TYPE, &type, &mask, 908 sizeof(type)); 909 irq_set_handler_locked(d, flow_handler); 910 911 return rc; 912 } 913 914 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on) 915 { 916 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 917 918 return irq_set_irq_wake(bus->irq, on); 919 } 920 921 static int qpnpint_get_irqchip_state(struct irq_data *d, 922 enum irqchip_irq_state which, 923 bool *state) 924 { 925 u8 irq = hwirq_to_irq(d->hwirq); 926 u8 status = 0; 927 928 if (which != IRQCHIP_STATE_LINE_LEVEL) 929 return -EINVAL; 930 931 qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1); 932 *state = !!(status & BIT(irq)); 933 934 return 0; 935 } 936 937 static int qpnpint_irq_domain_activate(struct irq_domain *domain, 938 struct irq_data *d, bool reserve) 939 { 940 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 941 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 942 u16 periph = hwirq_to_per(d->hwirq); 943 u16 apid = hwirq_to_apid(d->hwirq); 944 u16 sid = hwirq_to_sid(d->hwirq); 945 u16 irq = hwirq_to_irq(d->hwirq); 946 u8 buf; 947 948 if (bus->apid_data[apid].irq_ee != pmic_arb->ee) { 949 dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", 950 sid, periph, irq, pmic_arb->ee, 951 bus->apid_data[apid].irq_ee); 952 return -ENODEV; 953 } 954 955 buf = BIT(irq); 956 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); 957 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); 958 959 return 0; 960 } 961 962 static struct irq_chip pmic_arb_irqchip = { 963 .name = "pmic_arb", 964 .irq_ack = qpnpint_irq_ack, 965 .irq_mask = qpnpint_irq_mask, 966 .irq_unmask = qpnpint_irq_unmask, 967 .irq_set_type = qpnpint_irq_set_type, 968 .irq_set_wake = qpnpint_irq_set_wake, 969 .irq_get_irqchip_state = qpnpint_get_irqchip_state, 970 .flags = IRQCHIP_MASK_ON_SUSPEND, 971 }; 972 973 static int qpnpint_irq_domain_translate(struct irq_domain *d, 974 struct irq_fwspec *fwspec, 975 unsigned long *out_hwirq, 976 unsigned int *out_type) 977 { 978 struct spmi_pmic_arb_bus *bus = d->host_data; 979 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 980 u32 *intspec = fwspec->param; 981 u16 apid, ppid; 982 int rc; 983 984 dev_dbg(&bus->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", 985 intspec[0], intspec[1], intspec[2]); 986 987 if (irq_domain_get_of_node(d) != bus->spmic->dev.of_node) 988 return -EINVAL; 989 if (fwspec->param_count != 4) 990 return -EINVAL; 991 if (intspec[0] > FIELD_MAX(HWIRQ_SID_MASK) || intspec[1] > FIELD_MAX(HWIRQ_PID_MASK) || 992 intspec[2] > FIELD_MAX(HWIRQ_IRQID_MASK)) 993 return -EINVAL; 994 995 ppid = intspec[0] << 8 | intspec[1]; 996 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid); 997 if (rc < 0) { 998 dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n", 999 intspec[0], intspec[1], intspec[2], rc); 1000 return rc; 1001 } 1002 1003 apid = rc; 1004 /* Keep track of {max,min}_apid for bounding search during interrupt */ 1005 if (apid > bus->max_apid) 1006 bus->max_apid = apid; 1007 if (apid < bus->min_apid) 1008 bus->min_apid = apid; 1009 1010 *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid); 1011 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; 1012 1013 dev_dbg(&bus->spmic->dev, "out_hwirq = %lu\n", *out_hwirq); 1014 1015 return 0; 1016 } 1017 1018 static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class; 1019 1020 static void qpnpint_irq_domain_map(struct spmi_pmic_arb_bus *bus, 1021 struct irq_domain *domain, unsigned int virq, 1022 irq_hw_number_t hwirq, unsigned int type) 1023 { 1024 irq_flow_handler_t handler; 1025 1026 dev_dbg(&bus->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n", 1027 virq, hwirq, type); 1028 1029 if (type & IRQ_TYPE_EDGE_BOTH) 1030 handler = handle_edge_irq; 1031 else 1032 handler = handle_level_irq; 1033 1034 1035 irq_set_lockdep_class(virq, &qpnpint_irq_lock_class, 1036 &qpnpint_irq_request_class); 1037 irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, bus, 1038 handler, NULL, NULL); 1039 } 1040 1041 static int qpnpint_irq_domain_alloc(struct irq_domain *domain, 1042 unsigned int virq, unsigned int nr_irqs, 1043 void *data) 1044 { 1045 struct spmi_pmic_arb_bus *bus = domain->host_data; 1046 struct irq_fwspec *fwspec = data; 1047 irq_hw_number_t hwirq; 1048 unsigned int type; 1049 int ret, i; 1050 1051 ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type); 1052 if (ret) 1053 return ret; 1054 1055 for (i = 0; i < nr_irqs; i++) 1056 qpnpint_irq_domain_map(bus, domain, virq + i, hwirq + i, 1057 type); 1058 1059 return 0; 1060 } 1061 1062 static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb_bus *bus) 1063 { 1064 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1065 1066 /* 1067 * Initialize max_apid/min_apid to the opposite bounds, during 1068 * the irq domain translation, we are sure to update these 1069 */ 1070 bus->max_apid = 0; 1071 bus->min_apid = pmic_arb->max_periphs - 1; 1072 1073 return 0; 1074 } 1075 1076 static int pmic_arb_get_core_resources_v1(struct platform_device *pdev, 1077 void __iomem *core) 1078 { 1079 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1080 1081 pmic_arb->wr_base = core; 1082 pmic_arb->rd_base = core; 1083 1084 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS; 1085 1086 return 0; 1087 } 1088 1089 static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus, int index) 1090 { 1091 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1092 u32 *mapping_table; 1093 1094 if (index) { 1095 dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n", 1096 index); 1097 return -EINVAL; 1098 } 1099 1100 mapping_table = devm_kzalloc_objs(&bus->spmic->dev, *mapping_table, 1101 pmic_arb->max_periphs); 1102 if (!mapping_table) 1103 return -ENOMEM; 1104 1105 bus->mapping_table = mapping_table; 1106 1107 return pmic_arb_init_apid_min_max(bus); 1108 } 1109 1110 static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb_bus *bus, u16 ppid) 1111 { 1112 u32 *mapping_table = bus->mapping_table; 1113 int index = 0, i; 1114 u16 apid_valid; 1115 u16 apid; 1116 u32 data; 1117 1118 apid_valid = bus->ppid_to_apid[ppid]; 1119 if (apid_valid & PMIC_ARB_APID_VALID) { 1120 apid = apid_valid & ~PMIC_ARB_APID_VALID; 1121 return apid; 1122 } 1123 1124 for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { 1125 if (!test_and_set_bit(index, bus->mapping_table_valid)) 1126 mapping_table[index] = readl_relaxed(bus->cnfg + 1127 SPMI_MAPPING_TABLE_REG(index)); 1128 1129 data = mapping_table[index]; 1130 1131 if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) { 1132 if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { 1133 index = SPMI_MAPPING_BIT_IS_1_RESULT(data); 1134 } else { 1135 apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); 1136 bus->ppid_to_apid[ppid] 1137 = apid | PMIC_ARB_APID_VALID; 1138 bus->apid_data[apid].ppid = ppid; 1139 return apid; 1140 } 1141 } else { 1142 if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { 1143 index = SPMI_MAPPING_BIT_IS_0_RESULT(data); 1144 } else { 1145 apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); 1146 bus->ppid_to_apid[ppid] 1147 = apid | PMIC_ARB_APID_VALID; 1148 bus->apid_data[apid].ppid = ppid; 1149 return apid; 1150 } 1151 } 1152 } 1153 1154 return -ENODEV; 1155 } 1156 1157 /* v1 offset per ee */ 1158 static int pmic_arb_offset_v1(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1159 enum pmic_arb_channel ch_type) 1160 { 1161 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1162 return 0x800 + 0x80 * pmic_arb->channel; 1163 } 1164 1165 static u16 pmic_arb_find_apid(struct spmi_pmic_arb_bus *bus, u16 ppid) 1166 { 1167 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1168 struct apid_data *apidd = &bus->apid_data[bus->last_apid]; 1169 u32 regval, offset; 1170 u16 id, apid; 1171 1172 for (apid = bus->last_apid; ; apid++, apidd++) { 1173 offset = pmic_arb->ver_ops->apid_map_offset(apid); 1174 if (offset >= pmic_arb->core_size) 1175 break; 1176 1177 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, 1178 apid)); 1179 apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval); 1180 apidd->write_ee = apidd->irq_ee; 1181 1182 regval = readl_relaxed(pmic_arb->core + offset); 1183 if (!regval) 1184 continue; 1185 1186 id = (regval >> 8) & PMIC_ARB_PPID_MASK; 1187 bus->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID; 1188 apidd->ppid = id; 1189 if (id == ppid) { 1190 apid |= PMIC_ARB_APID_VALID; 1191 break; 1192 } 1193 } 1194 bus->last_apid = apid & ~PMIC_ARB_APID_VALID; 1195 1196 return apid; 1197 } 1198 1199 static int pmic_arb_get_obsrvr_chnls_v2(struct platform_device *pdev) 1200 { 1201 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1202 1203 pmic_arb->rd_base = devm_platform_ioremap_resource_byname(pdev, "obsrvr"); 1204 if (IS_ERR(pmic_arb->rd_base)) 1205 return PTR_ERR(pmic_arb->rd_base); 1206 1207 pmic_arb->wr_base = devm_platform_ioremap_resource_byname(pdev, "chnls"); 1208 if (IS_ERR(pmic_arb->wr_base)) 1209 return PTR_ERR(pmic_arb->wr_base); 1210 1211 return 0; 1212 } 1213 1214 static int pmic_arb_get_core_resources_v2(struct platform_device *pdev, 1215 void __iomem *core) 1216 { 1217 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1218 1219 pmic_arb->core = core; 1220 1221 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS; 1222 1223 return pmic_arb_get_obsrvr_chnls_v2(pdev); 1224 } 1225 1226 static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb_bus *bus, u16 ppid) 1227 { 1228 u16 apid_valid; 1229 1230 apid_valid = bus->ppid_to_apid[ppid]; 1231 if (!(apid_valid & PMIC_ARB_APID_VALID)) 1232 apid_valid = pmic_arb_find_apid(bus, ppid); 1233 if (!(apid_valid & PMIC_ARB_APID_VALID)) 1234 return -ENODEV; 1235 1236 return apid_valid & ~PMIC_ARB_APID_VALID; 1237 } 1238 1239 static int _pmic_arb_read_apid_map(struct spmi_pmic_arb_bus *bus, 1240 void __iomem *ppid_base, unsigned long ppid_mask, 1241 u8 ppid_shift, unsigned long irq_owner_mask) 1242 { 1243 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1244 struct apid_data *apidd; 1245 struct apid_data *prev_apidd; 1246 u16 i, apid, ppid, apid_max; 1247 bool valid, is_irq_ee; 1248 u32 regval, offset; 1249 1250 /* 1251 * In order to allow multiple EEs to write to a single PPID in arbiter 1252 * version 5,7 and 8, there can be more than one APID mapped to each PPID. 1253 * The owner field for each of these mappings specifies the EE which is 1254 * allowed to write to the APID. The owner of the last (highest) APID 1255 * which has the IRQ owner bit set for a given PPID will receive 1256 * interrupts from the PPID. 1257 * 1258 * In arbiter version 7, the APID numbering space is divided between 1259 * the primary bus (0) and secondary bus (1) such that: 1260 * APID = 0 to N-1 are assigned to the primary bus 1261 * APID = N to N+M-1 are assigned to the secondary bus 1262 * where N = number of APIDs supported by the primary bus and 1263 * M = number of APIDs supported by the secondary bus 1264 * 1265 * In arbiter version 8, the APID numbering space is divided between 1266 * the SPMI buses according to this mapping: 1267 * APID = 0 to N-1 --> bus 0 1268 * APID = N to N+M-1 --> bus 1 1269 * APID = N+M to N+M+P-1 --> bus 2 1270 * APID = N+M+P to N+M+P+Q-1 --> bus 3 1271 * where N = number of APIDs supported by bus 0 1272 * M = number of APIDs supported by bus 1 1273 * P = number of APIDs supported by bus 2 1274 * Q = number of APIDs supported by bus 3 1275 */ 1276 1277 apidd = &bus->apid_data[bus->base_apid]; 1278 apid_max = bus->base_apid + bus->apid_count; 1279 for (i = bus->base_apid; i < apid_max; i++, apidd++) { 1280 offset = pmic_arb->ver_ops->apid_map_offset(i); 1281 if (offset >= pmic_arb->core_size) 1282 break; 1283 regval = readl_relaxed(ppid_base + offset); 1284 if (!regval) 1285 continue; 1286 ppid = (regval >> ppid_shift) & ppid_mask; 1287 is_irq_ee = regval & irq_owner_mask; 1288 1289 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i)); 1290 apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval); 1291 1292 apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE; 1293 1294 valid = bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID; 1295 apid = bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; 1296 prev_apidd = &bus->apid_data[apid]; 1297 1298 if (!valid || apidd->write_ee == pmic_arb->ee) { 1299 /* First PPID mapping or one for this EE */ 1300 bus->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; 1301 } else if (valid && is_irq_ee && 1302 prev_apidd->write_ee == pmic_arb->ee) { 1303 /* 1304 * Duplicate PPID mapping after the one for this EE; 1305 * override the irq owner 1306 */ 1307 prev_apidd->irq_ee = apidd->irq_ee; 1308 } 1309 1310 apidd->ppid = ppid; 1311 bus->last_apid = i; 1312 } 1313 1314 /* Dump the mapping table for debug purposes. */ 1315 dev_dbg(&bus->spmic->dev, "PPID APID Write-EE IRQ-EE\n"); 1316 for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) { 1317 apid = bus->ppid_to_apid[ppid]; 1318 if (apid & PMIC_ARB_APID_VALID) { 1319 apid &= ~PMIC_ARB_APID_VALID; 1320 apidd = &bus->apid_data[apid]; 1321 dev_dbg(&bus->spmic->dev, "%#03X %3u %2u %2u\n", 1322 ppid, apid, apidd->write_ee, apidd->irq_ee); 1323 } 1324 } 1325 1326 return 0; 1327 } 1328 1329 static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus) 1330 { 1331 return _pmic_arb_read_apid_map(bus, bus->pmic_arb->core, PMIC_ARB_PPID_MASK, 1332 8, PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK); 1333 } 1334 1335 static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb_bus *bus, u16 ppid) 1336 { 1337 if (!(bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID)) 1338 return -ENODEV; 1339 1340 return bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; 1341 } 1342 1343 /* v2 offset per ppid and per ee */ 1344 static int pmic_arb_offset_v2(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1345 enum pmic_arb_channel ch_type) 1346 { 1347 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1348 u16 apid; 1349 u16 ppid; 1350 int rc; 1351 1352 ppid = sid << 8 | ((addr >> 8) & 0xFF); 1353 rc = pmic_arb_ppid_to_apid_v2(bus, ppid); 1354 if (rc < 0) 1355 return rc; 1356 1357 apid = rc; 1358 return 0x1000 * pmic_arb->ee + 0x8000 * apid; 1359 } 1360 1361 static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus, int index) 1362 { 1363 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1364 int ret; 1365 1366 if (index) { 1367 dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n", 1368 index); 1369 return -EINVAL; 1370 } 1371 1372 bus->base_apid = 0; 1373 bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & 1374 PMIC_ARB_FEATURES_PERIPH_MASK; 1375 1376 if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) { 1377 dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n", 1378 bus->base_apid + bus->apid_count); 1379 return -EINVAL; 1380 } 1381 1382 ret = pmic_arb_init_apid_min_max(bus); 1383 if (ret) 1384 return ret; 1385 1386 ret = pmic_arb_read_apid_map_v5(bus); 1387 if (ret) { 1388 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n", 1389 ret); 1390 return ret; 1391 } 1392 1393 return 0; 1394 } 1395 1396 /* 1397 * v5 offset per ee and per apid for observer channels and per apid for 1398 * read/write channels. 1399 */ 1400 static int pmic_arb_offset_v5(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1401 enum pmic_arb_channel ch_type) 1402 { 1403 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1404 u16 apid; 1405 int rc; 1406 u32 offset = 0; 1407 u16 ppid = (sid << 8) | (addr >> 8); 1408 1409 rc = pmic_arb_ppid_to_apid_v5(bus, ppid); 1410 if (rc < 0) 1411 return rc; 1412 1413 apid = rc; 1414 switch (ch_type) { 1415 case PMIC_ARB_CHANNEL_OBS: 1416 offset = 0x10000 * pmic_arb->ee + 0x80 * apid; 1417 break; 1418 case PMIC_ARB_CHANNEL_RW: 1419 if (bus->apid_data[apid].write_ee != pmic_arb->ee) { 1420 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", 1421 sid, addr); 1422 return -EPERM; 1423 } 1424 offset = 0x10000 * apid; 1425 break; 1426 } 1427 1428 return offset; 1429 } 1430 1431 static int pmic_arb_get_core_resources_v7(struct platform_device *pdev, 1432 void __iomem *core) 1433 { 1434 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1435 1436 pmic_arb->core = core; 1437 1438 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7; 1439 1440 return pmic_arb_get_obsrvr_chnls_v2(pdev); 1441 } 1442 1443 static int _pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index, 1444 int max_buses, unsigned long periph_mask) 1445 { 1446 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1447 int i; 1448 1449 if (index < 0 || index >= max_buses) { 1450 dev_err(&bus->spmic->dev, "Unsupported bus index %d detected\n", 1451 index); 1452 return -EINVAL; 1453 } 1454 1455 bus->base_apid = 0; 1456 bus->apid_count = 0; 1457 for (i = 0; i <= index; i++) { 1458 bus->base_apid += bus->apid_count; 1459 bus->apid_count = readl_relaxed(pmic_arb->core + 1460 PMIC_ARB_FEATURES + i * 4) & 1461 periph_mask; 1462 } 1463 1464 if (bus->apid_count == 0) { 1465 dev_err(&bus->spmic->dev, "Bus %d not implemented\n", index); 1466 return -EINVAL; 1467 } else if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) { 1468 dev_err(&bus->spmic->dev, "Unsupported max APID %d detected\n", 1469 bus->base_apid + bus->apid_count); 1470 return -EINVAL; 1471 } 1472 1473 return pmic_arb_init_apid_min_max(bus); 1474 } 1475 1476 /* 1477 * Arbiter v7 supports 2 buses. Each bus will get a different apid count, read 1478 * from different registers. 1479 */ 1480 static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index) 1481 { 1482 int ret = _pmic_arb_init_apid_v7(bus, index, 2, PMIC_ARB_FEATURES_PERIPH_MASK); 1483 if (ret) 1484 return ret; 1485 1486 ret = pmic_arb_read_apid_map_v5(bus); 1487 if (ret) { 1488 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n", 1489 ret); 1490 return ret; 1491 } 1492 1493 return 0; 1494 } 1495 1496 /* 1497 * v7 offset per ee and per apid for observer channels and per apid for 1498 * read/write channels. 1499 */ 1500 static int pmic_arb_offset_v7(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1501 enum pmic_arb_channel ch_type) 1502 { 1503 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1504 u16 apid; 1505 int rc; 1506 u32 offset = 0; 1507 u16 ppid = (sid << 8) | (addr >> 8); 1508 1509 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid); 1510 if (rc < 0) 1511 return rc; 1512 1513 apid = rc; 1514 switch (ch_type) { 1515 case PMIC_ARB_CHANNEL_OBS: 1516 offset = 0x8000 * pmic_arb->ee + 0x20 * apid; 1517 break; 1518 case PMIC_ARB_CHANNEL_RW: 1519 if (bus->apid_data[apid].write_ee != pmic_arb->ee) { 1520 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", 1521 sid, addr); 1522 return -EPERM; 1523 } 1524 offset = 0x1000 * apid; 1525 break; 1526 } 1527 1528 return offset; 1529 } 1530 1531 static int pmic_arb_get_core_resources_v8(struct platform_device *pdev, 1532 void __iomem *core) 1533 { 1534 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1535 1536 pmic_arb->apid_map = devm_platform_ioremap_resource_byname(pdev, "chnl_map"); 1537 if (IS_ERR(pmic_arb->apid_map)) 1538 return PTR_ERR(pmic_arb->apid_map); 1539 1540 pmic_arb->core = core; 1541 1542 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V8; 1543 1544 return pmic_arb_get_obsrvr_chnls_v2(pdev); 1545 } 1546 1547 static int pmic_arb_get_bus_resources_v8(struct platform_device *pdev, 1548 struct device_node *node, 1549 struct spmi_pmic_arb_bus *bus) 1550 { 1551 int index; 1552 1553 index = of_property_match_string(node, "reg-names", "chnl_owner"); 1554 if (index < 0) { 1555 dev_err(&pdev->dev, "chnl_owner reg region missing\n"); 1556 return -EINVAL; 1557 } 1558 1559 bus->apid_owner = devm_of_iomap(&pdev->dev, node, index, NULL); 1560 1561 return PTR_ERR_OR_ZERO(bus->apid_owner); 1562 } 1563 1564 static int pmic_arb_read_apid_map_v8(struct spmi_pmic_arb_bus *bus) 1565 { 1566 return _pmic_arb_read_apid_map(bus, bus->pmic_arb->apid_map, 1567 PMIC_ARB_V8_PPID_MASK, 0, 1568 PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK); 1569 } 1570 1571 /* 1572 * Arbiter v8 supports up to 4 buses. Each bus will get a different apid count, read 1573 * from different registers. 1574 */ 1575 static int pmic_arb_init_apid_v8(struct spmi_pmic_arb_bus *bus, int index) 1576 { 1577 int ret = _pmic_arb_init_apid_v7(bus, index, 4, 1578 PMIC_ARB_FEATURES_V8_PERIPH_MASK); 1579 if (ret) 1580 return ret; 1581 1582 ret = pmic_arb_read_apid_map_v8(bus); 1583 if (ret) { 1584 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n", 1585 ret); 1586 return ret; 1587 } 1588 1589 return 0; 1590 } 1591 1592 /* 1593 * v8 offset per ee and per apid for observer channels and per apid for 1594 * read/write channels. 1595 */ 1596 static int pmic_arb_offset_v8(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1597 enum pmic_arb_channel ch_type) 1598 { 1599 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1600 u16 apid; 1601 int rc; 1602 u32 offset = 0; 1603 u16 ppid = (sid << 8) | (addr >> 8); 1604 1605 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid); 1606 if (rc < 0) 1607 return rc; 1608 1609 apid = rc; 1610 switch (ch_type) { 1611 case PMIC_ARB_CHANNEL_OBS: 1612 offset = 0x40000 * pmic_arb->ee + 0x20 * apid; 1613 break; 1614 case PMIC_ARB_CHANNEL_RW: 1615 if (bus->apid_data[apid].write_ee != pmic_arb->ee) { 1616 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", 1617 sid, addr); 1618 return -EPERM; 1619 } 1620 offset = 0x200 * apid; 1621 break; 1622 } 1623 1624 return offset; 1625 } 1626 1627 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc) 1628 { 1629 return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7); 1630 } 1631 1632 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc) 1633 { 1634 return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); 1635 } 1636 1637 static void __iomem * 1638 pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1639 { 1640 return bus->intr + 0x20 * m + 0x4 * n; 1641 } 1642 1643 static void __iomem * 1644 pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1645 { 1646 return bus->intr + 0x100000 + 0x1000 * m + 0x4 * n; 1647 } 1648 1649 static void __iomem * 1650 pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1651 { 1652 return bus->intr + 0x200000 + 0x1000 * m + 0x4 * n; 1653 } 1654 1655 static void __iomem * 1656 pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1657 { 1658 return bus->intr + 0x10000 * m + 0x4 * n; 1659 } 1660 1661 static void __iomem * 1662 pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1663 { 1664 return bus->intr + 0x1000 * m + 0x4 * n; 1665 } 1666 1667 static void __iomem * 1668 pmic_arb_acc_enable_v1(struct spmi_pmic_arb_bus *bus, u16 n) 1669 { 1670 return bus->intr + 0x200 + 0x4 * n; 1671 } 1672 1673 static void __iomem * 1674 pmic_arb_acc_enable_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1675 { 1676 return bus->intr + 0x1000 * n; 1677 } 1678 1679 static void __iomem * 1680 pmic_arb_acc_enable_v5(struct spmi_pmic_arb_bus *bus, u16 n) 1681 { 1682 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1683 return pmic_arb->wr_base + 0x100 + 0x10000 * n; 1684 } 1685 1686 static void __iomem * 1687 pmic_arb_acc_enable_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1688 { 1689 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1690 return pmic_arb->wr_base + 0x100 + 0x1000 * n; 1691 } 1692 1693 static void __iomem * 1694 pmic_arb_acc_enable_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1695 { 1696 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1697 1698 return pmic_arb->wr_base + 0x100 + 0x200 * n; 1699 } 1700 1701 static void __iomem * 1702 pmic_arb_irq_status_v1(struct spmi_pmic_arb_bus *bus, u16 n) 1703 { 1704 return bus->intr + 0x600 + 0x4 * n; 1705 } 1706 1707 static void __iomem * 1708 pmic_arb_irq_status_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1709 { 1710 return bus->intr + 0x4 + 0x1000 * n; 1711 } 1712 1713 static void __iomem * 1714 pmic_arb_irq_status_v5(struct spmi_pmic_arb_bus *bus, u16 n) 1715 { 1716 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1717 return pmic_arb->wr_base + 0x104 + 0x10000 * n; 1718 } 1719 1720 static void __iomem * 1721 pmic_arb_irq_status_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1722 { 1723 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1724 return pmic_arb->wr_base + 0x104 + 0x1000 * n; 1725 } 1726 1727 static void __iomem * 1728 pmic_arb_irq_status_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1729 { 1730 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1731 1732 return pmic_arb->wr_base + 0x104 + 0x200 * n; 1733 } 1734 1735 static void __iomem * 1736 pmic_arb_irq_clear_v1(struct spmi_pmic_arb_bus *bus, u16 n) 1737 { 1738 return bus->intr + 0xA00 + 0x4 * n; 1739 } 1740 1741 static void __iomem * 1742 pmic_arb_irq_clear_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1743 { 1744 return bus->intr + 0x8 + 0x1000 * n; 1745 } 1746 1747 static void __iomem * 1748 pmic_arb_irq_clear_v5(struct spmi_pmic_arb_bus *bus, u16 n) 1749 { 1750 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1751 return pmic_arb->wr_base + 0x108 + 0x10000 * n; 1752 } 1753 1754 static void __iomem * 1755 pmic_arb_irq_clear_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1756 { 1757 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1758 return pmic_arb->wr_base + 0x108 + 0x1000 * n; 1759 } 1760 1761 static void __iomem * 1762 pmic_arb_irq_clear_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1763 { 1764 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1765 1766 return pmic_arb->wr_base + 0x108 + 0x200 * n; 1767 } 1768 1769 static u32 pmic_arb_apid_map_offset_v2(u16 n) 1770 { 1771 return 0x800 + 0x4 * n; 1772 } 1773 1774 static u32 pmic_arb_apid_map_offset_v5(u16 n) 1775 { 1776 return 0x900 + 0x4 * n; 1777 } 1778 1779 static u32 pmic_arb_apid_map_offset_v7(u16 n) 1780 { 1781 return 0x2000 + 0x4 * n; 1782 } 1783 1784 static u32 pmic_arb_apid_map_offset_v8(u16 n) 1785 { 1786 /* For v8, offset is from "chnl_map" base register, not "core". */ 1787 return 0x4 * n; 1788 } 1789 1790 static void __iomem * 1791 pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1792 { 1793 return bus->cnfg + 0x700 + 0x4 * n; 1794 } 1795 1796 /* 1797 * For arbiter version 7 and 8, APID ownership table registers have independent 1798 * numbering space for each SPMI bus instance, so each is indexed starting from 1799 * 0. 1800 */ 1801 static void __iomem * 1802 pmic_arb_apid_owner_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1803 { 1804 return bus->cnfg + 0x4 * (n - bus->base_apid); 1805 } 1806 1807 static void __iomem * 1808 pmic_arb_apid_owner_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1809 { 1810 return bus->apid_owner + 0x4 * (n - bus->base_apid); 1811 } 1812 1813 static const struct pmic_arb_ver_ops pmic_arb_v1 = { 1814 .ver_str = "v1", 1815 .get_core_resources = pmic_arb_get_core_resources_v1, 1816 .init_apid = pmic_arb_init_apid_v1, 1817 .ppid_to_apid = pmic_arb_ppid_to_apid_v1, 1818 .non_data_cmd = pmic_arb_non_data_cmd_v1, 1819 .offset = pmic_arb_offset_v1, 1820 .fmt_cmd = pmic_arb_fmt_cmd_v1, 1821 .owner_acc_status = pmic_arb_owner_acc_status_v1, 1822 .acc_enable = pmic_arb_acc_enable_v1, 1823 .irq_status = pmic_arb_irq_status_v1, 1824 .irq_clear = pmic_arb_irq_clear_v1, 1825 .apid_map_offset = pmic_arb_apid_map_offset_v2, 1826 .apid_owner = pmic_arb_apid_owner_v2, 1827 .check_chnl_status = pmic_arb_check_chnl_status_v1, 1828 }; 1829 1830 static const struct pmic_arb_ver_ops pmic_arb_v2 = { 1831 .ver_str = "v2", 1832 .get_core_resources = pmic_arb_get_core_resources_v2, 1833 .init_apid = pmic_arb_init_apid_v1, 1834 .ppid_to_apid = pmic_arb_ppid_to_apid_v2, 1835 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1836 .offset = pmic_arb_offset_v2, 1837 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1838 .owner_acc_status = pmic_arb_owner_acc_status_v2, 1839 .acc_enable = pmic_arb_acc_enable_v2, 1840 .irq_status = pmic_arb_irq_status_v2, 1841 .irq_clear = pmic_arb_irq_clear_v2, 1842 .apid_map_offset = pmic_arb_apid_map_offset_v2, 1843 .apid_owner = pmic_arb_apid_owner_v2, 1844 .check_chnl_status = pmic_arb_check_chnl_status_v1, 1845 }; 1846 1847 static const struct pmic_arb_ver_ops pmic_arb_v3 = { 1848 .ver_str = "v3", 1849 .get_core_resources = pmic_arb_get_core_resources_v2, 1850 .init_apid = pmic_arb_init_apid_v1, 1851 .ppid_to_apid = pmic_arb_ppid_to_apid_v2, 1852 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1853 .offset = pmic_arb_offset_v2, 1854 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1855 .owner_acc_status = pmic_arb_owner_acc_status_v3, 1856 .acc_enable = pmic_arb_acc_enable_v2, 1857 .irq_status = pmic_arb_irq_status_v2, 1858 .irq_clear = pmic_arb_irq_clear_v2, 1859 .apid_map_offset = pmic_arb_apid_map_offset_v2, 1860 .apid_owner = pmic_arb_apid_owner_v2, 1861 .check_chnl_status = pmic_arb_check_chnl_status_v1, 1862 }; 1863 1864 static const struct pmic_arb_ver_ops pmic_arb_v5 = { 1865 .ver_str = "v5", 1866 .get_core_resources = pmic_arb_get_core_resources_v2, 1867 .init_apid = pmic_arb_init_apid_v5, 1868 .ppid_to_apid = pmic_arb_ppid_to_apid_v5, 1869 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1870 .offset = pmic_arb_offset_v5, 1871 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1872 .owner_acc_status = pmic_arb_owner_acc_status_v5, 1873 .acc_enable = pmic_arb_acc_enable_v5, 1874 .irq_status = pmic_arb_irq_status_v5, 1875 .irq_clear = pmic_arb_irq_clear_v5, 1876 .apid_map_offset = pmic_arb_apid_map_offset_v5, 1877 .apid_owner = pmic_arb_apid_owner_v2, 1878 .check_chnl_status = pmic_arb_check_chnl_status_v1, 1879 }; 1880 1881 static const struct pmic_arb_ver_ops pmic_arb_v7 = { 1882 .ver_str = "v7", 1883 .get_core_resources = pmic_arb_get_core_resources_v7, 1884 .init_apid = pmic_arb_init_apid_v7, 1885 .ppid_to_apid = pmic_arb_ppid_to_apid_v5, 1886 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1887 .offset = pmic_arb_offset_v7, 1888 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1889 .owner_acc_status = pmic_arb_owner_acc_status_v7, 1890 .acc_enable = pmic_arb_acc_enable_v7, 1891 .irq_status = pmic_arb_irq_status_v7, 1892 .irq_clear = pmic_arb_irq_clear_v7, 1893 .apid_map_offset = pmic_arb_apid_map_offset_v7, 1894 .apid_owner = pmic_arb_apid_owner_v7, 1895 .check_chnl_status = pmic_arb_check_chnl_status_v1, 1896 }; 1897 1898 static const struct pmic_arb_ver_ops pmic_arb_v8 = { 1899 .ver_str = "v8", 1900 .get_core_resources = pmic_arb_get_core_resources_v8, 1901 .get_bus_resources = pmic_arb_get_bus_resources_v8, 1902 .init_apid = pmic_arb_init_apid_v8, 1903 .ppid_to_apid = pmic_arb_ppid_to_apid_v5, 1904 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1905 .offset = pmic_arb_offset_v8, 1906 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1907 .owner_acc_status = pmic_arb_owner_acc_status_v7, 1908 .acc_enable = pmic_arb_acc_enable_v8, 1909 .irq_status = pmic_arb_irq_status_v8, 1910 .irq_clear = pmic_arb_irq_clear_v8, 1911 .apid_map_offset = pmic_arb_apid_map_offset_v8, 1912 .apid_owner = pmic_arb_apid_owner_v8, 1913 .check_chnl_status = pmic_arb_check_chnl_status_v1, 1914 }; 1915 1916 static const struct pmic_arb_ver_ops pmic_arb_v8p5 = { 1917 .ver_str = "v8.5", 1918 .get_core_resources = pmic_arb_get_core_resources_v8, 1919 .get_bus_resources = pmic_arb_get_bus_resources_v8, 1920 .init_apid = pmic_arb_init_apid_v8, 1921 .ppid_to_apid = pmic_arb_ppid_to_apid_v5, 1922 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1923 .offset = pmic_arb_offset_v8, 1924 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1925 .owner_acc_status = pmic_arb_owner_acc_status_v7, 1926 .acc_enable = pmic_arb_acc_enable_v8, 1927 .irq_status = pmic_arb_irq_status_v8, 1928 .irq_clear = pmic_arb_irq_clear_v8, 1929 .apid_map_offset = pmic_arb_apid_map_offset_v8, 1930 .apid_owner = pmic_arb_apid_owner_v8, 1931 .check_chnl_status = pmic_arb_check_chnl_status_v8p5, 1932 }; 1933 1934 static const struct irq_domain_ops pmic_arb_irq_domain_ops = { 1935 .activate = qpnpint_irq_domain_activate, 1936 .alloc = qpnpint_irq_domain_alloc, 1937 .free = irq_domain_free_irqs_common, 1938 .translate = qpnpint_irq_domain_translate, 1939 }; 1940 1941 static int spmi_pmic_arb_bus_init(struct platform_device *pdev, 1942 struct device_node *node, 1943 struct spmi_pmic_arb *pmic_arb) 1944 { 1945 int bus_index = pmic_arb->buses_available; 1946 struct spmi_pmic_arb_bus *bus; 1947 struct device *dev = &pdev->dev; 1948 struct spmi_controller *ctrl; 1949 void __iomem *intr; 1950 void __iomem *cnfg; 1951 int index, ret; 1952 int irq; 1953 1954 ctrl = devm_spmi_controller_alloc(dev, sizeof(*bus)); 1955 if (IS_ERR(ctrl)) 1956 return PTR_ERR(ctrl); 1957 1958 ctrl->cmd = pmic_arb_cmd; 1959 ctrl->read_cmd = pmic_arb_read_cmd; 1960 ctrl->write_cmd = pmic_arb_write_cmd; 1961 1962 bus = spmi_controller_get_drvdata(ctrl); 1963 1964 pmic_arb->buses[bus_index] = bus; 1965 1966 raw_spin_lock_init(&bus->lock); 1967 1968 bus->ppid_to_apid = devm_kzalloc_objs(dev, *bus->ppid_to_apid, 1969 PMIC_ARB_MAX_PPID); 1970 if (!bus->ppid_to_apid) 1971 return -ENOMEM; 1972 1973 bus->apid_data = devm_kzalloc_objs(dev, *bus->apid_data, 1974 pmic_arb->max_periphs); 1975 if (!bus->apid_data) 1976 return -ENOMEM; 1977 1978 index = of_property_match_string(node, "reg-names", "cnfg"); 1979 if (index < 0) { 1980 dev_err(dev, "cnfg reg region missing\n"); 1981 return -EINVAL; 1982 } 1983 1984 cnfg = devm_of_iomap(dev, node, index, NULL); 1985 if (IS_ERR(cnfg)) 1986 return PTR_ERR(cnfg); 1987 1988 index = of_property_match_string(node, "reg-names", "intr"); 1989 if (index < 0) { 1990 dev_err(dev, "intr reg region missing\n"); 1991 return -EINVAL; 1992 } 1993 1994 intr = devm_of_iomap(dev, node, index, NULL); 1995 if (IS_ERR(intr)) 1996 return PTR_ERR(intr); 1997 1998 irq = of_irq_get_byname(node, "periph_irq"); 1999 if (irq <= 0) 2000 return irq ?: -ENXIO; 2001 2002 bus->pmic_arb = pmic_arb; 2003 bus->intr = intr; 2004 bus->cnfg = cnfg; 2005 bus->irq = irq; 2006 bus->spmic = ctrl; 2007 bus->id = bus_index; 2008 2009 if (pmic_arb->ver_ops->get_bus_resources) { 2010 ret = pmic_arb->ver_ops->get_bus_resources(pdev, node, bus); 2011 if (ret) 2012 return ret; 2013 } 2014 2015 ret = pmic_arb->ver_ops->init_apid(bus, bus_index); 2016 if (ret) 2017 return ret; 2018 2019 dev_dbg(&pdev->dev, "adding irq domain for bus %d\n", bus_index); 2020 2021 bus->domain = irq_domain_create_tree(of_fwnode_handle(node), &pmic_arb_irq_domain_ops, bus); 2022 if (!bus->domain) { 2023 dev_err(&pdev->dev, "unable to create irq_domain\n"); 2024 return -ENOMEM; 2025 } 2026 2027 irq_set_chained_handler_and_data(bus->irq, 2028 pmic_arb_chained_irq, bus); 2029 2030 ctrl->dev.of_node = node; 2031 dev_set_name(&ctrl->dev, "spmi-%d", bus_index); 2032 2033 ret = devm_spmi_controller_add(dev, ctrl); 2034 if (ret) 2035 return ret; 2036 2037 pmic_arb->buses_available++; 2038 2039 return 0; 2040 } 2041 2042 static int spmi_pmic_arb_register_buses(struct spmi_pmic_arb *pmic_arb, 2043 struct platform_device *pdev) 2044 { 2045 struct device *dev = &pdev->dev; 2046 struct device_node *node = dev->of_node; 2047 int ret; 2048 2049 /* legacy mode doesn't provide child node for the bus */ 2050 if (of_device_is_compatible(node, "qcom,spmi-pmic-arb")) 2051 return spmi_pmic_arb_bus_init(pdev, node, pmic_arb); 2052 2053 for_each_available_child_of_node_scoped(node, child) { 2054 if (of_node_name_eq(child, "spmi")) { 2055 ret = spmi_pmic_arb_bus_init(pdev, child, pmic_arb); 2056 if (ret) 2057 return ret; 2058 } 2059 } 2060 2061 return 0; 2062 } 2063 2064 static void spmi_pmic_arb_deregister_buses(struct spmi_pmic_arb *pmic_arb) 2065 { 2066 int i; 2067 2068 for (i = 0; i < pmic_arb->buses_available; i++) { 2069 struct spmi_pmic_arb_bus *bus = pmic_arb->buses[i]; 2070 2071 irq_set_chained_handler_and_data(bus->irq, 2072 NULL, NULL); 2073 irq_domain_remove(bus->domain); 2074 } 2075 } 2076 2077 static int spmi_pmic_arb_probe(struct platform_device *pdev) 2078 { 2079 struct spmi_pmic_arb *pmic_arb; 2080 struct device *dev = &pdev->dev; 2081 struct resource *res; 2082 void __iomem *core; 2083 u32 channel, ee, hw_ver; 2084 int err; 2085 2086 pmic_arb = devm_kzalloc_obj(dev, *pmic_arb); 2087 if (!pmic_arb) 2088 return -ENOMEM; 2089 2090 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); 2091 core = devm_ioremap(dev, res->start, resource_size(res)); 2092 if (!core) 2093 return -ENOMEM; 2094 2095 pmic_arb->core_size = resource_size(res); 2096 2097 platform_set_drvdata(pdev, pmic_arb); 2098 2099 hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); 2100 2101 if (hw_ver < PMIC_ARB_VERSION_V2_MIN) 2102 pmic_arb->ver_ops = &pmic_arb_v1; 2103 else if (hw_ver < PMIC_ARB_VERSION_V3_MIN) 2104 pmic_arb->ver_ops = &pmic_arb_v2; 2105 else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) 2106 pmic_arb->ver_ops = &pmic_arb_v3; 2107 else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) 2108 pmic_arb->ver_ops = &pmic_arb_v5; 2109 else if (hw_ver < PMIC_ARB_VERSION_V8_MIN) 2110 pmic_arb->ver_ops = &pmic_arb_v7; 2111 else if (hw_ver < PMIC_ARB_VERSION_V8P5_MIN) 2112 pmic_arb->ver_ops = &pmic_arb_v8; 2113 else 2114 pmic_arb->ver_ops = &pmic_arb_v8p5; 2115 2116 err = pmic_arb->ver_ops->get_core_resources(pdev, core); 2117 if (err) 2118 return err; 2119 2120 dev_info(dev, "PMIC arbiter version %s (0x%x)\n", 2121 pmic_arb->ver_ops->ver_str, hw_ver); 2122 2123 err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); 2124 if (err) { 2125 dev_err(&pdev->dev, "channel unspecified.\n"); 2126 return err; 2127 } 2128 2129 if (channel > 5) { 2130 dev_err(&pdev->dev, "invalid channel (%u) specified.\n", 2131 channel); 2132 return -EINVAL; 2133 } 2134 2135 pmic_arb->channel = channel; 2136 2137 err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee); 2138 if (err) { 2139 dev_err(&pdev->dev, "EE unspecified.\n"); 2140 return err; 2141 } 2142 2143 if (ee > 5) { 2144 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee); 2145 return -EINVAL; 2146 } 2147 2148 pmic_arb->ee = ee; 2149 2150 return spmi_pmic_arb_register_buses(pmic_arb, pdev); 2151 } 2152 2153 static void spmi_pmic_arb_remove(struct platform_device *pdev) 2154 { 2155 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 2156 2157 spmi_pmic_arb_deregister_buses(pmic_arb); 2158 } 2159 2160 static const struct of_device_id spmi_pmic_arb_match_table[] = { 2161 { .compatible = "qcom,spmi-pmic-arb", }, 2162 { .compatible = "qcom,x1e80100-spmi-pmic-arb", }, 2163 { .compatible = "qcom,glymur-spmi-pmic-arb", }, 2164 {}, 2165 }; 2166 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table); 2167 2168 static struct platform_driver spmi_pmic_arb_driver = { 2169 .probe = spmi_pmic_arb_probe, 2170 .remove = spmi_pmic_arb_remove, 2171 .driver = { 2172 .name = "spmi_pmic_arb", 2173 .of_match_table = spmi_pmic_arb_match_table, 2174 }, 2175 }; 2176 module_platform_driver(spmi_pmic_arb_driver); 2177 2178 MODULE_DESCRIPTION("Qualcomm MSM SPMI Controller (PMIC Arbiter) driver"); 2179 MODULE_LICENSE("GPL v2"); 2180 MODULE_ALIAS("platform:spmi_pmic_arb"); 2181