1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022, Analog Devices Inc.
3
4 #include <linux/acpi.h>
5 #include <linux/delay.h>
6 #include <linux/gpio/consumer.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <linux/slab.h>
13 #include <linux/cdev.h>
14 #include <sound/pcm.h>
15 #include <sound/pcm_params.h>
16 #include <sound/soc.h>
17 #include <sound/tlv.h>
18 #include "max98388.h"
19
20 static const struct reg_default max98388_reg[] = {
21 {MAX98388_R2000_SW_RESET, 0x00},
22 {MAX98388_R2001_INT_RAW1, 0x00},
23 {MAX98388_R2002_INT_RAW2, 0x00},
24 {MAX98388_R2004_INT_STATE1, 0x00},
25 {MAX98388_R2005_INT_STATE2, 0x00},
26 {MAX98388_R2020_THERM_WARN_THRESH, 0x0A},
27 {MAX98388_R2031_SPK_MON_THRESH, 0x58},
28 {MAX98388_R2032_SPK_MON_LD_SEL, 0x08},
29 {MAX98388_R2033_SPK_MON_DURATION, 0x02},
30 {MAX98388_R2037_ERR_MON_CTRL, 0x01},
31 {MAX98388_R2040_PCM_MODE_CFG, 0xC0},
32 {MAX98388_R2041_PCM_CLK_SETUP, 0x04},
33 {MAX98388_R2042_PCM_SR_SETUP, 0x88},
34 {MAX98388_R2044_PCM_TX_CTRL1, 0x00},
35 {MAX98388_R2045_PCM_TX_CTRL2, 0x00},
36 {MAX98388_R2050_PCM_TX_HIZ_CTRL1, 0xFF},
37 {MAX98388_R2051_PCM_TX_HIZ_CTRL2, 0xFF},
38 {MAX98388_R2052_PCM_TX_HIZ_CTRL3, 0xFF},
39 {MAX98388_R2053_PCM_TX_HIZ_CTRL4, 0xFF},
40 {MAX98388_R2054_PCM_TX_HIZ_CTRL5, 0xFF},
41 {MAX98388_R2055_PCM_TX_HIZ_CTRL6, 0xFF},
42 {MAX98388_R2056_PCM_TX_HIZ_CTRL7, 0xFF},
43 {MAX98388_R2057_PCM_TX_HIZ_CTRL8, 0xFF},
44 {MAX98388_R2058_PCM_RX_SRC1, 0x00},
45 {MAX98388_R2059_PCM_RX_SRC2, 0x01},
46 {MAX98388_R205C_PCM_TX_DRIVE_STRENGTH, 0x00},
47 {MAX98388_R205D_PCM_TX_SRC_EN, 0x00},
48 {MAX98388_R205E_PCM_RX_EN, 0x00},
49 {MAX98388_R205F_PCM_TX_EN, 0x00},
50 {MAX98388_R2090_SPK_CH_VOL_CTRL, 0x00},
51 {MAX98388_R2091_SPK_CH_CFG, 0x02},
52 {MAX98388_R2092_SPK_AMP_OUT_CFG, 0x03},
53 {MAX98388_R2093_SPK_AMP_SSM_CFG, 0x01},
54 {MAX98388_R2094_SPK_AMP_ER_CTRL, 0x00},
55 {MAX98388_R209E_SPK_CH_PINK_NOISE_EN, 0x00},
56 {MAX98388_R209F_SPK_CH_AMP_EN, 0x00},
57 {MAX98388_R20A0_IV_DATA_DSP_CTRL, 0x10},
58 {MAX98388_R20A7_IV_DATA_EN, 0x00},
59 {MAX98388_R20E0_BP_ALC_THRESH, 0x04},
60 {MAX98388_R20E1_BP_ALC_RATES, 0x20},
61 {MAX98388_R20E2_BP_ALC_ATTEN, 0x06},
62 {MAX98388_R20E3_BP_ALC_REL, 0x02},
63 {MAX98388_R20E4_BP_ALC_MUTE, 0x33},
64 {MAX98388_R20EE_BP_INF_HOLD_REL, 0x00},
65 {MAX98388_R20EF_BP_ALC_EN, 0x00},
66 {MAX98388_R210E_AUTO_RESTART, 0x00},
67 {MAX98388_R210F_GLOBAL_EN, 0x00},
68 {MAX98388_R22FF_REV_ID, 0x00},
69 };
70
max98388_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)71 static int max98388_dac_event(struct snd_soc_dapm_widget *w,
72 struct snd_kcontrol *kcontrol, int event)
73 {
74 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
75 struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
76
77 switch (event) {
78 case SND_SOC_DAPM_POST_PMU:
79 regmap_write(max98388->regmap,
80 MAX98388_R210F_GLOBAL_EN, 1);
81 usleep_range(30000, 31000);
82 break;
83 case SND_SOC_DAPM_PRE_PMD:
84 regmap_write(max98388->regmap,
85 MAX98388_R210F_GLOBAL_EN, 0);
86 usleep_range(30000, 31000);
87 max98388->tdm_mode = false;
88 break;
89 default:
90 return 0;
91 }
92 return 0;
93 }
94
95 static const char * const max98388_monomix_switch_text[] = {
96 "Left", "Right", "LeftRight"};
97
98 static const struct soc_enum dai_sel_enum =
99 SOC_ENUM_SINGLE(MAX98388_R2058_PCM_RX_SRC1,
100 MAX98388_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
101 3, max98388_monomix_switch_text);
102
103 static const struct snd_kcontrol_new max98388_dai_controls =
104 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
105
106 static const struct snd_kcontrol_new max98388_vi_control =
107 SOC_DAPM_SINGLE("Switch", MAX98388_R205F_PCM_TX_EN, 0, 1, 0);
108
109 static const struct snd_soc_dapm_widget max98388_dapm_widgets[] = {
110 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
111 MAX98388_R205E_PCM_RX_EN, 0, 0, max98388_dac_event,
112 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
113 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
114 &max98388_dai_controls),
115 SND_SOC_DAPM_OUTPUT("BE_OUT"),
116 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
117 MAX98388_R20A7_IV_DATA_EN, 0, 0),
118 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
119 MAX98388_R20A7_IV_DATA_EN, 1, 0),
120 SND_SOC_DAPM_ADC("ADC Voltage", NULL,
121 MAX98388_R205D_PCM_TX_SRC_EN, 0, 0),
122 SND_SOC_DAPM_ADC("ADC Current", NULL,
123 MAX98388_R205D_PCM_TX_SRC_EN, 1, 0),
124 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
125 &max98388_vi_control),
126 SND_SOC_DAPM_SIGGEN("VMON"),
127 SND_SOC_DAPM_SIGGEN("IMON"),
128 };
129
130 static DECLARE_TLV_DB_SCALE(max98388_digital_tlv, -6350, 50, 1);
131 static DECLARE_TLV_DB_SCALE(max98388_amp_gain_tlv, -300, 300, 0);
132
133 static const char * const max98388_alc_max_atten_text[] = {
134 "0dBFS", "-1dBFS", "-2dBFS", "-3dBFS", "-4dBFS", "-5dBFS",
135 "-6dBFS", "-7dBFS", "-8dBFS", "-9dBFS", "-10dBFS", "-11dBFS",
136 "-12dBFS", "-13dBFS", "-14dBFS", "-15dBFS"
137 };
138
139 static SOC_ENUM_SINGLE_DECL(max98388_alc_max_atten_enum,
140 MAX98388_R20E2_BP_ALC_ATTEN,
141 MAX98388_ALC_MAX_ATTEN_SHIFT,
142 max98388_alc_max_atten_text);
143
144 static const char * const max98388_thermal_warn_text[] = {
145 "95C", "105C", "115C", "125C"
146 };
147
148 static SOC_ENUM_SINGLE_DECL(max98388_thermal_warning_thresh_enum,
149 MAX98388_R2020_THERM_WARN_THRESH,
150 MAX98388_THERM_WARN_THRESH_SHIFT,
151 max98388_thermal_warn_text);
152
153 static const char * const max98388_thermal_shutdown_text[] = {
154 "135C", "145C", "155C", "165C"
155 };
156
157 static SOC_ENUM_SINGLE_DECL(max98388_thermal_shutdown_thresh_enum,
158 MAX98388_R2020_THERM_WARN_THRESH,
159 MAX98388_THERM_SHDN_THRESH_SHIFT,
160 max98388_thermal_shutdown_text);
161
162 static const char * const max98388_alc_thresh_single_text[] = {
163 "3.625V", "3.550V", "3.475V", "3.400V", "3.325V", "3.250V",
164 "3.175V", "3.100V", "3.025V", "2.950V", "2.875V", "2.800V",
165 "2.725V", "2.650V", "2.575V", "2.500V"
166 };
167
168 static SOC_ENUM_SINGLE_DECL(max98388_alc_thresh_single_enum,
169 MAX98388_R20E0_BP_ALC_THRESH,
170 MAX98388_ALC_THRESH_SHIFT,
171 max98388_alc_thresh_single_text);
172
173 static const char * const max98388_alc_attack_rate_text[] = {
174 "0", "10us", "20us", "40us", "80us", "160us",
175 "320us", "640us", "1.28ms", "2.56ms", "5.12ms", "10.24ms",
176 "20.48ms", "40.96ms", "81.92ms", "163.84ms"
177 };
178
179 static SOC_ENUM_SINGLE_DECL(max98388_alc_attack_rate_enum,
180 MAX98388_R20E1_BP_ALC_RATES,
181 MAX98388_ALC_ATTACK_RATE_SHIFT,
182 max98388_alc_attack_rate_text);
183
184 static const char * const max98388_alc_release_rate_text[] = {
185 "20us", "40us", "80us", "160us", "320us", "640us",
186 "1.28ms", "2.56ms", "5.12ms", "10.24ms", "20.48ms", "40.96ms",
187 "81.92ms", "163.84ms", "327.68ms", "655.36ms"
188 };
189
190 static SOC_ENUM_SINGLE_DECL(max98388_alc_release_rate_enum,
191 MAX98388_R20E1_BP_ALC_RATES,
192 MAX98388_ALC_RELEASE_RATE_SHIFT,
193 max98388_alc_release_rate_text);
194
195 static const char * const max98388_alc_debounce_text[] = {
196 "0.01ms", "0.1ms", "1ms", "10ms", "100ms", "250ms", "500ms", "hold"
197 };
198
199 static SOC_ENUM_SINGLE_DECL(max98388_alc_debouce_enum,
200 MAX98388_R20E3_BP_ALC_REL,
201 MAX98388_ALC_DEBOUNCE_TIME_SHIFT,
202 max98388_alc_debounce_text);
203
204 static const char * const max98388_alc_mute_delay_text[] = {
205 "0.01ms", "0.05ms", "0.1ms", "0.5ms", "1ms", "5ms", "25ms", "250ms"
206 };
207
208 static SOC_ENUM_SINGLE_DECL(max98388_alc_mute_delay_enum,
209 MAX98388_R20E4_BP_ALC_MUTE,
210 MAX98388_ALC_MUTE_DELAY_SHIFT,
211 max98388_alc_mute_delay_text);
212
213 static const char * const max98388_spkmon_duration_text[] = {
214 "10ms", "25ms", "50ms", "75ms", "100ms", "200ms", "300ms", "400ms",
215 "500ms", "600ms", "700ms", "800ms", "900ms", "1000ms", "1100ms", "1200ms"
216 };
217
218 static SOC_ENUM_SINGLE_DECL(max98388_spkmon_duration_enum,
219 MAX98388_R2033_SPK_MON_DURATION,
220 MAX98388_SPKMON_DURATION_SHIFT,
221 max98388_spkmon_duration_text);
222
223 static const char * const max98388_spkmon_thresh_text[] = {
224 "0.03V", "0.06V", "0.09V", "0.12V", "0.15V", "0.18V", "0.20V", "0.23V",
225 "0.26V", "0.29V", "0.32V", "0.35V", "0.38V", "0.41V", "0.44V", "0.47V",
226 "0.50V", "0.53V", "0.56V", "0.58V", "0.61V", "0.64V", "0.67V", "0.70V",
227 "0.73V", "0.76V", "0.79V", "0.82V", "0.85V", "0.88V", "0.91V", "0.94V",
228 "0.96V", "0.99V", "1.02V", "1.05V", "1.08V", "1.11V", "1.14V", "1.17V",
229 "1.20V", "1.23V", "1.26V", "1.29V", "1.32V", "1.35V", "1.37V", "1.40V",
230 "1.43V", "1.46V", "1.49V", "1.52V", "1.55V", "1.58V", "1.61V", "1.64V",
231 "1.67V", "1.70V", "1.73V", "1.75V", "1.78V", "1.81V", "1.84V", "1.87V",
232 "1.90V", "1.93V", "1.96V", "1.99V", "2.02V", "2.05V", "2.08V", "2.11V",
233 "2.13V", "2.16V", "2.19V", "2.22V", "2.25V", "2.28V", "2.31V", "2.34V",
234 "2.37V", "2.40V", "2.43V", "2.46V", "2.49V", "2.51V", "2.54V", "2.57V",
235 "2.60V", "2.63V", "2.66V", "2.69V", "2.72V", "2.75V", "2.78V", "2.81V",
236 "2.84V", "2.87V", "2.89V", "2.92V", "2.95V", "2.98V", "3.01V", "3.04V",
237 "3.07V", "3.10V", "3.13V", "3.16V", "3.19V", "3.22V", "3.25V", "3.27V",
238 "3.30V", "3.33V", "3.36V", "3.39V", "3.42V", "3.45V", "3.48V", "3.51V",
239 "3.54V", "3.57V", "3.60V", "3.63V", "3.66V", "3.68V", "3.71V", "3.74V"
240 };
241
242 static SOC_ENUM_SINGLE_DECL(max98388_spkmon_thresh_enum,
243 MAX98388_R2031_SPK_MON_THRESH,
244 MAX98388_SPKMON_THRESH_SHIFT,
245 max98388_spkmon_thresh_text);
246
247 static const char * const max98388_spkmon_load_text[] = {
248 "2.00ohm", "2.25ohm", "2.50ohm", "2.75ohm", "3.00ohm", "3.25ohm",
249 "3.50ohm", "3.75ohm", "4.00ohm", "4.25ohm", "4.50ohm", "4.75ohm",
250 "5.00ohm", "5.25ohm", "5.50ohm", "5.75ohm", "6.00ohm", "6.25ohm",
251 "6.50ohm", "6.75ohm", "7.00ohm", "7.25ohm", "7.50ohm", "7.75ohm",
252 "8.00ohm", "8.25ohm", "8.50ohm", "8.75ohm", "9.00ohm", "9.25ohm",
253 "9.50ohm", "9.75ohm", "10.00ohm", "10.25ohm", "10.50ohm", "10.75ohm",
254 "11.00ohm", "11.25ohm", "11.50ohm", "11.75ohm", "12.00ohm", "12.25ohm",
255 "12.50ohm", "12.75ohm", "13.00ohm", "13.25ohm", "13.50ohm", "13.75ohm",
256 "14.00ohm", "14.25ohm", "14.50ohm", "14.75ohm", "15.00ohm", "15.25ohm",
257 "15.50ohm", "15.75ohm", "16.00ohm", "16.25ohm", "16.50ohm", "16.75ohm",
258 "17.00ohm", "17.25ohm", "17.50ohm", "17.75ohm", "18.00ohm", "18.25ohm",
259 "18.50ohm", "18.75ohm", "19.00ohm", "19.25ohm", "19.50ohm", "19.75ohm",
260 "20.00ohm", "20.25ohm", "20.50ohm", "20.75ohm", "21.00ohm", "21.25ohm",
261 "21.50ohm", "21.75ohm", "22.00ohm", "22.25ohm", "22.50ohm", "22.75ohm",
262 "23.00ohm", "23.25ohm", "23.50ohm", "23.75ohm", "24.00ohm", "24.25ohm",
263 "24.50ohm", "24.75ohm", "25.00ohm", "25.25ohm", "25.50ohm", "25.75ohm",
264 "26.00ohm", "26.25ohm", "26.50ohm", "26.75ohm", "27.00ohm", "27.25ohm",
265 "27.50ohm", "27.75ohm", "28.00ohm", "28.25ohm", "28.50ohm", "28.75ohm",
266 "29.00ohm", "29.25ohm", "29.50ohm", "29.75ohm", "30.00ohm", "30.25ohm",
267 "30.50ohm", "30.75ohm", "31.00ohm", "31.25ohm", "31.50ohm", "31.75ohm",
268 "32.00ohm", "32.25ohm", "32.50ohm", "32.75ohm", "33.00ohm", "33.25ohm",
269 "33.50ohm", "33.75ohm"
270 };
271
272 static SOC_ENUM_SINGLE_DECL(max98388_spkmon_load_enum,
273 MAX98388_R2032_SPK_MON_LD_SEL,
274 MAX98388_SPKMON_LOAD_SHIFT,
275 max98388_spkmon_load_text);
276
277 static const char * const max98388_edge_rate_text[] = {
278 "Normal", "Reduced", "Maximum", "Increased",
279 };
280
281 static SOC_ENUM_SINGLE_DECL(max98388_edge_rate_falling_enum,
282 MAX98388_R2094_SPK_AMP_ER_CTRL,
283 MAX98388_EDGE_RATE_FALL_SHIFT,
284 max98388_edge_rate_text);
285
286 static SOC_ENUM_SINGLE_DECL(max98388_edge_rate_rising_enum,
287 MAX98388_R2094_SPK_AMP_ER_CTRL,
288 MAX98388_EDGE_RATE_RISE_SHIFT,
289 max98388_edge_rate_text);
290
291 static const char * const max98388_ssm_mod_text[] = {
292 "1.5%", "3.0%", "4.5%", "6.0%",
293 };
294
295 static SOC_ENUM_SINGLE_DECL(max98388_ssm_mod_enum,
296 MAX98388_R2093_SPK_AMP_SSM_CFG,
297 MAX98388_SPK_AMP_SSM_MOD_SHIFT,
298 max98388_ssm_mod_text);
299
300 static const struct snd_kcontrol_new max98388_snd_controls[] = {
301 SOC_SINGLE("Ramp Up Switch", MAX98388_R2091_SPK_CH_CFG,
302 MAX98388_SPK_CFG_VOL_RMPUP_SHIFT, 1, 0),
303 SOC_SINGLE("Ramp Down Switch", MAX98388_R2091_SPK_CH_CFG,
304 MAX98388_SPK_CFG_VOL_RMPDN_SHIFT, 1, 0),
305 /* Two Cell Mode Enable */
306 SOC_SINGLE("OP Mode Switch", MAX98388_R2092_SPK_AMP_OUT_CFG,
307 MAX98388_SPK_AMP_OUT_MODE_SHIFT, 1, 0),
308 /* Speaker Amplifier Overcurrent Automatic Restart Enable */
309 SOC_SINGLE("OVC Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
310 MAX98388_OVC_AUTORESTART_SHIFT, 1, 0),
311 /* Thermal Shutdown Automatic Restart Enable */
312 SOC_SINGLE("THERM Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
313 MAX98388_THERM_AUTORESTART_SHIFT, 1, 0),
314 /* PVDD UVLO Auto Restart */
315 SOC_SINGLE("UVLO Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
316 MAX98388_PVDD_UVLO_AUTORESTART_SHIFT, 1, 0),
317 /* Clock Monitor Automatic Restart Enable */
318 SOC_SINGLE("CMON Autorestart Switch", MAX98388_R210E_AUTO_RESTART,
319 MAX98388_CMON_AUTORESTART_SHIFT, 1, 0),
320 SOC_SINGLE("CLK Monitor Switch", MAX98388_R2037_ERR_MON_CTRL,
321 MAX98388_CLOCK_MON_SHIFT, 1, 0),
322 /* Pinknoise Generator Enable */
323 SOC_SINGLE("Pinknoise Gen Switch", MAX98388_R209E_SPK_CH_PINK_NOISE_EN,
324 MAX98388_PINK_NOISE_GEN_SHIFT, 1, 0),
325 /* Dither Enable */
326 SOC_SINGLE("Dither Switch", MAX98388_R2091_SPK_CH_CFG,
327 MAX98388_SPK_CFG_DITH_EN_SHIFT, 1, 0),
328 SOC_SINGLE("VI Dither Switch", MAX98388_R20A0_IV_DATA_DSP_CTRL,
329 MAX98388_AMP_DSP_CTRL_DITH_SHIFT, 1, 0),
330 /* DC Blocker Enable */
331 SOC_SINGLE("DC Blocker Switch", MAX98388_R2091_SPK_CH_CFG,
332 MAX98388_SPK_CFG_DCBLK_SHIFT, 1, 0),
333 SOC_SINGLE("Voltage DC Blocker Switch", MAX98388_R20A0_IV_DATA_DSP_CTRL,
334 MAX98388_AMP_DSP_CTRL_VOL_DCBLK_SHIFT, 1, 0),
335 SOC_SINGLE("Current DC Blocker Switch", MAX98388_R20A0_IV_DATA_DSP_CTRL,
336 MAX98388_AMP_DSP_CTRL_CUR_DCBLK_SHIFT, 1, 0),
337 /* Digital Volume */
338 SOC_SINGLE_TLV("Digital Volume", MAX98388_R2090_SPK_CH_VOL_CTRL,
339 0, 0x7F, 1, max98388_digital_tlv),
340 /* Speaker Volume */
341 SOC_SINGLE_TLV("Speaker Volume", MAX98388_R2092_SPK_AMP_OUT_CFG,
342 0, 5, 0, max98388_amp_gain_tlv),
343 SOC_ENUM("Thermal Warn Thresh", max98388_thermal_warning_thresh_enum),
344 SOC_ENUM("Thermal SHDN Thresh", max98388_thermal_shutdown_thresh_enum),
345 /* Brownout Protection Automatic Level Control */
346 SOC_SINGLE("ALC Switch", MAX98388_R20EF_BP_ALC_EN, 0, 1, 0),
347 SOC_ENUM("ALC Thresh", max98388_alc_thresh_single_enum),
348 SOC_ENUM("ALC Attack Rate", max98388_alc_attack_rate_enum),
349 SOC_ENUM("ALC Release Rate", max98388_alc_release_rate_enum),
350 SOC_ENUM("ALC Max Atten", max98388_alc_max_atten_enum),
351 SOC_ENUM("ALC Debounce Time", max98388_alc_debouce_enum),
352 SOC_SINGLE("ALC Unmute Ramp Switch", MAX98388_R20E4_BP_ALC_MUTE,
353 MAX98388_ALC_UNMUTE_RAMP_EN_SHIFT, 1, 0),
354 SOC_SINGLE("ALC Mute Ramp Switch", MAX98388_R20E4_BP_ALC_MUTE,
355 MAX98388_ALC_MUTE_RAMP_EN_SHIFT, 1, 0),
356 SOC_SINGLE("ALC Mute Switch", MAX98388_R20E4_BP_ALC_MUTE,
357 MAX98388_ALC_MUTE_EN_SHIFT, 1, 0),
358 SOC_ENUM("ALC Mute Delay", max98388_alc_mute_delay_enum),
359 /* Speaker Monitor */
360 SOC_SINGLE("SPKMON Switch", MAX98388_R2037_ERR_MON_CTRL,
361 MAX98388_SPK_MON_SHIFT, 1, 0),
362 SOC_ENUM("SPKMON Thresh", max98388_spkmon_thresh_enum),
363 SOC_ENUM("SPKMON Load", max98388_spkmon_load_enum),
364 SOC_ENUM("SPKMON Duration", max98388_spkmon_duration_enum),
365 /* General Parameters */
366 SOC_ENUM("Fall Slew Rate", max98388_edge_rate_falling_enum),
367 SOC_ENUM("Rise Slew Rate", max98388_edge_rate_rising_enum),
368 SOC_SINGLE("AMP SSM Switch", MAX98388_R2093_SPK_AMP_SSM_CFG,
369 MAX98388_SPK_AMP_SSM_EN_SHIFT, 1, 0),
370 SOC_ENUM("AMP SSM Mod", max98388_ssm_mod_enum),
371 };
372
373 static const struct snd_soc_dapm_route max98388_audio_map[] = {
374 /* Plabyack */
375 {"DAI Sel Mux", "Left", "Amp Enable"},
376 {"DAI Sel Mux", "Right", "Amp Enable"},
377 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
378 {"BE_OUT", NULL, "DAI Sel Mux"},
379 /* Capture */
380 { "ADC Voltage", NULL, "VMON"},
381 { "ADC Current", NULL, "IMON"},
382 { "VI Sense", "Switch", "ADC Voltage"},
383 { "VI Sense", "Switch", "ADC Current"},
384 { "Voltage Sense", NULL, "VI Sense"},
385 { "Current Sense", NULL, "VI Sense"},
386 };
387
max98388_reset(struct max98388_priv * max98388,struct device * dev)388 static void max98388_reset(struct max98388_priv *max98388, struct device *dev)
389 {
390 int ret, reg, count;
391
392 /* Software Reset */
393 ret = regmap_update_bits(max98388->regmap,
394 MAX98388_R2000_SW_RESET,
395 MAX98388_SOFT_RESET,
396 MAX98388_SOFT_RESET);
397 if (ret)
398 dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
399
400 count = 0;
401 while (count < 3) {
402 usleep_range(10000, 11000);
403 /* Software Reset Verification */
404 ret = regmap_read(max98388->regmap,
405 MAX98388_R22FF_REV_ID, ®);
406 if (!ret) {
407 dev_info(dev, "Reset completed (retry:%d)\n", count);
408 return;
409 }
410 count++;
411 }
412 dev_err(dev, "Reset failed. (ret:%d)\n", ret);
413 }
414
max98388_probe(struct snd_soc_component * component)415 static int max98388_probe(struct snd_soc_component *component)
416 {
417 struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
418
419 /* Software Reset */
420 max98388_reset(max98388, component->dev);
421
422 /* General channel source configuration */
423 regmap_write(max98388->regmap,
424 MAX98388_R2059_PCM_RX_SRC2,
425 0x10);
426
427 /* Enable DC blocker */
428 regmap_write(max98388->regmap,
429 MAX98388_R2091_SPK_CH_CFG,
430 0x1);
431 /* Enable IMON VMON DC blocker */
432 regmap_write(max98388->regmap,
433 MAX98388_R20A0_IV_DATA_DSP_CTRL,
434 0x3);
435 /* TX slot configuration */
436 regmap_write(max98388->regmap,
437 MAX98388_R2044_PCM_TX_CTRL1,
438 max98388->v_slot);
439
440 regmap_write(max98388->regmap,
441 MAX98388_R2045_PCM_TX_CTRL2,
442 max98388->i_slot);
443 /* Enable Auto-restart behavior by default */
444 regmap_write(max98388->regmap,
445 MAX98388_R210E_AUTO_RESTART, 0xF);
446 /* Set interleave mode */
447 if (max98388->interleave_mode)
448 regmap_update_bits(max98388->regmap,
449 MAX98388_R2040_PCM_MODE_CFG,
450 MAX98388_PCM_TX_CH_INTERLEAVE_MASK,
451 MAX98388_PCM_TX_CH_INTERLEAVE_MASK);
452
453 /* Speaker Amplifier Channel Enable */
454 regmap_update_bits(max98388->regmap,
455 MAX98388_R209F_SPK_CH_AMP_EN,
456 MAX98388_SPK_EN_MASK, 1);
457
458 return 0;
459 }
460
max98388_dai_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)461 static int max98388_dai_set_fmt(struct snd_soc_dai *codec_dai,
462 unsigned int fmt)
463 {
464 struct snd_soc_component *component = codec_dai->component;
465 struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
466 unsigned int format = 0;
467 unsigned int invert = 0;
468
469 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
470
471 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
472 case SND_SOC_DAIFMT_NB_NF:
473 break;
474 case SND_SOC_DAIFMT_IB_NF:
475 invert = MAX98388_PCM_MODE_CFG_PCM_BCLKEDGE;
476 break;
477 default:
478 dev_err(component->dev, "DAI invert mode unsupported\n");
479 return -EINVAL;
480 }
481
482 regmap_update_bits(max98388->regmap,
483 MAX98388_R2041_PCM_CLK_SETUP,
484 MAX98388_PCM_MODE_CFG_PCM_BCLKEDGE,
485 invert);
486
487 /* interface format */
488 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
489 case SND_SOC_DAIFMT_I2S:
490 format = MAX98388_PCM_FORMAT_I2S;
491 break;
492 case SND_SOC_DAIFMT_LEFT_J:
493 format = MAX98388_PCM_FORMAT_LJ;
494 break;
495 case SND_SOC_DAIFMT_DSP_A:
496 format = MAX98388_PCM_FORMAT_TDM_MODE1;
497 break;
498 case SND_SOC_DAIFMT_DSP_B:
499 format = MAX98388_PCM_FORMAT_TDM_MODE0;
500 break;
501 default:
502 return -EINVAL;
503 }
504
505 regmap_update_bits(max98388->regmap,
506 MAX98388_R2040_PCM_MODE_CFG,
507 MAX98388_PCM_MODE_CFG_FORMAT_MASK,
508 format << MAX98388_PCM_MODE_CFG_FORMAT_SHIFT);
509
510 return 0;
511 }
512
513 /* BCLKs per LRCLK */
514 static const int bclk_sel_table[] = {
515 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
516 };
517
max98388_get_bclk_sel(int bclk)518 static int max98388_get_bclk_sel(int bclk)
519 {
520 int i;
521 /* match BCLKs per LRCLK */
522 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
523 if (bclk_sel_table[i] == bclk)
524 return i + 2;
525 }
526 return 0;
527 }
528
max98388_set_clock(struct snd_soc_component * component,struct snd_pcm_hw_params * params)529 static int max98388_set_clock(struct snd_soc_component *component,
530 struct snd_pcm_hw_params *params)
531 {
532 struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
533 /* BCLK/LRCLK ratio calculation */
534 int blr_clk_ratio = params_channels(params) * max98388->ch_size;
535 int value;
536
537 if (!max98388->tdm_mode) {
538 /* BCLK configuration */
539 value = max98388_get_bclk_sel(blr_clk_ratio);
540 if (!value) {
541 dev_err(component->dev, "format unsupported %d\n",
542 params_format(params));
543 return -EINVAL;
544 }
545
546 regmap_update_bits(max98388->regmap,
547 MAX98388_R2041_PCM_CLK_SETUP,
548 MAX98388_PCM_CLK_SETUP_BSEL_MASK,
549 value);
550 }
551 return 0;
552 }
553
max98388_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)554 static int max98388_dai_hw_params(struct snd_pcm_substream *substream,
555 struct snd_pcm_hw_params *params,
556 struct snd_soc_dai *dai)
557 {
558 struct snd_soc_component *component = dai->component;
559 struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
560 unsigned int sampling_rate = 0;
561 unsigned int chan_sz = 0;
562 int ret, reg;
563 int status = 0;
564
565 /* pcm mode configuration */
566 switch (snd_pcm_format_width(params_format(params))) {
567 case 16:
568 chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_16;
569 break;
570 case 24:
571 chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_24;
572 break;
573 case 32:
574 chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_32;
575 break;
576 default:
577 dev_err(component->dev, "format unsupported %d\n",
578 params_format(params));
579 goto err;
580 }
581
582 max98388->ch_size = snd_pcm_format_width(params_format(params));
583
584 ret = regmap_read(max98388->regmap,
585 MAX98388_R2040_PCM_MODE_CFG, ®);
586 if (ret < 0)
587 goto err;
588
589 /* GLOBAL_EN OFF prior to the channel size re-configure */
590 if (chan_sz != (reg & MAX98388_PCM_MODE_CFG_CHANSZ_MASK)) {
591 ret = regmap_read(max98388->regmap,
592 MAX98388_R210F_GLOBAL_EN, &status);
593 if (ret < 0)
594 goto err;
595
596 if (status) {
597 regmap_write(max98388->regmap,
598 MAX98388_R210F_GLOBAL_EN, 0);
599 usleep_range(30000, 31000);
600 }
601 regmap_update_bits(max98388->regmap,
602 MAX98388_R2040_PCM_MODE_CFG,
603 MAX98388_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
604 }
605 dev_dbg(component->dev, "format supported %d",
606 params_format(params));
607
608 /* sampling rate configuration */
609 switch (params_rate(params)) {
610 case 8000:
611 sampling_rate = MAX98388_PCM_SR_8000;
612 break;
613 case 11025:
614 sampling_rate = MAX98388_PCM_SR_11025;
615 break;
616 case 12000:
617 sampling_rate = MAX98388_PCM_SR_12000;
618 break;
619 case 16000:
620 sampling_rate = MAX98388_PCM_SR_16000;
621 break;
622 case 22050:
623 sampling_rate = MAX98388_PCM_SR_22050;
624 break;
625 case 24000:
626 sampling_rate = MAX98388_PCM_SR_24000;
627 break;
628 case 32000:
629 sampling_rate = MAX98388_PCM_SR_32000;
630 break;
631 case 44100:
632 sampling_rate = MAX98388_PCM_SR_44100;
633 break;
634 case 48000:
635 sampling_rate = MAX98388_PCM_SR_48000;
636 break;
637 case 88200:
638 sampling_rate = MAX98388_PCM_SR_88200;
639 break;
640 case 96000:
641 sampling_rate = MAX98388_PCM_SR_96000;
642 break;
643 default:
644 dev_err(component->dev, "rate %d not supported\n",
645 params_rate(params));
646 goto err;
647 }
648
649 /* set DAI_SR to correct LRCLK frequency */
650 regmap_update_bits(max98388->regmap,
651 MAX98388_R2042_PCM_SR_SETUP,
652 MAX98388_PCM_SR_MASK,
653 sampling_rate);
654
655 /* set sampling rate of IV */
656 if (max98388->interleave_mode &&
657 sampling_rate > MAX98388_PCM_SR_16000)
658 regmap_update_bits(max98388->regmap,
659 MAX98388_R2042_PCM_SR_SETUP,
660 MAX98388_PCM_SR_IV_MASK,
661 (sampling_rate - 3) << MAX98388_PCM_SR_IV_SHIFT);
662 else
663 regmap_update_bits(max98388->regmap,
664 MAX98388_R2042_PCM_SR_SETUP,
665 MAX98388_PCM_SR_IV_MASK,
666 sampling_rate << MAX98388_PCM_SR_IV_SHIFT);
667
668 ret = max98388_set_clock(component, params);
669
670 if (status) {
671 regmap_write(max98388->regmap,
672 MAX98388_R210F_GLOBAL_EN, 1);
673 usleep_range(30000, 31000);
674 }
675
676 return ret;
677
678 err:
679 return -EINVAL;
680 }
681
682 #define MAX_NUM_SLOTS 16
683 #define MAX_NUM_CH 2
684
max98388_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)685 static int max98388_dai_tdm_slot(struct snd_soc_dai *dai,
686 unsigned int tx_mask, unsigned int rx_mask,
687 int slots, int slot_width)
688 {
689 struct snd_soc_component *component = dai->component;
690 struct max98388_priv *max98388 = snd_soc_component_get_drvdata(component);
691 int bsel = 0;
692 unsigned int chan_sz = 0;
693 unsigned int mask;
694 int cnt, slot_found;
695 int addr, bits;
696
697 if (!tx_mask && !rx_mask && !slots && !slot_width)
698 max98388->tdm_mode = false;
699 else
700 max98388->tdm_mode = true;
701
702 /* BCLK configuration */
703 bsel = max98388_get_bclk_sel(slots * slot_width);
704 if (bsel == 0) {
705 dev_err(component->dev, "BCLK %d not supported\n",
706 slots * slot_width);
707 return -EINVAL;
708 }
709
710 regmap_update_bits(max98388->regmap,
711 MAX98388_R2041_PCM_CLK_SETUP,
712 MAX98388_PCM_CLK_SETUP_BSEL_MASK,
713 bsel);
714
715 /* Channel size configuration */
716 switch (slot_width) {
717 case 16:
718 chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_16;
719 break;
720 case 24:
721 chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_24;
722 break;
723 case 32:
724 chan_sz = MAX98388_PCM_MODE_CFG_CHANSZ_32;
725 break;
726 default:
727 dev_err(component->dev, "format unsupported %d\n",
728 slot_width);
729 return -EINVAL;
730 }
731
732 regmap_update_bits(max98388->regmap,
733 MAX98388_R2040_PCM_MODE_CFG,
734 MAX98388_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
735
736 /* Rx slot configuration */
737 slot_found = 0;
738 mask = rx_mask;
739 for (cnt = 0 ; cnt < MAX_NUM_SLOTS ; cnt++, mask >>= 1) {
740 if (mask & 0x1) {
741 if (slot_found == 0)
742 regmap_update_bits(max98388->regmap,
743 MAX98388_R2059_PCM_RX_SRC2,
744 MAX98388_RX_SRC_CH0_SHIFT,
745 cnt);
746 else
747 regmap_update_bits(max98388->regmap,
748 MAX98388_R2059_PCM_RX_SRC2,
749 MAX98388_RX_SRC_CH1_SHIFT,
750 cnt);
751 slot_found++;
752 if (slot_found >= MAX_NUM_CH)
753 break;
754 }
755 }
756
757 /* speaker feedback slot configuration */
758 slot_found = 0;
759 mask = tx_mask;
760 for (cnt = 0 ; cnt < MAX_NUM_SLOTS ; cnt++, mask >>= 1) {
761 if (mask & 0x1) {
762 addr = MAX98388_R2044_PCM_TX_CTRL1 + (cnt / 8);
763 bits = cnt % 8;
764 regmap_update_bits(max98388->regmap, addr, bits, bits);
765 slot_found++;
766 if (slot_found >= MAX_NUM_CH)
767 break;
768 }
769 }
770
771 return 0;
772 }
773
774 #define MAX98388_RATES SNDRV_PCM_RATE_8000_96000
775
776 #define MAX98388_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
777 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
778
779 static const struct snd_soc_dai_ops max98388_dai_ops = {
780 .set_fmt = max98388_dai_set_fmt,
781 .hw_params = max98388_dai_hw_params,
782 .set_tdm_slot = max98388_dai_tdm_slot,
783 };
784
max98388_readable_register(struct device * dev,unsigned int reg)785 static bool max98388_readable_register(struct device *dev,
786 unsigned int reg)
787 {
788 switch (reg) {
789 case MAX98388_R2001_INT_RAW1 ... MAX98388_R2002_INT_RAW2:
790 case MAX98388_R2004_INT_STATE1... MAX98388_R2005_INT_STATE2:
791 case MAX98388_R2020_THERM_WARN_THRESH:
792 case MAX98388_R2031_SPK_MON_THRESH
793 ... MAX98388_R2033_SPK_MON_DURATION:
794 case MAX98388_R2037_ERR_MON_CTRL:
795 case MAX98388_R2040_PCM_MODE_CFG
796 ... MAX98388_R2042_PCM_SR_SETUP:
797 case MAX98388_R2044_PCM_TX_CTRL1
798 ... MAX98388_R2045_PCM_TX_CTRL2:
799 case MAX98388_R2050_PCM_TX_HIZ_CTRL1
800 ... MAX98388_R2059_PCM_RX_SRC2:
801 case MAX98388_R205C_PCM_TX_DRIVE_STRENGTH
802 ... MAX98388_R205F_PCM_TX_EN:
803 case MAX98388_R2090_SPK_CH_VOL_CTRL
804 ... MAX98388_R2094_SPK_AMP_ER_CTRL:
805 case MAX98388_R209E_SPK_CH_PINK_NOISE_EN
806 ... MAX98388_R209F_SPK_CH_AMP_EN:
807 case MAX98388_R20A0_IV_DATA_DSP_CTRL:
808 case MAX98388_R20A7_IV_DATA_EN:
809 case MAX98388_R20E0_BP_ALC_THRESH ... MAX98388_R20E4_BP_ALC_MUTE:
810 case MAX98388_R20EE_BP_INF_HOLD_REL ... MAX98388_R20EF_BP_ALC_EN:
811 case MAX98388_R210E_AUTO_RESTART:
812 case MAX98388_R210F_GLOBAL_EN:
813 case MAX98388_R22FF_REV_ID:
814 return true;
815 default:
816 return false;
817 }
818 };
819
max98388_volatile_reg(struct device * dev,unsigned int reg)820 static bool max98388_volatile_reg(struct device *dev, unsigned int reg)
821 {
822 switch (reg) {
823 case MAX98388_R2001_INT_RAW1 ... MAX98388_R2005_INT_STATE2:
824 case MAX98388_R210F_GLOBAL_EN:
825 case MAX98388_R22FF_REV_ID:
826 return true;
827 default:
828 return false;
829 }
830 }
831
832 static struct snd_soc_dai_driver max98388_dai[] = {
833 {
834 .name = "max98388-aif1",
835 .playback = {
836 .stream_name = "HiFi Playback",
837 .channels_min = 1,
838 .channels_max = 2,
839 .rates = MAX98388_RATES,
840 .formats = MAX98388_FORMATS,
841 },
842 .capture = {
843 .stream_name = "HiFi Capture",
844 .channels_min = 1,
845 .channels_max = 2,
846 .rates = MAX98388_RATES,
847 .formats = MAX98388_FORMATS,
848 },
849 .ops = &max98388_dai_ops,
850 }
851 };
852
max98388_suspend(struct device * dev)853 static int max98388_suspend(struct device *dev)
854 {
855 struct max98388_priv *max98388 = dev_get_drvdata(dev);
856
857 regcache_cache_only(max98388->regmap, true);
858 regcache_mark_dirty(max98388->regmap);
859
860 return 0;
861 }
862
max98388_resume(struct device * dev)863 static int max98388_resume(struct device *dev)
864 {
865 struct max98388_priv *max98388 = dev_get_drvdata(dev);
866 int ret;
867
868 regcache_cache_only(max98388->regmap, false);
869 max98388_reset(max98388, dev);
870 ret = regcache_sync(max98388->regmap);
871 if (ret) {
872 regcache_cache_only(max98388->regmap, true);
873 regcache_mark_dirty(max98388->regmap);
874 return ret;
875 }
876
877 return 0;
878 }
879
880 static const struct dev_pm_ops max98388_pm = {
881 SYSTEM_SLEEP_PM_OPS(max98388_suspend, max98388_resume)
882 };
883
884 static const struct regmap_config max98388_regmap = {
885 .reg_bits = 16,
886 .val_bits = 8,
887 .max_register = MAX98388_R22FF_REV_ID,
888 .reg_defaults = max98388_reg,
889 .num_reg_defaults = ARRAY_SIZE(max98388_reg),
890 .readable_reg = max98388_readable_register,
891 .volatile_reg = max98388_volatile_reg,
892 .cache_type = REGCACHE_RBTREE,
893 };
894
895 static const struct snd_soc_component_driver soc_codec_dev_max98388 = {
896 .probe = max98388_probe,
897 .controls = max98388_snd_controls,
898 .num_controls = ARRAY_SIZE(max98388_snd_controls),
899 .dapm_widgets = max98388_dapm_widgets,
900 .num_dapm_widgets = ARRAY_SIZE(max98388_dapm_widgets),
901 .dapm_routes = max98388_audio_map,
902 .num_dapm_routes = ARRAY_SIZE(max98388_audio_map),
903 .use_pmdown_time = 1,
904 .endianness = 1,
905 };
906
max98388_read_deveice_property(struct device * dev,struct max98388_priv * max98388)907 static void max98388_read_deveice_property(struct device *dev,
908 struct max98388_priv *max98388)
909 {
910 int value;
911
912 if (!device_property_read_u32(dev, "adi,vmon-slot-no", &value))
913 max98388->v_slot = value & 0xF;
914 else
915 max98388->v_slot = 0;
916
917 if (!device_property_read_u32(dev, "adi,imon-slot-no", &value))
918 max98388->i_slot = value & 0xF;
919 else
920 max98388->i_slot = 1;
921
922 if (device_property_read_bool(dev, "adi,interleave-mode"))
923 max98388->interleave_mode = true;
924 else
925 max98388->interleave_mode = false;
926 }
927
max98388_i2c_probe(struct i2c_client * i2c)928 static int max98388_i2c_probe(struct i2c_client *i2c)
929 {
930 int ret = 0;
931 int reg = 0;
932
933 struct max98388_priv *max98388 = NULL;
934
935 max98388 = devm_kzalloc(&i2c->dev, sizeof(*max98388), GFP_KERNEL);
936 if (!max98388)
937 return -ENOMEM;
938
939 i2c_set_clientdata(i2c, max98388);
940
941 /* regmap initialization */
942 max98388->regmap = devm_regmap_init_i2c(i2c, &max98388_regmap);
943 if (IS_ERR(max98388->regmap))
944 return dev_err_probe(&i2c->dev, PTR_ERR(max98388->regmap),
945 "Failed to allocate register map.\n");
946
947 /* voltage/current slot & gpio configuration */
948 max98388_read_deveice_property(&i2c->dev, max98388);
949
950 /* Device Reset */
951 max98388->reset_gpio = devm_gpiod_get_optional(&i2c->dev,
952 "reset", GPIOD_OUT_HIGH);
953 if (IS_ERR(max98388->reset_gpio))
954 return dev_err_probe(&i2c->dev, PTR_ERR(max98388->reset_gpio),
955 "Unable to request GPIO\n");
956
957 if (max98388->reset_gpio) {
958 usleep_range(5000, 6000);
959 gpiod_set_value_cansleep(max98388->reset_gpio, 0);
960 /* Wait for the hw reset done */
961 usleep_range(5000, 6000);
962 }
963
964 /* Read Revision ID */
965 ret = regmap_read(max98388->regmap,
966 MAX98388_R22FF_REV_ID, ®);
967 if (ret < 0)
968 return dev_err_probe(&i2c->dev, ret,
969 "Failed to read the revision ID\n");
970
971 dev_info(&i2c->dev, "MAX98388 revisionID: 0x%02X\n", reg);
972
973 /* codec registration */
974 ret = devm_snd_soc_register_component(&i2c->dev,
975 &soc_codec_dev_max98388,
976 max98388_dai,
977 ARRAY_SIZE(max98388_dai));
978 if (ret < 0)
979 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
980
981 return ret;
982 }
983
984 static const struct i2c_device_id max98388_i2c_id[] = {
985 { .name = "max98388" },
986 { }
987 };
988
989 MODULE_DEVICE_TABLE(i2c, max98388_i2c_id);
990
991 static const struct of_device_id max98388_of_match[] = {
992 { .compatible = "adi,max98388", },
993 { }
994 };
995 MODULE_DEVICE_TABLE(of, max98388_of_match);
996
997 static const struct acpi_device_id max98388_acpi_match[] = {
998 { "ADS8388", 0 },
999 {},
1000 };
1001 MODULE_DEVICE_TABLE(acpi, max98388_acpi_match);
1002
1003 static struct i2c_driver max98388_i2c_driver = {
1004 .driver = {
1005 .name = "max98388",
1006 .of_match_table = max98388_of_match,
1007 .acpi_match_table = max98388_acpi_match,
1008 .pm = pm_sleep_ptr(&max98388_pm),
1009 },
1010 .probe = max98388_i2c_probe,
1011 .id_table = max98388_i2c_id,
1012 };
1013
1014 module_i2c_driver(max98388_i2c_driver)
1015
1016 MODULE_DESCRIPTION("ALSA SoC MAX98388 driver");
1017 MODULE_AUTHOR("Ryan Lee <ryans.lee@analog.com>");
1018 MODULE_LICENSE("GPL");
1019