1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * MAX77620 pin control driver.
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Chaitanya Bandi <bandik@nvidia.com>
9 * Laxman Dewangan <ldewangan@nvidia.com>
10 */
11
12 #include <linux/mfd/max77620.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/property.h>
16 #include <linux/regmap.h>
17
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinmux.h>
22
23 #include "core.h"
24 #include "pinconf.h"
25 #include "pinctrl-utils.h"
26
27 #define MAX77620_PIN_NUM 8
28
29 enum max77620_pin_ppdrv {
30 MAX77620_PIN_UNCONFIG_DRV,
31 MAX77620_PIN_OD_DRV,
32 MAX77620_PIN_PP_DRV,
33 };
34
35 #define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
36 #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
37 #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
38 #define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
39 #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
40 #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
41
42 struct max77620_pin_function {
43 const char *name;
44 const char * const *groups;
45 unsigned int ngroups;
46 int mux_option;
47 };
48
49 static const struct pinconf_generic_params max77620_cfg_params[] = {
50 {
51 .property = "maxim,active-fps-source",
52 .param = MAX77620_ACTIVE_FPS_SOURCE,
53 }, {
54 .property = "maxim,active-fps-power-up-slot",
55 .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
56 }, {
57 .property = "maxim,active-fps-power-down-slot",
58 .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
59 }, {
60 .property = "maxim,suspend-fps-source",
61 .param = MAX77620_SUSPEND_FPS_SOURCE,
62 }, {
63 .property = "maxim,suspend-fps-power-up-slot",
64 .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
65 }, {
66 .property = "maxim,suspend-fps-power-down-slot",
67 .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
68 },
69 };
70
71 enum max77620_alternate_pinmux_option {
72 MAX77620_PINMUX_GPIO = 0,
73 MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
74 MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
75 MAX77620_PINMUX_32K_OUT1 = 3,
76 MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
77 MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
78 MAX77620_PINMUX_REFERENCE_OUT = 6,
79 };
80
81 struct max77620_pingroup {
82 const char *name;
83 const unsigned int pins[1];
84 unsigned int npins;
85 enum max77620_alternate_pinmux_option alt_option;
86 };
87
88 struct max77620_pin_info {
89 enum max77620_pin_ppdrv drv_type;
90 };
91
92 struct max77620_fps_config {
93 int active_fps_src;
94 int active_power_up_slots;
95 int active_power_down_slots;
96 int suspend_fps_src;
97 int suspend_power_up_slots;
98 int suspend_power_down_slots;
99 };
100
101 struct max77620_pctrl_info {
102 struct device *dev;
103 struct pinctrl_dev *pctl;
104 struct regmap *rmap;
105 const struct max77620_pin_function *functions;
106 unsigned int num_functions;
107 const struct max77620_pingroup *pin_groups;
108 int num_pin_groups;
109 const struct pinctrl_pin_desc *pins;
110 unsigned int num_pins;
111 struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
112 struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
113 };
114
115 static const struct pinctrl_pin_desc max77620_pins_desc[] = {
116 PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
117 PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
118 PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
119 PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
120 PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
121 PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
122 PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
123 PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
124 };
125
126 static const char * const gpio_groups[] = {
127 "gpio0",
128 "gpio1",
129 "gpio2",
130 "gpio3",
131 "gpio4",
132 "gpio5",
133 "gpio6",
134 "gpio7",
135 };
136
137 #define FUNCTION_GROUP(fname, mux) \
138 { \
139 .name = fname, \
140 .groups = gpio_groups, \
141 .ngroups = ARRAY_SIZE(gpio_groups), \
142 .mux_option = MAX77620_PINMUX_##mux, \
143 }
144
145 static const struct max77620_pin_function max77620_pin_function[] = {
146 FUNCTION_GROUP("gpio", GPIO),
147 FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
148 FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
149 FUNCTION_GROUP("32k-out1", 32K_OUT1),
150 FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
151 FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
152 FUNCTION_GROUP("reference-out", REFERENCE_OUT),
153 };
154
155 #define MAX77620_PINGROUP(pg_name, pin_id, option) \
156 { \
157 .name = #pg_name, \
158 .pins = {MAX77620_##pin_id}, \
159 .npins = 1, \
160 .alt_option = MAX77620_PINMUX_##option, \
161 }
162
163 static const struct max77620_pingroup max77620_pingroups[] = {
164 MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
165 MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
166 MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
167 MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
168 MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
169 MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
170 MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
171 MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
172 };
173
max77620_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)174 static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
175 {
176 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
177
178 return mpci->num_pin_groups;
179 }
180
max77620_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)181 static const char *max77620_pinctrl_get_group_name(
182 struct pinctrl_dev *pctldev, unsigned int group)
183 {
184 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
185
186 return mpci->pin_groups[group].name;
187 }
188
max77620_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)189 static int max77620_pinctrl_get_group_pins(
190 struct pinctrl_dev *pctldev, unsigned int group,
191 const unsigned int **pins, unsigned int *num_pins)
192 {
193 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
194
195 *pins = mpci->pin_groups[group].pins;
196 *num_pins = mpci->pin_groups[group].npins;
197
198 return 0;
199 }
200
201 static const struct pinctrl_ops max77620_pinctrl_ops = {
202 .get_groups_count = max77620_pinctrl_get_groups_count,
203 .get_group_name = max77620_pinctrl_get_group_name,
204 .get_group_pins = max77620_pinctrl_get_group_pins,
205 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
206 .dt_free_map = pinctrl_utils_free_map,
207 };
208
max77620_pinctrl_get_funcs_count(struct pinctrl_dev * pctldev)209 static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
210 {
211 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
212
213 return mpci->num_functions;
214 }
215
max77620_pinctrl_get_func_name(struct pinctrl_dev * pctldev,unsigned int function)216 static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
217 unsigned int function)
218 {
219 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
220
221 return mpci->functions[function].name;
222 }
223
max77620_pinctrl_get_func_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const num_groups)224 static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
225 unsigned int function,
226 const char * const **groups,
227 unsigned int * const num_groups)
228 {
229 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
230
231 *groups = mpci->functions[function].groups;
232 *num_groups = mpci->functions[function].ngroups;
233
234 return 0;
235 }
236
max77620_pinctrl_enable(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)237 static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
238 unsigned int function, unsigned int group)
239 {
240 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
241 u8 val;
242 int ret;
243
244 if (function == MAX77620_PINMUX_GPIO) {
245 val = 0;
246 } else if (function == mpci->pin_groups[group].alt_option) {
247 val = 1 << group;
248 } else {
249 dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
250 group, function);
251 return -EINVAL;
252 }
253 ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
254 BIT(group), val);
255 if (ret < 0)
256 dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
257
258 return ret;
259 }
260
261 static const struct pinmux_ops max77620_pinmux_ops = {
262 .get_functions_count = max77620_pinctrl_get_funcs_count,
263 .get_function_name = max77620_pinctrl_get_func_name,
264 .get_function_groups = max77620_pinctrl_get_func_groups,
265 .set_mux = max77620_pinctrl_enable,
266 };
267
max77620_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)268 static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
269 unsigned int pin, unsigned long *config)
270 {
271 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
272 struct device *dev = mpci->dev;
273 enum pin_config_param param = pinconf_to_config_param(*config);
274 unsigned int val;
275 int arg = 0;
276 int ret;
277
278 switch (param) {
279 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
280 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
281 arg = 1;
282 break;
283
284 case PIN_CONFIG_DRIVE_PUSH_PULL:
285 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
286 arg = 1;
287 break;
288
289 case PIN_CONFIG_BIAS_PULL_UP:
290 ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
291 if (ret < 0) {
292 dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
293 return ret;
294 }
295 if (val & BIT(pin))
296 arg = 1;
297 break;
298
299 case PIN_CONFIG_BIAS_PULL_DOWN:
300 ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
301 if (ret < 0) {
302 dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
303 return ret;
304 }
305 if (val & BIT(pin))
306 arg = 1;
307 break;
308
309 default:
310 dev_err(dev, "Properties not supported\n");
311 return -ENOTSUPP;
312 }
313
314 *config = pinconf_to_config_packed(param, (u16)arg);
315
316 return 0;
317 }
318
max77620_get_default_fps(struct max77620_pctrl_info * mpci,int addr,int * fps)319 static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
320 int addr, int *fps)
321 {
322 unsigned int val;
323 int ret;
324
325 ret = regmap_read(mpci->rmap, addr, &val);
326 if (ret < 0) {
327 dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
328 return ret;
329 }
330 *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
331
332 return 0;
333 }
334
max77620_set_fps_param(struct max77620_pctrl_info * mpci,int pin,int param)335 static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
336 int pin, int param)
337 {
338 struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
339 int addr, ret;
340 int param_val;
341 int mask, shift;
342
343 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
344 return 0;
345
346 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
347 switch (param) {
348 case MAX77620_ACTIVE_FPS_SOURCE:
349 case MAX77620_SUSPEND_FPS_SOURCE:
350 mask = MAX77620_FPS_SRC_MASK;
351 shift = MAX77620_FPS_SRC_SHIFT;
352 param_val = fps_config->active_fps_src;
353 if (param == MAX77620_SUSPEND_FPS_SOURCE)
354 param_val = fps_config->suspend_fps_src;
355 break;
356
357 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
358 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
359 mask = MAX77620_FPS_PU_PERIOD_MASK;
360 shift = MAX77620_FPS_PU_PERIOD_SHIFT;
361 param_val = fps_config->active_power_up_slots;
362 if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
363 param_val = fps_config->suspend_power_up_slots;
364 break;
365
366 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
367 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
368 mask = MAX77620_FPS_PD_PERIOD_MASK;
369 shift = MAX77620_FPS_PD_PERIOD_SHIFT;
370 param_val = fps_config->active_power_down_slots;
371 if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
372 param_val = fps_config->suspend_power_down_slots;
373 break;
374
375 default:
376 dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
377 param, pin);
378 return -EINVAL;
379 }
380
381 if (param_val < 0)
382 return 0;
383
384 ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
385 if (ret < 0)
386 dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
387
388 return ret;
389 }
390
max77620_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)391 static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
392 unsigned int pin, unsigned long *configs,
393 unsigned int num_configs)
394 {
395 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
396 struct device *dev = mpci->dev;
397 struct max77620_fps_config *fps_config;
398 int param;
399 u32 param_val;
400 unsigned int val;
401 unsigned int pu_val;
402 unsigned int pd_val;
403 int addr, ret;
404 int i;
405
406 for (i = 0; i < num_configs; i++) {
407 param = pinconf_to_config_param(configs[i]);
408 param_val = pinconf_to_config_argument(configs[i]);
409
410 switch (param) {
411 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
412 val = param_val ? 0 : 1;
413 ret = regmap_update_bits(mpci->rmap,
414 MAX77620_REG_GPIO0 + pin,
415 MAX77620_CNFG_GPIO_DRV_MASK,
416 val);
417 if (ret)
418 goto report_update_failure;
419
420 mpci->pin_info[pin].drv_type = val ?
421 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
422 break;
423
424 case PIN_CONFIG_DRIVE_PUSH_PULL:
425 val = param_val ? 1 : 0;
426 ret = regmap_update_bits(mpci->rmap,
427 MAX77620_REG_GPIO0 + pin,
428 MAX77620_CNFG_GPIO_DRV_MASK,
429 val);
430 if (ret)
431 goto report_update_failure;
432
433 mpci->pin_info[pin].drv_type = val ?
434 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
435 break;
436
437 case MAX77620_ACTIVE_FPS_SOURCE:
438 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
439 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
440 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
441 return -EINVAL;
442
443 fps_config = &mpci->fps_config[pin];
444
445 if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
446 (param_val == MAX77620_FPS_SRC_DEF)) {
447 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
448 ret = max77620_get_default_fps(
449 mpci, addr,
450 &fps_config->active_fps_src);
451 if (ret < 0)
452 return ret;
453 break;
454 }
455
456 if (param == MAX77620_ACTIVE_FPS_SOURCE)
457 fps_config->active_fps_src = param_val;
458 else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
459 fps_config->active_power_up_slots = param_val;
460 else
461 fps_config->active_power_down_slots = param_val;
462
463 ret = max77620_set_fps_param(mpci, pin, param);
464 if (ret < 0)
465 return ret;
466 break;
467
468 case MAX77620_SUSPEND_FPS_SOURCE:
469 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
470 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
471 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
472 return -EINVAL;
473
474 fps_config = &mpci->fps_config[pin];
475
476 if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
477 (param_val == MAX77620_FPS_SRC_DEF)) {
478 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
479 ret = max77620_get_default_fps(
480 mpci, addr,
481 &fps_config->suspend_fps_src);
482 if (ret < 0)
483 return ret;
484 break;
485 }
486
487 if (param == MAX77620_SUSPEND_FPS_SOURCE)
488 fps_config->suspend_fps_src = param_val;
489 else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
490 fps_config->suspend_power_up_slots = param_val;
491 else
492 fps_config->suspend_power_down_slots =
493 param_val;
494 break;
495
496 case PIN_CONFIG_BIAS_PULL_UP:
497 case PIN_CONFIG_BIAS_PULL_DOWN:
498 pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
499 BIT(pin) : 0;
500 pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
501 BIT(pin) : 0;
502
503 ret = regmap_update_bits(mpci->rmap,
504 MAX77620_REG_PUE_GPIO,
505 BIT(pin), pu_val);
506 if (ret < 0) {
507 dev_err(dev, "PUE_GPIO update failed: %d\n",
508 ret);
509 return ret;
510 }
511
512 ret = regmap_update_bits(mpci->rmap,
513 MAX77620_REG_PDE_GPIO,
514 BIT(pin), pd_val);
515 if (ret < 0) {
516 dev_err(dev, "PDE_GPIO update failed: %d\n",
517 ret);
518 return ret;
519 }
520 break;
521
522 default:
523 dev_err(dev, "Properties not supported\n");
524 return -ENOTSUPP;
525 }
526 }
527
528 return 0;
529
530 report_update_failure:
531 dev_err(dev, "Reg 0x%02x update failed %d\n",
532 MAX77620_REG_GPIO0 + pin, ret);
533 return ret;
534 }
535
536 static const struct pinconf_ops max77620_pinconf_ops = {
537 .pin_config_get = max77620_pinconf_get,
538 .pin_config_set = max77620_pinconf_set,
539 };
540
541 static struct pinctrl_desc max77620_pinctrl_desc = {
542 .pctlops = &max77620_pinctrl_ops,
543 .pmxops = &max77620_pinmux_ops,
544 .confops = &max77620_pinconf_ops,
545 .pins = max77620_pins_desc,
546 .npins = ARRAY_SIZE(max77620_pins_desc),
547 .num_custom_params = ARRAY_SIZE(max77620_cfg_params),
548 .custom_params = max77620_cfg_params,
549 };
550
max77620_pinctrl_probe(struct platform_device * pdev)551 static int max77620_pinctrl_probe(struct platform_device *pdev)
552 {
553 struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
554 struct max77620_pctrl_info *mpci;
555 int i;
556
557 device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
558
559 mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
560 if (!mpci)
561 return -ENOMEM;
562
563 mpci->dev = &pdev->dev;
564 mpci->rmap = max77620->rmap;
565
566 mpci->pins = max77620_pins_desc;
567 mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
568 mpci->functions = max77620_pin_function;
569 mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
570 mpci->pin_groups = max77620_pingroups;
571 mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
572 platform_set_drvdata(pdev, mpci);
573
574 max77620_pinctrl_desc.name = dev_name(&pdev->dev);
575
576 for (i = 0; i < MAX77620_PIN_NUM; ++i) {
577 mpci->fps_config[i].active_fps_src = -1;
578 mpci->fps_config[i].active_power_up_slots = -1;
579 mpci->fps_config[i].active_power_down_slots = -1;
580 mpci->fps_config[i].suspend_fps_src = -1;
581 mpci->fps_config[i].suspend_power_up_slots = -1;
582 mpci->fps_config[i].suspend_power_down_slots = -1;
583 }
584
585 mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
586 mpci);
587 if (IS_ERR(mpci->pctl)) {
588 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
589 return PTR_ERR(mpci->pctl);
590 }
591
592 return 0;
593 }
594
595 #ifdef CONFIG_PM_SLEEP
596 static int max77620_suspend_fps_param[] = {
597 MAX77620_SUSPEND_FPS_SOURCE,
598 MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
599 MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
600 };
601
602 static int max77620_active_fps_param[] = {
603 MAX77620_ACTIVE_FPS_SOURCE,
604 MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
605 MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
606 };
607
max77620_pinctrl_suspend(struct device * dev)608 static int max77620_pinctrl_suspend(struct device *dev)
609 {
610 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
611 int pin, p;
612
613 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
614 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
615 continue;
616 for (p = 0; p < 3; ++p)
617 max77620_set_fps_param(
618 mpci, pin, max77620_suspend_fps_param[p]);
619 }
620
621 return 0;
622 };
623
max77620_pinctrl_resume(struct device * dev)624 static int max77620_pinctrl_resume(struct device *dev)
625 {
626 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
627 int pin, p;
628
629 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
630 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
631 continue;
632 for (p = 0; p < 3; ++p)
633 max77620_set_fps_param(
634 mpci, pin, max77620_active_fps_param[p]);
635 }
636
637 return 0;
638 }
639 #endif
640
641 static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
642 SET_SYSTEM_SLEEP_PM_OPS(
643 max77620_pinctrl_suspend, max77620_pinctrl_resume)
644 };
645
646 static const struct platform_device_id max77620_pinctrl_devtype[] = {
647 { .name = "max77620-pinctrl" },
648 { .name = "max20024-pinctrl" },
649 { }
650 };
651 MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
652
653 static struct platform_driver max77620_pinctrl_driver = {
654 .driver = {
655 .name = "max77620-pinctrl",
656 .pm = &max77620_pinctrl_pm_ops,
657 },
658 .probe = max77620_pinctrl_probe,
659 .id_table = max77620_pinctrl_devtype,
660 };
661
662 module_platform_driver(max77620_pinctrl_driver);
663
664 MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
665 MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
666 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
667 MODULE_LICENSE("GPL v2");
668