1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * MAXIM MAX77620 GPIO driver
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/mfd/max77620.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14
15 #define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
16
17 struct max77620_gpio {
18 struct gpio_chip gpio_chip;
19 struct regmap *rmap;
20 struct device *dev;
21 struct mutex buslock; /* irq_bus_lock */
22 unsigned int irq_type[MAX77620_GPIO_NR];
23 bool irq_enabled[MAX77620_GPIO_NR];
24 };
25
max77620_gpio_irqhandler(int irq,void * data)26 static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
27 {
28 struct max77620_gpio *gpio = data;
29 unsigned int value, offset;
30 unsigned long pending;
31 int err;
32
33 err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
34 if (err < 0) {
35 dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
36 return IRQ_NONE;
37 }
38
39 pending = value;
40
41 for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
42 unsigned int virq;
43
44 virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
45 handle_nested_irq(virq);
46 }
47
48 return IRQ_HANDLED;
49 }
50
max77620_gpio_irq_mask(struct irq_data * data)51 static void max77620_gpio_irq_mask(struct irq_data *data)
52 {
53 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
54 struct max77620_gpio *gpio = gpiochip_get_data(chip);
55
56 gpio->irq_enabled[data->hwirq] = false;
57 gpiochip_disable_irq(chip, data->hwirq);
58 }
59
max77620_gpio_irq_unmask(struct irq_data * data)60 static void max77620_gpio_irq_unmask(struct irq_data *data)
61 {
62 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
63 struct max77620_gpio *gpio = gpiochip_get_data(chip);
64
65 gpiochip_enable_irq(chip, data->hwirq);
66 gpio->irq_enabled[data->hwirq] = true;
67 }
68
max77620_gpio_set_irq_type(struct irq_data * data,unsigned int type)69 static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
70 {
71 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
72 struct max77620_gpio *gpio = gpiochip_get_data(chip);
73 unsigned int irq_type;
74
75 switch (type) {
76 case IRQ_TYPE_EDGE_RISING:
77 irq_type = MAX77620_CNFG_GPIO_INT_RISING;
78 break;
79
80 case IRQ_TYPE_EDGE_FALLING:
81 irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
82 break;
83
84 case IRQ_TYPE_EDGE_BOTH:
85 irq_type = MAX77620_CNFG_GPIO_INT_RISING |
86 MAX77620_CNFG_GPIO_INT_FALLING;
87 break;
88
89 default:
90 return -EINVAL;
91 }
92
93 gpio->irq_type[data->hwirq] = irq_type;
94
95 return 0;
96 }
97
max77620_gpio_bus_lock(struct irq_data * data)98 static void max77620_gpio_bus_lock(struct irq_data *data)
99 {
100 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
101 struct max77620_gpio *gpio = gpiochip_get_data(chip);
102
103 mutex_lock(&gpio->buslock);
104 }
105
max77620_gpio_bus_sync_unlock(struct irq_data * data)106 static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
107 {
108 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
109 struct max77620_gpio *gpio = gpiochip_get_data(chip);
110 unsigned int value, offset = data->hwirq;
111 int err;
112
113 value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
114
115 err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
116 MAX77620_CNFG_GPIO_INT_MASK, value);
117 if (err < 0)
118 dev_err(chip->parent, "failed to update interrupt mask: %d\n",
119 err);
120
121 mutex_unlock(&gpio->buslock);
122 }
123
124 static const struct irq_chip max77620_gpio_irqchip = {
125 .name = "max77620-gpio",
126 .irq_mask = max77620_gpio_irq_mask,
127 .irq_unmask = max77620_gpio_irq_unmask,
128 .irq_set_type = max77620_gpio_set_irq_type,
129 .irq_bus_lock = max77620_gpio_bus_lock,
130 .irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
131 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
132 GPIOCHIP_IRQ_RESOURCE_HELPERS,
133 };
134
max77620_gpio_dir_input(struct gpio_chip * gc,unsigned int offset)135 static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
136 {
137 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
138 int ret;
139
140 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
141 MAX77620_CNFG_GPIO_DIR_MASK,
142 MAX77620_CNFG_GPIO_DIR_INPUT);
143 if (ret < 0)
144 dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
145
146 return ret;
147 }
148
max77620_gpio_get(struct gpio_chip * gc,unsigned int offset)149 static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
150 {
151 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
152 unsigned int val;
153 int ret;
154
155 ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
156 if (ret < 0) {
157 dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
158 return ret;
159 }
160
161 if (val & MAX77620_CNFG_GPIO_DIR_MASK)
162 return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
163 else
164 return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
165 }
166
max77620_gpio_dir_output(struct gpio_chip * gc,unsigned int offset,int value)167 static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
168 int value)
169 {
170 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
171 u8 val;
172 int ret;
173
174 val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
175 MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
176
177 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
178 MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
179 if (ret < 0) {
180 dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
181 return ret;
182 }
183
184 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
185 MAX77620_CNFG_GPIO_DIR_MASK,
186 MAX77620_CNFG_GPIO_DIR_OUTPUT);
187 if (ret < 0)
188 dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
189
190 return ret;
191 }
192
max77620_gpio_set_debounce(struct max77620_gpio * mgpio,unsigned int offset,unsigned int debounce)193 static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
194 unsigned int offset,
195 unsigned int debounce)
196 {
197 u8 val;
198 int ret;
199
200 switch (debounce) {
201 case 0:
202 val = MAX77620_CNFG_GPIO_DBNC_None;
203 break;
204 case 1 ... 8000:
205 val = MAX77620_CNFG_GPIO_DBNC_8ms;
206 break;
207 case 8001 ... 16000:
208 val = MAX77620_CNFG_GPIO_DBNC_16ms;
209 break;
210 case 16001 ... 32000:
211 val = MAX77620_CNFG_GPIO_DBNC_32ms;
212 break;
213 default:
214 dev_err(mgpio->dev, "Illegal value %u\n", debounce);
215 return -EINVAL;
216 }
217
218 ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
219 MAX77620_CNFG_GPIO_DBNC_MASK, val);
220 if (ret < 0)
221 dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
222
223 return ret;
224 }
225
max77620_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)226 static int max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
227 int value)
228 {
229 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
230 u8 val;
231
232 val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
233 MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
234
235 return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
236 MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
237 }
238
max77620_gpio_set_config(struct gpio_chip * gc,unsigned int offset,unsigned long config)239 static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
240 unsigned long config)
241 {
242 struct max77620_gpio *mgpio = gpiochip_get_data(gc);
243
244 switch (pinconf_to_config_param(config)) {
245 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
246 return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
247 MAX77620_CNFG_GPIO_DRV_MASK,
248 MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
249 case PIN_CONFIG_DRIVE_PUSH_PULL:
250 return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
251 MAX77620_CNFG_GPIO_DRV_MASK,
252 MAX77620_CNFG_GPIO_DRV_PUSHPULL);
253 case PIN_CONFIG_INPUT_DEBOUNCE:
254 return max77620_gpio_set_debounce(mgpio, offset,
255 pinconf_to_config_argument(config));
256 default:
257 break;
258 }
259
260 return -ENOTSUPP;
261 }
262
max77620_gpio_irq_init_hw(struct gpio_chip * gc)263 static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
264 {
265 struct max77620_gpio *gpio = gpiochip_get_data(gc);
266 unsigned int i;
267 int err;
268
269 /*
270 * GPIO interrupts may be left ON after bootloader, hence let's
271 * pre-initialize hardware to the expected state by disabling all
272 * the interrupts.
273 */
274 for (i = 0; i < MAX77620_GPIO_NR; i++) {
275 err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
276 MAX77620_CNFG_GPIO_INT_MASK, 0);
277 if (err < 0) {
278 dev_err(gpio->dev,
279 "failed to disable interrupt: %d\n", err);
280 return err;
281 }
282 }
283
284 return 0;
285 }
286
max77620_gpio_probe(struct platform_device * pdev)287 static int max77620_gpio_probe(struct platform_device *pdev)
288 {
289 struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
290 struct max77620_gpio *mgpio;
291 struct gpio_irq_chip *girq;
292 unsigned int gpio_irq;
293 int ret;
294
295 ret = platform_get_irq(pdev, 0);
296 if (ret < 0)
297 return ret;
298
299 gpio_irq = ret;
300
301 mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
302 if (!mgpio)
303 return -ENOMEM;
304
305 mutex_init(&mgpio->buslock);
306 mgpio->rmap = chip->rmap;
307 mgpio->dev = &pdev->dev;
308
309 mgpio->gpio_chip.label = pdev->name;
310 mgpio->gpio_chip.parent = pdev->dev.parent;
311 mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
312 mgpio->gpio_chip.get = max77620_gpio_get;
313 mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
314 mgpio->gpio_chip.set_rv = max77620_gpio_set;
315 mgpio->gpio_chip.set_config = max77620_gpio_set_config;
316 mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
317 mgpio->gpio_chip.can_sleep = 1;
318 mgpio->gpio_chip.base = -1;
319
320 girq = &mgpio->gpio_chip.irq;
321 gpio_irq_chip_set_chip(girq, &max77620_gpio_irqchip);
322 /* This will let us handle the parent IRQ in the driver */
323 girq->parent_handler = NULL;
324 girq->num_parents = 0;
325 girq->parents = NULL;
326 girq->default_type = IRQ_TYPE_NONE;
327 girq->handler = handle_edge_irq;
328 girq->init_hw = max77620_gpio_irq_init_hw;
329 girq->threaded = true;
330
331 ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
332 if (ret < 0) {
333 dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
334 return ret;
335 }
336
337 ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
338 max77620_gpio_irqhandler, IRQF_ONESHOT,
339 "max77620-gpio", mgpio);
340 if (ret < 0) {
341 dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
342 return ret;
343 }
344
345 return 0;
346 }
347
348 static const struct platform_device_id max77620_gpio_devtype[] = {
349 { .name = "max77620-gpio", },
350 { .name = "max20024-gpio", },
351 {},
352 };
353 MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
354
355 static struct platform_driver max77620_gpio_driver = {
356 .driver.name = "max77620-gpio",
357 .probe = max77620_gpio_probe,
358 .id_table = max77620_gpio_devtype,
359 };
360
361 module_platform_driver(max77620_gpio_driver);
362
363 MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
364 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
365 MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
366 MODULE_LICENSE("GPL v2");
367