1 // SPDX-License-Identifier: GPL-2.0-only
2
3 /*
4 * Copyright (c) Linumiz 2021
5 *
6 * max31865.c - Maxim MAX31865 RTD-to-Digital Converter sensor driver
7 *
8 * Author: Navin Sankar Velliangiri <navin@linumiz.com>
9 */
10
11 #include <linux/ctype.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/property.h>
19 #include <linux/spi/spi.h>
20 #include <linux/unaligned.h>
21
22 /*
23 * The MSB of the register value determines whether the following byte will
24 * be written or read. If it is 0, read will follow and if it is 1, write
25 * will follow.
26 */
27 #define MAX31865_RD_WR_BIT BIT(7)
28
29 #define MAX31865_CFG_VBIAS BIT(7)
30 #define MAX31865_CFG_1SHOT BIT(5)
31 #define MAX31865_3WIRE_RTD BIT(4)
32 #define MAX31865_FAULT_STATUS_CLEAR BIT(1)
33 #define MAX31865_FILTER_50HZ BIT(0)
34
35 /* The MAX31865 registers */
36 #define MAX31865_CFG_REG 0x00
37 #define MAX31865_RTD_MSB 0x01
38 #define MAX31865_FAULT_STATUS 0x07
39
40 #define MAX31865_FAULT_OVUV BIT(2)
41
42 static const char max31865_show_samp_freq[] = "50 60";
43
44 static const struct iio_chan_spec max31865_channels[] = {
45 { /* RTD Temperature */
46 .type = IIO_TEMP,
47 .info_mask_separate =
48 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE)
49 },
50 };
51
52 struct max31865_data {
53 struct spi_device *spi;
54 struct mutex lock;
55 bool filter_50hz;
56 bool three_wire;
57 u8 buf[2] __aligned(IIO_DMA_MINALIGN);
58 };
59
max31865_read(struct max31865_data * data,u8 reg,unsigned int read_size)60 static int max31865_read(struct max31865_data *data, u8 reg,
61 unsigned int read_size)
62 {
63 return spi_write_then_read(data->spi, ®, 1, data->buf, read_size);
64 }
65
max31865_write(struct max31865_data * data,size_t len)66 static int max31865_write(struct max31865_data *data, size_t len)
67 {
68 return spi_write(data->spi, data->buf, len);
69 }
70
enable_bias(struct max31865_data * data)71 static int enable_bias(struct max31865_data *data)
72 {
73 u8 cfg;
74 int ret;
75
76 ret = max31865_read(data, MAX31865_CFG_REG, 1);
77 if (ret)
78 return ret;
79
80 cfg = data->buf[0];
81
82 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
83 data->buf[1] = cfg | MAX31865_CFG_VBIAS;
84
85 return max31865_write(data, 2);
86 }
87
disable_bias(struct max31865_data * data)88 static int disable_bias(struct max31865_data *data)
89 {
90 u8 cfg;
91 int ret;
92
93 ret = max31865_read(data, MAX31865_CFG_REG, 1);
94 if (ret)
95 return ret;
96
97 cfg = data->buf[0];
98 cfg &= ~MAX31865_CFG_VBIAS;
99
100 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
101 data->buf[1] = cfg;
102
103 return max31865_write(data, 2);
104 }
105
max31865_rtd_read(struct max31865_data * data,int * val)106 static int max31865_rtd_read(struct max31865_data *data, int *val)
107 {
108 u8 reg;
109 int ret;
110
111 /* Enable BIAS to start the conversion */
112 ret = enable_bias(data);
113 if (ret)
114 return ret;
115
116 /* wait 10.5ms before initiating the conversion */
117 msleep(11);
118
119 ret = max31865_read(data, MAX31865_CFG_REG, 1);
120 if (ret)
121 return ret;
122
123 reg = data->buf[0];
124 reg |= MAX31865_CFG_1SHOT | MAX31865_FAULT_STATUS_CLEAR;
125 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
126 data->buf[1] = reg;
127
128 ret = max31865_write(data, 2);
129 if (ret)
130 return ret;
131
132 if (data->filter_50hz) {
133 /* 50Hz filter mode requires 62.5ms to complete */
134 msleep(63);
135 } else {
136 /* 60Hz filter mode requires 52ms to complete */
137 msleep(52);
138 }
139
140 ret = max31865_read(data, MAX31865_RTD_MSB, 2);
141 if (ret)
142 return ret;
143
144 *val = get_unaligned_be16(&data->buf) >> 1;
145
146 return disable_bias(data);
147 }
148
max31865_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)149 static int max31865_read_raw(struct iio_dev *indio_dev,
150 struct iio_chan_spec const *chan,
151 int *val, int *val2, long mask)
152 {
153 struct max31865_data *data = iio_priv(indio_dev);
154 int ret;
155
156 switch (mask) {
157 case IIO_CHAN_INFO_RAW:
158 mutex_lock(&data->lock);
159 ret = max31865_rtd_read(data, val);
160 mutex_unlock(&data->lock);
161 if (ret)
162 return ret;
163 return IIO_VAL_INT;
164 case IIO_CHAN_INFO_SCALE:
165 /* Temp. Data resolution is 0.03125 degree centigrade */
166 *val = 31;
167 *val2 = 250000; /* 1000 * 0.03125 */
168 return IIO_VAL_INT_PLUS_MICRO;
169 default:
170 return -EINVAL;
171 }
172 }
173
max31865_init(struct max31865_data * data)174 static int max31865_init(struct max31865_data *data)
175 {
176 u8 cfg;
177 int ret;
178
179 ret = max31865_read(data, MAX31865_CFG_REG, 1);
180 if (ret)
181 return ret;
182
183 cfg = data->buf[0];
184
185 if (data->three_wire)
186 /* 3-wire RTD connection */
187 cfg |= MAX31865_3WIRE_RTD;
188
189 if (data->filter_50hz)
190 /* 50Hz noise rejection filter */
191 cfg |= MAX31865_FILTER_50HZ;
192
193 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT;
194 data->buf[1] = cfg;
195
196 return max31865_write(data, 2);
197 }
198
show_fault(struct device * dev,u8 faultbit,char * buf)199 static ssize_t show_fault(struct device *dev, u8 faultbit, char *buf)
200 {
201 int ret;
202 bool fault;
203 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
204 struct max31865_data *data = iio_priv(indio_dev);
205
206 ret = max31865_read(data, MAX31865_FAULT_STATUS, 1);
207 if (ret)
208 return ret;
209
210 fault = data->buf[0] & faultbit;
211
212 return sysfs_emit(buf, "%d\n", fault);
213 }
214
show_fault_ovuv(struct device * dev,struct device_attribute * attr,char * buf)215 static ssize_t show_fault_ovuv(struct device *dev,
216 struct device_attribute *attr,
217 char *buf)
218 {
219 return show_fault(dev, MAX31865_FAULT_OVUV, buf);
220 }
221
show_filter(struct device * dev,struct device_attribute * attr,char * buf)222 static ssize_t show_filter(struct device *dev,
223 struct device_attribute *attr,
224 char *buf)
225 {
226 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
227 struct max31865_data *data = iio_priv(indio_dev);
228
229 return sysfs_emit(buf, "%d\n", data->filter_50hz ? 50 : 60);
230 }
231
set_filter(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)232 static ssize_t set_filter(struct device *dev,
233 struct device_attribute *attr,
234 const char *buf,
235 size_t len)
236 {
237 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
238 struct max31865_data *data = iio_priv(indio_dev);
239 unsigned int freq;
240 int ret;
241
242 ret = kstrtouint(buf, 10, &freq);
243 if (ret)
244 return ret;
245
246 switch (freq) {
247 case 50:
248 data->filter_50hz = true;
249 break;
250 case 60:
251 data->filter_50hz = false;
252 break;
253 default:
254 return -EINVAL;
255 }
256
257 mutex_lock(&data->lock);
258 ret = max31865_init(data);
259 mutex_unlock(&data->lock);
260 if (ret)
261 return ret;
262
263 return len;
264 }
265
266 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(max31865_show_samp_freq);
267 static IIO_DEVICE_ATTR(fault_ovuv, 0444, show_fault_ovuv, NULL, 0);
268 static IIO_DEVICE_ATTR(in_filter_notch_center_frequency, 0644,
269 show_filter, set_filter, 0);
270
271 static struct attribute *max31865_attributes[] = {
272 &iio_dev_attr_fault_ovuv.dev_attr.attr,
273 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
274 &iio_dev_attr_in_filter_notch_center_frequency.dev_attr.attr,
275 NULL,
276 };
277
278 static const struct attribute_group max31865_group = {
279 .attrs = max31865_attributes,
280 };
281
282 static const struct iio_info max31865_info = {
283 .read_raw = max31865_read_raw,
284 .attrs = &max31865_group,
285 };
286
max31865_probe(struct spi_device * spi)287 static int max31865_probe(struct spi_device *spi)
288 {
289 const struct spi_device_id *id = spi_get_device_id(spi);
290 struct iio_dev *indio_dev;
291 struct max31865_data *data;
292 int ret;
293
294 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
295 if (!indio_dev)
296 return -ENOMEM;
297
298 data = iio_priv(indio_dev);
299 data->spi = spi;
300 data->filter_50hz = false;
301 mutex_init(&data->lock);
302
303 indio_dev->info = &max31865_info;
304 indio_dev->name = id->name;
305 indio_dev->modes = INDIO_DIRECT_MODE;
306 indio_dev->channels = max31865_channels;
307 indio_dev->num_channels = ARRAY_SIZE(max31865_channels);
308
309 if (device_property_read_bool(&spi->dev, "maxim,3-wire")) {
310 /* select 3 wire */
311 data->three_wire = 1;
312 } else {
313 /* select 2 or 4 wire */
314 data->three_wire = 0;
315 }
316
317 ret = max31865_init(data);
318 if (ret) {
319 dev_err(&spi->dev, "error: Failed to configure max31865\n");
320 return ret;
321 }
322
323 return devm_iio_device_register(&spi->dev, indio_dev);
324 }
325
326 static const struct spi_device_id max31865_id[] = {
327 { .name = "max31865" },
328 { }
329 };
330 MODULE_DEVICE_TABLE(spi, max31865_id);
331
332 static const struct of_device_id max31865_of_match[] = {
333 { .compatible = "maxim,max31865" },
334 { }
335 };
336 MODULE_DEVICE_TABLE(of, max31865_of_match);
337
338 static struct spi_driver max31865_driver = {
339 .driver = {
340 .name = "max31865",
341 .of_match_table = max31865_of_match,
342 },
343 .probe = max31865_probe,
344 .id_table = max31865_id,
345 };
346 module_spi_driver(max31865_driver);
347
348 MODULE_AUTHOR("Navin Sankar Velliangiri <navin@linumiz.com>");
349 MODULE_DESCRIPTION("Maxim MAX31865 RTD-to-Digital Converter sensor driver");
350 MODULE_LICENSE("GPL v2");
351