1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 *
5 * Read out the current hardware modeset state, and sanitize it to the current
6 * state.
7 */
8
9 #include <drm/drm_atomic_uapi.h>
10 #include <drm/drm_atomic_state_helper.h>
11 #include <drm/drm_vblank.h>
12
13 #include "i915_drv.h"
14 #include "i915_reg.h"
15 #include "i9xx_wm.h"
16 #include "intel_atomic.h"
17 #include "intel_bw.h"
18 #include "intel_color.h"
19 #include "intel_crtc.h"
20 #include "intel_crtc_state_dump.h"
21 #include "intel_ddi.h"
22 #include "intel_de.h"
23 #include "intel_display.h"
24 #include "intel_display_power.h"
25 #include "intel_display_types.h"
26 #include "intel_dmc.h"
27 #include "intel_fifo_underrun.h"
28 #include "intel_modeset_setup.h"
29 #include "intel_pch_display.h"
30 #include "intel_pmdemand.h"
31 #include "intel_tc.h"
32 #include "intel_vblank.h"
33 #include "intel_wm.h"
34 #include "skl_watermark.h"
35
intel_crtc_disable_noatomic_begin(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)36 static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
37 struct drm_modeset_acquire_ctx *ctx)
38 {
39 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
40 struct intel_crtc_state *crtc_state =
41 to_intel_crtc_state(crtc->base.state);
42 struct intel_plane *plane;
43 struct drm_atomic_state *state;
44 struct intel_crtc *temp_crtc;
45 enum pipe pipe = crtc->pipe;
46
47 if (!crtc_state->hw.active)
48 return;
49
50 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
51 const struct intel_plane_state *plane_state =
52 to_intel_plane_state(plane->base.state);
53
54 if (plane_state->uapi.visible)
55 intel_plane_disable_noatomic(crtc, plane);
56 }
57
58 state = drm_atomic_state_alloc(&i915->drm);
59 if (!state) {
60 drm_dbg_kms(&i915->drm,
61 "failed to disable [CRTC:%d:%s], out of memory",
62 crtc->base.base.id, crtc->base.name);
63 return;
64 }
65
66 state->acquire_ctx = ctx;
67 to_intel_atomic_state(state)->internal = true;
68
69 /* Everything's already locked, -EDEADLK can't happen. */
70 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
71 BIT(pipe) |
72 intel_crtc_joiner_secondary_pipes(crtc_state)) {
73 struct intel_crtc_state *temp_crtc_state =
74 intel_atomic_get_crtc_state(state, temp_crtc);
75 int ret;
76
77 ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base);
78
79 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
80 }
81
82 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
83
84 drm_atomic_state_put(state);
85
86 drm_dbg_kms(&i915->drm,
87 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
88 crtc->base.base.id, crtc->base.name);
89
90 crtc->active = false;
91 crtc->base.enabled = false;
92
93 if (crtc_state->shared_dpll)
94 intel_unreference_shared_dpll_crtc(crtc,
95 crtc_state->shared_dpll,
96 &crtc_state->shared_dpll->state);
97 }
98
set_encoder_for_connector(struct intel_connector * connector,struct intel_encoder * encoder)99 static void set_encoder_for_connector(struct intel_connector *connector,
100 struct intel_encoder *encoder)
101 {
102 struct drm_connector_state *conn_state = connector->base.state;
103
104 if (conn_state->crtc)
105 drm_connector_put(&connector->base);
106
107 if (encoder) {
108 conn_state->best_encoder = &encoder->base;
109 conn_state->crtc = encoder->base.crtc;
110 drm_connector_get(&connector->base);
111 } else {
112 conn_state->best_encoder = NULL;
113 conn_state->crtc = NULL;
114 }
115 }
116
reset_encoder_connector_state(struct intel_encoder * encoder)117 static void reset_encoder_connector_state(struct intel_encoder *encoder)
118 {
119 struct intel_display *display = to_intel_display(encoder);
120 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
121 struct intel_pmdemand_state *pmdemand_state =
122 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
123 struct intel_connector *connector;
124 struct drm_connector_list_iter conn_iter;
125
126 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
127 for_each_intel_connector_iter(connector, &conn_iter) {
128 if (connector->base.encoder != &encoder->base)
129 continue;
130
131 /* Clear the corresponding bit in pmdemand active phys mask */
132 intel_pmdemand_update_phys_mask(display, encoder,
133 pmdemand_state, false);
134
135 set_encoder_for_connector(connector, NULL);
136
137 connector->base.dpms = DRM_MODE_DPMS_OFF;
138 connector->base.encoder = NULL;
139 }
140 drm_connector_list_iter_end(&conn_iter);
141 }
142
reset_crtc_encoder_state(struct intel_crtc * crtc)143 static void reset_crtc_encoder_state(struct intel_crtc *crtc)
144 {
145 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
146 struct intel_encoder *encoder;
147
148 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) {
149 reset_encoder_connector_state(encoder);
150 encoder->base.crtc = NULL;
151 }
152 }
153
intel_crtc_disable_noatomic_complete(struct intel_crtc * crtc)154 static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
155 {
156 struct intel_display *display = to_intel_display(crtc);
157 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
158 struct intel_bw_state *bw_state =
159 to_intel_bw_state(i915->display.bw.obj.state);
160 struct intel_cdclk_state *cdclk_state =
161 to_intel_cdclk_state(i915->display.cdclk.obj.state);
162 struct intel_dbuf_state *dbuf_state =
163 to_intel_dbuf_state(i915->display.dbuf.obj.state);
164 struct intel_pmdemand_state *pmdemand_state =
165 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
166 struct intel_crtc_state *crtc_state =
167 to_intel_crtc_state(crtc->base.state);
168 enum pipe pipe = crtc->pipe;
169
170 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
171 intel_crtc_free_hw_state(crtc_state);
172 intel_crtc_state_reset(crtc_state, crtc);
173
174 reset_crtc_encoder_state(crtc);
175
176 intel_fbc_disable(crtc);
177 intel_update_watermarks(i915);
178
179 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
180
181 cdclk_state->min_cdclk[pipe] = 0;
182 cdclk_state->min_voltage_level[pipe] = 0;
183 cdclk_state->active_pipes &= ~BIT(pipe);
184
185 dbuf_state->active_pipes &= ~BIT(pipe);
186
187 bw_state->data_rate[pipe] = 0;
188 bw_state->num_active_planes[pipe] = 0;
189
190 intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);
191 }
192
193 /*
194 * Return all the pipes using a transcoder in @transcoder_mask.
195 * For joiner configs return only the joiner primary.
196 */
get_transcoder_pipes(struct drm_i915_private * i915,u8 transcoder_mask)197 static u8 get_transcoder_pipes(struct drm_i915_private *i915,
198 u8 transcoder_mask)
199 {
200 struct intel_crtc *temp_crtc;
201 u8 pipes = 0;
202
203 for_each_intel_crtc(&i915->drm, temp_crtc) {
204 struct intel_crtc_state *temp_crtc_state =
205 to_intel_crtc_state(temp_crtc->base.state);
206
207 if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER)
208 continue;
209
210 if (intel_crtc_is_joiner_secondary(temp_crtc_state))
211 continue;
212
213 if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
214 pipes |= BIT(temp_crtc->pipe);
215 }
216
217 return pipes;
218 }
219
220 /*
221 * Return the port sync master and slave pipes linked to @crtc.
222 * For joiner configs return only the joiner primary pipes.
223 */
get_portsync_pipes(struct intel_crtc * crtc,u8 * master_pipe_mask,u8 * slave_pipes_mask)224 static void get_portsync_pipes(struct intel_crtc *crtc,
225 u8 *master_pipe_mask, u8 *slave_pipes_mask)
226 {
227 struct intel_display *display = to_intel_display(crtc);
228 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
229 struct intel_crtc_state *crtc_state =
230 to_intel_crtc_state(crtc->base.state);
231 struct intel_crtc *master_crtc;
232 struct intel_crtc_state *master_crtc_state;
233 enum transcoder master_transcoder;
234
235 if (!is_trans_port_sync_mode(crtc_state)) {
236 *master_pipe_mask = BIT(crtc->pipe);
237 *slave_pipes_mask = 0;
238
239 return;
240 }
241
242 if (is_trans_port_sync_master(crtc_state))
243 master_transcoder = crtc_state->cpu_transcoder;
244 else
245 master_transcoder = crtc_state->master_transcoder;
246
247 *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder));
248 drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask));
249
250 master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1);
251 master_crtc_state = to_intel_crtc_state(master_crtc->base.state);
252 *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask);
253 }
254
get_joiner_secondary_pipes(struct drm_i915_private * i915,u8 primary_pipes_mask)255 static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_pipes_mask)
256 {
257 struct intel_crtc *primary_crtc;
258 u8 pipes = 0;
259
260 for_each_intel_crtc_in_pipe_mask(&i915->drm, primary_crtc, primary_pipes_mask) {
261 struct intel_crtc_state *primary_crtc_state =
262 to_intel_crtc_state(primary_crtc->base.state);
263
264 pipes |= intel_crtc_joiner_secondary_pipes(primary_crtc_state);
265 }
266
267 return pipes;
268 }
269
intel_crtc_disable_noatomic(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)270 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
271 struct drm_modeset_acquire_ctx *ctx)
272 {
273 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
274 u8 portsync_master_mask;
275 u8 portsync_slaves_mask;
276 u8 joiner_secondaries_mask;
277 struct intel_crtc *temp_crtc;
278
279 /* TODO: Add support for MST */
280 get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask);
281 joiner_secondaries_mask = get_joiner_secondary_pipes(i915,
282 portsync_master_mask |
283 portsync_slaves_mask);
284
285 drm_WARN_ON(&i915->drm,
286 portsync_master_mask & portsync_slaves_mask ||
287 portsync_master_mask & joiner_secondaries_mask ||
288 portsync_slaves_mask & joiner_secondaries_mask);
289
290 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_secondaries_mask)
291 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
292
293 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask)
294 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
295
296 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask)
297 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
298
299 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
300 joiner_secondaries_mask |
301 portsync_slaves_mask |
302 portsync_master_mask)
303 intel_crtc_disable_noatomic_complete(temp_crtc);
304 }
305
intel_modeset_update_connector_atomic_state(struct drm_i915_private * i915)306 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
307 {
308 struct intel_connector *connector;
309 struct drm_connector_list_iter conn_iter;
310
311 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
312 for_each_intel_connector_iter(connector, &conn_iter) {
313 struct drm_connector_state *conn_state = connector->base.state;
314 struct intel_encoder *encoder =
315 to_intel_encoder(connector->base.encoder);
316
317 set_encoder_for_connector(connector, encoder);
318
319 if (encoder) {
320 struct intel_crtc *crtc =
321 to_intel_crtc(encoder->base.crtc);
322 const struct intel_crtc_state *crtc_state =
323 to_intel_crtc_state(crtc->base.state);
324
325 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
326 }
327 }
328 drm_connector_list_iter_end(&conn_iter);
329 }
330
intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state * crtc_state)331 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
332 {
333 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
334
335 if (intel_crtc_is_joiner_secondary(crtc_state))
336 return;
337
338 crtc_state->uapi.enable = crtc_state->hw.enable;
339 crtc_state->uapi.active = crtc_state->hw.active;
340 drm_WARN_ON(crtc_state->uapi.crtc->dev,
341 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
342
343 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
344 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
345
346 if (DISPLAY_INFO(i915)->color.degamma_lut_size) {
347 /* assume 1:1 mapping */
348 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
349 crtc_state->pre_csc_lut);
350 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
351 crtc_state->post_csc_lut);
352 } else {
353 /*
354 * ilk/snb hw may be configured for either pre_csc_lut
355 * or post_csc_lut, but we don't advertise degamma_lut as
356 * being available in the uapi since there is only one
357 * hardware LUT. Always assign the result of the readout
358 * to gamma_lut as that is the only valid source of LUTs
359 * in the uapi.
360 */
361 drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut &&
362 crtc_state->pre_csc_lut);
363
364 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
365 NULL);
366 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
367 crtc_state->post_csc_lut ?:
368 crtc_state->pre_csc_lut);
369 }
370
371 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
372 crtc_state->hw.degamma_lut);
373 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
374 crtc_state->hw.gamma_lut);
375 drm_property_replace_blob(&crtc_state->uapi.ctm,
376 crtc_state->hw.ctm);
377 }
378
379 static void
intel_sanitize_plane_mapping(struct drm_i915_private * i915)380 intel_sanitize_plane_mapping(struct drm_i915_private *i915)
381 {
382 struct intel_display *display = &i915->display;
383 struct intel_crtc *crtc;
384
385 if (DISPLAY_VER(i915) >= 4)
386 return;
387
388 for_each_intel_crtc(&i915->drm, crtc) {
389 struct intel_plane *plane =
390 to_intel_plane(crtc->base.primary);
391 struct intel_crtc *plane_crtc;
392 enum pipe pipe;
393
394 if (!plane->get_hw_state(plane, &pipe))
395 continue;
396
397 if (pipe == crtc->pipe)
398 continue;
399
400 drm_dbg_kms(&i915->drm,
401 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
402 plane->base.base.id, plane->base.name);
403
404 plane_crtc = intel_crtc_for_pipe(display, pipe);
405 intel_plane_disable_noatomic(plane_crtc, plane);
406 }
407 }
408
intel_crtc_has_encoders(struct intel_crtc * crtc)409 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
410 {
411 struct drm_device *dev = crtc->base.dev;
412 struct intel_encoder *encoder;
413
414 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
415 return true;
416
417 return false;
418 }
419
intel_crtc_needs_link_reset(struct intel_crtc * crtc)420 static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc)
421 {
422 struct drm_device *dev = crtc->base.dev;
423 struct intel_encoder *encoder;
424
425 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
426 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
427
428 if (dig_port && intel_tc_port_link_needs_reset(dig_port))
429 return true;
430 }
431
432 return false;
433 }
434
intel_encoder_find_connector(struct intel_encoder * encoder)435 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
436 {
437 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
438 struct drm_connector_list_iter conn_iter;
439 struct intel_connector *connector;
440 struct intel_connector *found_connector = NULL;
441
442 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
443 for_each_intel_connector_iter(connector, &conn_iter) {
444 if (&encoder->base == connector->base.encoder) {
445 found_connector = connector;
446 break;
447 }
448 }
449 drm_connector_list_iter_end(&conn_iter);
450
451 return found_connector;
452 }
453
intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state * crtc_state)454 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
455 {
456 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
457 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
458
459 /*
460 * We start out with underrun reporting disabled on active
461 * pipes to avoid races.
462 *
463 * Also on gmch platforms we dont have any hardware bits to
464 * disable the underrun reporting. Which means we need to start
465 * out with underrun reporting disabled also on inactive pipes,
466 * since otherwise we'll complain about the garbage we read when
467 * e.g. coming up after runtime pm.
468 *
469 * No protection against concurrent access is required - at
470 * worst a fifo underrun happens which also sets this to false.
471 */
472 intel_init_fifo_underrun_reporting(i915, crtc,
473 !crtc_state->hw.active &&
474 !HAS_GMCH(i915));
475 }
476
intel_sanitize_crtc(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)477 static bool intel_sanitize_crtc(struct intel_crtc *crtc,
478 struct drm_modeset_acquire_ctx *ctx)
479 {
480 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
481 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
482 bool needs_link_reset;
483
484 if (crtc_state->hw.active) {
485 struct intel_plane *plane;
486
487 /* Disable everything but the primary plane */
488 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
489 const struct intel_plane_state *plane_state =
490 to_intel_plane_state(plane->base.state);
491
492 if (plane_state->uapi.visible &&
493 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
494 intel_plane_disable_noatomic(crtc, plane);
495 }
496
497 /* Disable any background color/etc. set by the BIOS */
498 intel_color_commit_noarm(NULL, crtc_state);
499 intel_color_commit_arm(NULL, crtc_state);
500 }
501
502 if (!crtc_state->hw.active ||
503 intel_crtc_is_joiner_secondary(crtc_state))
504 return false;
505
506 needs_link_reset = intel_crtc_needs_link_reset(crtc);
507
508 /*
509 * Adjust the state of the output pipe according to whether we have
510 * active connectors/encoders.
511 */
512 if (!needs_link_reset && intel_crtc_has_encoders(crtc))
513 return false;
514
515 intel_crtc_disable_noatomic(crtc, ctx);
516
517 /*
518 * The HPD state on other active/disconnected TC ports may be stuck in
519 * the connected state until this port is disabled and a ~10ms delay has
520 * passed, wait here for that so that sanitizing other CRTCs will see the
521 * up-to-date HPD state.
522 */
523 if (needs_link_reset)
524 msleep(20);
525
526 return true;
527 }
528
intel_sanitize_all_crtcs(struct drm_i915_private * i915,struct drm_modeset_acquire_ctx * ctx)529 static void intel_sanitize_all_crtcs(struct drm_i915_private *i915,
530 struct drm_modeset_acquire_ctx *ctx)
531 {
532 struct intel_crtc *crtc;
533 u32 crtcs_forced_off = 0;
534
535 /*
536 * An active and disconnected TypeC port prevents the HPD live state
537 * to get updated on other active/disconnected TypeC ports, so after
538 * a port gets disabled the CRTCs using other TypeC ports must be
539 * rechecked wrt. their link status.
540 */
541 for (;;) {
542 u32 old_mask = crtcs_forced_off;
543
544 for_each_intel_crtc(&i915->drm, crtc) {
545 u32 crtc_mask = drm_crtc_mask(&crtc->base);
546
547 if (crtcs_forced_off & crtc_mask)
548 continue;
549
550 if (intel_sanitize_crtc(crtc, ctx))
551 crtcs_forced_off |= crtc_mask;
552 }
553 if (crtcs_forced_off == old_mask)
554 break;
555 }
556
557 for_each_intel_crtc(&i915->drm, crtc) {
558 struct intel_crtc_state *crtc_state =
559 to_intel_crtc_state(crtc->base.state);
560
561 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
562 }
563 }
564
has_bogus_dpll_config(const struct intel_crtc_state * crtc_state)565 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
566 {
567 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
568
569 /*
570 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
571 * the hardware when a high res displays plugged in. DPLL P
572 * divider is zero, and the pipe timings are bonkers. We'll
573 * try to disable everything in that case.
574 *
575 * FIXME would be nice to be able to sanitize this state
576 * without several WARNs, but for now let's take the easy
577 * road.
578 */
579 return IS_SANDYBRIDGE(i915) &&
580 crtc_state->hw.active &&
581 crtc_state->shared_dpll &&
582 crtc_state->port_clock == 0;
583 }
584
intel_sanitize_encoder(struct intel_encoder * encoder)585 static void intel_sanitize_encoder(struct intel_encoder *encoder)
586 {
587 struct intel_display *display = to_intel_display(encoder);
588 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
589 struct intel_connector *connector;
590 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
591 struct intel_crtc_state *crtc_state = crtc ?
592 to_intel_crtc_state(crtc->base.state) : NULL;
593 struct intel_pmdemand_state *pmdemand_state =
594 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
595
596 /*
597 * We need to check both for a crtc link (meaning that the encoder is
598 * active and trying to read from a pipe) and the pipe itself being
599 * active.
600 */
601 bool has_active_crtc = crtc_state &&
602 crtc_state->hw.active;
603
604 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
605 drm_dbg_kms(&i915->drm,
606 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
607 pipe_name(crtc->pipe));
608 has_active_crtc = false;
609 }
610
611 connector = intel_encoder_find_connector(encoder);
612 if (connector && !has_active_crtc) {
613 drm_dbg_kms(&i915->drm,
614 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
615 encoder->base.base.id,
616 encoder->base.name);
617
618 /* Clear the corresponding bit in pmdemand active phys mask */
619 intel_pmdemand_update_phys_mask(display, encoder,
620 pmdemand_state, false);
621
622 /*
623 * Connector is active, but has no active pipe. This is fallout
624 * from our resume register restoring. Disable the encoder
625 * manually again.
626 */
627 if (crtc_state) {
628 struct drm_encoder *best_encoder;
629
630 drm_dbg_kms(&i915->drm,
631 "[ENCODER:%d:%s] manually disabled\n",
632 encoder->base.base.id,
633 encoder->base.name);
634
635 /* avoid oopsing in case the hooks consult best_encoder */
636 best_encoder = connector->base.state->best_encoder;
637 connector->base.state->best_encoder = &encoder->base;
638
639 /* FIXME NULL atomic state passed! */
640 if (encoder->disable)
641 encoder->disable(NULL, encoder, crtc_state,
642 connector->base.state);
643 if (encoder->post_disable)
644 encoder->post_disable(NULL, encoder, crtc_state,
645 connector->base.state);
646
647 connector->base.state->best_encoder = best_encoder;
648 }
649 encoder->base.crtc = NULL;
650
651 /*
652 * Inconsistent output/port/pipe state happens presumably due to
653 * a bug in one of the get_hw_state functions. Or someplace else
654 * in our code, like the register restore mess on resume. Clamp
655 * things to off as a safer default.
656 */
657 connector->base.dpms = DRM_MODE_DPMS_OFF;
658 connector->base.encoder = NULL;
659 }
660
661 /* notify opregion of the sanitized encoder state */
662 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
663
664 if (HAS_DDI(i915))
665 intel_ddi_sanitize_encoder_pll_mapping(encoder);
666 }
667
668 /* FIXME read out full plane state for all planes */
readout_plane_state(struct drm_i915_private * i915)669 static void readout_plane_state(struct drm_i915_private *i915)
670 {
671 struct intel_display *display = &i915->display;
672 struct intel_plane *plane;
673 struct intel_crtc *crtc;
674
675 for_each_intel_plane(&i915->drm, plane) {
676 struct intel_plane_state *plane_state =
677 to_intel_plane_state(plane->base.state);
678 struct intel_crtc_state *crtc_state;
679 enum pipe pipe = PIPE_A;
680 bool visible;
681
682 visible = plane->get_hw_state(plane, &pipe);
683
684 crtc = intel_crtc_for_pipe(display, pipe);
685 crtc_state = to_intel_crtc_state(crtc->base.state);
686
687 intel_set_plane_visible(crtc_state, plane_state, visible);
688
689 drm_dbg_kms(&i915->drm,
690 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
691 plane->base.base.id, plane->base.name,
692 str_enabled_disabled(visible), pipe_name(pipe));
693 }
694
695 for_each_intel_crtc(&i915->drm, crtc) {
696 struct intel_crtc_state *crtc_state =
697 to_intel_crtc_state(crtc->base.state);
698
699 intel_plane_fixup_bitmasks(crtc_state);
700 }
701 }
702
intel_modeset_readout_hw_state(struct drm_i915_private * i915)703 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
704 {
705 struct intel_display *display = &i915->display;
706 struct intel_cdclk_state *cdclk_state =
707 to_intel_cdclk_state(i915->display.cdclk.obj.state);
708 struct intel_dbuf_state *dbuf_state =
709 to_intel_dbuf_state(i915->display.dbuf.obj.state);
710 struct intel_pmdemand_state *pmdemand_state =
711 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
712 enum pipe pipe;
713 struct intel_crtc *crtc;
714 struct intel_encoder *encoder;
715 struct intel_connector *connector;
716 struct drm_connector_list_iter conn_iter;
717 u8 active_pipes = 0;
718
719 for_each_intel_crtc(&i915->drm, crtc) {
720 struct intel_crtc_state *crtc_state =
721 to_intel_crtc_state(crtc->base.state);
722
723 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
724 intel_crtc_free_hw_state(crtc_state);
725 intel_crtc_state_reset(crtc_state, crtc);
726
727 intel_crtc_get_pipe_config(crtc_state);
728
729 crtc_state->hw.enable = crtc_state->hw.active;
730
731 crtc->base.enabled = crtc_state->hw.enable;
732 crtc->active = crtc_state->hw.active;
733
734 if (crtc_state->hw.active)
735 active_pipes |= BIT(crtc->pipe);
736
737 drm_dbg_kms(&i915->drm,
738 "[CRTC:%d:%s] hw state readout: %s\n",
739 crtc->base.base.id, crtc->base.name,
740 str_enabled_disabled(crtc_state->hw.active));
741 }
742
743 cdclk_state->active_pipes = active_pipes;
744 dbuf_state->active_pipes = active_pipes;
745
746 readout_plane_state(i915);
747
748 for_each_intel_encoder(&i915->drm, encoder) {
749 struct intel_crtc_state *crtc_state = NULL;
750
751 pipe = 0;
752
753 if (encoder->get_hw_state(encoder, &pipe)) {
754 crtc = intel_crtc_for_pipe(display, pipe);
755 crtc_state = to_intel_crtc_state(crtc->base.state);
756
757 encoder->base.crtc = &crtc->base;
758 intel_encoder_get_config(encoder, crtc_state);
759
760 /* read out to secondary crtc as well for joiner */
761 if (crtc_state->joiner_pipes) {
762 struct intel_crtc *secondary_crtc;
763
764 /* encoder should read be linked to joiner primary */
765 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
766
767 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
768 intel_crtc_joiner_secondary_pipes(crtc_state)) {
769 struct intel_crtc_state *secondary_crtc_state;
770
771 secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state);
772 intel_encoder_get_config(encoder, secondary_crtc_state);
773 }
774 }
775
776 intel_pmdemand_update_phys_mask(display, encoder,
777 pmdemand_state,
778 true);
779 } else {
780 intel_pmdemand_update_phys_mask(display, encoder,
781 pmdemand_state,
782 false);
783
784 encoder->base.crtc = NULL;
785 }
786
787 if (encoder->sync_state)
788 encoder->sync_state(encoder, crtc_state);
789
790 drm_dbg_kms(&i915->drm,
791 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
792 encoder->base.base.id, encoder->base.name,
793 str_enabled_disabled(encoder->base.crtc),
794 pipe_name(pipe));
795 }
796
797 intel_dpll_readout_hw_state(i915);
798
799 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
800 for_each_intel_connector_iter(connector, &conn_iter) {
801 struct intel_crtc_state *crtc_state = NULL;
802
803 if (connector->get_hw_state(connector)) {
804 struct intel_crtc *crtc;
805
806 connector->base.dpms = DRM_MODE_DPMS_ON;
807
808 encoder = intel_attached_encoder(connector);
809 connector->base.encoder = &encoder->base;
810
811 crtc = to_intel_crtc(encoder->base.crtc);
812 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
813
814 if (crtc_state && crtc_state->hw.active) {
815 /*
816 * This has to be done during hardware readout
817 * because anything calling .crtc_disable may
818 * rely on the connector_mask being accurate.
819 */
820 crtc_state->uapi.connector_mask |=
821 drm_connector_mask(&connector->base);
822 crtc_state->uapi.encoder_mask |=
823 drm_encoder_mask(&encoder->base);
824 }
825 } else {
826 connector->base.dpms = DRM_MODE_DPMS_OFF;
827 connector->base.encoder = NULL;
828 }
829
830 if (connector->sync_state)
831 connector->sync_state(connector, crtc_state);
832
833 drm_dbg_kms(&i915->drm,
834 "[CONNECTOR:%d:%s] hw state readout: %s\n",
835 connector->base.base.id, connector->base.name,
836 str_enabled_disabled(connector->base.encoder));
837 }
838 drm_connector_list_iter_end(&conn_iter);
839
840 for_each_intel_crtc(&i915->drm, crtc) {
841 struct intel_bw_state *bw_state =
842 to_intel_bw_state(i915->display.bw.obj.state);
843 struct intel_crtc_state *crtc_state =
844 to_intel_crtc_state(crtc->base.state);
845 struct intel_plane *plane;
846 int min_cdclk = 0;
847
848 if (crtc_state->hw.active) {
849 /*
850 * The initial mode needs to be set in order to keep
851 * the atomic core happy. It wants a valid mode if the
852 * crtc's enabled, so we do the above call.
853 *
854 * But we don't set all the derived state fully, hence
855 * set a flag to indicate that a full recalculation is
856 * needed on the next commit.
857 */
858 crtc_state->inherited = true;
859
860 intel_crtc_update_active_timings(crtc_state,
861 crtc_state->vrr.enable);
862
863 intel_crtc_copy_hw_to_uapi_state(crtc_state);
864 }
865
866 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
867 const struct intel_plane_state *plane_state =
868 to_intel_plane_state(plane->base.state);
869
870 /*
871 * FIXME don't have the fb yet, so can't
872 * use intel_plane_data_rate() :(
873 */
874 if (plane_state->uapi.visible)
875 crtc_state->data_rate[plane->id] =
876 4 * crtc_state->pixel_rate;
877 /*
878 * FIXME don't have the fb yet, so can't
879 * use plane->min_cdclk() :(
880 */
881 if (plane_state->uapi.visible && plane->min_cdclk) {
882 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
883 crtc_state->min_cdclk[plane->id] =
884 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
885 else
886 crtc_state->min_cdclk[plane->id] =
887 crtc_state->pixel_rate;
888 }
889 drm_dbg_kms(&i915->drm,
890 "[PLANE:%d:%s] min_cdclk %d kHz\n",
891 plane->base.base.id, plane->base.name,
892 crtc_state->min_cdclk[plane->id]);
893 }
894
895 if (crtc_state->hw.active) {
896 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
897 if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
898 min_cdclk = 0;
899 }
900
901 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
902 cdclk_state->min_voltage_level[crtc->pipe] =
903 crtc_state->min_voltage_level;
904
905 intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
906 crtc_state->port_clock);
907
908 intel_bw_crtc_update(bw_state, crtc_state);
909 }
910
911 intel_pmdemand_init_pmdemand_params(display, pmdemand_state);
912 }
913
914 static void
get_encoder_power_domains(struct drm_i915_private * i915)915 get_encoder_power_domains(struct drm_i915_private *i915)
916 {
917 struct intel_encoder *encoder;
918
919 for_each_intel_encoder(&i915->drm, encoder) {
920 struct intel_crtc_state *crtc_state;
921
922 if (!encoder->get_power_domains)
923 continue;
924
925 /*
926 * MST-primary and inactive encoders don't have a crtc state
927 * and neither of these require any power domain references.
928 */
929 if (!encoder->base.crtc)
930 continue;
931
932 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
933 encoder->get_power_domains(encoder, crtc_state);
934 }
935 }
936
intel_early_display_was(struct drm_i915_private * i915)937 static void intel_early_display_was(struct drm_i915_private *i915)
938 {
939 /*
940 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
941 * Also known as Wa_14010480278.
942 */
943 if (IS_DISPLAY_VER(i915, 10, 12))
944 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
945
946 /*
947 * WaRsPkgCStateDisplayPMReq:hsw
948 * System hang if this isn't done before disabling all planes!
949 */
950 if (IS_HASWELL(i915))
951 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
952
953 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
954 /* Display WA #1142:kbl,cfl,cml */
955 intel_de_rmw(i915, CHICKEN_PAR1_1,
956 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
957 intel_de_rmw(i915, CHICKEN_MISC_2,
958 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
959 KBL_ARB_FILL_SPARE_14);
960 }
961 }
962
intel_modeset_setup_hw_state(struct drm_i915_private * i915,struct drm_modeset_acquire_ctx * ctx)963 void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
964 struct drm_modeset_acquire_ctx *ctx)
965 {
966 struct intel_display *display = &i915->display;
967 struct intel_encoder *encoder;
968 struct intel_crtc *crtc;
969 intel_wakeref_t wakeref;
970
971 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
972
973 intel_early_display_was(i915);
974 intel_modeset_readout_hw_state(i915);
975
976 /* HW state is read out, now we need to sanitize this mess. */
977 get_encoder_power_domains(i915);
978
979 intel_pch_sanitize(i915);
980
981 /*
982 * intel_sanitize_plane_mapping() may need to do vblank
983 * waits, so we need vblank interrupts restored beforehand.
984 */
985 for_each_intel_crtc(&i915->drm, crtc) {
986 struct intel_crtc_state *crtc_state =
987 to_intel_crtc_state(crtc->base.state);
988
989 intel_sanitize_fifo_underrun_reporting(crtc_state);
990
991 drm_crtc_vblank_reset(&crtc->base);
992
993 if (crtc_state->hw.active) {
994 intel_dmc_enable_pipe(display, crtc->pipe);
995 intel_crtc_vblank_on(crtc_state);
996 }
997 }
998
999 intel_fbc_sanitize(&i915->display);
1000
1001 intel_sanitize_plane_mapping(i915);
1002
1003 for_each_intel_encoder(&i915->drm, encoder)
1004 intel_sanitize_encoder(encoder);
1005
1006 /*
1007 * Sanitizing CRTCs needs their connector atomic state to be
1008 * up-to-date, so ensure that already here.
1009 */
1010 intel_modeset_update_connector_atomic_state(i915);
1011
1012 intel_sanitize_all_crtcs(i915, ctx);
1013
1014 intel_dpll_sanitize_state(i915);
1015
1016 intel_wm_get_hw_state(i915);
1017
1018 for_each_intel_crtc(&i915->drm, crtc) {
1019 struct intel_crtc_state *crtc_state =
1020 to_intel_crtc_state(crtc->base.state);
1021 struct intel_power_domain_mask put_domains;
1022
1023 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
1024 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
1025 intel_modeset_put_crtc_power_domains(crtc, &put_domains);
1026 }
1027
1028 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
1029
1030 intel_power_domains_sanitize_state(display);
1031 }
1032