1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Components shared between ASoC and HDA CS35L56 drivers
4 //
5 // Copyright (C) 2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <kunit/static_stub.h>
9 #include <linux/array_size.h>
10 #include <linux/bitfield.h>
11 #include <linux/cleanup.h>
12 #include <linux/debugfs.h>
13 #include <linux/firmware/cirrus/wmfw.h>
14 #include <linux/fs.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/kstrtox.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21 #include <linux/stddef.h>
22 #include <linux/string.h>
23 #include <linux/string_choices.h>
24 #include <linux/types.h>
25 #include <sound/cs-amp-lib.h>
26
27 #include "cs35l56.h"
28
29 static const struct reg_sequence cs35l56_asp_patch[] = {
30 /*
31 * Firmware can change these to non-defaults to satisfy SDCA.
32 * Ensure that they are at known defaults.
33 */
34 { CS35L56_ASP1_ENABLES1, 0x00000000 },
35 { CS35L56_ASP1_CONTROL1, 0x00000028 },
36 { CS35L56_ASP1_CONTROL2, 0x18180200 },
37 { CS35L56_ASP1_CONTROL3, 0x00000002 },
38 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
39 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
40 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
41 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
42 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
43 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
44 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
45 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
46 };
47
cs35l56_set_asp_patch(struct cs35l56_base * cs35l56_base)48 int cs35l56_set_asp_patch(struct cs35l56_base *cs35l56_base)
49 {
50 return regmap_register_patch(cs35l56_base->regmap, cs35l56_asp_patch,
51 ARRAY_SIZE(cs35l56_asp_patch));
52 }
53 EXPORT_SYMBOL_NS_GPL(cs35l56_set_asp_patch, "SND_SOC_CS35L56_SHARED");
54
55 static const struct reg_sequence cs35l56_patch[] = {
56 /*
57 * Firmware can change these to non-defaults to satisfy SDCA.
58 * Ensure that they are at known defaults.
59 */
60 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
61 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
62 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
63 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
64 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
65 };
66
67 static const struct reg_sequence cs35l56_patch_fw[] = {
68 /* These are not reset by a soft-reset, so patch to defaults. */
69 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
70 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
71 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
72 };
73
74 static const struct reg_sequence cs35l63_patch_fw[] = {
75 /* These are not reset by a soft-reset, so patch to defaults. */
76 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 },
77 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 },
78 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 },
79 };
80
cs35l56_set_patch(struct cs35l56_base * cs35l56_base)81 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
82 {
83 int ret;
84
85 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
86 ARRAY_SIZE(cs35l56_patch));
87 if (ret)
88 return ret;
89
90
91 switch (cs35l56_base->type) {
92 case 0x54:
93 case 0x56:
94 case 0x57:
95 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw,
96 ARRAY_SIZE(cs35l56_patch_fw));
97 break;
98 case 0x63:
99 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw,
100 ARRAY_SIZE(cs35l63_patch_fw));
101 break;
102 default:
103 break;
104 }
105
106 return ret;
107 }
108 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED");
109
110 static const struct reg_default cs35l56_reg_defaults[] = {
111 { CS35L56_ASP1_ENABLES1, 0x00000000 },
112 { CS35L56_ASP1_CONTROL1, 0x00000028 },
113 { CS35L56_ASP1_CONTROL2, 0x18180200 },
114 { CS35L56_ASP1_CONTROL3, 0x00000002 },
115 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
116 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
117 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
118 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
119 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
120 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
121 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
122 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
123 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
124 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
125 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
126 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
127 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
128 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
129 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
130 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
131 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
132 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
133 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
134 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
135 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
136 };
137
138 static const struct reg_default cs35l63_reg_defaults[] = {
139 { CS35L56_ASP1_ENABLES1, 0x00000000 },
140 { CS35L56_ASP1_CONTROL1, 0x00000028 },
141 { CS35L56_ASP1_CONTROL2, 0x18180200 },
142 { CS35L56_ASP1_CONTROL3, 0x00000002 },
143 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
144 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
145 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
146 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
147 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
148 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
149 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
150 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
151 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
152 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
153 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
154 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
155 { CS35L56_IRQ1_MASK_1, 0x8003ffff },
156 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
157 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
158 { CS35L56_IRQ1_MASK_8, 0x8c000fff },
159 { CS35L56_IRQ1_MASK_18, 0x0760f000 },
160 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
161 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 },
162 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 },
163 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 },
164 };
165
cs35l56_is_dsp_memory(unsigned int reg)166 static bool cs35l56_is_dsp_memory(unsigned int reg)
167 {
168 switch (reg) {
169 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
170 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
171 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
172 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
173 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
174 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
175 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
176 return true;
177 default:
178 return false;
179 }
180 }
181
cs35l56_readable_reg(struct device * dev,unsigned int reg)182 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
183 {
184 switch (reg) {
185 case CS35L56_DEVID:
186 case CS35L56_REVID:
187 case CS35L56_RELID:
188 case CS35L56_OTPID:
189 case CS35L56_SFT_RESET:
190 case CS35L56_GLOBAL_ENABLES:
191 case CS35L56_BLOCK_ENABLES:
192 case CS35L56_BLOCK_ENABLES2:
193 case CS35L56_REFCLK_INPUT:
194 case CS35L56_GLOBAL_SAMPLE_RATE:
195 case CS35L56_OTP_MEM_53:
196 case CS35L56_OTP_MEM_54:
197 case CS35L56_OTP_MEM_55:
198 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG:
199 case CS35L56_UPDATE_REGS:
200 case CS35L56_ASP1_ENABLES1:
201 case CS35L56_ASP1_CONTROL1:
202 case CS35L56_ASP1_CONTROL2:
203 case CS35L56_ASP1_CONTROL3:
204 case CS35L56_ASP1_FRAME_CONTROL1:
205 case CS35L56_ASP1_FRAME_CONTROL5:
206 case CS35L56_ASP1_DATA_CONTROL1:
207 case CS35L56_ASP1_DATA_CONTROL5:
208 case CS35L56_DACPCM1_INPUT:
209 case CS35L56_DACPCM2_INPUT:
210 case CS35L56_ASP1TX1_INPUT:
211 case CS35L56_ASP1TX2_INPUT:
212 case CS35L56_ASP1TX3_INPUT:
213 case CS35L56_ASP1TX4_INPUT:
214 case CS35L56_DSP1RX1_INPUT:
215 case CS35L56_DSP1RX2_INPUT:
216 case CS35L56_SWIRE_DP3_CH1_INPUT:
217 case CS35L56_SWIRE_DP3_CH2_INPUT:
218 case CS35L56_SWIRE_DP3_CH3_INPUT:
219 case CS35L56_SWIRE_DP3_CH4_INPUT:
220 case CS35L56_IRQ1_CFG:
221 case CS35L56_IRQ1_STATUS:
222 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
223 case CS35L56_IRQ1_EINT_18:
224 case CS35L56_IRQ1_EINT_20:
225 case CS35L56_IRQ1_MASK_1:
226 case CS35L56_IRQ1_MASK_2:
227 case CS35L56_IRQ1_MASK_4:
228 case CS35L56_IRQ1_MASK_8:
229 case CS35L56_IRQ1_MASK_18:
230 case CS35L56_IRQ1_MASK_20:
231 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1:
232 case CS35L56_MIXER_NGATE_CH1_CFG:
233 case CS35L56_MIXER_NGATE_CH2_CFG:
234 case CS35L56_DSP_VIRTUAL1_MBOX_1:
235 case CS35L56_DSP_VIRTUAL1_MBOX_2:
236 case CS35L56_DSP_VIRTUAL1_MBOX_3:
237 case CS35L56_DSP_VIRTUAL1_MBOX_4:
238 case CS35L56_DSP_VIRTUAL1_MBOX_5:
239 case CS35L56_DSP_VIRTUAL1_MBOX_6:
240 case CS35L56_DSP_VIRTUAL1_MBOX_7:
241 case CS35L56_DSP_VIRTUAL1_MBOX_8:
242 case CS35L56_DIE_STS1:
243 case CS35L56_DIE_STS2:
244 case CS35L56_DSP_RESTRICT_STS1:
245 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
246 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
247 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
248 case CS35L56_DSP1_SCRATCH1:
249 case CS35L56_DSP1_SCRATCH2:
250 case CS35L56_DSP1_SCRATCH3:
251 case CS35L56_DSP1_SCRATCH4:
252 return true;
253 default:
254 return cs35l56_is_dsp_memory(reg);
255 }
256 }
257
cs35l56_precious_reg(struct device * dev,unsigned int reg)258 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
259 {
260 switch (reg) {
261 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
262 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
263 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
264 return true;
265 default:
266 return false;
267 }
268 }
269
cs35l56_common_volatile_reg(unsigned int reg)270 static bool cs35l56_common_volatile_reg(unsigned int reg)
271 {
272 switch (reg) {
273 case CS35L56_DEVID:
274 case CS35L56_REVID:
275 case CS35L56_RELID:
276 case CS35L56_OTPID:
277 case CS35L56_SFT_RESET:
278 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
279 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
280 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
281 case CS35L56_OTP_MEM_53:
282 case CS35L56_OTP_MEM_54:
283 case CS35L56_OTP_MEM_55:
284 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG:
285 case CS35L56_UPDATE_REGS:
286 case CS35L56_REFCLK_INPUT: /* owned by firmware */
287 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
288 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
289 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
290 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
291 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
292 case CS35L56_IRQ1_STATUS:
293 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
294 case CS35L56_IRQ1_EINT_18:
295 case CS35L56_IRQ1_EINT_20:
296 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1:
297 case CS35L56_MIXER_NGATE_CH1_CFG:
298 case CS35L56_MIXER_NGATE_CH2_CFG:
299 case CS35L56_DSP_VIRTUAL1_MBOX_1:
300 case CS35L56_DSP_VIRTUAL1_MBOX_2:
301 case CS35L56_DSP_VIRTUAL1_MBOX_3:
302 case CS35L56_DSP_VIRTUAL1_MBOX_4:
303 case CS35L56_DSP_VIRTUAL1_MBOX_5:
304 case CS35L56_DSP_VIRTUAL1_MBOX_6:
305 case CS35L56_DSP_VIRTUAL1_MBOX_7:
306 case CS35L56_DSP_VIRTUAL1_MBOX_8:
307 case CS35L56_DSP_RESTRICT_STS1:
308 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
309 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
310 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
311 case CS35L56_DSP1_SCRATCH1:
312 case CS35L56_DSP1_SCRATCH2:
313 case CS35L56_DSP1_SCRATCH3:
314 case CS35L56_DSP1_SCRATCH4:
315 return true;
316 default:
317 return cs35l56_is_dsp_memory(reg);
318 }
319 }
320
cs35l56_volatile_reg(struct device * dev,unsigned int reg)321 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
322 {
323 switch (reg) {
324 case CS35L56_MAIN_RENDER_USER_MUTE:
325 case CS35L56_MAIN_RENDER_USER_VOLUME:
326 case CS35L56_MAIN_POSTURE_NUMBER:
327 return false;
328 default:
329 return cs35l56_common_volatile_reg(reg);
330 }
331 }
332
cs35l63_volatile_reg(struct device * dev,unsigned int reg)333 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg)
334 {
335 switch (reg) {
336 case CS35L63_MAIN_RENDER_USER_MUTE:
337 case CS35L63_MAIN_RENDER_USER_VOLUME:
338 case CS35L63_MAIN_POSTURE_NUMBER:
339 return false;
340 default:
341 return cs35l56_common_volatile_reg(reg);
342 }
343 }
344
345 static const struct cs35l56_fw_reg cs35l56_fw_reg = {
346 .fw_ver = CS35L56_DSP1_FW_VER,
347 .halo_state = CS35L56_DSP1_HALO_STATE,
348 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE,
349 .prot_sts = CS35L56_PROTECTION_STATUS,
350 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS,
351 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE,
352 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME,
353 .posture_number = CS35L56_MAIN_POSTURE_NUMBER,
354 };
355
356 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = {
357 .fw_ver = CS35L56_DSP1_FW_VER,
358 .halo_state = CS35L56_B2_DSP1_HALO_STATE,
359 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE,
360 .prot_sts = CS35L56_PROTECTION_STATUS,
361 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS,
362 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE,
363 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME,
364 .posture_number = CS35L56_MAIN_POSTURE_NUMBER,
365 };
366
367 static const struct cs35l56_fw_reg cs35l63_fw_reg = {
368 .fw_ver = CS35L63_DSP1_FW_VER,
369 .halo_state = CS35L63_DSP1_HALO_STATE,
370 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE,
371 .prot_sts = CS35L63_PROTECTION_STATUS,
372 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS,
373 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE,
374 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME,
375 .posture_number = CS35L63_MAIN_POSTURE_NUMBER,
376 };
377
cs35l56_set_fw_reg_table(struct cs35l56_base * cs35l56_base)378 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base)
379 {
380 switch (cs35l56_base->type) {
381 default:
382 switch (cs35l56_base->rev) {
383 case 0xb0:
384 cs35l56_base->fw_reg = &cs35l56_fw_reg;
385 break;
386 default:
387 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg;
388 break;
389 }
390 break;
391 case 0x63:
392 cs35l56_base->fw_reg = &cs35l63_fw_reg;
393 break;
394 }
395 }
396
cs35l56_mbox_send(struct cs35l56_base * cs35l56_base,unsigned int command)397 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
398 {
399 unsigned int val;
400 int ret;
401
402 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
403 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
404 val, (val == 0),
405 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
406 if (ret) {
407 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
408 return ret;
409 }
410
411 return 0;
412 }
413 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED");
414
cs35l56_firmware_shutdown(struct cs35l56_base * cs35l56_base)415 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
416 {
417 int ret;
418 unsigned int val;
419
420 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
421 if (ret)
422 return ret;
423
424 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
425 cs35l56_base->fw_reg->pm_cur_stat,
426 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
427 CS35L56_HALO_STATE_POLL_US,
428 CS35L56_HALO_STATE_TIMEOUT_US);
429 if (ret < 0)
430 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
431 val, ret);
432 return ret;
433 }
434 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED");
435
cs35l56_wait_for_firmware_boot(struct cs35l56_base * cs35l56_base)436 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
437 {
438 unsigned int val = 0;
439 int read_ret, poll_ret;
440
441 /*
442 * The regmap must remain in cache-only until the chip has
443 * booted, so use a bypassed read of the status register.
444 */
445 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret,
446 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
447 CS35L56_HALO_STATE_POLL_US,
448 CS35L56_HALO_STATE_TIMEOUT_US,
449 false,
450 cs35l56_base->regmap,
451 cs35l56_base->fw_reg->halo_state,
452 &val);
453
454 if (poll_ret) {
455 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
456 read_ret, val);
457 return -EIO;
458 }
459
460 return 0;
461 }
462 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED");
463
cs35l56_wait_control_port_ready(void)464 void cs35l56_wait_control_port_ready(void)
465 {
466 /* Wait for control port to be ready (datasheet tIRS). */
467 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
468 }
469 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED");
470
cs35l56_wait_min_reset_pulse(void)471 void cs35l56_wait_min_reset_pulse(void)
472 {
473 /* Satisfy minimum reset pulse width spec */
474 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
475 }
476 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED");
477
478 static const struct {
479 u32 addr;
480 u32 value;
481 } cs35l56_spi_system_reset_stages[] = {
482 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET },
483 /* The next write is necessary to delimit the soft reset */
484 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING },
485 };
486
cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base * cs35l56_base,struct spi_device * spi)487 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base,
488 struct spi_device *spi)
489 {
490 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf;
491 struct spi_transfer t = {
492 .tx_buf = buf,
493 .len = sizeof(*buf),
494 };
495 struct spi_message m;
496 int i, ret;
497
498 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) {
499 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr);
500 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value);
501 spi_message_init_with_transfers(&m, &t, 1);
502 ret = spi_sync_locked(spi, &m);
503 if (ret)
504 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret);
505
506 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US,
507 2 * CS35L56_SPI_RESET_TO_PORT_READY_US);
508 }
509 }
510
cs35l56_spi_system_reset(struct cs35l56_base * cs35l56_base)511 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base)
512 {
513 struct spi_device *spi = to_spi_device(cs35l56_base->dev);
514 unsigned int val;
515 int read_ret, ret;
516
517 /*
518 * There must not be any other SPI bus activity while the amp is
519 * soft-resetting.
520 */
521 ret = spi_bus_lock(spi->controller);
522 if (ret) {
523 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret);
524 return;
525 }
526
527 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi);
528 spi_bus_unlock(spi->controller);
529
530 /*
531 * Check firmware boot by testing for a response in MBOX_2.
532 * HALO_STATE cannot be trusted yet because the reset sequence
533 * can leave it with stale state. But MBOX is reset.
534 * The regmap must remain in cache-only until the chip has
535 * booted, so use a bypassed read.
536 */
537 ret = read_poll_timeout(regmap_read_bypassed, read_ret,
538 (val > 0) && (val < 0xffffffff),
539 CS35L56_HALO_STATE_POLL_US,
540 CS35L56_HALO_STATE_TIMEOUT_US,
541 false,
542 cs35l56_base->regmap,
543 CS35L56_DSP_VIRTUAL1_MBOX_2,
544 &val);
545 if (ret) {
546 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n",
547 read_ret, val);
548 }
549 }
550
551 static const struct reg_sequence cs35l56_system_reset_seq[] = {
552 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
553 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
554 };
555
556 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = {
557 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0),
558 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
559 };
560
561 static const struct reg_sequence cs35l63_system_reset_seq[] = {
562 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0),
563 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
564 };
565
cs35l56_system_reset(struct cs35l56_base * cs35l56_base,bool is_soundwire)566 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
567 {
568 /*
569 * Must enter cache-only first so there can't be any more register
570 * accesses other than the controlled system reset sequence below.
571 */
572 regcache_cache_only(cs35l56_base->regmap, true);
573
574 if (cs35l56_is_spi(cs35l56_base)) {
575 cs35l56_spi_system_reset(cs35l56_base);
576 return;
577 }
578
579 switch (cs35l56_base->type) {
580 case 0x54:
581 case 0x56:
582 case 0x57:
583 switch (cs35l56_base->rev) {
584 case 0xb0:
585 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
586 cs35l56_system_reset_seq,
587 ARRAY_SIZE(cs35l56_system_reset_seq));
588 break;
589 default:
590 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
591 cs35l56_b2_system_reset_seq,
592 ARRAY_SIZE(cs35l56_b2_system_reset_seq));
593 break;
594 }
595 break;
596 case 0x63:
597 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
598 cs35l63_system_reset_seq,
599 ARRAY_SIZE(cs35l63_system_reset_seq));
600 break;
601 default:
602 break;
603 }
604
605 /* On SoundWire the registers won't be accessible until it re-enumerates. */
606 if (is_soundwire)
607 return;
608
609 cs35l56_wait_control_port_ready();
610
611 /* Leave in cache-only. This will be revoked when the chip has rebooted. */
612 }
613 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED");
614
cs35l56_irq_request(struct cs35l56_base * cs35l56_base,int irq)615 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
616 {
617 int ret;
618
619 if (irq < 1)
620 return 0;
621
622 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
623 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
624 "cs35l56", cs35l56_base);
625 if (!ret)
626 cs35l56_base->irq = irq;
627 else
628 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
629
630 return ret;
631 }
632 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED");
633
cs35l56_irq(int irq,void * data)634 irqreturn_t cs35l56_irq(int irq, void *data)
635 {
636 struct cs35l56_base *cs35l56_base = data;
637 unsigned int status1 = 0, status8 = 0, status20 = 0;
638 unsigned int mask1, mask8, mask20;
639 unsigned int val;
640 int rv;
641
642 irqreturn_t ret = IRQ_NONE;
643
644 if (!cs35l56_base->init_done)
645 return IRQ_NONE;
646
647 mutex_lock(&cs35l56_base->irq_lock);
648
649 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
650 if (rv < 0) {
651 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
652 goto err_unlock;
653 }
654
655 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
656 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
657 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
658 goto err;
659 }
660
661 /* Ack interrupts */
662 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
663 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
664 status1 &= ~mask1;
665 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
666
667 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
668 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
669 status8 &= ~mask8;
670 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
671
672 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
673 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
674 status20 &= ~mask20;
675 /* We don't want EINT20 but they default to unmasked: force mask */
676 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
677
678 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
679
680 /* Check to see if unmasked bits are active */
681 if (!status1 && !status8 && !status20)
682 goto err;
683
684 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
685 dev_crit(cs35l56_base->dev, "Amp short error\n");
686
687 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
688 dev_crit(cs35l56_base->dev, "Overtemp error\n");
689
690 ret = IRQ_HANDLED;
691
692 err:
693 pm_runtime_put(cs35l56_base->dev);
694 err_unlock:
695 mutex_unlock(&cs35l56_base->irq_lock);
696
697 return ret;
698 }
699 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED");
700
cs35l56_is_fw_reload_needed(struct cs35l56_base * cs35l56_base)701 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
702 {
703 unsigned int val;
704 int ret;
705
706 /*
707 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
708 * can't be used here to test for memory retention.
709 * Assume that tuning must be re-loaded.
710 */
711 if (cs35l56_base->secured)
712 return true;
713
714 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
715 if (ret) {
716 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
717 return ret;
718 }
719
720 ret = regmap_read(cs35l56_base->regmap,
721 cs35l56_base->fw_reg->prot_sts,
722 &val);
723 if (ret)
724 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
725 else
726 ret = !!(val & CS35L56_FIRMWARE_MISSING);
727
728 pm_runtime_put_autosuspend(cs35l56_base->dev);
729
730 return ret;
731 }
732 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED");
733
734 static const struct reg_sequence cs35l56_hibernate_seq[] = {
735 /* This must be the last register access */
736 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
737 };
738
cs35l56_issue_wake_event(struct cs35l56_base * cs35l56_base)739 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
740 {
741 unsigned int val;
742
743 /*
744 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two
745 * transactions to meet the minimum required time from the rising edge
746 * to the last falling edge of wake.
747 *
748 * It uses bypassed read because we must wake the chip before
749 * disabling regmap cache-only.
750 */
751 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
752
753 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
754
755 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
756
757 cs35l56_wait_control_port_ready();
758 }
759
cs35l56_wait_for_ps3(struct cs35l56_base * cs35l56_base)760 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base)
761 {
762 unsigned int val;
763 int ret;
764
765 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
766 cs35l56_base->fw_reg->transducer_actual_ps,
767 val, (val >= CS35L56_PS3),
768 CS35L56_PS3_POLL_US,
769 CS35L56_PS3_TIMEOUT_US);
770 if (ret)
771 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
772
773 return ret;
774 }
775
cs35l56_runtime_suspend_common(struct cs35l56_base * cs35l56_base)776 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
777 {
778 if (!cs35l56_base->init_done)
779 return 0;
780
781 /* Firmware must have entered a power-save state */
782 cs35l56_wait_for_ps3(cs35l56_base);
783
784 /* Clear BOOT_DONE so it can be used to detect a reboot */
785 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
786
787 if (!cs35l56_base->can_hibernate) {
788 regcache_cache_only(cs35l56_base->regmap, true);
789 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
790
791 return 0;
792 }
793
794 /*
795 * Must enter cache-only first so there can't be any more register
796 * accesses other than the controlled hibernate sequence below.
797 */
798 regcache_cache_only(cs35l56_base->regmap, true);
799
800 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
801 cs35l56_hibernate_seq,
802 ARRAY_SIZE(cs35l56_hibernate_seq));
803
804 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
805
806 return 0;
807 }
808 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED");
809
cs35l56_runtime_resume_common(struct cs35l56_base * cs35l56_base,bool is_soundwire)810 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
811 {
812 unsigned int val;
813 int ret;
814
815 if (!cs35l56_base->init_done)
816 return 0;
817
818 if (!cs35l56_base->can_hibernate)
819 goto out_sync;
820
821 /* Must be done before releasing cache-only */
822 if (!is_soundwire)
823 cs35l56_issue_wake_event(cs35l56_base);
824
825 out_sync:
826 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
827 if (ret) {
828 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
829 goto err;
830 }
831
832 regcache_cache_only(cs35l56_base->regmap, false);
833
834 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
835 if (ret)
836 goto err;
837
838 /* BOOT_DONE will be 1 if the amp reset */
839 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
840 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
841 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
842 regcache_mark_dirty(cs35l56_base->regmap);
843 }
844
845 regcache_sync(cs35l56_base->regmap);
846
847 dev_dbg(cs35l56_base->dev, "Resumed");
848
849 return 0;
850
851 err:
852 regcache_cache_only(cs35l56_base->regmap, true);
853
854 if (cs35l56_base->can_hibernate) {
855 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
856 cs35l56_hibernate_seq,
857 ARRAY_SIZE(cs35l56_hibernate_seq));
858 }
859
860 return ret;
861 }
862 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED");
863
864 static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
865 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
866 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
867 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
868 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
869 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
870 };
871
cs35l56_init_cs_dsp(struct cs35l56_base * cs35l56_base,struct cs_dsp * cs_dsp)872 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
873 {
874 cs_dsp->num = 1;
875 cs_dsp->type = WMFW_HALO;
876 cs_dsp->rev = 0;
877 cs_dsp->dev = cs35l56_base->dev;
878 cs_dsp->regmap = cs35l56_base->regmap;
879 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
880 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
881 cs_dsp->mem = cs35l56_dsp1_regions;
882 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
883 cs_dsp->no_core_startstop = true;
884
885 cs35l56_base->dsp = cs_dsp;
886 }
887 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED");
888
889 struct cs35l56_pte {
890 u8 x;
891 u8 wafer_id;
892 u8 pte[2];
893 u8 lot[3];
894 u8 y;
895 u8 unused[3];
896 u8 dvs;
897 } __packed;
898 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0);
899
cs35l56_read_silicon_uid(struct cs35l56_base * cs35l56_base)900 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base)
901 {
902 struct cs35l56_pte pte;
903 u64 unique_id;
904 int ret;
905
906 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte));
907 if (ret) {
908 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret);
909 return ret;
910 }
911
912 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16);
913 unique_id <<= 32;
914 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) |
915 ((u32)pte.dvs << 24);
916
917 cs35l56_base->silicon_uid = unique_id;
918
919 return 0;
920 }
921
cs35l63_read_silicon_uid(struct cs35l56_base * cs35l56_base)922 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base)
923 {
924 u32 tmp[2];
925 u64 unique_id;
926 int ret;
927
928 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp));
929 if (ret) {
930 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret);
931 return ret;
932 }
933
934 unique_id = tmp[1];
935 unique_id <<= 32;
936 unique_id |= tmp[0];
937
938 cs35l56_base->silicon_uid = unique_id;
939
940 return 0;
941 }
942
943 /* Firmware calibration controls */
944 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = {
945 .alg_id = 0x9f210,
946 .mem_region = WMFW_ADSP2_YM,
947 .ambient = "CAL_AMBIENT",
948 .calr = "CAL_R",
949 .status = "CAL_STATUS",
950 .checksum = "CAL_CHECKSUM",
951 };
952 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED");
953
954 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = {
955 .alg_id = 0xbf210,
956 .mem_region = WMFW_ADSP2_YM,
957 .ambient = "CAL_AMBIENT",
958 .calr = "CAL_R",
959 .status = "CAL_STATUS",
960 .checksum = "CAL_CHECKSUM",
961 };
962
cs35l56_get_calibration(struct cs35l56_base * cs35l56_base)963 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base)
964 {
965 int ret;
966
967 /* Driver can't apply calibration to a secured part, so skip */
968 if (cs35l56_base->secured)
969 return 0;
970
971 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev,
972 cs35l56_base->silicon_uid,
973 cs35l56_base->cal_index,
974 &cs35l56_base->cal_data);
975
976 /* Only return an error status if probe should be aborted */
977 if ((ret == -ENOENT) || (ret == -EOVERFLOW))
978 return 0;
979
980 if (ret < 0)
981 return ret;
982
983 cs35l56_base->cal_data_valid = true;
984
985 return 0;
986 }
987 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED");
988
cs35l56_stash_calibration(struct cs35l56_base * cs35l56_base,const struct cirrus_amp_cal_data * data)989 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base,
990 const struct cirrus_amp_cal_data *data)
991 {
992
993 /* Ignore if it is empty */
994 if (!data->calTime[0] && !data->calTime[1])
995 return -ENODATA;
996
997 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) {
998 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n");
999 return -EINVAL;
1000 }
1001
1002 cs35l56_base->cal_data = *data;
1003 cs35l56_base->cal_data_valid = true;
1004
1005 return 0;
1006 }
1007 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED");
1008
cs35l56_perform_calibration(struct cs35l56_base * cs35l56_base)1009 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base)
1010 {
1011 const struct cirrus_amp_cal_controls *calibration_controls =
1012 cs35l56_base->calibration_controls;
1013 struct cs_dsp *dsp = cs35l56_base->dsp;
1014 struct cirrus_amp_cal_data cal_data;
1015 struct cs_dsp_coeff_ctl *ctl;
1016 bool ngate_ch1_was_enabled = false;
1017 bool ngate_ch2_was_enabled = false;
1018 int cali_norm_en_alg_id, cali_norm_en_mem;
1019 int ret;
1020 __be32 val;
1021
1022 if (cs35l56_base->silicon_uid == 0) {
1023 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n");
1024 return -ENXIO;
1025 }
1026
1027 switch (cs35l56_base->type) {
1028 case 0x54:
1029 case 0x56:
1030 case 0x57:
1031 if (cs35l56_base->rev < 0xb2) {
1032 cali_norm_en_alg_id = 0x9f22f;
1033 cali_norm_en_mem = WMFW_ADSP2_YM;
1034 } else {
1035 cali_norm_en_alg_id = 0x9f210;
1036 cali_norm_en_mem = WMFW_ADSP2_XM;
1037 }
1038 break;
1039 default:
1040 cali_norm_en_alg_id = 0xbf210;
1041 cali_norm_en_mem = WMFW_ADSP2_XM;
1042 break;
1043 }
1044
1045 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
1046 if (ret)
1047 return ret;
1048
1049 ret = cs35l56_wait_for_ps3(cs35l56_base);
1050 if (ret) {
1051 ret = -EBUSY;
1052 goto err_pm_put;
1053 }
1054
1055 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG,
1056 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled);
1057 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG,
1058 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled);
1059
1060 scoped_guard(mutex, &dsp->pwr_lock) {
1061 ctl = cs_dsp_get_ctl(dsp,
1062 calibration_controls->status,
1063 calibration_controls->mem_region,
1064 calibration_controls->alg_id);
1065 if (!ctl) {
1066 dev_err(cs35l56_base->dev, "Could not get %s control\n",
1067 calibration_controls->status);
1068 ret = -EIO;
1069 goto err;
1070 }
1071
1072 val = cpu_to_be32(0);
1073 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp,
1074 "CALI_NORM_EN",
1075 cali_norm_en_mem,
1076 cali_norm_en_alg_id),
1077 0, &val, sizeof(val));
1078 if (ret < 0) {
1079 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret);
1080 ret = -EIO;
1081 goto err;
1082 }
1083
1084 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION);
1085 if (ret) {
1086 ret = -EIO;
1087 goto err;
1088 }
1089
1090 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret,
1091 (val == cpu_to_be32(1)),
1092 CS35L56_CALIBRATION_POLL_US,
1093 CS35L56_CALIBRATION_TIMEOUT_US,
1094 true,
1095 ctl, 0, &val, sizeof(val))) {
1096 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n",
1097 be32_to_cpu(val));
1098 switch (be32_to_cpu(val)) {
1099 case CS35L56_CAL_STATUS_OUT_OF_RANGE:
1100 ret = -ERANGE;
1101 goto err;
1102 default:
1103 ret = -ETIMEDOUT;
1104 goto err;
1105 }
1106 }
1107 }
1108
1109 cs35l56_base->cal_data_valid = false;
1110 memset(&cal_data, 0, sizeof(cal_data));
1111 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data);
1112 if (ret) {
1113 ret = -EIO;
1114 goto err;
1115 }
1116
1117 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n",
1118 cal_data.calStatus, cal_data.calR, cal_data.calAmbient);
1119
1120 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid;
1121 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32);
1122 cs35l56_base->cal_data = cal_data;
1123 cs35l56_base->cal_data_valid = true;
1124
1125 ret = 0;
1126
1127 err:
1128 if (ngate_ch1_was_enabled) {
1129 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG,
1130 CS35L56_AUX_NGATE_CHn_EN);
1131 }
1132 if (ngate_ch2_was_enabled) {
1133 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG,
1134 CS35L56_AUX_NGATE_CHn_EN);
1135 }
1136 err_pm_put:
1137 pm_runtime_put(cs35l56_base->dev);
1138
1139 return ret;
1140 }
1141
cs35l56_calibrate_debugfs_write(struct cs35l56_base * cs35l56_base,const char __user * from,size_t count,loff_t * ppos)1142 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base,
1143 const char __user *from, size_t count,
1144 loff_t *ppos)
1145 {
1146 static const char * const options[] = { "factory", "store_uefi" };
1147 char buf[11] = { 0 };
1148 int num_amps, ret;
1149
1150 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON))
1151 return -ENXIO;
1152
1153 if (*ppos)
1154 return -EINVAL;
1155
1156 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count);
1157 if (ret < 0)
1158 return ret;
1159
1160 switch (sysfs_match_string(options, buf)) {
1161 case 0:
1162 ret = cs35l56_perform_calibration(cs35l56_base);
1163 if (ret < 0)
1164 return ret;
1165 break;
1166 case 1:
1167 if (!cs35l56_base->cal_data_valid)
1168 return -ENODATA;
1169
1170 num_amps = cs35l56_base->num_amps;
1171 if (num_amps == 0)
1172 num_amps = -1;
1173
1174 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev,
1175 cs35l56_base->cal_index,
1176 num_amps,
1177 &cs35l56_base->cal_data);
1178 if (ret < 0)
1179 return ret;
1180 break;
1181 default:
1182 return -EOPNOTSUPP;
1183 }
1184
1185 return count;
1186 }
1187 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED");
1188
cs35l56_factory_calibrate(struct cs35l56_base * cs35l56_base)1189 int cs35l56_factory_calibrate(struct cs35l56_base *cs35l56_base)
1190 {
1191 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_PERFORM_CTRL))
1192 return -ENXIO;
1193
1194 return cs35l56_perform_calibration(cs35l56_base);
1195 }
1196 EXPORT_SYMBOL_NS_GPL(cs35l56_factory_calibrate, "SND_SOC_CS35L56_SHARED");
1197
cs35l56_cal_ambient_debugfs_write(struct cs35l56_base * cs35l56_base,const char __user * from,size_t count,loff_t * ppos)1198 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base,
1199 const char __user *from, size_t count,
1200 loff_t *ppos)
1201 {
1202 unsigned long val;
1203 int ret;
1204
1205 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON))
1206 return -ENXIO;
1207
1208 if (*ppos)
1209 return -EINVAL;
1210
1211 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
1212 if (ret)
1213 return ret;
1214
1215 ret = kstrtoul_from_user(from, count, 10, &val);
1216 if (ret < 0)
1217 goto out;
1218
1219 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val);
1220 if (ret)
1221 ret = -EIO;
1222 out:
1223 pm_runtime_put(cs35l56_base->dev);
1224
1225 if (ret < 0)
1226 return ret;
1227
1228 return count;
1229 }
1230 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED");
1231
cs35l56_cal_data_debugfs_read(struct cs35l56_base * cs35l56_base,char __user * to,size_t count,loff_t * ppos)1232 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base,
1233 char __user *to, size_t count,
1234 loff_t *ppos)
1235 {
1236 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON))
1237 return -ENXIO;
1238
1239 if (!cs35l56_base->cal_data_valid)
1240 return 0;
1241
1242 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data,
1243 sizeof(cs35l56_base->cal_data));
1244 }
1245 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED");
1246
cs35l56_cal_data_debugfs_write(struct cs35l56_base * cs35l56_base,const char __user * from,size_t count,loff_t * ppos)1247 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base,
1248 const char __user *from, size_t count,
1249 loff_t *ppos)
1250 {
1251 struct cirrus_amp_cal_data cal_data;
1252 int ret;
1253
1254 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON))
1255 return -ENXIO;
1256
1257 /* Only allow a full blob to be written */
1258 if (*ppos || (count != sizeof(cal_data)))
1259 return -EMSGSIZE;
1260
1261 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count);
1262 if (ret)
1263 return ret;
1264
1265 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data);
1266 if (ret)
1267 return ret;
1268
1269 return count;
1270 }
1271 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED");
1272
cs35l56_create_cal_debugfs(struct cs35l56_base * cs35l56_base,const struct cs35l56_cal_debugfs_fops * fops)1273 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base,
1274 const struct cs35l56_cal_debugfs_fops *fops)
1275 {
1276 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON))
1277 return;
1278
1279 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev);
1280
1281 debugfs_create_file("calibrate",
1282 0200, cs35l56_base->debugfs, cs35l56_base,
1283 &fops->calibrate);
1284 debugfs_create_file("cal_temperature",
1285 0200, cs35l56_base->debugfs, cs35l56_base,
1286 &fops->cal_temperature);
1287 debugfs_create_file("cal_data",
1288 0644, cs35l56_base->debugfs, cs35l56_base,
1289 &fops->cal_data);
1290 }
1291 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED");
1292
cs35l56_remove_cal_debugfs(struct cs35l56_base * cs35l56_base)1293 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base)
1294 {
1295 debugfs_remove_recursive(cs35l56_base->debugfs);
1296 }
1297 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED");
1298
1299 const char * const cs35l56_cal_set_status_text[] = {
1300 "Unknown", "Default", "Set",
1301 };
1302 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED");
1303
cs35l56_cal_set_status_get(struct cs35l56_base * cs35l56_base,struct snd_ctl_elem_value * uvalue)1304 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base,
1305 struct snd_ctl_elem_value *uvalue)
1306 {
1307 struct cs_dsp *dsp = cs35l56_base->dsp;
1308 __be32 cal_set_status_be;
1309 int alg_id;
1310 int ret;
1311
1312 switch (cs35l56_base->type) {
1313 case 0x54:
1314 case 0x56:
1315 case 0x57:
1316 alg_id = 0x9f210;
1317 break;
1318 default:
1319 alg_id = 0xbf210;
1320 break;
1321 }
1322
1323 scoped_guard(mutex, &dsp->pwr_lock) {
1324 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp,
1325 "CAL_SET_STATUS",
1326 WMFW_ADSP2_YM, alg_id),
1327 0, &cal_set_status_be,
1328 sizeof(cal_set_status_be));
1329 }
1330 if (ret) {
1331 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN;
1332 return 0;
1333 }
1334
1335 switch (be32_to_cpu(cal_set_status_be)) {
1336 case CS35L56_CAL_SET_STATUS_DEFAULT:
1337 case CS35L56_CAL_SET_STATUS_SET:
1338 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be);
1339 return 0;
1340 default:
1341 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN;
1342 return 0;
1343 }
1344 }
1345 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED");
1346
cs35l56_read_prot_status(struct cs35l56_base * cs35l56_base,bool * fw_missing,unsigned int * fw_version)1347 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base,
1348 bool *fw_missing, unsigned int *fw_version)
1349 {
1350 unsigned int prot_status;
1351 int ret;
1352
1353 ret = regmap_read(cs35l56_base->regmap,
1354 cs35l56_base->fw_reg->prot_sts, &prot_status);
1355 if (ret) {
1356 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret);
1357 return ret;
1358 }
1359
1360 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING);
1361
1362 ret = regmap_read(cs35l56_base->regmap,
1363 cs35l56_base->fw_reg->fw_ver, fw_version);
1364 if (ret) {
1365 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret);
1366 return ret;
1367 }
1368
1369 return 0;
1370 }
1371 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED");
1372
cs35l56_warn_if_firmware_missing(struct cs35l56_base * cs35l56_base)1373 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base)
1374 {
1375 unsigned int firmware_version;
1376 bool firmware_missing;
1377 int ret;
1378
1379 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version);
1380 if (ret)
1381 return;
1382
1383 if (!firmware_missing)
1384 return;
1385
1386 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n");
1387 }
1388 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED");
1389
cs35l56_log_tuning(struct cs35l56_base * cs35l56_base,struct cs_dsp * cs_dsp)1390 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
1391 {
1392 __be32 pid, sid, tid;
1393 unsigned int alg_id;
1394 int ret;
1395
1396 switch (cs35l56_base->type) {
1397 case 0x54:
1398 case 0x56:
1399 case 0x57:
1400 alg_id = 0x9f212;
1401 break;
1402 default:
1403 alg_id = 0xbf212;
1404 break;
1405 }
1406
1407 scoped_guard(mutex, &cs_dsp->pwr_lock) {
1408 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID",
1409 WMFW_ADSP2_XM, alg_id),
1410 0, &pid, sizeof(pid));
1411 if (!ret)
1412 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID",
1413 WMFW_ADSP2_XM, alg_id),
1414 0, &sid, sizeof(sid));
1415 if (!ret)
1416 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID",
1417 WMFW_ADSP2_XM, alg_id),
1418 0, &tid, sizeof(tid));
1419 }
1420
1421 if (ret)
1422 dev_warn(cs35l56_base->dev, "Can't read tuning IDs");
1423 else
1424 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n",
1425 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid));
1426 }
1427 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED");
1428
cs35l56_hw_init(struct cs35l56_base * cs35l56_base)1429 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
1430 {
1431 int ret;
1432 unsigned int devid, revid, otpid, secured, fw_ver;
1433 bool fw_missing;
1434
1435 /*
1436 * When the system is not using a reset_gpio ensure the device is
1437 * awake, otherwise the device has just been released from reset and
1438 * the driver must wait for the control port to become usable.
1439 */
1440 if (!cs35l56_base->reset_gpio)
1441 cs35l56_issue_wake_event(cs35l56_base);
1442 else
1443 cs35l56_wait_control_port_ready();
1444
1445 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid);
1446 if (ret < 0) {
1447 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
1448 return ret;
1449 }
1450 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
1451 cs35l56_set_fw_reg_table(cs35l56_base);
1452
1453 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
1454 if (ret)
1455 return ret;
1456
1457 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid);
1458 if (ret < 0) {
1459 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
1460 return ret;
1461 }
1462 devid &= CS35L56_DEVID_MASK;
1463
1464 switch (devid) {
1465 case 0x35A54:
1466 case 0x35A56:
1467 case 0x35A57:
1468 cs35l56_base->calibration_controls = &cs35l56_calibration_controls;
1469 break;
1470 case 0x35A630:
1471 cs35l56_base->calibration_controls = &cs35l63_calibration_controls;
1472 devid = devid >> 4;
1473 break;
1474 default:
1475 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
1476 return -ENODEV;
1477 }
1478
1479 cs35l56_base->type = devid & 0xFF;
1480
1481 /* Silicon is now identified and booted so exit cache-only */
1482 regcache_cache_only(cs35l56_base->regmap, false);
1483
1484 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
1485 if (ret) {
1486 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
1487 return ret;
1488 }
1489
1490 /* When any bus is restricted treat the device as secured */
1491 if (secured & CS35L56_RESTRICTED_MASK)
1492 cs35l56_base->secured = true;
1493
1494 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
1495 if (ret < 0) {
1496 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
1497 return ret;
1498 }
1499
1500 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver);
1501 if (ret)
1502 return ret;
1503
1504 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n",
1505 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid,
1506 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing);
1507
1508 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
1509 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
1510 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
1511 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
1512 0);
1513 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
1514 CS35L56_TEMP_ERR_EINT1_MASK,
1515 0);
1516
1517 switch (cs35l56_base->type) {
1518 case 0x54:
1519 case 0x56:
1520 case 0x57:
1521 ret = cs35l56_read_silicon_uid(cs35l56_base);
1522 break;
1523 default:
1524 ret = cs35l63_read_silicon_uid(cs35l56_base);
1525 break;
1526 }
1527 if (ret)
1528 return ret;
1529
1530 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid);
1531
1532 return 0;
1533 }
1534 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED");
1535
cs35l56_get_speaker_id(struct cs35l56_base * cs35l56_base)1536 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base)
1537 {
1538 struct gpio_descs *descs;
1539 u32 speaker_id;
1540 int i, ret;
1541
1542 /* Check for vendor-specific speaker ID method */
1543 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev);
1544 if (ret >= 0) {
1545 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret);
1546 return ret;
1547 } else if (ret != -ENOENT) {
1548 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret);
1549 return ret;
1550 }
1551
1552 /* Attempt to read the speaker type from a device property */
1553 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id);
1554 if (!ret) {
1555 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
1556 return speaker_id;
1557 }
1558
1559 /* Read the speaker type qualifier from the motherboard GPIOs */
1560 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN);
1561 if (!descs) {
1562 return -ENOENT;
1563 } else if (IS_ERR(descs)) {
1564 ret = PTR_ERR(descs);
1565 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n");
1566 }
1567
1568 speaker_id = 0;
1569 for (i = 0; i < descs->ndescs; i++) {
1570 ret = gpiod_get_value_cansleep(descs->desc[i]);
1571 if (ret < 0) {
1572 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i);
1573 goto err;
1574 }
1575
1576 speaker_id |= (ret << i);
1577 }
1578
1579 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
1580 ret = speaker_id;
1581 err:
1582 gpiod_put_array(descs);
1583
1584 return ret;
1585 }
1586 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED");
1587
cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base * cs35l56_base,const u32 * gpios,int num_gpios,const u32 * pulls,int num_pulls)1588 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base,
1589 const u32 *gpios, int num_gpios,
1590 const u32 *pulls, int num_pulls)
1591 {
1592 int max_gpio;
1593 int ret = 0;
1594 int i;
1595
1596 if ((num_gpios > ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)) ||
1597 (num_pulls > ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls)))
1598 return -EOVERFLOW;
1599
1600 switch (cs35l56_base->type) {
1601 case 0x54:
1602 case 0x56:
1603 case 0x57:
1604 max_gpio = CS35L56_MAX_GPIO;
1605 break;
1606 default:
1607 max_gpio = CS35L63_MAX_GPIO;
1608 break;
1609 }
1610
1611 for (i = 0; i < num_gpios; i++) {
1612 if (gpios[i] < 1 || gpios[i] > max_gpio) {
1613 dev_err(cs35l56_base->dev, "Invalid spkid GPIO %d\n", gpios[i]);
1614 /* Keep going so we log all bad values */
1615 ret = -EINVAL;
1616 }
1617
1618 /* Change to zero-based */
1619 cs35l56_base->onchip_spkid_gpios[i] = gpios[i] - 1;
1620 }
1621
1622 for (i = 0; i < num_pulls; i++) {
1623 switch (pulls[i]) {
1624 case 0:
1625 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_NONE;
1626 break;
1627 case 1:
1628 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_UP;
1629 break;
1630 case 2:
1631 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_DOWN;
1632 break;
1633 default:
1634 dev_err(cs35l56_base->dev, "Invalid spkid pull %d\n", pulls[i]);
1635 /* Keep going so we log all bad values */
1636 ret = -EINVAL;
1637 break;
1638 }
1639 }
1640 if (ret)
1641 return ret;
1642
1643 cs35l56_base->num_onchip_spkid_gpios = num_gpios;
1644 cs35l56_base->num_onchip_spkid_pulls = num_pulls;
1645
1646 return 0;
1647 }
1648 EXPORT_SYMBOL_NS_GPL(cs35l56_check_and_save_onchip_spkid_gpios, "SND_SOC_CS35L56_SHARED");
1649
1650 /* Caller must pm_runtime resume before calling this function */
cs35l56_configure_onchip_spkid_pads(struct cs35l56_base * cs35l56_base)1651 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base)
1652 {
1653 struct regmap *regmap = cs35l56_base->regmap;
1654 unsigned int addr_offset, val;
1655 int num_gpios, num_pulls;
1656 int i, ret;
1657
1658 KUNIT_STATIC_STUB_REDIRECT(cs35l56_configure_onchip_spkid_pads, cs35l56_base);
1659
1660 if (cs35l56_base->num_onchip_spkid_gpios == 0)
1661 return 0;
1662
1663 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios,
1664 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios));
1665 num_pulls = min(cs35l56_base->num_onchip_spkid_pulls,
1666 ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls));
1667
1668 for (i = 0; i < num_gpios; i++) {
1669 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32);
1670
1671 /* Set unspecified pulls to NONE */
1672 if (i < num_pulls) {
1673 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK,
1674 cs35l56_base->onchip_spkid_pulls[i]);
1675 } else {
1676 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, CS35L56_PAD_PULL_NONE);
1677 }
1678
1679 ret = regmap_update_bits(regmap, CS35L56_SYNC_GPIO1_CFG + addr_offset,
1680 CS35L56_PAD_GPIO_PULL_MASK | CS35L56_PAD_GPIO_IE,
1681 val | CS35L56_PAD_GPIO_IE);
1682 if (ret) {
1683 dev_err(cs35l56_base->dev, "GPIO%d set pad fail: %d\n",
1684 cs35l56_base->onchip_spkid_gpios[i] + 1, ret);
1685 return ret;
1686 }
1687 }
1688
1689 ret = regmap_write(regmap, CS35L56_UPDATE_REGS, CS35L56_UPDT_GPIO_PRES);
1690 if (ret) {
1691 dev_err(cs35l56_base->dev, "UPDT_GPIO_PRES failed:%d\n", ret);
1692 return ret;
1693 }
1694
1695 usleep_range(CS35L56_PAD_PULL_SETTLE_US, CS35L56_PAD_PULL_SETTLE_US * 2);
1696
1697 return 0;
1698 }
1699 EXPORT_SYMBOL_NS_GPL(cs35l56_configure_onchip_spkid_pads, "SND_SOC_CS35L56_SHARED");
1700
1701 /* Caller must pm_runtime resume before calling this function */
cs35l56_read_onchip_spkid(struct cs35l56_base * cs35l56_base)1702 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base)
1703 {
1704 struct regmap *regmap = cs35l56_base->regmap;
1705 unsigned int addr_offset, val;
1706 int num_gpios;
1707 int speaker_id = 0;
1708 int i, ret;
1709
1710 KUNIT_STATIC_STUB_REDIRECT(cs35l56_read_onchip_spkid, cs35l56_base);
1711
1712 if (cs35l56_base->num_onchip_spkid_gpios == 0)
1713 return -ENOENT;
1714
1715 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios,
1716 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios));
1717
1718 for (i = 0; i < num_gpios; i++) {
1719 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32);
1720
1721 ret = regmap_update_bits(regmap, CS35L56_GPIO1_CTRL1 + addr_offset,
1722 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_MASK,
1723 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_GPIO);
1724 if (ret) {
1725 dev_err(cs35l56_base->dev, "GPIO%u set func fail: %d\n",
1726 cs35l56_base->onchip_spkid_gpios[i] + 1, ret);
1727 return ret;
1728 }
1729 }
1730
1731 ret = regmap_read(regmap, CS35L56_GPIO_STATUS1, &val);
1732 if (ret) {
1733 dev_err(cs35l56_base->dev, "GPIO status read failed: %d\n", ret);
1734 return ret;
1735 }
1736
1737 for (i = 0; i < num_gpios; i++) {
1738 speaker_id <<= 1;
1739
1740 if (val & BIT(cs35l56_base->onchip_spkid_gpios[i]))
1741 speaker_id |= 1;
1742 }
1743
1744 dev_dbg(cs35l56_base->dev, "Onchip GPIO Speaker ID = %d\n", speaker_id);
1745
1746 return speaker_id;
1747 }
1748 EXPORT_SYMBOL_NS_GPL(cs35l56_read_onchip_spkid, "SND_SOC_CS35L56_SHARED");
1749
1750 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
1751 [0x0C] = 128000,
1752 [0x0F] = 256000,
1753 [0x11] = 384000,
1754 [0x12] = 512000,
1755 [0x15] = 768000,
1756 [0x17] = 1024000,
1757 [0x1A] = 1500000,
1758 [0x1B] = 1536000,
1759 [0x1C] = 2000000,
1760 [0x1D] = 2048000,
1761 [0x1E] = 2400000,
1762 [0x20] = 3000000,
1763 [0x21] = 3072000,
1764 [0x23] = 4000000,
1765 [0x24] = 4096000,
1766 [0x25] = 4800000,
1767 [0x27] = 6000000,
1768 [0x28] = 6144000,
1769 [0x29] = 6250000,
1770 [0x2A] = 6400000,
1771 [0x2E] = 8000000,
1772 [0x2F] = 8192000,
1773 [0x30] = 9600000,
1774 [0x32] = 12000000,
1775 [0x33] = 12288000,
1776 [0x37] = 13500000,
1777 [0x38] = 19200000,
1778 [0x39] = 22579200,
1779 [0x3B] = 24576000,
1780 };
1781
cs35l56_get_bclk_freq_id(unsigned int freq)1782 int cs35l56_get_bclk_freq_id(unsigned int freq)
1783 {
1784 int i;
1785
1786 if (freq == 0)
1787 return -EINVAL;
1788
1789 /* The BCLK frequency must be a valid PLL REFCLK */
1790 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
1791 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
1792 return i;
1793 }
1794
1795 return -EINVAL;
1796 }
1797 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED");
1798
1799 static const char * const cs35l56_supplies[/* auto-sized */] = {
1800 "VDD_P",
1801 "VDD_IO",
1802 "VDD_A",
1803 };
1804
cs35l56_fill_supply_names(struct regulator_bulk_data * data)1805 void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
1806 {
1807 int i;
1808
1809 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
1810 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
1811 data[i].supply = cs35l56_supplies[i];
1812 }
1813 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED");
1814
1815 const char * const cs35l56_tx_input_texts[] = {
1816 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
1817 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
1818 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
1819 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
1820 };
1821 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED");
1822
1823 const unsigned int cs35l56_tx_input_values[] = {
1824 CS35L56_INPUT_SRC_NONE,
1825 CS35L56_INPUT_SRC_ASP1RX1,
1826 CS35L56_INPUT_SRC_ASP1RX2,
1827 CS35L56_INPUT_SRC_VMON,
1828 CS35L56_INPUT_SRC_IMON,
1829 CS35L56_INPUT_SRC_ERR_VOL,
1830 CS35L56_INPUT_SRC_CLASSH,
1831 CS35L56_INPUT_SRC_VDDBMON,
1832 CS35L56_INPUT_SRC_VBSTMON,
1833 CS35L56_INPUT_SRC_DSP1TX1,
1834 CS35L56_INPUT_SRC_DSP1TX2,
1835 CS35L56_INPUT_SRC_DSP1TX3,
1836 CS35L56_INPUT_SRC_DSP1TX4,
1837 CS35L56_INPUT_SRC_DSP1TX5,
1838 CS35L56_INPUT_SRC_DSP1TX6,
1839 CS35L56_INPUT_SRC_DSP1TX7,
1840 CS35L56_INPUT_SRC_DSP1TX8,
1841 CS35L56_INPUT_SRC_TEMPMON,
1842 CS35L56_INPUT_SRC_INTERPOLATOR,
1843 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
1844 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
1845 };
1846 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED");
1847
1848 const struct regmap_config cs35l56_regmap_i2c = {
1849 .reg_bits = 32,
1850 .val_bits = 32,
1851 .reg_stride = 4,
1852 .reg_format_endian = REGMAP_ENDIAN_BIG,
1853 .val_format_endian = REGMAP_ENDIAN_BIG,
1854 .max_register = CS35L56_DSP1_PMEM_5114,
1855 .reg_defaults = cs35l56_reg_defaults,
1856 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1857 .volatile_reg = cs35l56_volatile_reg,
1858 .readable_reg = cs35l56_readable_reg,
1859 .precious_reg = cs35l56_precious_reg,
1860 .cache_type = REGCACHE_MAPLE,
1861 };
1862 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED");
1863
1864 const struct regmap_config cs35l56_regmap_spi = {
1865 .reg_bits = 32,
1866 .val_bits = 32,
1867 .pad_bits = 16,
1868 .reg_stride = 4,
1869 .reg_format_endian = REGMAP_ENDIAN_BIG,
1870 .val_format_endian = REGMAP_ENDIAN_BIG,
1871 .max_register = CS35L56_DSP1_PMEM_5114,
1872 .reg_defaults = cs35l56_reg_defaults,
1873 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1874 .volatile_reg = cs35l56_volatile_reg,
1875 .readable_reg = cs35l56_readable_reg,
1876 .precious_reg = cs35l56_precious_reg,
1877 .cache_type = REGCACHE_MAPLE,
1878 };
1879 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED");
1880
1881 const struct regmap_config cs35l56_regmap_sdw = {
1882 .reg_bits = 32,
1883 .val_bits = 32,
1884 .reg_stride = 4,
1885 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
1886 .val_format_endian = REGMAP_ENDIAN_BIG,
1887 .max_register = CS35L56_DSP1_PMEM_5114,
1888 .reg_defaults = cs35l56_reg_defaults,
1889 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1890 .volatile_reg = cs35l56_volatile_reg,
1891 .readable_reg = cs35l56_readable_reg,
1892 .precious_reg = cs35l56_precious_reg,
1893 .cache_type = REGCACHE_MAPLE,
1894 };
1895 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED");
1896
1897 const struct regmap_config cs35l63_regmap_i2c = {
1898 .reg_bits = 32,
1899 .val_bits = 32,
1900 .reg_stride = 4,
1901 .reg_base = 0x8000,
1902 .reg_format_endian = REGMAP_ENDIAN_BIG,
1903 .val_format_endian = REGMAP_ENDIAN_BIG,
1904 .max_register = CS35L56_DSP1_PMEM_5114,
1905 .reg_defaults = cs35l63_reg_defaults,
1906 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults),
1907 .volatile_reg = cs35l63_volatile_reg,
1908 .readable_reg = cs35l56_readable_reg,
1909 .precious_reg = cs35l56_precious_reg,
1910 .cache_type = REGCACHE_MAPLE,
1911 };
1912 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED");
1913
1914 const struct regmap_config cs35l63_regmap_sdw = {
1915 .reg_bits = 32,
1916 .val_bits = 32,
1917 .reg_stride = 4,
1918 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
1919 .val_format_endian = REGMAP_ENDIAN_BIG,
1920 .max_register = CS35L56_DSP1_PMEM_5114,
1921 .reg_defaults = cs35l63_reg_defaults,
1922 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults),
1923 .volatile_reg = cs35l63_volatile_reg,
1924 .readable_reg = cs35l56_readable_reg,
1925 .precious_reg = cs35l56_precious_reg,
1926 .cache_type = REGCACHE_MAPLE,
1927 };
1928 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED");
1929
1930 MODULE_DESCRIPTION("ASoC CS35L56 Shared");
1931 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
1932 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
1933 MODULE_LICENSE("GPL");
1934 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB");
1935 MODULE_IMPORT_NS("FW_CS_DSP");
1936