1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver
4 *
5 * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
6 */
7
8 #include <linux/device.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/io.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15
16 #include <dt-bindings/interconnect/qcom,msm8996.h>
17
18 #include "icc-rpm.h"
19 #include "msm8996.h"
20
21 static const char * const mm_intf_clocks[] = {
22 "iface"
23 };
24
25 static const char * const a0noc_intf_clocks[] = {
26 "aggre0_snoc_axi",
27 "aggre0_cnoc_ahb",
28 "aggre0_noc_mpu_cfg"
29 };
30
31 static const char * const a2noc_intf_clocks[] = {
32 "aggre2_ufs_axi",
33 "ufs_axi"
34 };
35
36 static const u16 mas_a0noc_common_links[] = {
37 MSM8996_SLAVE_A0NOC_SNOC
38 };
39
40 static struct qcom_icc_node mas_pcie_0 = {
41 .name = "mas_pcie_0",
42 .id = MSM8996_MASTER_PCIE_0,
43 .buswidth = 8,
44 .mas_rpm_id = 65,
45 .slv_rpm_id = -1,
46 .qos.ap_owned = true,
47 .qos.qos_mode = NOC_QOS_MODE_FIXED,
48 .qos.areq_prio = 1,
49 .qos.prio_level = 1,
50 .qos.qos_port = 0,
51 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
52 .links = mas_a0noc_common_links
53 };
54
55 static struct qcom_icc_node mas_pcie_1 = {
56 .name = "mas_pcie_1",
57 .id = MSM8996_MASTER_PCIE_1,
58 .buswidth = 8,
59 .mas_rpm_id = 66,
60 .slv_rpm_id = -1,
61 .qos.ap_owned = true,
62 .qos.qos_mode = NOC_QOS_MODE_FIXED,
63 .qos.areq_prio = 1,
64 .qos.prio_level = 1,
65 .qos.qos_port = 1,
66 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
67 .links = mas_a0noc_common_links
68 };
69
70 static struct qcom_icc_node mas_pcie_2 = {
71 .name = "mas_pcie_2",
72 .id = MSM8996_MASTER_PCIE_2,
73 .buswidth = 8,
74 .mas_rpm_id = 119,
75 .slv_rpm_id = -1,
76 .qos.ap_owned = true,
77 .qos.qos_mode = NOC_QOS_MODE_FIXED,
78 .qos.areq_prio = 1,
79 .qos.prio_level = 1,
80 .qos.qos_port = 2,
81 .num_links = ARRAY_SIZE(mas_a0noc_common_links),
82 .links = mas_a0noc_common_links
83 };
84
85 static const u16 mas_a1noc_common_links[] = {
86 MSM8996_SLAVE_A1NOC_SNOC
87 };
88
89 static struct qcom_icc_node mas_cnoc_a1noc = {
90 .name = "mas_cnoc_a1noc",
91 .id = MSM8996_MASTER_CNOC_A1NOC,
92 .buswidth = 8,
93 .mas_rpm_id = 116,
94 .slv_rpm_id = -1,
95 .qos.ap_owned = true,
96 .qos.qos_mode = NOC_QOS_MODE_INVALID,
97 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
98 .links = mas_a1noc_common_links
99 };
100
101 static struct qcom_icc_node mas_crypto_c0 = {
102 .name = "mas_crypto_c0",
103 .id = MSM8996_MASTER_CRYPTO_CORE0,
104 .buswidth = 8,
105 .mas_rpm_id = 23,
106 .slv_rpm_id = -1,
107 .qos.ap_owned = true,
108 .qos.qos_mode = NOC_QOS_MODE_FIXED,
109 .qos.areq_prio = 1,
110 .qos.prio_level = 1,
111 .qos.qos_port = 0,
112 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
113 .links = mas_a1noc_common_links
114 };
115
116 static struct qcom_icc_node mas_pnoc_a1noc = {
117 .name = "mas_pnoc_a1noc",
118 .id = MSM8996_MASTER_PNOC_A1NOC,
119 .buswidth = 8,
120 .mas_rpm_id = 117,
121 .slv_rpm_id = -1,
122 .qos.ap_owned = false,
123 .qos.qos_mode = NOC_QOS_MODE_FIXED,
124 .qos.areq_prio = 0,
125 .qos.prio_level = 0,
126 .qos.qos_port = 1,
127 .num_links = ARRAY_SIZE(mas_a1noc_common_links),
128 .links = mas_a1noc_common_links
129 };
130
131 static const u16 mas_a2noc_common_links[] = {
132 MSM8996_SLAVE_A2NOC_SNOC
133 };
134
135 static struct qcom_icc_node mas_usb3 = {
136 .name = "mas_usb3",
137 .id = MSM8996_MASTER_USB3,
138 .buswidth = 8,
139 .mas_rpm_id = 32,
140 .slv_rpm_id = -1,
141 .qos.ap_owned = true,
142 .qos.qos_mode = NOC_QOS_MODE_FIXED,
143 .qos.areq_prio = 1,
144 .qos.prio_level = 1,
145 .qos.qos_port = 3,
146 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
147 .links = mas_a2noc_common_links
148 };
149
150 static struct qcom_icc_node mas_ipa = {
151 .name = "mas_ipa",
152 .id = MSM8996_MASTER_IPA,
153 .buswidth = 8,
154 .mas_rpm_id = 59,
155 .slv_rpm_id = -1,
156 .qos.ap_owned = true,
157 .qos.qos_mode = NOC_QOS_MODE_FIXED,
158 .qos.areq_prio = 0,
159 .qos.prio_level = 0,
160 .qos.qos_port = -1,
161 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
162 .links = mas_a2noc_common_links
163 };
164
165 static struct qcom_icc_node mas_ufs = {
166 .name = "mas_ufs",
167 .id = MSM8996_MASTER_UFS,
168 .buswidth = 8,
169 .mas_rpm_id = 68,
170 .slv_rpm_id = -1,
171 .qos.ap_owned = true,
172 .qos.qos_mode = NOC_QOS_MODE_FIXED,
173 .qos.areq_prio = 1,
174 .qos.prio_level = 1,
175 .qos.qos_port = 2,
176 .num_links = ARRAY_SIZE(mas_a2noc_common_links),
177 .links = mas_a2noc_common_links
178 };
179
180 static const u16 mas_apps_proc_links[] = {
181 MSM8996_SLAVE_BIMC_SNOC_1,
182 MSM8996_SLAVE_EBI_CH0,
183 MSM8996_SLAVE_BIMC_SNOC_0
184 };
185
186 static struct qcom_icc_node mas_apps_proc = {
187 .name = "mas_apps_proc",
188 .id = MSM8996_MASTER_AMPSS_M0,
189 .buswidth = 8,
190 .mas_rpm_id = 0,
191 .slv_rpm_id = -1,
192 .qos.ap_owned = true,
193 .qos.qos_mode = NOC_QOS_MODE_FIXED,
194 .qos.areq_prio = 0,
195 .qos.prio_level = 0,
196 .qos.qos_port = 0,
197 .num_links = ARRAY_SIZE(mas_apps_proc_links),
198 .links = mas_apps_proc_links
199 };
200
201 static const u16 mas_oxili_common_links[] = {
202 MSM8996_SLAVE_BIMC_SNOC_1,
203 MSM8996_SLAVE_HMSS_L3,
204 MSM8996_SLAVE_EBI_CH0,
205 MSM8996_SLAVE_BIMC_SNOC_0
206 };
207
208 static struct qcom_icc_node mas_oxili = {
209 .name = "mas_oxili",
210 .id = MSM8996_MASTER_GRAPHICS_3D,
211 .buswidth = 8,
212 .mas_rpm_id = 6,
213 .slv_rpm_id = -1,
214 .qos.ap_owned = true,
215 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
216 .qos.areq_prio = 0,
217 .qos.prio_level = 0,
218 .qos.qos_port = 1,
219 .num_links = ARRAY_SIZE(mas_oxili_common_links),
220 .links = mas_oxili_common_links
221 };
222
223 static struct qcom_icc_node mas_mnoc_bimc = {
224 .name = "mas_mnoc_bimc",
225 .id = MSM8996_MASTER_MNOC_BIMC,
226 .buswidth = 8,
227 .mas_rpm_id = 2,
228 .slv_rpm_id = -1,
229 .qos.ap_owned = true,
230 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
231 .qos.areq_prio = 0,
232 .qos.prio_level = 0,
233 .qos.qos_port = 2,
234 .num_links = ARRAY_SIZE(mas_oxili_common_links),
235 .links = mas_oxili_common_links
236 };
237
238 static const u16 mas_snoc_bimc_links[] = {
239 MSM8996_SLAVE_HMSS_L3,
240 MSM8996_SLAVE_EBI_CH0
241 };
242
243 static struct qcom_icc_node mas_snoc_bimc = {
244 .name = "mas_snoc_bimc",
245 .id = MSM8996_MASTER_SNOC_BIMC,
246 .buswidth = 8,
247 .mas_rpm_id = 3,
248 .slv_rpm_id = -1,
249 .qos.ap_owned = false,
250 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
251 .qos.areq_prio = 0,
252 .qos.prio_level = 0,
253 .qos.qos_port = -1,
254 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
255 .links = mas_snoc_bimc_links
256 };
257
258 static const u16 mas_snoc_cnoc_links[] = {
259 MSM8996_SLAVE_CLK_CTL,
260 MSM8996_SLAVE_RBCPR_CX,
261 MSM8996_SLAVE_A2NOC_SMMU_CFG,
262 MSM8996_SLAVE_A0NOC_MPU_CFG,
263 MSM8996_SLAVE_MESSAGE_RAM,
264 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
265 MSM8996_SLAVE_PCIE_0_CFG,
266 MSM8996_SLAVE_TLMM,
267 MSM8996_SLAVE_MPM,
268 MSM8996_SLAVE_A0NOC_SMMU_CFG,
269 MSM8996_SLAVE_EBI1_PHY_CFG,
270 MSM8996_SLAVE_BIMC_CFG,
271 MSM8996_SLAVE_PIMEM_CFG,
272 MSM8996_SLAVE_RBCPR_MX,
273 MSM8996_SLAVE_PRNG,
274 MSM8996_SLAVE_PCIE20_AHB2PHY,
275 MSM8996_SLAVE_A2NOC_MPU_CFG,
276 MSM8996_SLAVE_QDSS_CFG,
277 MSM8996_SLAVE_A2NOC_CFG,
278 MSM8996_SLAVE_A0NOC_CFG,
279 MSM8996_SLAVE_UFS_CFG,
280 MSM8996_SLAVE_CRYPTO_0_CFG,
281 MSM8996_SLAVE_PCIE_1_CFG,
282 MSM8996_SLAVE_SNOC_CFG,
283 MSM8996_SLAVE_SNOC_MPU_CFG,
284 MSM8996_SLAVE_A1NOC_MPU_CFG,
285 MSM8996_SLAVE_A1NOC_SMMU_CFG,
286 MSM8996_SLAVE_PCIE_2_CFG,
287 MSM8996_SLAVE_CNOC_MNOC_CFG,
288 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
289 MSM8996_SLAVE_PMIC_ARB,
290 MSM8996_SLAVE_IMEM_CFG,
291 MSM8996_SLAVE_A1NOC_CFG,
292 MSM8996_SLAVE_SSC_CFG,
293 MSM8996_SLAVE_TCSR,
294 MSM8996_SLAVE_LPASS_SMMU_CFG,
295 MSM8996_SLAVE_DCC_CFG
296 };
297
298 static struct qcom_icc_node mas_snoc_cnoc = {
299 .name = "mas_snoc_cnoc",
300 .id = MSM8996_MASTER_SNOC_CNOC,
301 .buswidth = 8,
302 .mas_rpm_id = 52,
303 .slv_rpm_id = -1,
304 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
305 .links = mas_snoc_cnoc_links
306 };
307
308 static const u16 mas_qdss_dap_links[] = {
309 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
310 MSM8996_SLAVE_RBCPR_CX,
311 MSM8996_SLAVE_A2NOC_SMMU_CFG,
312 MSM8996_SLAVE_A0NOC_MPU_CFG,
313 MSM8996_SLAVE_MESSAGE_RAM,
314 MSM8996_SLAVE_PCIE_0_CFG,
315 MSM8996_SLAVE_TLMM,
316 MSM8996_SLAVE_MPM,
317 MSM8996_SLAVE_A0NOC_SMMU_CFG,
318 MSM8996_SLAVE_EBI1_PHY_CFG,
319 MSM8996_SLAVE_BIMC_CFG,
320 MSM8996_SLAVE_PIMEM_CFG,
321 MSM8996_SLAVE_RBCPR_MX,
322 MSM8996_SLAVE_CLK_CTL,
323 MSM8996_SLAVE_PRNG,
324 MSM8996_SLAVE_PCIE20_AHB2PHY,
325 MSM8996_SLAVE_A2NOC_MPU_CFG,
326 MSM8996_SLAVE_QDSS_CFG,
327 MSM8996_SLAVE_A2NOC_CFG,
328 MSM8996_SLAVE_A0NOC_CFG,
329 MSM8996_SLAVE_UFS_CFG,
330 MSM8996_SLAVE_CRYPTO_0_CFG,
331 MSM8996_SLAVE_CNOC_A1NOC,
332 MSM8996_SLAVE_PCIE_1_CFG,
333 MSM8996_SLAVE_SNOC_CFG,
334 MSM8996_SLAVE_SNOC_MPU_CFG,
335 MSM8996_SLAVE_A1NOC_MPU_CFG,
336 MSM8996_SLAVE_A1NOC_SMMU_CFG,
337 MSM8996_SLAVE_PCIE_2_CFG,
338 MSM8996_SLAVE_CNOC_MNOC_CFG,
339 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
340 MSM8996_SLAVE_PMIC_ARB,
341 MSM8996_SLAVE_IMEM_CFG,
342 MSM8996_SLAVE_A1NOC_CFG,
343 MSM8996_SLAVE_SSC_CFG,
344 MSM8996_SLAVE_TCSR,
345 MSM8996_SLAVE_LPASS_SMMU_CFG,
346 MSM8996_SLAVE_DCC_CFG
347 };
348
349 static struct qcom_icc_node mas_qdss_dap = {
350 .name = "mas_qdss_dap",
351 .id = MSM8996_MASTER_QDSS_DAP,
352 .buswidth = 8,
353 .mas_rpm_id = 49,
354 .slv_rpm_id = -1,
355 .qos.ap_owned = true,
356 .qos.qos_mode = NOC_QOS_MODE_INVALID,
357 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
358 .links = mas_qdss_dap_links
359 };
360
361 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
362 MSM8996_SLAVE_MMAGIC_CFG,
363 MSM8996_SLAVE_DSA_MPU_CFG,
364 MSM8996_SLAVE_MMSS_CLK_CFG,
365 MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
366 MSM8996_SLAVE_VENUS_CFG,
367 MSM8996_SLAVE_SMMU_VFE_CFG,
368 MSM8996_SLAVE_MISC_CFG,
369 MSM8996_SLAVE_SMMU_CPP_CFG,
370 MSM8996_SLAVE_GRAPHICS_3D_CFG,
371 MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
372 MSM8996_SLAVE_VENUS_THROTTLE_CFG,
373 MSM8996_SLAVE_CAMERA_CFG,
374 MSM8996_SLAVE_DISPLAY_CFG,
375 MSM8996_SLAVE_CPR_CFG,
376 MSM8996_SLAVE_SMMU_ROTATOR_CFG,
377 MSM8996_SLAVE_DSA_CFG,
378 MSM8996_SLAVE_SMMU_VENUS_CFG,
379 MSM8996_SLAVE_VMEM_CFG,
380 MSM8996_SLAVE_SMMU_JPEG_CFG,
381 MSM8996_SLAVE_SMMU_MDP_CFG,
382 MSM8996_SLAVE_MNOC_MPU_CFG
383 };
384
385 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
386 .name = "mas_cnoc_mnoc_mmss_cfg",
387 .id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG,
388 .buswidth = 8,
389 .mas_rpm_id = 4,
390 .slv_rpm_id = -1,
391 .qos.ap_owned = true,
392 .qos.qos_mode = NOC_QOS_MODE_INVALID,
393 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
394 .links = mas_cnoc_mnoc_mmss_cfg_links
395 };
396
397 static const u16 mas_cnoc_mnoc_cfg_links[] = {
398 MSM8996_SLAVE_SERVICE_MNOC
399 };
400
401 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
402 .name = "mas_cnoc_mnoc_cfg",
403 .id = MSM8996_MASTER_CNOC_MNOC_CFG,
404 .buswidth = 8,
405 .mas_rpm_id = 5,
406 .slv_rpm_id = -1,
407 .qos.ap_owned = true,
408 .qos.qos_mode = NOC_QOS_MODE_INVALID,
409 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
410 .links = mas_cnoc_mnoc_cfg_links
411 };
412
413 static const u16 mas_mnoc_bimc_common_links[] = {
414 MSM8996_SLAVE_MNOC_BIMC
415 };
416
417 static struct qcom_icc_node mas_cpp = {
418 .name = "mas_cpp",
419 .id = MSM8996_MASTER_CPP,
420 .buswidth = 32,
421 .mas_rpm_id = 115,
422 .slv_rpm_id = -1,
423 .qos.ap_owned = true,
424 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
425 .qos.areq_prio = 0,
426 .qos.prio_level = 0,
427 .qos.qos_port = 5,
428 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
429 .links = mas_mnoc_bimc_common_links
430 };
431
432 static struct qcom_icc_node mas_jpeg = {
433 .name = "mas_jpeg",
434 .id = MSM8996_MASTER_JPEG,
435 .buswidth = 32,
436 .mas_rpm_id = 7,
437 .slv_rpm_id = -1,
438 .qos.ap_owned = true,
439 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
440 .qos.areq_prio = 0,
441 .qos.prio_level = 0,
442 .qos.qos_port = 7,
443 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
444 .links = mas_mnoc_bimc_common_links
445 };
446
447 static struct qcom_icc_node mas_mdp_p0 = {
448 .name = "mas_mdp_p0",
449 .id = MSM8996_MASTER_MDP_PORT0,
450 .buswidth = 32,
451 .ib_coeff = 25,
452 .mas_rpm_id = 8,
453 .slv_rpm_id = -1,
454 .qos.ap_owned = true,
455 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
456 .qos.areq_prio = 0,
457 .qos.prio_level = 0,
458 .qos.qos_port = 1,
459 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
460 .links = mas_mnoc_bimc_common_links
461 };
462
463 static struct qcom_icc_node mas_mdp_p1 = {
464 .name = "mas_mdp_p1",
465 .id = MSM8996_MASTER_MDP_PORT1,
466 .buswidth = 32,
467 .ib_coeff = 25,
468 .mas_rpm_id = 61,
469 .slv_rpm_id = -1,
470 .qos.ap_owned = true,
471 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
472 .qos.areq_prio = 0,
473 .qos.prio_level = 0,
474 .qos.qos_port = 2,
475 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
476 .links = mas_mnoc_bimc_common_links
477 };
478
479 static struct qcom_icc_node mas_rotator = {
480 .name = "mas_rotator",
481 .id = MSM8996_MASTER_ROTATOR,
482 .buswidth = 32,
483 .mas_rpm_id = 120,
484 .slv_rpm_id = -1,
485 .qos.ap_owned = true,
486 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
487 .qos.areq_prio = 0,
488 .qos.prio_level = 0,
489 .qos.qos_port = 0,
490 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
491 .links = mas_mnoc_bimc_common_links
492 };
493
494 static struct qcom_icc_node mas_venus = {
495 .name = "mas_venus",
496 .id = MSM8996_MASTER_VIDEO_P0,
497 .buswidth = 32,
498 .mas_rpm_id = 9,
499 .slv_rpm_id = -1,
500 .qos.ap_owned = true,
501 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
502 .qos.areq_prio = 0,
503 .qos.prio_level = 0,
504 .qos.qos_port = 3,
505 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
506 .links = mas_mnoc_bimc_common_links
507 };
508
509 static struct qcom_icc_node mas_vfe = {
510 .name = "mas_vfe",
511 .id = MSM8996_MASTER_VFE,
512 .buswidth = 32,
513 .mas_rpm_id = 11,
514 .slv_rpm_id = -1,
515 .qos.ap_owned = true,
516 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
517 .qos.areq_prio = 0,
518 .qos.prio_level = 0,
519 .qos.qos_port = 6,
520 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
521 .links = mas_mnoc_bimc_common_links
522 };
523
524 static const u16 mas_vmem_common_links[] = {
525 MSM8996_SLAVE_VMEM
526 };
527
528 static struct qcom_icc_node mas_snoc_vmem = {
529 .name = "mas_snoc_vmem",
530 .id = MSM8996_MASTER_SNOC_VMEM,
531 .buswidth = 32,
532 .mas_rpm_id = 114,
533 .slv_rpm_id = -1,
534 .qos.ap_owned = true,
535 .qos.qos_mode = NOC_QOS_MODE_INVALID,
536 .num_links = ARRAY_SIZE(mas_vmem_common_links),
537 .links = mas_vmem_common_links
538 };
539
540 static struct qcom_icc_node mas_venus_vmem = {
541 .name = "mas_venus_vmem",
542 .id = MSM8996_MASTER_VIDEO_P0_OCMEM,
543 .buswidth = 32,
544 .mas_rpm_id = 121,
545 .slv_rpm_id = -1,
546 .qos.ap_owned = true,
547 .qos.qos_mode = NOC_QOS_MODE_INVALID,
548 .num_links = ARRAY_SIZE(mas_vmem_common_links),
549 .links = mas_vmem_common_links
550 };
551
552 static const u16 mas_snoc_pnoc_links[] = {
553 MSM8996_SLAVE_BLSP_1,
554 MSM8996_SLAVE_BLSP_2,
555 MSM8996_SLAVE_SDCC_1,
556 MSM8996_SLAVE_SDCC_2,
557 MSM8996_SLAVE_SDCC_4,
558 MSM8996_SLAVE_TSIF,
559 MSM8996_SLAVE_PDM,
560 MSM8996_SLAVE_AHB2PHY
561 };
562
563 static struct qcom_icc_node mas_snoc_pnoc = {
564 .name = "mas_snoc_pnoc",
565 .id = MSM8996_MASTER_SNOC_PNOC,
566 .buswidth = 8,
567 .mas_rpm_id = 44,
568 .slv_rpm_id = -1,
569 .num_links = ARRAY_SIZE(mas_snoc_pnoc_links),
570 .links = mas_snoc_pnoc_links
571 };
572
573 static const u16 mas_pnoc_a1noc_common_links[] = {
574 MSM8996_SLAVE_PNOC_A1NOC
575 };
576
577 static struct qcom_icc_node mas_sdcc_1 = {
578 .name = "mas_sdcc_1",
579 .id = MSM8996_MASTER_SDCC_1,
580 .buswidth = 8,
581 .mas_rpm_id = 33,
582 .slv_rpm_id = -1,
583 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
584 .links = mas_pnoc_a1noc_common_links
585 };
586
587 static struct qcom_icc_node mas_sdcc_2 = {
588 .name = "mas_sdcc_2",
589 .id = MSM8996_MASTER_SDCC_2,
590 .buswidth = 8,
591 .mas_rpm_id = 35,
592 .slv_rpm_id = -1,
593 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
594 .links = mas_pnoc_a1noc_common_links
595 };
596
597 static struct qcom_icc_node mas_sdcc_4 = {
598 .name = "mas_sdcc_4",
599 .id = MSM8996_MASTER_SDCC_4,
600 .buswidth = 8,
601 .mas_rpm_id = 36,
602 .slv_rpm_id = -1,
603 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
604 .links = mas_pnoc_a1noc_common_links
605 };
606
607 static struct qcom_icc_node mas_usb_hs = {
608 .name = "mas_usb_hs",
609 .id = MSM8996_MASTER_USB_HS,
610 .buswidth = 8,
611 .mas_rpm_id = 42,
612 .slv_rpm_id = -1,
613 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
614 .links = mas_pnoc_a1noc_common_links
615 };
616
617 static struct qcom_icc_node mas_blsp_1 = {
618 .name = "mas_blsp_1",
619 .id = MSM8996_MASTER_BLSP_1,
620 .buswidth = 4,
621 .mas_rpm_id = 41,
622 .slv_rpm_id = -1,
623 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
624 .links = mas_pnoc_a1noc_common_links
625 };
626
627 static struct qcom_icc_node mas_blsp_2 = {
628 .name = "mas_blsp_2",
629 .id = MSM8996_MASTER_BLSP_2,
630 .buswidth = 4,
631 .mas_rpm_id = 39,
632 .slv_rpm_id = -1,
633 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
634 .links = mas_pnoc_a1noc_common_links
635 };
636
637 static struct qcom_icc_node mas_tsif = {
638 .name = "mas_tsif",
639 .id = MSM8996_MASTER_TSIF,
640 .buswidth = 4,
641 .mas_rpm_id = 37,
642 .slv_rpm_id = -1,
643 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
644 .links = mas_pnoc_a1noc_common_links
645 };
646
647 static const u16 mas_hmss_links[] = {
648 MSM8996_SLAVE_PIMEM,
649 MSM8996_SLAVE_OCIMEM,
650 MSM8996_SLAVE_SNOC_BIMC
651 };
652
653 static struct qcom_icc_node mas_hmss = {
654 .name = "mas_hmss",
655 .id = MSM8996_MASTER_HMSS,
656 .buswidth = 8,
657 .mas_rpm_id = 118,
658 .slv_rpm_id = -1,
659 .qos.ap_owned = true,
660 .qos.qos_mode = NOC_QOS_MODE_FIXED,
661 .qos.areq_prio = 1,
662 .qos.prio_level = 1,
663 .qos.qos_port = 4,
664 .num_links = ARRAY_SIZE(mas_hmss_links),
665 .links = mas_hmss_links
666 };
667
668 static const u16 mas_qdss_common_links[] = {
669 MSM8996_SLAVE_PIMEM,
670 MSM8996_SLAVE_USB3,
671 MSM8996_SLAVE_OCIMEM,
672 MSM8996_SLAVE_SNOC_BIMC,
673 MSM8996_SLAVE_SNOC_PNOC
674 };
675
676 static struct qcom_icc_node mas_qdss_bam = {
677 .name = "mas_qdss_bam",
678 .id = MSM8996_MASTER_QDSS_BAM,
679 .buswidth = 16,
680 .mas_rpm_id = 19,
681 .slv_rpm_id = -1,
682 .qos.ap_owned = true,
683 .qos.qos_mode = NOC_QOS_MODE_FIXED,
684 .qos.areq_prio = 1,
685 .qos.prio_level = 1,
686 .qos.qos_port = 2,
687 .num_links = ARRAY_SIZE(mas_qdss_common_links),
688 .links = mas_qdss_common_links
689 };
690
691 static const u16 mas_snoc_cfg_links[] = {
692 MSM8996_SLAVE_SERVICE_SNOC
693 };
694
695 static struct qcom_icc_node mas_snoc_cfg = {
696 .name = "mas_snoc_cfg",
697 .id = MSM8996_MASTER_SNOC_CFG,
698 .buswidth = 16,
699 .mas_rpm_id = 20,
700 .slv_rpm_id = -1,
701 .qos.ap_owned = true,
702 .qos.qos_mode = NOC_QOS_MODE_INVALID,
703 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
704 .links = mas_snoc_cfg_links
705 };
706
707 static const u16 mas_bimc_snoc_0_links[] = {
708 MSM8996_SLAVE_SNOC_VMEM,
709 MSM8996_SLAVE_USB3,
710 MSM8996_SLAVE_PIMEM,
711 MSM8996_SLAVE_LPASS,
712 MSM8996_SLAVE_APPSS,
713 MSM8996_SLAVE_SNOC_CNOC,
714 MSM8996_SLAVE_SNOC_PNOC,
715 MSM8996_SLAVE_OCIMEM,
716 MSM8996_SLAVE_QDSS_STM
717 };
718
719 static struct qcom_icc_node mas_bimc_snoc_0 = {
720 .name = "mas_bimc_snoc_0",
721 .id = MSM8996_MASTER_BIMC_SNOC_0,
722 .buswidth = 16,
723 .mas_rpm_id = 21,
724 .slv_rpm_id = -1,
725 .qos.ap_owned = true,
726 .qos.qos_mode = NOC_QOS_MODE_INVALID,
727 .num_links = ARRAY_SIZE(mas_bimc_snoc_0_links),
728 .links = mas_bimc_snoc_0_links
729 };
730
731 static const u16 mas_bimc_snoc_1_links[] = {
732 MSM8996_SLAVE_PCIE_2,
733 MSM8996_SLAVE_PCIE_1,
734 MSM8996_SLAVE_PCIE_0
735 };
736
737 static struct qcom_icc_node mas_bimc_snoc_1 = {
738 .name = "mas_bimc_snoc_1",
739 .id = MSM8996_MASTER_BIMC_SNOC_1,
740 .buswidth = 16,
741 .mas_rpm_id = 109,
742 .slv_rpm_id = -1,
743 .qos.ap_owned = true,
744 .qos.qos_mode = NOC_QOS_MODE_INVALID,
745 .num_links = ARRAY_SIZE(mas_bimc_snoc_1_links),
746 .links = mas_bimc_snoc_1_links
747 };
748
749 static const u16 mas_a0noc_snoc_links[] = {
750 MSM8996_SLAVE_SNOC_PNOC,
751 MSM8996_SLAVE_OCIMEM,
752 MSM8996_SLAVE_APPSS,
753 MSM8996_SLAVE_SNOC_BIMC,
754 MSM8996_SLAVE_PIMEM
755 };
756
757 static struct qcom_icc_node mas_a0noc_snoc = {
758 .name = "mas_a0noc_snoc",
759 .id = MSM8996_MASTER_A0NOC_SNOC,
760 .buswidth = 16,
761 .mas_rpm_id = 110,
762 .slv_rpm_id = -1,
763 .qos.ap_owned = true,
764 .qos.qos_mode = NOC_QOS_MODE_INVALID,
765 .num_links = ARRAY_SIZE(mas_a0noc_snoc_links),
766 .links = mas_a0noc_snoc_links
767 };
768
769 static const u16 mas_a1noc_snoc_links[] = {
770 MSM8996_SLAVE_SNOC_VMEM,
771 MSM8996_SLAVE_USB3,
772 MSM8996_SLAVE_PCIE_0,
773 MSM8996_SLAVE_PIMEM,
774 MSM8996_SLAVE_PCIE_2,
775 MSM8996_SLAVE_LPASS,
776 MSM8996_SLAVE_PCIE_1,
777 MSM8996_SLAVE_APPSS,
778 MSM8996_SLAVE_SNOC_BIMC,
779 MSM8996_SLAVE_SNOC_CNOC,
780 MSM8996_SLAVE_SNOC_PNOC,
781 MSM8996_SLAVE_OCIMEM,
782 MSM8996_SLAVE_QDSS_STM
783 };
784
785 static struct qcom_icc_node mas_a1noc_snoc = {
786 .name = "mas_a1noc_snoc",
787 .id = MSM8996_MASTER_A1NOC_SNOC,
788 .buswidth = 16,
789 .mas_rpm_id = 111,
790 .slv_rpm_id = -1,
791 .num_links = ARRAY_SIZE(mas_a1noc_snoc_links),
792 .links = mas_a1noc_snoc_links
793 };
794
795 static const u16 mas_a2noc_snoc_links[] = {
796 MSM8996_SLAVE_SNOC_VMEM,
797 MSM8996_SLAVE_USB3,
798 MSM8996_SLAVE_PCIE_1,
799 MSM8996_SLAVE_PIMEM,
800 MSM8996_SLAVE_PCIE_2,
801 MSM8996_SLAVE_QDSS_STM,
802 MSM8996_SLAVE_LPASS,
803 MSM8996_SLAVE_SNOC_BIMC,
804 MSM8996_SLAVE_SNOC_CNOC,
805 MSM8996_SLAVE_SNOC_PNOC,
806 MSM8996_SLAVE_OCIMEM,
807 MSM8996_SLAVE_PCIE_0
808 };
809
810 static struct qcom_icc_node mas_a2noc_snoc = {
811 .name = "mas_a2noc_snoc",
812 .id = MSM8996_MASTER_A2NOC_SNOC,
813 .buswidth = 16,
814 .mas_rpm_id = 112,
815 .slv_rpm_id = -1,
816 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
817 .links = mas_a2noc_snoc_links
818 };
819
820 static struct qcom_icc_node mas_qdss_etr = {
821 .name = "mas_qdss_etr",
822 .id = MSM8996_MASTER_QDSS_ETR,
823 .buswidth = 16,
824 .mas_rpm_id = 31,
825 .slv_rpm_id = -1,
826 .qos.ap_owned = true,
827 .qos.qos_mode = NOC_QOS_MODE_FIXED,
828 .qos.areq_prio = 1,
829 .qos.prio_level = 1,
830 .qos.qos_port = 3,
831 .num_links = ARRAY_SIZE(mas_qdss_common_links),
832 .links = mas_qdss_common_links
833 };
834
835 static const u16 slv_a0noc_snoc_links[] = {
836 MSM8996_MASTER_A0NOC_SNOC
837 };
838
839 static struct qcom_icc_node slv_a0noc_snoc = {
840 .name = "slv_a0noc_snoc",
841 .id = MSM8996_SLAVE_A0NOC_SNOC,
842 .buswidth = 8,
843 .mas_rpm_id = -1,
844 .slv_rpm_id = 141,
845 .qos.ap_owned = true,
846 .qos.qos_mode = NOC_QOS_MODE_INVALID,
847 .num_links = ARRAY_SIZE(slv_a0noc_snoc_links),
848 .links = slv_a0noc_snoc_links
849 };
850
851 static const u16 slv_a1noc_snoc_links[] = {
852 MSM8996_MASTER_A1NOC_SNOC
853 };
854
855 static struct qcom_icc_node slv_a1noc_snoc = {
856 .name = "slv_a1noc_snoc",
857 .id = MSM8996_SLAVE_A1NOC_SNOC,
858 .buswidth = 8,
859 .mas_rpm_id = -1,
860 .slv_rpm_id = 142,
861 .num_links = ARRAY_SIZE(slv_a1noc_snoc_links),
862 .links = slv_a1noc_snoc_links
863 };
864
865 static const u16 slv_a2noc_snoc_links[] = {
866 MSM8996_MASTER_A2NOC_SNOC
867 };
868
869 static struct qcom_icc_node slv_a2noc_snoc = {
870 .name = "slv_a2noc_snoc",
871 .id = MSM8996_SLAVE_A2NOC_SNOC,
872 .buswidth = 8,
873 .mas_rpm_id = -1,
874 .slv_rpm_id = 143,
875 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
876 .links = slv_a2noc_snoc_links
877 };
878
879 static struct qcom_icc_node slv_ebi = {
880 .name = "slv_ebi",
881 .id = MSM8996_SLAVE_EBI_CH0,
882 .buswidth = 8,
883 .mas_rpm_id = -1,
884 .slv_rpm_id = 0
885 };
886
887 static struct qcom_icc_node slv_hmss_l3 = {
888 .name = "slv_hmss_l3",
889 .id = MSM8996_SLAVE_HMSS_L3,
890 .buswidth = 8,
891 .mas_rpm_id = -1,
892 .slv_rpm_id = 160
893 };
894
895 static const u16 slv_bimc_snoc_0_links[] = {
896 MSM8996_MASTER_BIMC_SNOC_0
897 };
898
899 static struct qcom_icc_node slv_bimc_snoc_0 = {
900 .name = "slv_bimc_snoc_0",
901 .id = MSM8996_SLAVE_BIMC_SNOC_0,
902 .buswidth = 8,
903 .mas_rpm_id = -1,
904 .slv_rpm_id = 2,
905 .qos.ap_owned = true,
906 .qos.qos_mode = NOC_QOS_MODE_INVALID,
907 .num_links = ARRAY_SIZE(slv_bimc_snoc_0_links),
908 .links = slv_bimc_snoc_0_links
909 };
910
911 static const u16 slv_bimc_snoc_1_links[] = {
912 MSM8996_MASTER_BIMC_SNOC_1
913 };
914
915 static struct qcom_icc_node slv_bimc_snoc_1 = {
916 .name = "slv_bimc_snoc_1",
917 .id = MSM8996_SLAVE_BIMC_SNOC_1,
918 .buswidth = 8,
919 .mas_rpm_id = -1,
920 .slv_rpm_id = 138,
921 .qos.ap_owned = true,
922 .qos.qos_mode = NOC_QOS_MODE_INVALID,
923 .num_links = ARRAY_SIZE(slv_bimc_snoc_1_links),
924 .links = slv_bimc_snoc_1_links
925 };
926
927 static const u16 slv_cnoc_a1noc_links[] = {
928 MSM8996_MASTER_CNOC_A1NOC
929 };
930
931 static struct qcom_icc_node slv_cnoc_a1noc = {
932 .name = "slv_cnoc_a1noc",
933 .id = MSM8996_SLAVE_CNOC_A1NOC,
934 .buswidth = 4,
935 .mas_rpm_id = -1,
936 .slv_rpm_id = 75,
937 .qos.ap_owned = true,
938 .qos.qos_mode = NOC_QOS_MODE_INVALID,
939 .num_links = ARRAY_SIZE(slv_cnoc_a1noc_links),
940 .links = slv_cnoc_a1noc_links
941 };
942
943 static struct qcom_icc_node slv_clk_ctl = {
944 .name = "slv_clk_ctl",
945 .id = MSM8996_SLAVE_CLK_CTL,
946 .buswidth = 4,
947 .mas_rpm_id = -1,
948 .slv_rpm_id = 47
949 };
950
951 static struct qcom_icc_node slv_tcsr = {
952 .name = "slv_tcsr",
953 .id = MSM8996_SLAVE_TCSR,
954 .buswidth = 4,
955 .mas_rpm_id = -1,
956 .slv_rpm_id = 50
957 };
958
959 static struct qcom_icc_node slv_tlmm = {
960 .name = "slv_tlmm",
961 .id = MSM8996_SLAVE_TLMM,
962 .buswidth = 4,
963 .mas_rpm_id = -1,
964 .slv_rpm_id = 51
965 };
966
967 static struct qcom_icc_node slv_crypto0_cfg = {
968 .name = "slv_crypto0_cfg",
969 .id = MSM8996_SLAVE_CRYPTO_0_CFG,
970 .buswidth = 4,
971 .mas_rpm_id = -1,
972 .slv_rpm_id = 52,
973 .qos.ap_owned = true,
974 .qos.qos_mode = NOC_QOS_MODE_INVALID
975 };
976
977 static struct qcom_icc_node slv_mpm = {
978 .name = "slv_mpm",
979 .id = MSM8996_SLAVE_MPM,
980 .buswidth = 4,
981 .mas_rpm_id = -1,
982 .slv_rpm_id = 62,
983 .qos.ap_owned = true,
984 .qos.qos_mode = NOC_QOS_MODE_INVALID
985 };
986
987 static struct qcom_icc_node slv_pimem_cfg = {
988 .name = "slv_pimem_cfg",
989 .id = MSM8996_SLAVE_PIMEM_CFG,
990 .buswidth = 4,
991 .mas_rpm_id = -1,
992 .slv_rpm_id = 167,
993 .qos.ap_owned = true,
994 .qos.qos_mode = NOC_QOS_MODE_INVALID
995 };
996
997 static struct qcom_icc_node slv_imem_cfg = {
998 .name = "slv_imem_cfg",
999 .id = MSM8996_SLAVE_IMEM_CFG,
1000 .buswidth = 4,
1001 .mas_rpm_id = -1,
1002 .slv_rpm_id = 54,
1003 .qos.ap_owned = true,
1004 .qos.qos_mode = NOC_QOS_MODE_INVALID
1005 };
1006
1007 static struct qcom_icc_node slv_message_ram = {
1008 .name = "slv_message_ram",
1009 .id = MSM8996_SLAVE_MESSAGE_RAM,
1010 .buswidth = 4,
1011 .mas_rpm_id = -1,
1012 .slv_rpm_id = 55
1013 };
1014
1015 static struct qcom_icc_node slv_bimc_cfg = {
1016 .name = "slv_bimc_cfg",
1017 .id = MSM8996_SLAVE_BIMC_CFG,
1018 .buswidth = 4,
1019 .mas_rpm_id = -1,
1020 .slv_rpm_id = 56,
1021 .qos.ap_owned = true,
1022 .qos.qos_mode = NOC_QOS_MODE_INVALID
1023 };
1024
1025 static struct qcom_icc_node slv_pmic_arb = {
1026 .name = "slv_pmic_arb",
1027 .id = MSM8996_SLAVE_PMIC_ARB,
1028 .buswidth = 4,
1029 .mas_rpm_id = -1,
1030 .slv_rpm_id = 59
1031 };
1032
1033 static struct qcom_icc_node slv_prng = {
1034 .name = "slv_prng",
1035 .id = MSM8996_SLAVE_PRNG,
1036 .buswidth = 4,
1037 .mas_rpm_id = -1,
1038 .slv_rpm_id = 127,
1039 .qos.ap_owned = true,
1040 .qos.qos_mode = NOC_QOS_MODE_INVALID
1041 };
1042
1043 static struct qcom_icc_node slv_dcc_cfg = {
1044 .name = "slv_dcc_cfg",
1045 .id = MSM8996_SLAVE_DCC_CFG,
1046 .buswidth = 4,
1047 .mas_rpm_id = -1,
1048 .slv_rpm_id = 155,
1049 .qos.ap_owned = true,
1050 .qos.qos_mode = NOC_QOS_MODE_INVALID
1051 };
1052
1053 static struct qcom_icc_node slv_rbcpr_mx = {
1054 .name = "slv_rbcpr_mx",
1055 .id = MSM8996_SLAVE_RBCPR_MX,
1056 .buswidth = 4,
1057 .mas_rpm_id = -1,
1058 .slv_rpm_id = 170,
1059 .qos.ap_owned = true,
1060 .qos.qos_mode = NOC_QOS_MODE_INVALID
1061 };
1062
1063 static struct qcom_icc_node slv_qdss_cfg = {
1064 .name = "slv_qdss_cfg",
1065 .id = MSM8996_SLAVE_QDSS_CFG,
1066 .buswidth = 4,
1067 .mas_rpm_id = -1,
1068 .slv_rpm_id = 63,
1069 .qos.ap_owned = true,
1070 .qos.qos_mode = NOC_QOS_MODE_INVALID
1071 };
1072
1073 static struct qcom_icc_node slv_rbcpr_cx = {
1074 .name = "slv_rbcpr_cx",
1075 .id = MSM8996_SLAVE_RBCPR_CX,
1076 .buswidth = 4,
1077 .mas_rpm_id = -1,
1078 .slv_rpm_id = 169,
1079 .qos.ap_owned = true,
1080 .qos.qos_mode = NOC_QOS_MODE_INVALID
1081 };
1082
1083 static struct qcom_icc_node slv_cpu_apu_cfg = {
1084 .name = "slv_cpu_apu_cfg",
1085 .id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
1086 .buswidth = 4,
1087 .mas_rpm_id = -1,
1088 .slv_rpm_id = 168,
1089 .qos.ap_owned = true,
1090 .qos.qos_mode = NOC_QOS_MODE_INVALID
1091 };
1092
1093 static const u16 slv_cnoc_mnoc_cfg_links[] = {
1094 MSM8996_MASTER_CNOC_MNOC_CFG
1095 };
1096
1097 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
1098 .name = "slv_cnoc_mnoc_cfg",
1099 .id = MSM8996_SLAVE_CNOC_MNOC_CFG,
1100 .buswidth = 4,
1101 .mas_rpm_id = -1,
1102 .slv_rpm_id = 66,
1103 .qos.ap_owned = true,
1104 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1105 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
1106 .links = slv_cnoc_mnoc_cfg_links
1107 };
1108
1109 static struct qcom_icc_node slv_snoc_cfg = {
1110 .name = "slv_snoc_cfg",
1111 .id = MSM8996_SLAVE_SNOC_CFG,
1112 .buswidth = 4,
1113 .mas_rpm_id = -1,
1114 .slv_rpm_id = 70,
1115 .qos.ap_owned = true,
1116 .qos.qos_mode = NOC_QOS_MODE_INVALID
1117 };
1118
1119 static struct qcom_icc_node slv_snoc_mpu_cfg = {
1120 .name = "slv_snoc_mpu_cfg",
1121 .id = MSM8996_SLAVE_SNOC_MPU_CFG,
1122 .buswidth = 4,
1123 .mas_rpm_id = -1,
1124 .slv_rpm_id = 67,
1125 .qos.ap_owned = true,
1126 .qos.qos_mode = NOC_QOS_MODE_INVALID
1127 };
1128
1129 static struct qcom_icc_node slv_ebi1_phy_cfg = {
1130 .name = "slv_ebi1_phy_cfg",
1131 .id = MSM8996_SLAVE_EBI1_PHY_CFG,
1132 .buswidth = 4,
1133 .mas_rpm_id = -1,
1134 .slv_rpm_id = 73,
1135 .qos.ap_owned = true,
1136 .qos.qos_mode = NOC_QOS_MODE_INVALID
1137 };
1138
1139 static struct qcom_icc_node slv_a0noc_cfg = {
1140 .name = "slv_a0noc_cfg",
1141 .id = MSM8996_SLAVE_A0NOC_CFG,
1142 .buswidth = 4,
1143 .mas_rpm_id = -1,
1144 .slv_rpm_id = 144,
1145 .qos.ap_owned = true,
1146 .qos.qos_mode = NOC_QOS_MODE_INVALID
1147 };
1148
1149 static struct qcom_icc_node slv_pcie_1_cfg = {
1150 .name = "slv_pcie_1_cfg",
1151 .id = MSM8996_SLAVE_PCIE_1_CFG,
1152 .buswidth = 4,
1153 .mas_rpm_id = -1,
1154 .slv_rpm_id = 89,
1155 .qos.ap_owned = true,
1156 .qos.qos_mode = NOC_QOS_MODE_INVALID
1157 };
1158
1159 static struct qcom_icc_node slv_pcie_2_cfg = {
1160 .name = "slv_pcie_2_cfg",
1161 .id = MSM8996_SLAVE_PCIE_2_CFG,
1162 .buswidth = 4,
1163 .mas_rpm_id = -1,
1164 .slv_rpm_id = 165,
1165 .qos.ap_owned = true,
1166 .qos.qos_mode = NOC_QOS_MODE_INVALID
1167 };
1168
1169 static struct qcom_icc_node slv_pcie_0_cfg = {
1170 .name = "slv_pcie_0_cfg",
1171 .id = MSM8996_SLAVE_PCIE_0_CFG,
1172 .buswidth = 4,
1173 .mas_rpm_id = -1,
1174 .slv_rpm_id = 88,
1175 .qos.ap_owned = true,
1176 .qos.qos_mode = NOC_QOS_MODE_INVALID
1177 };
1178
1179 static struct qcom_icc_node slv_pcie20_ahb2phy = {
1180 .name = "slv_pcie20_ahb2phy",
1181 .id = MSM8996_SLAVE_PCIE20_AHB2PHY,
1182 .buswidth = 4,
1183 .mas_rpm_id = -1,
1184 .slv_rpm_id = 163,
1185 .qos.ap_owned = true,
1186 .qos.qos_mode = NOC_QOS_MODE_INVALID
1187 };
1188
1189 static struct qcom_icc_node slv_a0noc_mpu_cfg = {
1190 .name = "slv_a0noc_mpu_cfg",
1191 .id = MSM8996_SLAVE_A0NOC_MPU_CFG,
1192 .buswidth = 4,
1193 .mas_rpm_id = -1,
1194 .slv_rpm_id = 145,
1195 .qos.ap_owned = true,
1196 .qos.qos_mode = NOC_QOS_MODE_INVALID
1197 };
1198
1199 static struct qcom_icc_node slv_ufs_cfg = {
1200 .name = "slv_ufs_cfg",
1201 .id = MSM8996_SLAVE_UFS_CFG,
1202 .buswidth = 4,
1203 .mas_rpm_id = -1,
1204 .slv_rpm_id = 92,
1205 .qos.ap_owned = true,
1206 .qos.qos_mode = NOC_QOS_MODE_INVALID
1207 };
1208
1209 static struct qcom_icc_node slv_a1noc_cfg = {
1210 .name = "slv_a1noc_cfg",
1211 .id = MSM8996_SLAVE_A1NOC_CFG,
1212 .buswidth = 4,
1213 .mas_rpm_id = -1,
1214 .slv_rpm_id = 147,
1215 .qos.ap_owned = true,
1216 .qos.qos_mode = NOC_QOS_MODE_INVALID
1217 };
1218
1219 static struct qcom_icc_node slv_a1noc_mpu_cfg = {
1220 .name = "slv_a1noc_mpu_cfg",
1221 .id = MSM8996_SLAVE_A1NOC_MPU_CFG,
1222 .buswidth = 4,
1223 .mas_rpm_id = -1,
1224 .slv_rpm_id = 148,
1225 .qos.ap_owned = true,
1226 .qos.qos_mode = NOC_QOS_MODE_INVALID
1227 };
1228
1229 static struct qcom_icc_node slv_a2noc_cfg = {
1230 .name = "slv_a2noc_cfg",
1231 .id = MSM8996_SLAVE_A2NOC_CFG,
1232 .buswidth = 4,
1233 .mas_rpm_id = -1,
1234 .slv_rpm_id = 150,
1235 .qos.ap_owned = true,
1236 .qos.qos_mode = NOC_QOS_MODE_INVALID
1237 };
1238
1239 static struct qcom_icc_node slv_a2noc_mpu_cfg = {
1240 .name = "slv_a2noc_mpu_cfg",
1241 .id = MSM8996_SLAVE_A2NOC_MPU_CFG,
1242 .buswidth = 4,
1243 .mas_rpm_id = -1,
1244 .slv_rpm_id = 151,
1245 .qos.ap_owned = true,
1246 .qos.qos_mode = NOC_QOS_MODE_INVALID
1247 };
1248
1249 static struct qcom_icc_node slv_ssc_cfg = {
1250 .name = "slv_ssc_cfg",
1251 .id = MSM8996_SLAVE_SSC_CFG,
1252 .buswidth = 4,
1253 .mas_rpm_id = -1,
1254 .slv_rpm_id = 177,
1255 .qos.ap_owned = true,
1256 .qos.qos_mode = NOC_QOS_MODE_INVALID
1257 };
1258
1259 static struct qcom_icc_node slv_a0noc_smmu_cfg = {
1260 .name = "slv_a0noc_smmu_cfg",
1261 .id = MSM8996_SLAVE_A0NOC_SMMU_CFG,
1262 .buswidth = 8,
1263 .mas_rpm_id = -1,
1264 .slv_rpm_id = 146,
1265 .qos.ap_owned = true,
1266 .qos.qos_mode = NOC_QOS_MODE_INVALID
1267 };
1268
1269 static struct qcom_icc_node slv_a1noc_smmu_cfg = {
1270 .name = "slv_a1noc_smmu_cfg",
1271 .id = MSM8996_SLAVE_A1NOC_SMMU_CFG,
1272 .buswidth = 8,
1273 .mas_rpm_id = -1,
1274 .slv_rpm_id = 149,
1275 .qos.ap_owned = true,
1276 .qos.qos_mode = NOC_QOS_MODE_INVALID
1277 };
1278
1279 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1280 .name = "slv_a2noc_smmu_cfg",
1281 .id = MSM8996_SLAVE_A2NOC_SMMU_CFG,
1282 .buswidth = 8,
1283 .mas_rpm_id = -1,
1284 .slv_rpm_id = 152,
1285 .qos.ap_owned = true,
1286 .qos.qos_mode = NOC_QOS_MODE_INVALID
1287 };
1288
1289 static struct qcom_icc_node slv_lpass_smmu_cfg = {
1290 .name = "slv_lpass_smmu_cfg",
1291 .id = MSM8996_SLAVE_LPASS_SMMU_CFG,
1292 .buswidth = 8,
1293 .mas_rpm_id = -1,
1294 .slv_rpm_id = 161,
1295 .qos.ap_owned = true,
1296 .qos.qos_mode = NOC_QOS_MODE_INVALID
1297 };
1298
1299 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1300 MSM8996_MASTER_CNOC_MNOC_MMSS_CFG
1301 };
1302
1303 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1304 .name = "slv_cnoc_mnoc_mmss_cfg",
1305 .id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
1306 .buswidth = 8,
1307 .mas_rpm_id = -1,
1308 .slv_rpm_id = 58,
1309 .qos.ap_owned = true,
1310 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1311 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1312 .links = slv_cnoc_mnoc_mmss_cfg_links
1313 };
1314
1315 static struct qcom_icc_node slv_mmagic_cfg = {
1316 .name = "slv_mmagic_cfg",
1317 .id = MSM8996_SLAVE_MMAGIC_CFG,
1318 .buswidth = 8,
1319 .mas_rpm_id = -1,
1320 .slv_rpm_id = 162,
1321 .qos.ap_owned = true,
1322 .qos.qos_mode = NOC_QOS_MODE_INVALID
1323 };
1324
1325 static struct qcom_icc_node slv_cpr_cfg = {
1326 .name = "slv_cpr_cfg",
1327 .id = MSM8996_SLAVE_CPR_CFG,
1328 .buswidth = 8,
1329 .mas_rpm_id = -1,
1330 .slv_rpm_id = 6,
1331 .qos.ap_owned = true,
1332 .qos.qos_mode = NOC_QOS_MODE_INVALID
1333 };
1334
1335 static struct qcom_icc_node slv_misc_cfg = {
1336 .name = "slv_misc_cfg",
1337 .id = MSM8996_SLAVE_MISC_CFG,
1338 .buswidth = 8,
1339 .mas_rpm_id = -1,
1340 .slv_rpm_id = 8,
1341 .qos.ap_owned = true,
1342 .qos.qos_mode = NOC_QOS_MODE_INVALID
1343 };
1344
1345 static struct qcom_icc_node slv_venus_throttle_cfg = {
1346 .name = "slv_venus_throttle_cfg",
1347 .id = MSM8996_SLAVE_VENUS_THROTTLE_CFG,
1348 .buswidth = 8,
1349 .mas_rpm_id = -1,
1350 .slv_rpm_id = 178,
1351 .qos.ap_owned = true,
1352 .qos.qos_mode = NOC_QOS_MODE_INVALID
1353 };
1354
1355 static struct qcom_icc_node slv_venus_cfg = {
1356 .name = "slv_venus_cfg",
1357 .id = MSM8996_SLAVE_VENUS_CFG,
1358 .buswidth = 8,
1359 .mas_rpm_id = -1,
1360 .slv_rpm_id = 10,
1361 .qos.ap_owned = true,
1362 .qos.qos_mode = NOC_QOS_MODE_INVALID
1363 };
1364
1365 static struct qcom_icc_node slv_vmem_cfg = {
1366 .name = "slv_vmem_cfg",
1367 .id = MSM8996_SLAVE_VMEM_CFG,
1368 .buswidth = 8,
1369 .mas_rpm_id = -1,
1370 .slv_rpm_id = 180,
1371 .qos.ap_owned = true,
1372 .qos.qos_mode = NOC_QOS_MODE_INVALID
1373 };
1374
1375 static struct qcom_icc_node slv_dsa_cfg = {
1376 .name = "slv_dsa_cfg",
1377 .id = MSM8996_SLAVE_DSA_CFG,
1378 .buswidth = 8,
1379 .mas_rpm_id = -1,
1380 .slv_rpm_id = 157,
1381 .qos.ap_owned = true,
1382 .qos.qos_mode = NOC_QOS_MODE_INVALID
1383 };
1384
1385 static struct qcom_icc_node slv_mnoc_clocks_cfg = {
1386 .name = "slv_mnoc_clocks_cfg",
1387 .id = MSM8996_SLAVE_MMSS_CLK_CFG,
1388 .buswidth = 8,
1389 .mas_rpm_id = -1,
1390 .slv_rpm_id = 12,
1391 .qos.ap_owned = true,
1392 .qos.qos_mode = NOC_QOS_MODE_INVALID
1393 };
1394
1395 static struct qcom_icc_node slv_dsa_mpu_cfg = {
1396 .name = "slv_dsa_mpu_cfg",
1397 .id = MSM8996_SLAVE_DSA_MPU_CFG,
1398 .buswidth = 8,
1399 .mas_rpm_id = -1,
1400 .slv_rpm_id = 158,
1401 .qos.ap_owned = true,
1402 .qos.qos_mode = NOC_QOS_MODE_INVALID
1403 };
1404
1405 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1406 .name = "slv_mnoc_mpu_cfg",
1407 .id = MSM8996_SLAVE_MNOC_MPU_CFG,
1408 .buswidth = 8,
1409 .mas_rpm_id = -1,
1410 .slv_rpm_id = 14,
1411 .qos.ap_owned = true,
1412 .qos.qos_mode = NOC_QOS_MODE_INVALID
1413 };
1414
1415 static struct qcom_icc_node slv_display_cfg = {
1416 .name = "slv_display_cfg",
1417 .id = MSM8996_SLAVE_DISPLAY_CFG,
1418 .buswidth = 8,
1419 .mas_rpm_id = -1,
1420 .slv_rpm_id = 4,
1421 .qos.ap_owned = true,
1422 .qos.qos_mode = NOC_QOS_MODE_INVALID
1423 };
1424
1425 static struct qcom_icc_node slv_display_throttle_cfg = {
1426 .name = "slv_display_throttle_cfg",
1427 .id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
1428 .buswidth = 8,
1429 .mas_rpm_id = -1,
1430 .slv_rpm_id = 156,
1431 .qos.ap_owned = true,
1432 .qos.qos_mode = NOC_QOS_MODE_INVALID
1433 };
1434
1435 static struct qcom_icc_node slv_camera_cfg = {
1436 .name = "slv_camera_cfg",
1437 .id = MSM8996_SLAVE_CAMERA_CFG,
1438 .buswidth = 8,
1439 .mas_rpm_id = -1,
1440 .slv_rpm_id = 3,
1441 .qos.ap_owned = true,
1442 .qos.qos_mode = NOC_QOS_MODE_INVALID
1443 };
1444
1445 static struct qcom_icc_node slv_camera_throttle_cfg = {
1446 .name = "slv_camera_throttle_cfg",
1447 .id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
1448 .buswidth = 8,
1449 .mas_rpm_id = -1,
1450 .slv_rpm_id = 154,
1451 .qos.ap_owned = true,
1452 .qos.qos_mode = NOC_QOS_MODE_INVALID
1453 };
1454
1455 static struct qcom_icc_node slv_oxili_cfg = {
1456 .name = "slv_oxili_cfg",
1457 .id = MSM8996_SLAVE_GRAPHICS_3D_CFG,
1458 .buswidth = 8,
1459 .mas_rpm_id = -1,
1460 .slv_rpm_id = 11,
1461 .qos.ap_owned = true,
1462 .qos.qos_mode = NOC_QOS_MODE_INVALID
1463 };
1464
1465 static struct qcom_icc_node slv_smmu_mdp_cfg = {
1466 .name = "slv_smmu_mdp_cfg",
1467 .id = MSM8996_SLAVE_SMMU_MDP_CFG,
1468 .buswidth = 8,
1469 .mas_rpm_id = -1,
1470 .slv_rpm_id = 173,
1471 .qos.ap_owned = true,
1472 .qos.qos_mode = NOC_QOS_MODE_INVALID
1473 };
1474
1475 static struct qcom_icc_node slv_smmu_rot_cfg = {
1476 .name = "slv_smmu_rot_cfg",
1477 .id = MSM8996_SLAVE_SMMU_ROTATOR_CFG,
1478 .buswidth = 8,
1479 .mas_rpm_id = -1,
1480 .slv_rpm_id = 174,
1481 .qos.ap_owned = true,
1482 .qos.qos_mode = NOC_QOS_MODE_INVALID
1483 };
1484
1485 static struct qcom_icc_node slv_smmu_venus_cfg = {
1486 .name = "slv_smmu_venus_cfg",
1487 .id = MSM8996_SLAVE_SMMU_VENUS_CFG,
1488 .buswidth = 8,
1489 .mas_rpm_id = -1,
1490 .slv_rpm_id = 175,
1491 .qos.ap_owned = true,
1492 .qos.qos_mode = NOC_QOS_MODE_INVALID
1493 };
1494
1495 static struct qcom_icc_node slv_smmu_cpp_cfg = {
1496 .name = "slv_smmu_cpp_cfg",
1497 .id = MSM8996_SLAVE_SMMU_CPP_CFG,
1498 .buswidth = 8,
1499 .mas_rpm_id = -1,
1500 .slv_rpm_id = 171,
1501 .qos.ap_owned = true,
1502 .qos.qos_mode = NOC_QOS_MODE_INVALID
1503 };
1504
1505 static struct qcom_icc_node slv_smmu_jpeg_cfg = {
1506 .name = "slv_smmu_jpeg_cfg",
1507 .id = MSM8996_SLAVE_SMMU_JPEG_CFG,
1508 .buswidth = 8,
1509 .mas_rpm_id = -1,
1510 .slv_rpm_id = 172,
1511 .qos.ap_owned = true,
1512 .qos.qos_mode = NOC_QOS_MODE_INVALID
1513 };
1514
1515 static struct qcom_icc_node slv_smmu_vfe_cfg = {
1516 .name = "slv_smmu_vfe_cfg",
1517 .id = MSM8996_SLAVE_SMMU_VFE_CFG,
1518 .buswidth = 8,
1519 .mas_rpm_id = -1,
1520 .slv_rpm_id = 176,
1521 .qos.ap_owned = true,
1522 .qos.qos_mode = NOC_QOS_MODE_INVALID
1523 };
1524
1525 static const u16 slv_mnoc_bimc_links[] = {
1526 MSM8996_MASTER_MNOC_BIMC
1527 };
1528
1529 static struct qcom_icc_node slv_mnoc_bimc = {
1530 .name = "slv_mnoc_bimc",
1531 .id = MSM8996_SLAVE_MNOC_BIMC,
1532 .buswidth = 32,
1533 .mas_rpm_id = -1,
1534 .slv_rpm_id = 16,
1535 .qos.ap_owned = true,
1536 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1537 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1538 .links = slv_mnoc_bimc_links
1539 };
1540
1541 static struct qcom_icc_node slv_vmem = {
1542 .name = "slv_vmem",
1543 .id = MSM8996_SLAVE_VMEM,
1544 .buswidth = 32,
1545 .mas_rpm_id = -1,
1546 .slv_rpm_id = 179,
1547 .qos.ap_owned = true,
1548 .qos.qos_mode = NOC_QOS_MODE_INVALID
1549 };
1550
1551 static struct qcom_icc_node slv_srvc_mnoc = {
1552 .name = "slv_srvc_mnoc",
1553 .id = MSM8996_SLAVE_SERVICE_MNOC,
1554 .buswidth = 8,
1555 .mas_rpm_id = -1,
1556 .slv_rpm_id = 17,
1557 .qos.ap_owned = true,
1558 .qos.qos_mode = NOC_QOS_MODE_INVALID
1559 };
1560
1561 static const u16 slv_pnoc_a1noc_links[] = {
1562 MSM8996_MASTER_PNOC_A1NOC
1563 };
1564
1565 static struct qcom_icc_node slv_pnoc_a1noc = {
1566 .name = "slv_pnoc_a1noc",
1567 .id = MSM8996_SLAVE_PNOC_A1NOC,
1568 .buswidth = 8,
1569 .mas_rpm_id = -1,
1570 .slv_rpm_id = 139,
1571 .num_links = ARRAY_SIZE(slv_pnoc_a1noc_links),
1572 .links = slv_pnoc_a1noc_links
1573 };
1574
1575 static struct qcom_icc_node slv_usb_hs = {
1576 .name = "slv_usb_hs",
1577 .id = MSM8996_SLAVE_USB_HS,
1578 .buswidth = 4,
1579 .mas_rpm_id = -1,
1580 .slv_rpm_id = 40
1581 };
1582
1583 static struct qcom_icc_node slv_sdcc_2 = {
1584 .name = "slv_sdcc_2",
1585 .id = MSM8996_SLAVE_SDCC_2,
1586 .buswidth = 4,
1587 .mas_rpm_id = -1,
1588 .slv_rpm_id = 33
1589 };
1590
1591 static struct qcom_icc_node slv_sdcc_4 = {
1592 .name = "slv_sdcc_4",
1593 .id = MSM8996_SLAVE_SDCC_4,
1594 .buswidth = 4,
1595 .mas_rpm_id = -1,
1596 .slv_rpm_id = 34
1597 };
1598
1599 static struct qcom_icc_node slv_tsif = {
1600 .name = "slv_tsif",
1601 .id = MSM8996_SLAVE_TSIF,
1602 .buswidth = 4,
1603 .mas_rpm_id = -1,
1604 .slv_rpm_id = 35
1605 };
1606
1607 static struct qcom_icc_node slv_blsp_2 = {
1608 .name = "slv_blsp_2",
1609 .id = MSM8996_SLAVE_BLSP_2,
1610 .buswidth = 4,
1611 .mas_rpm_id = -1,
1612 .slv_rpm_id = 37
1613 };
1614
1615 static struct qcom_icc_node slv_sdcc_1 = {
1616 .name = "slv_sdcc_1",
1617 .id = MSM8996_SLAVE_SDCC_1,
1618 .buswidth = 4,
1619 .mas_rpm_id = -1,
1620 .slv_rpm_id = 31
1621 };
1622
1623 static struct qcom_icc_node slv_blsp_1 = {
1624 .name = "slv_blsp_1",
1625 .id = MSM8996_SLAVE_BLSP_1,
1626 .buswidth = 4,
1627 .mas_rpm_id = -1,
1628 .slv_rpm_id = 39
1629 };
1630
1631 static struct qcom_icc_node slv_pdm = {
1632 .name = "slv_pdm",
1633 .id = MSM8996_SLAVE_PDM,
1634 .buswidth = 4,
1635 .mas_rpm_id = -1,
1636 .slv_rpm_id = 41
1637 };
1638
1639 static struct qcom_icc_node slv_ahb2phy = {
1640 .name = "slv_ahb2phy",
1641 .id = MSM8996_SLAVE_AHB2PHY,
1642 .buswidth = 4,
1643 .mas_rpm_id = -1,
1644 .slv_rpm_id = 153,
1645 .qos.ap_owned = true,
1646 .qos.qos_mode = NOC_QOS_MODE_INVALID
1647 };
1648
1649 static struct qcom_icc_node slv_hmss = {
1650 .name = "slv_hmss",
1651 .id = MSM8996_SLAVE_APPSS,
1652 .buswidth = 16,
1653 .mas_rpm_id = -1,
1654 .slv_rpm_id = 20,
1655 .qos.ap_owned = true,
1656 .qos.qos_mode = NOC_QOS_MODE_INVALID
1657 };
1658
1659 static struct qcom_icc_node slv_lpass = {
1660 .name = "slv_lpass",
1661 .id = MSM8996_SLAVE_LPASS,
1662 .buswidth = 16,
1663 .mas_rpm_id = -1,
1664 .slv_rpm_id = 21,
1665 .qos.ap_owned = true,
1666 .qos.qos_mode = NOC_QOS_MODE_INVALID
1667 };
1668
1669 static struct qcom_icc_node slv_usb3 = {
1670 .name = "slv_usb3",
1671 .id = MSM8996_SLAVE_USB3,
1672 .buswidth = 16,
1673 .mas_rpm_id = -1,
1674 .slv_rpm_id = 22,
1675 .qos.ap_owned = true,
1676 .qos.qos_mode = NOC_QOS_MODE_INVALID
1677 };
1678
1679 static const u16 slv_snoc_bimc_links[] = {
1680 MSM8996_MASTER_SNOC_BIMC
1681 };
1682
1683 static struct qcom_icc_node slv_snoc_bimc = {
1684 .name = "slv_snoc_bimc",
1685 .id = MSM8996_SLAVE_SNOC_BIMC,
1686 .buswidth = 32,
1687 .mas_rpm_id = -1,
1688 .slv_rpm_id = 24,
1689 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1690 .links = slv_snoc_bimc_links
1691 };
1692
1693 static const u16 slv_snoc_cnoc_links[] = {
1694 MSM8996_MASTER_SNOC_CNOC
1695 };
1696
1697 static struct qcom_icc_node slv_snoc_cnoc = {
1698 .name = "slv_snoc_cnoc",
1699 .id = MSM8996_SLAVE_SNOC_CNOC,
1700 .buswidth = 16,
1701 .mas_rpm_id = -1,
1702 .slv_rpm_id = 25,
1703 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1704 .links = slv_snoc_cnoc_links
1705 };
1706
1707 static struct qcom_icc_node slv_imem = {
1708 .name = "slv_imem",
1709 .id = MSM8996_SLAVE_OCIMEM,
1710 .buswidth = 16,
1711 .mas_rpm_id = -1,
1712 .slv_rpm_id = 26
1713 };
1714
1715 static struct qcom_icc_node slv_pimem = {
1716 .name = "slv_pimem",
1717 .id = MSM8996_SLAVE_PIMEM,
1718 .buswidth = 16,
1719 .mas_rpm_id = -1,
1720 .slv_rpm_id = 166
1721 };
1722
1723 static const u16 slv_snoc_vmem_links[] = {
1724 MSM8996_MASTER_SNOC_VMEM
1725 };
1726
1727 static struct qcom_icc_node slv_snoc_vmem = {
1728 .name = "slv_snoc_vmem",
1729 .id = MSM8996_SLAVE_SNOC_VMEM,
1730 .buswidth = 16,
1731 .mas_rpm_id = -1,
1732 .slv_rpm_id = 140,
1733 .qos.ap_owned = true,
1734 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1735 .num_links = ARRAY_SIZE(slv_snoc_vmem_links),
1736 .links = slv_snoc_vmem_links
1737 };
1738
1739 static const u16 slv_snoc_pnoc_links[] = {
1740 MSM8996_MASTER_SNOC_PNOC
1741 };
1742
1743 static struct qcom_icc_node slv_snoc_pnoc = {
1744 .name = "slv_snoc_pnoc",
1745 .id = MSM8996_SLAVE_SNOC_PNOC,
1746 .buswidth = 16,
1747 .mas_rpm_id = -1,
1748 .slv_rpm_id = 28,
1749 .num_links = ARRAY_SIZE(slv_snoc_pnoc_links),
1750 .links = slv_snoc_pnoc_links
1751 };
1752
1753 static struct qcom_icc_node slv_qdss_stm = {
1754 .name = "slv_qdss_stm",
1755 .id = MSM8996_SLAVE_QDSS_STM,
1756 .buswidth = 16,
1757 .mas_rpm_id = -1,
1758 .slv_rpm_id = 30
1759 };
1760
1761 static struct qcom_icc_node slv_pcie_0 = {
1762 .name = "slv_pcie_0",
1763 .id = MSM8996_SLAVE_PCIE_0,
1764 .buswidth = 16,
1765 .mas_rpm_id = -1,
1766 .slv_rpm_id = 84,
1767 .qos.ap_owned = true,
1768 .qos.qos_mode = NOC_QOS_MODE_INVALID
1769 };
1770
1771 static struct qcom_icc_node slv_pcie_1 = {
1772 .name = "slv_pcie_1",
1773 .id = MSM8996_SLAVE_PCIE_1,
1774 .buswidth = 16,
1775 .mas_rpm_id = -1,
1776 .slv_rpm_id = 85,
1777 .qos.ap_owned = true,
1778 .qos.qos_mode = NOC_QOS_MODE_INVALID
1779 };
1780
1781 static struct qcom_icc_node slv_pcie_2 = {
1782 .name = "slv_pcie_2",
1783 .id = MSM8996_SLAVE_PCIE_2,
1784 .buswidth = 16,
1785 .mas_rpm_id = -1,
1786 .slv_rpm_id = 164,
1787 .qos.ap_owned = true,
1788 .qos.qos_mode = NOC_QOS_MODE_INVALID
1789 };
1790
1791 static struct qcom_icc_node slv_srvc_snoc = {
1792 .name = "slv_srvc_snoc",
1793 .id = MSM8996_SLAVE_SERVICE_SNOC,
1794 .buswidth = 16,
1795 .mas_rpm_id = -1,
1796 .slv_rpm_id = 29,
1797 .qos.ap_owned = true,
1798 .qos.qos_mode = NOC_QOS_MODE_INVALID
1799 };
1800
1801 static struct qcom_icc_node * const a0noc_nodes[] = {
1802 [MASTER_PCIE_0] = &mas_pcie_0,
1803 [MASTER_PCIE_1] = &mas_pcie_1,
1804 [MASTER_PCIE_2] = &mas_pcie_2
1805 };
1806
1807 static const struct regmap_config msm8996_a0noc_regmap_config = {
1808 .reg_bits = 32,
1809 .reg_stride = 4,
1810 .val_bits = 32,
1811 .max_register = 0x6000,
1812 .fast_io = true
1813 };
1814
1815 static const struct qcom_icc_desc msm8996_a0noc = {
1816 .type = QCOM_ICC_NOC,
1817 .nodes = a0noc_nodes,
1818 .num_nodes = ARRAY_SIZE(a0noc_nodes),
1819 .intf_clocks = a0noc_intf_clocks,
1820 .num_intf_clocks = ARRAY_SIZE(a0noc_intf_clocks),
1821 .regmap_cfg = &msm8996_a0noc_regmap_config
1822 };
1823
1824 static struct qcom_icc_node * const a1noc_nodes[] = {
1825 [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc,
1826 [MASTER_CRYPTO_CORE0] = &mas_crypto_c0,
1827 [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc
1828 };
1829
1830 static const struct regmap_config msm8996_a1noc_regmap_config = {
1831 .reg_bits = 32,
1832 .reg_stride = 4,
1833 .val_bits = 32,
1834 .max_register = 0x5000,
1835 .fast_io = true
1836 };
1837
1838 static const struct qcom_icc_desc msm8996_a1noc = {
1839 .type = QCOM_ICC_NOC,
1840 .nodes = a1noc_nodes,
1841 .num_nodes = ARRAY_SIZE(a1noc_nodes),
1842 .bus_clk_desc = &aggre1_branch_clk,
1843 .regmap_cfg = &msm8996_a1noc_regmap_config
1844 };
1845
1846 static struct qcom_icc_node * const a2noc_nodes[] = {
1847 [MASTER_USB3] = &mas_usb3,
1848 [MASTER_IPA] = &mas_ipa,
1849 [MASTER_UFS] = &mas_ufs
1850 };
1851
1852 static const struct regmap_config msm8996_a2noc_regmap_config = {
1853 .reg_bits = 32,
1854 .reg_stride = 4,
1855 .val_bits = 32,
1856 .max_register = 0x7000,
1857 .fast_io = true
1858 };
1859
1860 static const struct qcom_icc_desc msm8996_a2noc = {
1861 .type = QCOM_ICC_NOC,
1862 .nodes = a2noc_nodes,
1863 .num_nodes = ARRAY_SIZE(a2noc_nodes),
1864 .bus_clk_desc = &aggre2_branch_clk,
1865 .intf_clocks = a2noc_intf_clocks,
1866 .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
1867 .regmap_cfg = &msm8996_a2noc_regmap_config
1868 };
1869
1870 static struct qcom_icc_node * const bimc_nodes[] = {
1871 [MASTER_AMPSS_M0] = &mas_apps_proc,
1872 [MASTER_GRAPHICS_3D] = &mas_oxili,
1873 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1874 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1875 [SLAVE_EBI_CH0] = &slv_ebi,
1876 [SLAVE_HMSS_L3] = &slv_hmss_l3,
1877 [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0,
1878 [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1
1879 };
1880
1881 static const struct regmap_config msm8996_bimc_regmap_config = {
1882 .reg_bits = 32,
1883 .reg_stride = 4,
1884 .val_bits = 32,
1885 .max_register = 0x5a000,
1886 .fast_io = true
1887 };
1888
1889 static const struct qcom_icc_desc msm8996_bimc = {
1890 .type = QCOM_ICC_BIMC,
1891 .nodes = bimc_nodes,
1892 .num_nodes = ARRAY_SIZE(bimc_nodes),
1893 .bus_clk_desc = &bimc_clk,
1894 .regmap_cfg = &msm8996_bimc_regmap_config,
1895 .ab_coeff = 154,
1896 };
1897
1898 static struct qcom_icc_node * const cnoc_nodes[] = {
1899 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1900 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1901 [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc,
1902 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1903 [SLAVE_TCSR] = &slv_tcsr,
1904 [SLAVE_TLMM] = &slv_tlmm,
1905 [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg,
1906 [SLAVE_MPM] = &slv_mpm,
1907 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1908 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1909 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1910 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1911 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1912 [SLAVE_PRNG] = &slv_prng,
1913 [SLAVE_DCC_CFG] = &slv_dcc_cfg,
1914 [SLAVE_RBCPR_MX] = &slv_rbcpr_mx,
1915 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1916 [SLAVE_RBCPR_CX] = &slv_rbcpr_cx,
1917 [SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg,
1918 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1919 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1920 [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
1921 [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
1922 [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg,
1923 [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg,
1924 [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg,
1925 [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg,
1926 [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy,
1927 [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg,
1928 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1929 [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg,
1930 [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg,
1931 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1932 [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg,
1933 [SLAVE_SSC_CFG] = &slv_ssc_cfg,
1934 [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg,
1935 [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg,
1936 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1937 [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg,
1938 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg
1939 };
1940
1941 static const struct regmap_config msm8996_cnoc_regmap_config = {
1942 .reg_bits = 32,
1943 .reg_stride = 4,
1944 .val_bits = 32,
1945 .max_register = 0x1000,
1946 .fast_io = true
1947 };
1948
1949 static const struct qcom_icc_desc msm8996_cnoc = {
1950 .type = QCOM_ICC_NOC,
1951 .nodes = cnoc_nodes,
1952 .num_nodes = ARRAY_SIZE(cnoc_nodes),
1953 .bus_clk_desc = &bus_2_clk,
1954 .regmap_cfg = &msm8996_cnoc_regmap_config
1955 };
1956
1957 static struct qcom_icc_node * const mnoc_nodes[] = {
1958 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1959 [MASTER_CPP] = &mas_cpp,
1960 [MASTER_JPEG] = &mas_jpeg,
1961 [MASTER_MDP_PORT0] = &mas_mdp_p0,
1962 [MASTER_MDP_PORT1] = &mas_mdp_p1,
1963 [MASTER_ROTATOR] = &mas_rotator,
1964 [MASTER_VIDEO_P0] = &mas_venus,
1965 [MASTER_VFE] = &mas_vfe,
1966 [MASTER_SNOC_VMEM] = &mas_snoc_vmem,
1967 [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem,
1968 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1969 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1970 [SLAVE_VMEM] = &slv_vmem,
1971 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
1972 [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg,
1973 [SLAVE_CPR_CFG] = &slv_cpr_cfg,
1974 [SLAVE_MISC_CFG] = &slv_misc_cfg,
1975 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1976 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1977 [SLAVE_VMEM_CFG] = &slv_vmem_cfg,
1978 [SLAVE_DSA_CFG] = &slv_dsa_cfg,
1979 [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg,
1980 [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg,
1981 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1982 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1983 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1984 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1985 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1986 [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg,
1987 [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg,
1988 [SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg,
1989 [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg,
1990 [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg,
1991 [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg,
1992 [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg
1993 };
1994
1995 static const struct regmap_config msm8996_mnoc_regmap_config = {
1996 .reg_bits = 32,
1997 .reg_stride = 4,
1998 .val_bits = 32,
1999 .max_register = 0x1c000,
2000 .fast_io = true
2001 };
2002
2003 static const struct qcom_icc_desc msm8996_mnoc = {
2004 .type = QCOM_ICC_NOC,
2005 .nodes = mnoc_nodes,
2006 .num_nodes = ARRAY_SIZE(mnoc_nodes),
2007 .bus_clk_desc = &mmaxi_0_clk,
2008 .intf_clocks = mm_intf_clocks,
2009 .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
2010 .regmap_cfg = &msm8996_mnoc_regmap_config,
2011 .ab_coeff = 154,
2012 };
2013
2014 static struct qcom_icc_node * const pnoc_nodes[] = {
2015 [MASTER_SNOC_PNOC] = &mas_snoc_pnoc,
2016 [MASTER_SDCC_1] = &mas_sdcc_1,
2017 [MASTER_SDCC_2] = &mas_sdcc_2,
2018 [MASTER_SDCC_4] = &mas_sdcc_4,
2019 [MASTER_USB_HS] = &mas_usb_hs,
2020 [MASTER_BLSP_1] = &mas_blsp_1,
2021 [MASTER_BLSP_2] = &mas_blsp_2,
2022 [MASTER_TSIF] = &mas_tsif,
2023 [SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc,
2024 [SLAVE_USB_HS] = &slv_usb_hs,
2025 [SLAVE_SDCC_2] = &slv_sdcc_2,
2026 [SLAVE_SDCC_4] = &slv_sdcc_4,
2027 [SLAVE_TSIF] = &slv_tsif,
2028 [SLAVE_BLSP_2] = &slv_blsp_2,
2029 [SLAVE_SDCC_1] = &slv_sdcc_1,
2030 [SLAVE_BLSP_1] = &slv_blsp_1,
2031 [SLAVE_PDM] = &slv_pdm,
2032 [SLAVE_AHB2PHY] = &slv_ahb2phy
2033 };
2034
2035 static const struct regmap_config msm8996_pnoc_regmap_config = {
2036 .reg_bits = 32,
2037 .reg_stride = 4,
2038 .val_bits = 32,
2039 .max_register = 0x3000,
2040 .fast_io = true
2041 };
2042
2043 static const struct qcom_icc_desc msm8996_pnoc = {
2044 .type = QCOM_ICC_NOC,
2045 .nodes = pnoc_nodes,
2046 .num_nodes = ARRAY_SIZE(pnoc_nodes),
2047 .bus_clk_desc = &bus_0_clk,
2048 .regmap_cfg = &msm8996_pnoc_regmap_config
2049 };
2050
2051 static struct qcom_icc_node * const snoc_nodes[] = {
2052 [MASTER_HMSS] = &mas_hmss,
2053 [MASTER_QDSS_BAM] = &mas_qdss_bam,
2054 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
2055 [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0,
2056 [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1,
2057 [MASTER_A0NOC_SNOC] = &mas_a0noc_snoc,
2058 [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc,
2059 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
2060 [MASTER_QDSS_ETR] = &mas_qdss_etr,
2061 [SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc,
2062 [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc,
2063 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
2064 [SLAVE_HMSS] = &slv_hmss,
2065 [SLAVE_LPASS] = &slv_lpass,
2066 [SLAVE_USB3] = &slv_usb3,
2067 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
2068 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
2069 [SLAVE_IMEM] = &slv_imem,
2070 [SLAVE_PIMEM] = &slv_pimem,
2071 [SLAVE_SNOC_VMEM] = &slv_snoc_vmem,
2072 [SLAVE_SNOC_PNOC] = &slv_snoc_pnoc,
2073 [SLAVE_QDSS_STM] = &slv_qdss_stm,
2074 [SLAVE_PCIE_0] = &slv_pcie_0,
2075 [SLAVE_PCIE_1] = &slv_pcie_1,
2076 [SLAVE_PCIE_2] = &slv_pcie_2,
2077 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc
2078 };
2079
2080 static const struct regmap_config msm8996_snoc_regmap_config = {
2081 .reg_bits = 32,
2082 .reg_stride = 4,
2083 .val_bits = 32,
2084 .max_register = 0x20000,
2085 .fast_io = true
2086 };
2087
2088 static const struct qcom_icc_desc msm8996_snoc = {
2089 .type = QCOM_ICC_NOC,
2090 .nodes = snoc_nodes,
2091 .num_nodes = ARRAY_SIZE(snoc_nodes),
2092 .bus_clk_desc = &bus_1_clk,
2093 .regmap_cfg = &msm8996_snoc_regmap_config
2094 };
2095
2096 static const struct of_device_id qnoc_of_match[] = {
2097 { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc},
2098 { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc},
2099 { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc},
2100 { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc},
2101 { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc},
2102 { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc},
2103 { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc},
2104 { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc},
2105 { }
2106 };
2107 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2108
2109 static struct platform_driver qnoc_driver = {
2110 .probe = qnoc_probe,
2111 .remove_new = qnoc_remove,
2112 .driver = {
2113 .name = "qnoc-msm8996",
2114 .of_match_table = qnoc_of_match,
2115 .sync_state = icc_sync_state,
2116 }
2117 };
qnoc_driver_init(void)2118 static int __init qnoc_driver_init(void)
2119 {
2120 return platform_driver_register(&qnoc_driver);
2121 }
2122 core_initcall(qnoc_driver_init);
2123
qnoc_driver_exit(void)2124 static void __exit qnoc_driver_exit(void)
2125 {
2126 platform_driver_unregister(&qnoc_driver);
2127 }
2128 module_exit(qnoc_driver_exit);
2129
2130 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
2131 MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver");
2132 MODULE_LICENSE("GPL v2");
2133