1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #ifndef _MANA_H 5 #define _MANA_H 6 7 #include <linux/dim.h> 8 #include <net/xdp.h> 9 #include <net/net_shaper.h> 10 11 #include "gdma.h" 12 #include "hw_channel.h" 13 14 /* Microsoft Azure Network Adapter (MANA)'s definitions 15 * 16 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 17 * them are naturally aligned and hence don't need __packed. 18 */ 19 20 /* MANA protocol version */ 21 #define MANA_MAJOR_VERSION 0 22 #define MANA_MINOR_VERSION 1 23 #define MANA_MICRO_VERSION 1 24 25 typedef u64 mana_handle_t; 26 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 27 28 enum TRI_STATE { 29 TRI_STATE_UNKNOWN = -1, 30 TRI_STATE_FALSE = 0, 31 TRI_STATE_TRUE = 1 32 }; 33 34 /* MANA ethtool private flag bit positions */ 35 enum mana_priv_flag_bits { 36 MANA_PRIV_FLAG_USE_FULL_PAGE_RXBUF = 0, 37 MANA_PRIV_FLAG_MAX, 38 }; 39 40 /* Number of entries for hardware indirection table must be in power of 2 */ 41 #define MANA_INDIRECT_TABLE_MAX_SIZE 512 42 #define MANA_INDIRECT_TABLE_DEF_SIZE 64 43 44 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 45 #define MANA_HASH_KEY_SIZE 40 46 47 #define COMP_ENTRY_SIZE 64 48 49 /* This Max value for RX buffers is derived from __alloc_page()'s max page 50 * allocation calculation. It allows maximum 2^(MAX_ORDER -1) pages. RX buffer 51 * size beyond this value gets rejected by __alloc_page() call. 52 */ 53 #define MAX_RX_BUFFERS_PER_QUEUE 8192 54 #define DEF_RX_BUFFERS_PER_QUEUE 1024 55 #define MIN_RX_BUFFERS_PER_QUEUE 128 56 57 /* This max value for TX buffers is derived as the maximum allocatable 58 * pages supported on host per guest through testing. TX buffer size beyond 59 * this value is rejected by the hardware. 60 */ 61 #define MAX_TX_BUFFERS_PER_QUEUE 16384 62 #define DEF_TX_BUFFERS_PER_QUEUE 256 63 #define MIN_TX_BUFFERS_PER_QUEUE 128 64 65 #define EQ_SIZE (8 * MANA_PAGE_SIZE) 66 67 #define LOG2_EQ_THROTTLE 3 68 69 #define MAX_PORTS_IN_MANA_DEV 256 70 71 /* Maximum number of PPIs per coalesced CQE */ 72 #define MANA_RXCOMP_OOB_NUM_PPI 4 73 74 /* 8-pkt mode packs up to 2 packets per PPI entry */ 75 #define MANA_CQE_COAL_PKTS_8 8 76 77 /* Default/max interrupt moderation settings */ 78 #define MANA_INTR_MODR_USEC_DEF 0 79 #define MANA_INTR_MODR_COMP_DEF 0 80 81 #define MANA_ADAPTIVE_RX_DEF true 82 #define MANA_ADAPTIVE_TX_DEF true 83 84 /* DIM doorbell value field layout */ 85 #define MANA_INTR_MODR_USEC_MAX GENMASK(9, 0) 86 #define MANA_INTR_MODR_USEC_VLD BIT(15) 87 #define MANA_INTR_MODR_COMP_MAX GENMASK(7, 0) 88 #define MANA_INTR_MODR_COMP_MASK GENMASK(23, 16) 89 90 /* Update this count whenever the respective structures are changed */ 91 #define MANA_STATS_RX_COUNT (6 + MANA_CQE_COAL_PKTS_8 - 1) 92 #define MANA_STATS_TX_COUNT 11 93 94 #define MANA_RX_FRAG_ALIGNMENT 64 95 96 struct mana_stats_rx { 97 u64 packets; 98 u64 bytes; 99 u64 xdp_drop; 100 u64 xdp_tx; 101 u64 xdp_redirect; 102 u64 pkt_len0_err; 103 u64 coalesced_cqe[MANA_CQE_COAL_PKTS_8 - 1]; 104 struct u64_stats_sync syncp; 105 }; 106 107 struct mana_stats_tx { 108 u64 packets; 109 u64 bytes; 110 u64 xdp_xmit; 111 u64 tso_packets; 112 u64 tso_bytes; 113 u64 tso_inner_packets; 114 u64 tso_inner_bytes; 115 u64 short_pkt_fmt; 116 u64 long_pkt_fmt; 117 u64 csum_partial; 118 u64 mana_map_err; 119 struct u64_stats_sync syncp; 120 }; 121 122 struct mana_txq { 123 struct gdma_queue *gdma_sq; 124 125 union { 126 u32 gdma_txq_id; 127 struct { 128 u32 reserved1 : 10; 129 u32 vsq_frame : 14; 130 u32 reserved2 : 8; 131 }; 132 }; 133 134 u16 vp_offset; 135 136 struct net_device *ndev; 137 138 /* The SKBs are sent to the HW and we are waiting for the CQEs. */ 139 struct sk_buff_head pending_skbs; 140 struct netdev_queue *net_txq; 141 142 atomic_t pending_sends; 143 144 bool napi_initialized; 145 146 struct mana_stats_tx stats; 147 }; 148 149 /* skb data and frags dma mappings */ 150 struct mana_skb_head { 151 /* GSO pkts may have 2 SGEs for the linear part*/ 152 dma_addr_t dma_handle[MAX_SKB_FRAGS + 2]; 153 154 u32 size[MAX_SKB_FRAGS + 2]; 155 }; 156 157 #define MANA_HEADROOM sizeof(struct mana_skb_head) 158 159 enum mana_tx_pkt_format { 160 MANA_SHORT_PKT_FMT = 0, 161 MANA_LONG_PKT_FMT = 1, 162 }; 163 164 struct mana_tx_short_oob { 165 u32 pkt_fmt : 2; 166 u32 is_outer_ipv4 : 1; 167 u32 is_outer_ipv6 : 1; 168 u32 comp_iphdr_csum : 1; 169 u32 comp_tcp_csum : 1; 170 u32 comp_udp_csum : 1; 171 u32 supress_txcqe_gen : 1; 172 u32 vcq_num : 24; 173 174 u32 trans_off : 10; /* Transport header offset */ 175 u32 vsq_frame : 14; 176 u32 short_vp_offset : 8; 177 }; /* HW DATA */ 178 179 struct mana_tx_long_oob { 180 u32 is_encap : 1; 181 u32 inner_is_ipv6 : 1; 182 u32 inner_tcp_opt : 1; 183 u32 inject_vlan_pri_tag : 1; 184 u32 reserved1 : 12; 185 u32 pcp : 3; /* 802.1Q */ 186 u32 dei : 1; /* 802.1Q */ 187 u32 vlan_id : 12; /* 802.1Q */ 188 189 u32 inner_frame_offset : 10; 190 u32 inner_ip_rel_offset : 6; 191 u32 long_vp_offset : 12; 192 u32 reserved2 : 4; 193 194 u32 reserved3; 195 u32 reserved4; 196 }; /* HW DATA */ 197 198 struct mana_tx_oob { 199 struct mana_tx_short_oob s_oob; 200 struct mana_tx_long_oob l_oob; 201 }; /* HW DATA */ 202 203 enum mana_cq_type { 204 MANA_CQ_TYPE_RX, 205 MANA_CQ_TYPE_TX, 206 }; 207 208 enum mana_cqe_type { 209 CQE_INVALID = 0, 210 CQE_RX_OKAY = 1, 211 CQE_RX_COALESCED_4 = 2, 212 CQE_RX_OBJECT_FENCE = 3, 213 CQE_RX_TRUNCATED = 4, 214 CQE_RX_COALESCED_8 = 7, 215 216 CQE_TX_OKAY = 32, 217 CQE_TX_SA_DROP = 33, 218 CQE_TX_MTU_DROP = 34, 219 CQE_TX_INVALID_OOB = 35, 220 CQE_TX_INVALID_ETH_TYPE = 36, 221 CQE_TX_HDR_PROCESSING_ERROR = 37, 222 CQE_TX_VF_DISABLED = 38, 223 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 224 CQE_TX_VPORT_DISABLED = 40, 225 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 226 }; 227 228 #define MANA_CQE_COMPLETION 1 229 230 struct mana_cqe_header { 231 u32 cqe_type : 6; 232 u32 client_type : 2; 233 u32 vendor_err : 24; 234 }; /* HW DATA */ 235 236 /* NDIS HASH Types */ 237 #define NDIS_HASH_IPV4 BIT(0) 238 #define NDIS_HASH_TCP_IPV4 BIT(1) 239 #define NDIS_HASH_UDP_IPV4 BIT(2) 240 #define NDIS_HASH_IPV6 BIT(3) 241 #define NDIS_HASH_TCP_IPV6 BIT(4) 242 #define NDIS_HASH_UDP_IPV6 BIT(5) 243 #define NDIS_HASH_IPV6_EX BIT(6) 244 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 245 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 246 247 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 248 #define MANA_HASH_L4 \ 249 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 250 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 251 #define MANA_HASH_ENABLE_SUPPORTED \ 252 (NDIS_HASH_IPV4 | NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | \ 253 NDIS_HASH_IPV6 | NDIS_HASH_TCP_IPV6 | NDIS_HASH_UDP_IPV6) 254 255 /* Read PPI in two different layouts based on cqe_type */ 256 union mana_rxcomp_perpkt_info { 257 struct { 258 u32 pkt_len : 16; 259 u32 reserved1 : 16; 260 u32 reserved2; 261 u32 pkt_hash; 262 }; 263 264 /* Up to two pkts per PPI entry */ 265 struct { 266 u32 pkt_hash0; 267 u16 pkt_len0; 268 u16 pkt_len1; 269 u32 pkt_hash1; 270 }; 271 }; /* HW DATA */ 272 273 /* Receive completion OOB */ 274 struct mana_rxcomp_oob { 275 struct mana_cqe_header cqe_hdr; 276 277 u32 rx_vlan_id : 12; 278 u32 rx_vlantag_present : 1; 279 u32 rx_outer_iphdr_csum_succeed : 1; 280 u32 rx_outer_iphdr_csum_fail : 1; 281 u32 reserved1 : 1; 282 u32 rx_hashtype : 9; 283 u32 rx_iphdr_csum_succeed : 1; 284 u32 rx_iphdr_csum_fail : 1; 285 u32 rx_tcp_csum_succeed : 1; 286 u32 rx_tcp_csum_fail : 1; 287 u32 rx_udp_csum_succeed : 1; 288 u32 rx_udp_csum_fail : 1; 289 u32 reserved2 : 1; 290 291 union mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 292 293 u32 rx_wqe_offset; 294 }; /* HW DATA */ 295 296 struct mana_tx_comp_oob { 297 struct mana_cqe_header cqe_hdr; 298 299 u32 tx_data_offset; 300 301 u32 tx_sgl_offset : 5; 302 u32 tx_wqe_offset : 27; 303 304 u32 reserved[12]; 305 }; /* HW DATA */ 306 307 struct mana_rxq; 308 309 #define CQE_POLLING_BUFFER 512 310 311 struct mana_cq { 312 struct gdma_queue *gdma_cq; 313 314 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 315 u32 gdma_id; 316 317 /* Type of the CQ: TX or RX */ 318 enum mana_cq_type type; 319 320 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 321 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 322 */ 323 struct mana_rxq *rxq; 324 325 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 326 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 327 */ 328 struct mana_txq *txq; 329 330 /* Buffer which the CQ handler can copy the CQE's into. */ 331 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 332 333 /* NAPI data */ 334 struct napi_struct napi; 335 int work_done; 336 int work_done_since_doorbell; 337 int budget; 338 339 /* DIM - Dynamic Interrupt Moderation */ 340 struct dim dim; 341 u16 dim_event_ctr; 342 343 /* Cumulative TX completions fed to DIM. Updated and read only in 344 * NAPI context (mana_poll_tx_cq() / mana_update_tx_dim()), so they 345 * measure the hardware completion rate and need no u64_stats_sync. 346 */ 347 u64 tx_dim_pkts; 348 u64 tx_dim_bytes; 349 }; 350 351 struct mana_recv_buf_oob { 352 /* A valid GDMA work request representing the data buffer. */ 353 struct gdma_wqe_request wqe_req; 354 355 void *buf_va; 356 bool from_pool; /* allocated from a page pool */ 357 /* head page of the page_pool fragment; valid only when 358 * from_pool && frag_count > 1. 359 */ 360 struct page *pp_page; 361 /* Fragment offset plus rxq->headroom, passed to 362 * page_pool_dma_sync_for_cpu(). 363 */ 364 u32 dma_sync_offset; 365 366 /* SGL of the buffer going to be sent as part of the work request. */ 367 u32 num_sge; 368 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 369 370 /* Required to store the result of mana_gd_post_work_request. 371 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 372 * work queue when the WQE is consumed. 373 */ 374 struct gdma_posted_wqe_info wqe_inf; 375 }; 376 377 #define MANA_RXBUF_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) \ 378 + ETH_HLEN) 379 380 #define MANA_XDP_MTU_MAX (PAGE_SIZE - MANA_RXBUF_PAD - XDP_PACKET_HEADROOM) 381 382 struct mana_rxq { 383 struct gdma_queue *gdma_rq; 384 /* Cache the gdma receive queue id */ 385 u32 gdma_id; 386 387 /* Index of RQ in the vPort, not gdma receive queue id */ 388 u32 rxq_idx; 389 390 u32 datasize; 391 u32 alloc_size; 392 u32 headroom; 393 u32 frag_count; 394 395 mana_handle_t rxobj; 396 397 struct mana_cq rx_cq; 398 399 struct completion fence_event; 400 401 struct net_device *ndev; 402 403 /* Total number of receive buffers to be allocated */ 404 u32 num_rx_buf; 405 406 u32 buf_index; 407 408 struct mana_stats_rx stats; 409 410 struct bpf_prog __rcu *bpf_prog; 411 struct xdp_rxq_info xdp_rxq; 412 void *xdp_save_va; /* for reusing */ 413 bool xdp_flush; 414 int xdp_rc; /* XDP redirect return code */ 415 416 struct page_pool *page_pool; 417 struct dentry *mana_rx_debugfs; 418 419 /* MUST BE THE LAST MEMBER: 420 * Each receive buffer has an associated mana_recv_buf_oob. 421 */ 422 struct mana_recv_buf_oob rx_oobs[] __counted_by(num_rx_buf); 423 }; 424 425 struct mana_tx_qp { 426 struct mana_txq txq; 427 428 struct mana_cq tx_cq; 429 430 mana_handle_t tx_object; 431 432 struct dentry *mana_tx_debugfs; 433 }; 434 435 struct mana_ethtool_stats { 436 u64 stop_queue; 437 u64 wake_queue; 438 u64 tx_cqe_err; 439 u64 tx_cqe_unknown_type; 440 u64 tx_linear_pkt_cnt; 441 u64 rx_cqe_unknown_type; 442 }; 443 444 struct mana_ethtool_hc_stats { 445 u64 hc_rx_discards_no_wqe; 446 u64 hc_rx_err_vport_disabled; 447 u64 hc_rx_bytes; 448 u64 hc_rx_ucast_pkts; 449 u64 hc_rx_ucast_bytes; 450 u64 hc_rx_bcast_pkts; 451 u64 hc_rx_bcast_bytes; 452 u64 hc_rx_mcast_pkts; 453 u64 hc_rx_mcast_bytes; 454 u64 hc_tx_err_gf_disabled; 455 u64 hc_tx_err_vport_disabled; 456 u64 hc_tx_err_inval_vportoffset_pkt; 457 u64 hc_tx_err_vlan_enforcement; 458 u64 hc_tx_err_eth_type_enforcement; 459 u64 hc_tx_err_sa_enforcement; 460 u64 hc_tx_err_sqpdid_enforcement; 461 u64 hc_tx_err_cqpdid_enforcement; 462 u64 hc_tx_err_mtu_violation; 463 u64 hc_tx_err_inval_oob; 464 u64 hc_tx_bytes; 465 u64 hc_tx_ucast_pkts; 466 u64 hc_tx_ucast_bytes; 467 u64 hc_tx_bcast_pkts; 468 u64 hc_tx_bcast_bytes; 469 u64 hc_tx_mcast_pkts; 470 u64 hc_tx_mcast_bytes; 471 u64 hc_tx_err_gdma; 472 }; 473 474 struct mana_ethtool_phy_stats { 475 /* Drop Counters */ 476 u64 rx_pkt_drop_phy; 477 u64 tx_pkt_drop_phy; 478 479 /* Per TC traffic Counters */ 480 u64 rx_pkt_tc0_phy; 481 u64 tx_pkt_tc0_phy; 482 u64 rx_pkt_tc1_phy; 483 u64 tx_pkt_tc1_phy; 484 u64 rx_pkt_tc2_phy; 485 u64 tx_pkt_tc2_phy; 486 u64 rx_pkt_tc3_phy; 487 u64 tx_pkt_tc3_phy; 488 u64 rx_pkt_tc4_phy; 489 u64 tx_pkt_tc4_phy; 490 u64 rx_pkt_tc5_phy; 491 u64 tx_pkt_tc5_phy; 492 u64 rx_pkt_tc6_phy; 493 u64 tx_pkt_tc6_phy; 494 u64 rx_pkt_tc7_phy; 495 u64 tx_pkt_tc7_phy; 496 497 u64 rx_byte_tc0_phy; 498 u64 tx_byte_tc0_phy; 499 u64 rx_byte_tc1_phy; 500 u64 tx_byte_tc1_phy; 501 u64 rx_byte_tc2_phy; 502 u64 tx_byte_tc2_phy; 503 u64 rx_byte_tc3_phy; 504 u64 tx_byte_tc3_phy; 505 u64 rx_byte_tc4_phy; 506 u64 tx_byte_tc4_phy; 507 u64 rx_byte_tc5_phy; 508 u64 tx_byte_tc5_phy; 509 u64 rx_byte_tc6_phy; 510 u64 tx_byte_tc6_phy; 511 u64 rx_byte_tc7_phy; 512 u64 tx_byte_tc7_phy; 513 514 /* Per TC pause Counters */ 515 u64 rx_pause_tc0_phy; 516 u64 tx_pause_tc0_phy; 517 u64 rx_pause_tc1_phy; 518 u64 tx_pause_tc1_phy; 519 u64 rx_pause_tc2_phy; 520 u64 tx_pause_tc2_phy; 521 u64 rx_pause_tc3_phy; 522 u64 tx_pause_tc3_phy; 523 u64 rx_pause_tc4_phy; 524 u64 tx_pause_tc4_phy; 525 u64 rx_pause_tc5_phy; 526 u64 tx_pause_tc5_phy; 527 u64 rx_pause_tc6_phy; 528 u64 tx_pause_tc6_phy; 529 u64 rx_pause_tc7_phy; 530 u64 tx_pause_tc7_phy; 531 }; 532 533 struct mana_context { 534 struct gdma_dev *gdma_dev; 535 536 u16 num_ports; 537 u8 bm_hostmode; 538 539 struct mana_ethtool_hc_stats hc_stats; 540 struct workqueue_struct *per_port_queue_reset_wq; 541 /* Workqueue for querying hardware stats */ 542 struct delayed_work gf_stats_work; 543 bool hwc_timeout_occurred; 544 545 struct net_device *ports[MAX_PORTS_IN_MANA_DEV]; 546 547 /* Link state change work */ 548 struct work_struct link_change_work; 549 u32 link_event; 550 }; 551 552 struct mana_port_context { 553 struct mana_context *ac; 554 struct net_device *ndev; 555 struct work_struct queue_reset_work; 556 557 /* Debug knob to log TX timeout but skip recovery reset */ 558 bool tx_timeout_skip_reset; 559 560 u8 mac_addr[ETH_ALEN]; 561 562 struct mana_eq *eqs; 563 struct dentry *mana_eqs_debugfs; 564 565 enum TRI_STATE rss_state; 566 567 mana_handle_t default_rxobj; 568 bool tx_shortform_allowed; 569 u16 tx_vp_offset; 570 571 struct mana_tx_qp **tx_qp; 572 573 /* Indirection Table for RX & TX. The values are queue indexes */ 574 u32 *indir_table; 575 u32 indir_table_sz; 576 577 /* Indirection table containing RxObject Handles */ 578 mana_handle_t *rxobj_table; 579 580 /* Hash key used by the NIC */ 581 u8 hashkey[MANA_HASH_KEY_SIZE]; 582 583 /* This points to an array of num_queues of RQ pointers. */ 584 struct mana_rxq **rxqs; 585 586 /* pre-allocated rx buffer array */ 587 void **rxbufs_pre; 588 dma_addr_t *das_pre; 589 int rxbpre_total; 590 u32 rxbpre_datasize; 591 u32 rxbpre_alloc_size; 592 u32 rxbpre_headroom; 593 u32 rxbpre_frag_count; 594 595 u32 priv_flags; 596 597 struct bpf_prog *bpf_prog; 598 599 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 600 unsigned int max_queues; 601 unsigned int num_queues; 602 603 unsigned int rx_queue_size; 604 unsigned int tx_queue_size; 605 606 mana_handle_t port_handle; 607 mana_handle_t pf_filter_handle; 608 609 /* Mutex for sharing access to vport_use_count */ 610 struct mutex vport_mutex; 611 int vport_use_count; 612 613 /* Set by mana_set_channels() under vport_mutex to block RDMA 614 * from grabbing the vport during the detach/attach window. 615 * Checked by mana_cfg_vport() when called from the RDMA path. 616 */ 617 bool channel_changing; 618 619 /* Net shaper handle*/ 620 struct net_shaper_handle handle; 621 622 u16 port_idx; 623 /* Currently configured speed (mbps) */ 624 u32 speed; 625 /* Maximum speed supported by the SKU (mbps) */ 626 u32 max_speed; 627 /* 1 = not queried, 0 = cached success, negative = permanent error. 628 * Protected by the netdev instance lock. 629 */ 630 int link_cfg_error; 631 632 bool port_is_up; 633 bool port_st_save; /* Saved port state */ 634 635 u8 cqe_coalescing_enable; 636 u8 cqe8_coalescing_enable; 637 u32 cqe_coalescing_timeout_ns; 638 639 /* Interrupt moderation settings */ 640 u16 intr_modr_rx_usec; 641 u16 intr_modr_rx_comp; 642 u16 intr_modr_tx_usec; 643 u16 intr_modr_tx_comp; 644 645 bool rx_dim_enabled; 646 bool tx_dim_enabled; 647 648 struct mana_ethtool_stats eth_stats; 649 650 struct mana_ethtool_phy_stats phy_stats; 651 652 /* Debugfs */ 653 struct dentry *mana_port_debugfs; 654 655 /* Cached vport/steering config for debugfs */ 656 u32 vport_max_sq; 657 u32 vport_max_rq; 658 u32 steer_rx; 659 u32 steer_rss; 660 bool steer_update_tab; 661 u32 steer_cqe_coalescing; 662 }; 663 664 netdev_tx_t mana_start_xmit(struct sk_buff *skb, struct net_device *ndev); 665 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 666 bool update_hash, bool update_tab); 667 int mana_disable_vport_rx(struct mana_port_context *apc); 668 669 int mana_alloc_queues(struct net_device *ndev); 670 int mana_attach(struct net_device *ndev); 671 int mana_detach(struct net_device *ndev, bool from_close); 672 673 void mana_dim_change(struct mana_cq *cq, bool enable); 674 675 int mana_probe(struct gdma_dev *gd, bool resuming); 676 void mana_remove(struct gdma_dev *gd, bool suspending); 677 678 int mana_rdma_probe(struct gdma_dev *gd); 679 void mana_rdma_remove(struct gdma_dev *gd); 680 681 void mana_xdp_tx(struct sk_buff *skb, struct net_device *ndev); 682 int mana_xdp_xmit(struct net_device *ndev, int n, struct xdp_frame **frames, 683 u32 flags); 684 u32 mana_run_xdp(struct net_device *ndev, struct mana_rxq *rxq, 685 struct xdp_buff *xdp, void *buf_va, uint pkt_len); 686 struct bpf_prog *mana_xdp_get(struct mana_port_context *apc); 687 void mana_chn_setxdp(struct mana_port_context *apc, struct bpf_prog *prog); 688 int mana_bpf(struct net_device *ndev, struct netdev_bpf *bpf); 689 int mana_query_gf_stats(struct mana_context *ac); 690 int mana_query_link_cfg(struct mana_port_context *apc); 691 int mana_set_bw_clamp(struct mana_port_context *apc, u32 speed, 692 int enable_clamping); 693 void mana_query_phy_stats(struct mana_port_context *apc); 694 int mana_pre_alloc_rxbufs(struct mana_port_context *apc, int mtu, int num_queues); 695 void mana_pre_dealloc_rxbufs(struct mana_port_context *apc); 696 void mana_unmap_skb(struct sk_buff *skb, struct mana_port_context *apc); 697 698 extern const struct ethtool_ops mana_ethtool_ops; 699 extern struct dentry *mana_debugfs_root; 700 701 /* A CQ can be created not associated with any EQ */ 702 #define GDMA_CQ_NO_EQ 0xffff 703 704 struct mana_obj_spec { 705 u32 queue_index; 706 u64 gdma_region; 707 u32 queue_size; 708 u32 attached_eq; 709 u32 modr_ctx_id; 710 u8 req_cq_moderation; 711 u16 cq_moderation_comp; 712 u16 cq_moderation_usec; 713 }; 714 715 enum mana_command_code { 716 MANA_QUERY_DEV_CONFIG = 0x20001, 717 MANA_QUERY_GF_STAT = 0x20002, 718 MANA_CONFIG_VPORT_TX = 0x20003, 719 MANA_CREATE_WQ_OBJ = 0x20004, 720 MANA_DESTROY_WQ_OBJ = 0x20005, 721 MANA_FENCE_RQ = 0x20006, 722 MANA_CONFIG_VPORT_RX = 0x20007, 723 MANA_QUERY_VPORT_CONFIG = 0x20008, 724 MANA_QUERY_LINK_CONFIG = 0x2000A, 725 MANA_SET_BW_CLAMP = 0x2000B, 726 MANA_QUERY_PHY_STAT = 0x2000c, 727 728 /* Privileged commands for the PF mode */ 729 MANA_REGISTER_FILTER = 0x28000, 730 MANA_DEREGISTER_FILTER = 0x28001, 731 MANA_REGISTER_HW_PORT = 0x28003, 732 MANA_DEREGISTER_HW_PORT = 0x28004, 733 }; 734 735 /* Query Link Configuration*/ 736 struct mana_query_link_config_req { 737 struct gdma_req_hdr hdr; 738 mana_handle_t vport; 739 }; /* HW DATA */ 740 741 struct mana_query_link_config_resp { 742 struct gdma_resp_hdr hdr; 743 u32 qos_speed_mbps; 744 u8 qos_unconfigured; 745 u8 reserved1[3]; 746 u32 link_speed_mbps; 747 u8 reserved2[4]; 748 }; /* HW DATA */ 749 750 /* Set Bandwidth Clamp*/ 751 struct mana_set_bw_clamp_req { 752 struct gdma_req_hdr hdr; 753 mana_handle_t vport; 754 enum TRI_STATE enable_clamping; 755 u32 link_speed_mbps; 756 }; /* HW DATA */ 757 758 struct mana_set_bw_clamp_resp { 759 struct gdma_resp_hdr hdr; 760 u8 qos_unconfigured; 761 u8 reserved[7]; 762 }; /* HW DATA */ 763 764 /* Query Device Configuration */ 765 struct mana_query_device_cfg_req { 766 struct gdma_req_hdr hdr; 767 768 /* MANA Nic Driver Capability flags */ 769 u64 mn_drv_cap_flags1; 770 u64 mn_drv_cap_flags2; 771 u64 mn_drv_cap_flags3; 772 u64 mn_drv_cap_flags4; 773 774 u32 proto_major_ver; 775 u32 proto_minor_ver; 776 u32 proto_micro_ver; 777 778 u32 reserved; 779 }; /* HW DATA */ 780 781 #define MANA_PF_FLAG_1_CQE_8_COALESCING_SUPPORTED BIT(5) 782 783 struct mana_query_device_cfg_resp { 784 struct gdma_resp_hdr hdr; 785 786 u64 pf_cap_flags1; 787 u64 pf_cap_flags2; 788 u64 pf_cap_flags3; 789 u64 pf_cap_flags4; 790 791 u16 max_num_vports; 792 u8 bm_hostmode; /* response v3: Bare Metal Host Mode */ 793 u8 reserved; 794 u32 max_num_eqs; 795 796 /* response v2: */ 797 u16 adapter_mtu; 798 u16 reserved2; 799 u32 reserved3; 800 }; /* HW DATA */ 801 802 /* Query vPort Configuration */ 803 struct mana_query_vport_cfg_req { 804 struct gdma_req_hdr hdr; 805 u32 vport_index; 806 }; /* HW DATA */ 807 808 struct mana_query_vport_cfg_resp { 809 struct gdma_resp_hdr hdr; 810 u32 max_num_sq; 811 u32 max_num_rq; 812 u32 num_indirection_ent; 813 u32 reserved1; 814 u8 mac_addr[6]; 815 u8 reserved2[2]; 816 mana_handle_t vport; 817 }; /* HW DATA */ 818 819 /* Configure vPort */ 820 struct mana_config_vport_req { 821 struct gdma_req_hdr hdr; 822 mana_handle_t vport; 823 u32 pdid; 824 u32 doorbell_pageid; 825 }; /* HW DATA */ 826 827 struct mana_config_vport_resp { 828 struct gdma_resp_hdr hdr; 829 u16 tx_vport_offset; 830 u8 short_form_allowed; 831 u8 reserved; 832 }; /* HW DATA */ 833 834 /* Create WQ Object */ 835 struct mana_create_wqobj_req { 836 struct gdma_req_hdr hdr; 837 mana_handle_t vport; 838 u32 wq_type; 839 u32 reserved; 840 u64 wq_gdma_region; 841 u64 cq_gdma_region; 842 u32 wq_size; 843 u32 cq_size; 844 u32 cq_moderation_ctx_id; 845 u32 cq_parent_qid; 846 847 /* V2 */ 848 u8 allow_rqwqe_chain; 849 850 /* V3 */ 851 u8 req_cq_moderation; 852 u16 cq_moderation_comp; 853 u16 cq_moderation_usec; 854 u8 reserved2[2]; 855 }; /* HW DATA */ 856 857 struct mana_create_wqobj_resp { 858 struct gdma_resp_hdr hdr; 859 u32 wq_id; 860 u32 cq_id; 861 mana_handle_t wq_obj; 862 863 /* V2 */ 864 u16 cq_moderation_comp; 865 u16 cq_moderation_usec; 866 u8 cq_moderation_enabled; 867 u8 reserved1[3]; 868 }; /* HW DATA */ 869 870 /* Destroy WQ Object */ 871 struct mana_destroy_wqobj_req { 872 struct gdma_req_hdr hdr; 873 u32 wq_type; 874 u32 reserved; 875 mana_handle_t wq_obj_handle; 876 }; /* HW DATA */ 877 878 struct mana_destroy_wqobj_resp { 879 struct gdma_resp_hdr hdr; 880 }; /* HW DATA */ 881 882 /* Fence RQ */ 883 struct mana_fence_rq_req { 884 struct gdma_req_hdr hdr; 885 mana_handle_t wq_obj_handle; 886 }; /* HW DATA */ 887 888 struct mana_fence_rq_resp { 889 struct gdma_resp_hdr hdr; 890 }; /* HW DATA */ 891 892 /* Query stats RQ */ 893 struct mana_query_gf_stat_req { 894 struct gdma_req_hdr hdr; 895 u64 req_stats; 896 }; /* HW DATA */ 897 898 struct mana_query_gf_stat_resp { 899 struct gdma_resp_hdr hdr; 900 u64 reported_stats; 901 /* rx errors/discards */ 902 u64 rx_discards_nowqe; 903 u64 rx_err_vport_disabled; 904 /* rx bytes/packets */ 905 u64 hc_rx_bytes; 906 u64 hc_rx_ucast_pkts; 907 u64 hc_rx_ucast_bytes; 908 u64 hc_rx_bcast_pkts; 909 u64 hc_rx_bcast_bytes; 910 u64 hc_rx_mcast_pkts; 911 u64 hc_rx_mcast_bytes; 912 /* tx errors */ 913 u64 tx_err_gf_disabled; 914 u64 tx_err_vport_disabled; 915 u64 tx_err_inval_vport_offset_pkt; 916 u64 tx_err_vlan_enforcement; 917 u64 tx_err_ethtype_enforcement; 918 u64 tx_err_SA_enforcement; 919 u64 tx_err_SQPDID_enforcement; 920 u64 tx_err_CQPDID_enforcement; 921 u64 tx_err_mtu_violation; 922 u64 tx_err_inval_oob; 923 /* tx bytes/packets */ 924 u64 hc_tx_bytes; 925 u64 hc_tx_ucast_pkts; 926 u64 hc_tx_ucast_bytes; 927 u64 hc_tx_bcast_pkts; 928 u64 hc_tx_bcast_bytes; 929 u64 hc_tx_mcast_pkts; 930 u64 hc_tx_mcast_bytes; 931 /* tx error */ 932 u64 tx_err_gdma; 933 }; /* HW DATA */ 934 935 /* Query phy stats */ 936 struct mana_query_phy_stat_req { 937 struct gdma_req_hdr hdr; 938 u64 req_stats; 939 }; /* HW DATA */ 940 941 struct mana_query_phy_stat_resp { 942 struct gdma_resp_hdr hdr; 943 u64 reported_stats; 944 945 /* Aggregate Drop Counters */ 946 u64 rx_pkt_drop_phy; 947 u64 tx_pkt_drop_phy; 948 949 /* Per TC(Traffic class) traffic Counters */ 950 u64 rx_pkt_tc0_phy; 951 u64 tx_pkt_tc0_phy; 952 u64 rx_pkt_tc1_phy; 953 u64 tx_pkt_tc1_phy; 954 u64 rx_pkt_tc2_phy; 955 u64 tx_pkt_tc2_phy; 956 u64 rx_pkt_tc3_phy; 957 u64 tx_pkt_tc3_phy; 958 u64 rx_pkt_tc4_phy; 959 u64 tx_pkt_tc4_phy; 960 u64 rx_pkt_tc5_phy; 961 u64 tx_pkt_tc5_phy; 962 u64 rx_pkt_tc6_phy; 963 u64 tx_pkt_tc6_phy; 964 u64 rx_pkt_tc7_phy; 965 u64 tx_pkt_tc7_phy; 966 967 u64 rx_byte_tc0_phy; 968 u64 tx_byte_tc0_phy; 969 u64 rx_byte_tc1_phy; 970 u64 tx_byte_tc1_phy; 971 u64 rx_byte_tc2_phy; 972 u64 tx_byte_tc2_phy; 973 u64 rx_byte_tc3_phy; 974 u64 tx_byte_tc3_phy; 975 u64 rx_byte_tc4_phy; 976 u64 tx_byte_tc4_phy; 977 u64 rx_byte_tc5_phy; 978 u64 tx_byte_tc5_phy; 979 u64 rx_byte_tc6_phy; 980 u64 tx_byte_tc6_phy; 981 u64 rx_byte_tc7_phy; 982 u64 tx_byte_tc7_phy; 983 984 /* Per TC(Traffic Class) pause Counters */ 985 u64 rx_pause_tc0_phy; 986 u64 tx_pause_tc0_phy; 987 u64 rx_pause_tc1_phy; 988 u64 tx_pause_tc1_phy; 989 u64 rx_pause_tc2_phy; 990 u64 tx_pause_tc2_phy; 991 u64 rx_pause_tc3_phy; 992 u64 tx_pause_tc3_phy; 993 u64 rx_pause_tc4_phy; 994 u64 tx_pause_tc4_phy; 995 u64 rx_pause_tc5_phy; 996 u64 tx_pause_tc5_phy; 997 u64 rx_pause_tc6_phy; 998 u64 tx_pause_tc6_phy; 999 u64 rx_pause_tc7_phy; 1000 u64 tx_pause_tc7_phy; 1001 }; /* HW DATA */ 1002 1003 /* Configure vPort Rx Steering */ 1004 struct mana_cfg_rx_steer_req_v2 { 1005 struct gdma_req_hdr hdr; 1006 mana_handle_t vport; 1007 u16 num_indir_entries; 1008 u16 indir_tab_offset; 1009 u32 rx_enable; 1010 u32 rss_enable; 1011 u8 update_default_rxobj; 1012 u8 update_hashkey; 1013 u8 update_indir_tab; 1014 u8 reserved; 1015 mana_handle_t default_rxobj; 1016 u8 hashkey[MANA_HASH_KEY_SIZE]; 1017 u8 cqe_coalescing_enable; 1018 u8 reserved2[3]; 1019 u16 rss_hash_types; 1020 u8 cqe8_coalescing_enable; /* v5 message */ 1021 u8 reserved3; 1022 mana_handle_t indir_tab[] __counted_by(num_indir_entries); 1023 }; /* HW DATA */ 1024 1025 struct mana_cfg_rx_steer_resp { 1026 struct gdma_resp_hdr hdr; 1027 1028 /* V2 */ 1029 u32 cqe_coalescing_timeout_ns; 1030 u32 reserved1; 1031 }; /* HW DATA */ 1032 1033 /* Register HW vPort */ 1034 struct mana_register_hw_vport_req { 1035 struct gdma_req_hdr hdr; 1036 u16 attached_gfid; 1037 u8 is_pf_default_vport; 1038 u8 reserved1; 1039 u8 allow_all_ether_types; 1040 u8 reserved2; 1041 u8 reserved3; 1042 u8 reserved4; 1043 }; /* HW DATA */ 1044 1045 struct mana_register_hw_vport_resp { 1046 struct gdma_resp_hdr hdr; 1047 mana_handle_t hw_vport_handle; 1048 }; /* HW DATA */ 1049 1050 /* Deregister HW vPort */ 1051 struct mana_deregister_hw_vport_req { 1052 struct gdma_req_hdr hdr; 1053 mana_handle_t hw_vport_handle; 1054 }; /* HW DATA */ 1055 1056 struct mana_deregister_hw_vport_resp { 1057 struct gdma_resp_hdr hdr; 1058 }; /* HW DATA */ 1059 1060 /* Register filter */ 1061 struct mana_register_filter_req { 1062 struct gdma_req_hdr hdr; 1063 mana_handle_t vport; 1064 u8 mac_addr[6]; 1065 u8 reserved1; 1066 u8 reserved2; 1067 u8 reserved3; 1068 u8 reserved4; 1069 u16 reserved5; 1070 u32 reserved6; 1071 u32 reserved7; 1072 u32 reserved8; 1073 }; /* HW DATA */ 1074 1075 struct mana_register_filter_resp { 1076 struct gdma_resp_hdr hdr; 1077 mana_handle_t filter_handle; 1078 }; /* HW DATA */ 1079 1080 /* Deregister filter */ 1081 struct mana_deregister_filter_req { 1082 struct gdma_req_hdr hdr; 1083 mana_handle_t filter_handle; 1084 }; /* HW DATA */ 1085 1086 struct mana_deregister_filter_resp { 1087 struct gdma_resp_hdr hdr; 1088 }; /* HW DATA */ 1089 1090 /* Requested GF stats Flags */ 1091 /* Rx discards/Errors */ 1092 #define STATISTICS_FLAGS_RX_DISCARDS_NO_WQE 0x0000000000000001 1093 #define STATISTICS_FLAGS_RX_ERRORS_VPORT_DISABLED 0x0000000000000002 1094 /* Rx bytes/pkts */ 1095 #define STATISTICS_FLAGS_HC_RX_BYTES 0x0000000000000004 1096 #define STATISTICS_FLAGS_HC_RX_UCAST_PACKETS 0x0000000000000008 1097 #define STATISTICS_FLAGS_HC_RX_UCAST_BYTES 0x0000000000000010 1098 #define STATISTICS_FLAGS_HC_RX_MCAST_PACKETS 0x0000000000000020 1099 #define STATISTICS_FLAGS_HC_RX_MCAST_BYTES 0x0000000000000040 1100 #define STATISTICS_FLAGS_HC_RX_BCAST_PACKETS 0x0000000000000080 1101 #define STATISTICS_FLAGS_HC_RX_BCAST_BYTES 0x0000000000000100 1102 /* Tx errors */ 1103 #define STATISTICS_FLAGS_TX_ERRORS_GF_DISABLED 0x0000000000000200 1104 #define STATISTICS_FLAGS_TX_ERRORS_VPORT_DISABLED 0x0000000000000400 1105 #define STATISTICS_FLAGS_TX_ERRORS_INVAL_VPORT_OFFSET_PACKETS \ 1106 0x0000000000000800 1107 #define STATISTICS_FLAGS_TX_ERRORS_VLAN_ENFORCEMENT 0x0000000000001000 1108 #define STATISTICS_FLAGS_TX_ERRORS_ETH_TYPE_ENFORCEMENT \ 1109 0x0000000000002000 1110 #define STATISTICS_FLAGS_TX_ERRORS_SA_ENFORCEMENT 0x0000000000004000 1111 #define STATISTICS_FLAGS_TX_ERRORS_SQPDID_ENFORCEMENT 0x0000000000008000 1112 #define STATISTICS_FLAGS_TX_ERRORS_CQPDID_ENFORCEMENT 0x0000000000010000 1113 #define STATISTICS_FLAGS_TX_ERRORS_MTU_VIOLATION 0x0000000000020000 1114 #define STATISTICS_FLAGS_TX_ERRORS_INVALID_OOB 0x0000000000040000 1115 /* Tx bytes/pkts */ 1116 #define STATISTICS_FLAGS_HC_TX_BYTES 0x0000000000080000 1117 #define STATISTICS_FLAGS_HC_TX_UCAST_PACKETS 0x0000000000100000 1118 #define STATISTICS_FLAGS_HC_TX_UCAST_BYTES 0x0000000000200000 1119 #define STATISTICS_FLAGS_HC_TX_MCAST_PACKETS 0x0000000000400000 1120 #define STATISTICS_FLAGS_HC_TX_MCAST_BYTES 0x0000000000800000 1121 #define STATISTICS_FLAGS_HC_TX_BCAST_PACKETS 0x0000000001000000 1122 #define STATISTICS_FLAGS_HC_TX_BCAST_BYTES 0x0000000002000000 1123 /* Tx error */ 1124 #define STATISTICS_FLAGS_TX_ERRORS_GDMA_ERROR 0x0000000004000000 1125 1126 #define MANA_MAX_NUM_QUEUES 64 1127 #define MANA_DEF_NUM_QUEUES 16 1128 1129 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 1130 1131 struct mana_tx_package { 1132 struct gdma_wqe_request wqe_req; 1133 struct gdma_sge sgl_array[5]; 1134 struct gdma_sge *sgl_ptr; 1135 1136 struct mana_tx_oob tx_oob; 1137 1138 struct gdma_posted_wqe_info wqe_info; 1139 }; 1140 1141 int mana_create_wq_obj(struct mana_port_context *apc, 1142 mana_handle_t vport, 1143 u32 wq_type, struct mana_obj_spec *wq_spec, 1144 struct mana_obj_spec *cq_spec, 1145 mana_handle_t *wq_obj); 1146 1147 void mana_destroy_wq_obj(struct mana_port_context *apc, u32 wq_type, 1148 mana_handle_t wq_obj); 1149 1150 int mana_cfg_vport(struct mana_port_context *apc, u32 protection_dom_id, 1151 u32 doorbell_pg_id, bool check_channel_changing); 1152 void mana_uncfg_vport(struct mana_port_context *apc); 1153 int mana_create_eq(struct mana_port_context *apc); 1154 void mana_destroy_eq(struct mana_port_context *apc); 1155 1156 struct net_device *mana_get_primary_netdev(struct mana_context *ac, 1157 u32 port_index, 1158 netdevice_tracker *tracker); 1159 #endif /* _MANA_H */ 1160