1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Network device driver for the MACE ethernet controller on
4 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 *
6 * Copyright (C) 1996 Paul Mackerras.
7 */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/netdevice.h>
12 #include <linux/etherdevice.h>
13 #include <linux/delay.h>
14 #include <linux/string.h>
15 #include <linux/timer.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/crc32.h>
19 #include <linux/spinlock.h>
20 #include <linux/bitrev.h>
21 #include <linux/slab.h>
22 #include <linux/pgtable.h>
23 #include <asm/dbdma.h>
24 #include <asm/io.h>
25 #include <asm/macio.h>
26
27 #include "mace.h"
28
29 static int port_aaui = -1;
30
31 #define N_RX_RING 8
32 #define N_TX_RING 6
33 #define MAX_TX_ACTIVE 1
34 #define NCMDS_TX 1 /* dma commands per element in tx ring */
35 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
36 #define TX_TIMEOUT HZ /* 1 second */
37
38 /* Chip rev needs workaround on HW & multicast addr change */
39 #define BROKEN_ADDRCHG_REV 0x0941
40
41 /* Bits in transmit DMA status */
42 #define TX_DMA_ERR 0x80
43
44 struct mace_data {
45 volatile struct mace __iomem *mace;
46 volatile struct dbdma_regs __iomem *tx_dma;
47 int tx_dma_intr;
48 volatile struct dbdma_regs __iomem *rx_dma;
49 int rx_dma_intr;
50 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
51 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
52 struct sk_buff *rx_bufs[N_RX_RING];
53 int rx_fill;
54 int rx_empty;
55 struct sk_buff *tx_bufs[N_TX_RING];
56 int tx_fill;
57 int tx_empty;
58 unsigned char maccc;
59 unsigned char tx_fullup;
60 unsigned char tx_active;
61 unsigned char tx_bad_runt;
62 struct timer_list tx_timeout;
63 int timeout_active;
64 int port_aaui;
65 int chipid;
66 struct macio_dev *mdev;
67 spinlock_t lock;
68 };
69
70 /*
71 * Number of bytes of private data per MACE: allow enough for
72 * the rx and tx dma commands plus a branch dma command each,
73 * and another 16 bytes to allow us to align the dma command
74 * buffers on a 16 byte boundary.
75 */
76 #define PRIV_BYTES (sizeof(struct mace_data) \
77 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
78
79 static int mace_open(struct net_device *dev);
80 static int mace_close(struct net_device *dev);
81 static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
82 static void mace_set_multicast(struct net_device *dev);
83 static void mace_reset(struct net_device *dev);
84 static int mace_set_address(struct net_device *dev, void *addr);
85 static irqreturn_t mace_interrupt(int irq, void *dev_id);
86 static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
87 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
88 static void mace_set_timeout(struct net_device *dev);
89 static void mace_tx_timeout(struct timer_list *t);
90 static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
91 static inline void mace_clean_rings(struct mace_data *mp);
92 static void __mace_set_address(struct net_device *dev, const void *addr);
93
94 /*
95 * If we can't get a skbuff when we need it, we use this area for DMA.
96 */
97 static unsigned char *dummy_buf;
98
99 static const struct net_device_ops mace_netdev_ops = {
100 .ndo_open = mace_open,
101 .ndo_stop = mace_close,
102 .ndo_start_xmit = mace_xmit_start,
103 .ndo_set_rx_mode = mace_set_multicast,
104 .ndo_set_mac_address = mace_set_address,
105 .ndo_validate_addr = eth_validate_addr,
106 };
107
mace_probe(struct macio_dev * mdev,const struct of_device_id * match)108 static int mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
109 {
110 struct device_node *mace = macio_get_of_node(mdev);
111 struct net_device *dev;
112 struct mace_data *mp;
113 const unsigned char *addr;
114 u8 macaddr[ETH_ALEN];
115 int j, rev, rc = -EBUSY;
116
117 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
118 printk(KERN_ERR "can't use MACE %pOF: need 3 addrs and 3 irqs\n",
119 mace);
120 return -ENODEV;
121 }
122
123 addr = of_get_property(mace, "mac-address", NULL);
124 if (addr == NULL) {
125 addr = of_get_property(mace, "local-mac-address", NULL);
126 if (addr == NULL) {
127 printk(KERN_ERR "Can't get mac-address for MACE %pOF\n",
128 mace);
129 return -ENODEV;
130 }
131 }
132
133 /*
134 * lazy allocate the driver-wide dummy buffer. (Note that we
135 * never have more than one MACE in the system anyway)
136 */
137 if (dummy_buf == NULL) {
138 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
139 if (dummy_buf == NULL)
140 return -ENOMEM;
141 }
142
143 if (macio_request_resources(mdev, "mace")) {
144 printk(KERN_ERR "MACE: can't request IO resources !\n");
145 return -EBUSY;
146 }
147
148 dev = alloc_etherdev(PRIV_BYTES);
149 if (!dev) {
150 rc = -ENOMEM;
151 goto err_release;
152 }
153 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
154
155 mp = netdev_priv(dev);
156 mp->mdev = mdev;
157 macio_set_drvdata(mdev, dev);
158
159 dev->base_addr = macio_resource_start(mdev, 0);
160 mp->mace = ioremap(dev->base_addr, 0x1000);
161 if (mp->mace == NULL) {
162 printk(KERN_ERR "MACE: can't map IO resources !\n");
163 rc = -ENOMEM;
164 goto err_free;
165 }
166 dev->irq = macio_irq(mdev, 0);
167
168 rev = addr[0] == 0 && addr[1] == 0xA0;
169 for (j = 0; j < 6; ++j) {
170 macaddr[j] = rev ? bitrev8(addr[j]): addr[j];
171 }
172 eth_hw_addr_set(dev, macaddr);
173 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
174 in_8(&mp->mace->chipid_lo);
175
176
177 mp = netdev_priv(dev);
178 mp->maccc = ENXMT | ENRCV;
179
180 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
181 if (mp->tx_dma == NULL) {
182 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
183 rc = -ENOMEM;
184 goto err_unmap_io;
185 }
186 mp->tx_dma_intr = macio_irq(mdev, 1);
187
188 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
189 if (mp->rx_dma == NULL) {
190 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
191 rc = -ENOMEM;
192 goto err_unmap_tx_dma;
193 }
194 mp->rx_dma_intr = macio_irq(mdev, 2);
195
196 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
197 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
198
199 memset((char *) mp->tx_cmds, 0,
200 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
201 timer_setup(&mp->tx_timeout, mace_tx_timeout, 0);
202 spin_lock_init(&mp->lock);
203 mp->timeout_active = 0;
204
205 if (port_aaui >= 0)
206 mp->port_aaui = port_aaui;
207 else {
208 /* Apple Network Server uses the AAUI port */
209 if (of_machine_is_compatible("AAPL,ShinerESB"))
210 mp->port_aaui = 1;
211 else {
212 #ifdef CONFIG_MACE_AAUI_PORT
213 mp->port_aaui = 1;
214 #else
215 mp->port_aaui = 0;
216 #endif
217 }
218 }
219
220 dev->netdev_ops = &mace_netdev_ops;
221
222 /*
223 * Most of what is below could be moved to mace_open()
224 */
225 mace_reset(dev);
226
227 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
228 if (rc) {
229 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
230 goto err_unmap_rx_dma;
231 }
232 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
233 if (rc) {
234 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
235 goto err_free_irq;
236 }
237 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
238 if (rc) {
239 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
240 goto err_free_tx_irq;
241 }
242
243 rc = register_netdev(dev);
244 if (rc) {
245 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
246 goto err_free_rx_irq;
247 }
248
249 printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
250 dev->name, dev->dev_addr,
251 mp->chipid >> 8, mp->chipid & 0xff);
252
253 return 0;
254
255 err_free_rx_irq:
256 free_irq(macio_irq(mdev, 2), dev);
257 err_free_tx_irq:
258 free_irq(macio_irq(mdev, 1), dev);
259 err_free_irq:
260 free_irq(macio_irq(mdev, 0), dev);
261 err_unmap_rx_dma:
262 iounmap(mp->rx_dma);
263 err_unmap_tx_dma:
264 iounmap(mp->tx_dma);
265 err_unmap_io:
266 iounmap(mp->mace);
267 err_free:
268 free_netdev(dev);
269 err_release:
270 macio_release_resources(mdev);
271
272 return rc;
273 }
274
mace_remove(struct macio_dev * mdev)275 static void mace_remove(struct macio_dev *mdev)
276 {
277 struct net_device *dev = macio_get_drvdata(mdev);
278 struct mace_data *mp;
279
280 BUG_ON(dev == NULL);
281
282 macio_set_drvdata(mdev, NULL);
283
284 mp = netdev_priv(dev);
285
286 unregister_netdev(dev);
287
288 free_irq(dev->irq, dev);
289 free_irq(mp->tx_dma_intr, dev);
290 free_irq(mp->rx_dma_intr, dev);
291
292 iounmap(mp->rx_dma);
293 iounmap(mp->tx_dma);
294 iounmap(mp->mace);
295
296 free_netdev(dev);
297
298 macio_release_resources(mdev);
299 }
300
dbdma_reset(volatile struct dbdma_regs __iomem * dma)301 static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
302 {
303 int i;
304
305 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
306
307 /*
308 * Yes this looks peculiar, but apparently it needs to be this
309 * way on some machines.
310 */
311 for (i = 200; i > 0; --i)
312 if (le32_to_cpu(dma->control) & RUN)
313 udelay(1);
314 }
315
mace_reset(struct net_device * dev)316 static void mace_reset(struct net_device *dev)
317 {
318 struct mace_data *mp = netdev_priv(dev);
319 volatile struct mace __iomem *mb = mp->mace;
320 int i;
321
322 /* soft-reset the chip */
323 i = 200;
324 while (--i) {
325 out_8(&mb->biucc, SWRST);
326 if (in_8(&mb->biucc) & SWRST) {
327 udelay(10);
328 continue;
329 }
330 break;
331 }
332 if (!i) {
333 printk(KERN_ERR "mace: cannot reset chip!\n");
334 return;
335 }
336
337 out_8(&mb->imr, 0xff); /* disable all intrs for now */
338 i = in_8(&mb->ir);
339 out_8(&mb->maccc, 0); /* turn off tx, rx */
340
341 out_8(&mb->biucc, XMTSP_64);
342 out_8(&mb->utr, RTRD);
343 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
344 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
345 out_8(&mb->rcvfc, 0);
346
347 /* load up the hardware address */
348 __mace_set_address(dev, dev->dev_addr);
349
350 /* clear the multicast filter */
351 if (mp->chipid == BROKEN_ADDRCHG_REV)
352 out_8(&mb->iac, LOGADDR);
353 else {
354 out_8(&mb->iac, ADDRCHG | LOGADDR);
355 while ((in_8(&mb->iac) & ADDRCHG) != 0)
356 ;
357 }
358 for (i = 0; i < 8; ++i)
359 out_8(&mb->ladrf, 0);
360
361 /* done changing address */
362 if (mp->chipid != BROKEN_ADDRCHG_REV)
363 out_8(&mb->iac, 0);
364
365 if (mp->port_aaui)
366 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
367 else
368 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
369 }
370
__mace_set_address(struct net_device * dev,const void * addr)371 static void __mace_set_address(struct net_device *dev, const void *addr)
372 {
373 struct mace_data *mp = netdev_priv(dev);
374 volatile struct mace __iomem *mb = mp->mace;
375 const unsigned char *p = addr;
376 u8 macaddr[ETH_ALEN];
377 int i;
378
379 /* load up the hardware address */
380 if (mp->chipid == BROKEN_ADDRCHG_REV)
381 out_8(&mb->iac, PHYADDR);
382 else {
383 out_8(&mb->iac, ADDRCHG | PHYADDR);
384 while ((in_8(&mb->iac) & ADDRCHG) != 0)
385 ;
386 }
387 for (i = 0; i < 6; ++i)
388 out_8(&mb->padr, macaddr[i] = p[i]);
389
390 eth_hw_addr_set(dev, macaddr);
391
392 if (mp->chipid != BROKEN_ADDRCHG_REV)
393 out_8(&mb->iac, 0);
394 }
395
mace_set_address(struct net_device * dev,void * addr)396 static int mace_set_address(struct net_device *dev, void *addr)
397 {
398 struct mace_data *mp = netdev_priv(dev);
399 volatile struct mace __iomem *mb = mp->mace;
400 unsigned long flags;
401
402 spin_lock_irqsave(&mp->lock, flags);
403
404 __mace_set_address(dev, addr);
405
406 /* note: setting ADDRCHG clears ENRCV */
407 out_8(&mb->maccc, mp->maccc);
408
409 spin_unlock_irqrestore(&mp->lock, flags);
410 return 0;
411 }
412
mace_clean_rings(struct mace_data * mp)413 static inline void mace_clean_rings(struct mace_data *mp)
414 {
415 int i;
416
417 /* free some skb's */
418 for (i = 0; i < N_RX_RING; ++i) {
419 if (mp->rx_bufs[i] != NULL) {
420 dev_kfree_skb(mp->rx_bufs[i]);
421 mp->rx_bufs[i] = NULL;
422 }
423 }
424 for (i = mp->tx_empty; i != mp->tx_fill; ) {
425 dev_kfree_skb(mp->tx_bufs[i]);
426 if (++i >= N_TX_RING)
427 i = 0;
428 }
429 }
430
mace_open(struct net_device * dev)431 static int mace_open(struct net_device *dev)
432 {
433 struct mace_data *mp = netdev_priv(dev);
434 volatile struct mace __iomem *mb = mp->mace;
435 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
436 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
437 volatile struct dbdma_cmd *cp;
438 int i;
439 struct sk_buff *skb;
440 unsigned char *data;
441
442 /* reset the chip */
443 mace_reset(dev);
444
445 /* initialize list of sk_buffs for receiving and set up recv dma */
446 mace_clean_rings(mp);
447 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
448 cp = mp->rx_cmds;
449 for (i = 0; i < N_RX_RING - 1; ++i) {
450 skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
451 if (!skb) {
452 data = dummy_buf;
453 } else {
454 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
455 data = skb->data;
456 }
457 mp->rx_bufs[i] = skb;
458 cp->req_count = cpu_to_le16(RX_BUFLEN);
459 cp->command = cpu_to_le16(INPUT_LAST + INTR_ALWAYS);
460 cp->phy_addr = cpu_to_le32(virt_to_bus(data));
461 cp->xfer_status = 0;
462 ++cp;
463 }
464 mp->rx_bufs[i] = NULL;
465 cp->command = cpu_to_le16(DBDMA_STOP);
466 mp->rx_fill = i;
467 mp->rx_empty = 0;
468
469 /* Put a branch back to the beginning of the receive command list */
470 ++cp;
471 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
472 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->rx_cmds));
473
474 /* start rx dma */
475 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
476 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
477 out_le32(&rd->control, (RUN << 16) | RUN);
478
479 /* put a branch at the end of the tx command list */
480 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
481 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
482 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->tx_cmds));
483
484 /* reset tx dma */
485 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
486 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
487 mp->tx_fill = 0;
488 mp->tx_empty = 0;
489 mp->tx_fullup = 0;
490 mp->tx_active = 0;
491 mp->tx_bad_runt = 0;
492
493 /* turn it on! */
494 out_8(&mb->maccc, mp->maccc);
495 /* enable all interrupts except receive interrupts */
496 out_8(&mb->imr, RCVINT);
497
498 return 0;
499 }
500
mace_close(struct net_device * dev)501 static int mace_close(struct net_device *dev)
502 {
503 struct mace_data *mp = netdev_priv(dev);
504 volatile struct mace __iomem *mb = mp->mace;
505 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
506 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
507
508 /* disable rx and tx */
509 out_8(&mb->maccc, 0);
510 out_8(&mb->imr, 0xff); /* disable all intrs */
511
512 /* disable rx and tx dma */
513 rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
514 td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
515
516 mace_clean_rings(mp);
517
518 return 0;
519 }
520
mace_set_timeout(struct net_device * dev)521 static inline void mace_set_timeout(struct net_device *dev)
522 {
523 struct mace_data *mp = netdev_priv(dev);
524
525 if (mp->timeout_active)
526 del_timer(&mp->tx_timeout);
527 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
528 add_timer(&mp->tx_timeout);
529 mp->timeout_active = 1;
530 }
531
mace_xmit_start(struct sk_buff * skb,struct net_device * dev)532 static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
533 {
534 struct mace_data *mp = netdev_priv(dev);
535 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
536 volatile struct dbdma_cmd *cp, *np;
537 unsigned long flags;
538 int fill, next, len;
539
540 /* see if there's a free slot in the tx ring */
541 spin_lock_irqsave(&mp->lock, flags);
542 fill = mp->tx_fill;
543 next = fill + 1;
544 if (next >= N_TX_RING)
545 next = 0;
546 if (next == mp->tx_empty) {
547 netif_stop_queue(dev);
548 mp->tx_fullup = 1;
549 spin_unlock_irqrestore(&mp->lock, flags);
550 return NETDEV_TX_BUSY; /* can't take it at the moment */
551 }
552 spin_unlock_irqrestore(&mp->lock, flags);
553
554 /* partially fill in the dma command block */
555 len = skb->len;
556 if (len > ETH_FRAME_LEN) {
557 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
558 len = ETH_FRAME_LEN;
559 }
560 mp->tx_bufs[fill] = skb;
561 cp = mp->tx_cmds + NCMDS_TX * fill;
562 cp->req_count = cpu_to_le16(len);
563 cp->phy_addr = cpu_to_le32(virt_to_bus(skb->data));
564
565 np = mp->tx_cmds + NCMDS_TX * next;
566 out_le16(&np->command, DBDMA_STOP);
567
568 /* poke the tx dma channel */
569 spin_lock_irqsave(&mp->lock, flags);
570 mp->tx_fill = next;
571 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
572 out_le16(&cp->xfer_status, 0);
573 out_le16(&cp->command, OUTPUT_LAST);
574 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
575 ++mp->tx_active;
576 mace_set_timeout(dev);
577 }
578 if (++next >= N_TX_RING)
579 next = 0;
580 if (next == mp->tx_empty)
581 netif_stop_queue(dev);
582 spin_unlock_irqrestore(&mp->lock, flags);
583
584 return NETDEV_TX_OK;
585 }
586
mace_set_multicast(struct net_device * dev)587 static void mace_set_multicast(struct net_device *dev)
588 {
589 struct mace_data *mp = netdev_priv(dev);
590 volatile struct mace __iomem *mb = mp->mace;
591 int i;
592 u32 crc;
593 unsigned long flags;
594
595 spin_lock_irqsave(&mp->lock, flags);
596 mp->maccc &= ~PROM;
597 if (dev->flags & IFF_PROMISC) {
598 mp->maccc |= PROM;
599 } else {
600 unsigned char multicast_filter[8];
601 struct netdev_hw_addr *ha;
602
603 if (dev->flags & IFF_ALLMULTI) {
604 for (i = 0; i < 8; i++)
605 multicast_filter[i] = 0xff;
606 } else {
607 for (i = 0; i < 8; i++)
608 multicast_filter[i] = 0;
609 netdev_for_each_mc_addr(ha, dev) {
610 crc = ether_crc_le(6, ha->addr);
611 i = crc >> 26; /* bit number in multicast_filter */
612 multicast_filter[i >> 3] |= 1 << (i & 7);
613 }
614 }
615 #if 0
616 printk("Multicast filter :");
617 for (i = 0; i < 8; i++)
618 printk("%02x ", multicast_filter[i]);
619 printk("\n");
620 #endif
621
622 if (mp->chipid == BROKEN_ADDRCHG_REV)
623 out_8(&mb->iac, LOGADDR);
624 else {
625 out_8(&mb->iac, ADDRCHG | LOGADDR);
626 while ((in_8(&mb->iac) & ADDRCHG) != 0)
627 ;
628 }
629 for (i = 0; i < 8; ++i)
630 out_8(&mb->ladrf, multicast_filter[i]);
631 if (mp->chipid != BROKEN_ADDRCHG_REV)
632 out_8(&mb->iac, 0);
633 }
634 /* reset maccc */
635 out_8(&mb->maccc, mp->maccc);
636 spin_unlock_irqrestore(&mp->lock, flags);
637 }
638
mace_handle_misc_intrs(struct mace_data * mp,int intr,struct net_device * dev)639 static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
640 {
641 volatile struct mace __iomem *mb = mp->mace;
642 static int mace_babbles, mace_jabbers;
643
644 if (intr & MPCO)
645 dev->stats.rx_missed_errors += 256;
646 dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
647 if (intr & RNTPCO)
648 dev->stats.rx_length_errors += 256;
649 dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
650 if (intr & CERR)
651 ++dev->stats.tx_heartbeat_errors;
652 if (intr & BABBLE)
653 if (mace_babbles++ < 4)
654 printk(KERN_DEBUG "mace: babbling transmitter\n");
655 if (intr & JABBER)
656 if (mace_jabbers++ < 4)
657 printk(KERN_DEBUG "mace: jabbering transceiver\n");
658 }
659
mace_interrupt(int irq,void * dev_id)660 static irqreturn_t mace_interrupt(int irq, void *dev_id)
661 {
662 struct net_device *dev = (struct net_device *) dev_id;
663 struct mace_data *mp = netdev_priv(dev);
664 volatile struct mace __iomem *mb = mp->mace;
665 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
666 volatile struct dbdma_cmd *cp;
667 int intr, fs, i, stat, x;
668 int xcount, dstat;
669 unsigned long flags;
670 /* static int mace_last_fs, mace_last_xcount; */
671
672 spin_lock_irqsave(&mp->lock, flags);
673 intr = in_8(&mb->ir); /* read interrupt register */
674 in_8(&mb->xmtrc); /* get retries */
675 mace_handle_misc_intrs(mp, intr, dev);
676
677 i = mp->tx_empty;
678 while (in_8(&mb->pr) & XMTSV) {
679 del_timer(&mp->tx_timeout);
680 mp->timeout_active = 0;
681 /*
682 * Clear any interrupt indication associated with this status
683 * word. This appears to unlatch any error indication from
684 * the DMA controller.
685 */
686 intr = in_8(&mb->ir);
687 if (intr != 0)
688 mace_handle_misc_intrs(mp, intr, dev);
689 if (mp->tx_bad_runt) {
690 fs = in_8(&mb->xmtfs);
691 mp->tx_bad_runt = 0;
692 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
693 continue;
694 }
695 dstat = le32_to_cpu(td->status);
696 /* stop DMA controller */
697 out_le32(&td->control, RUN << 16);
698 /*
699 * xcount is the number of complete frames which have been
700 * written to the fifo but for which status has not been read.
701 */
702 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
703 if (xcount == 0 || (dstat & DEAD)) {
704 /*
705 * If a packet was aborted before the DMA controller has
706 * finished transferring it, it seems that there are 2 bytes
707 * which are stuck in some buffer somewhere. These will get
708 * transmitted as soon as we read the frame status (which
709 * reenables the transmit data transfer request). Turning
710 * off the DMA controller and/or resetting the MACE doesn't
711 * help. So we disable auto-padding and FCS transmission
712 * so the two bytes will only be a runt packet which should
713 * be ignored by other stations.
714 */
715 out_8(&mb->xmtfc, DXMTFCS);
716 }
717 fs = in_8(&mb->xmtfs);
718 if ((fs & XMTSV) == 0) {
719 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
720 fs, xcount, dstat);
721 mace_reset(dev);
722 /*
723 * XXX mace likes to hang the machine after a xmtfs error.
724 * This is hard to reproduce, resetting *may* help
725 */
726 }
727 cp = mp->tx_cmds + NCMDS_TX * i;
728 stat = le16_to_cpu(cp->xfer_status);
729 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
730 /*
731 * Check whether there were in fact 2 bytes written to
732 * the transmit FIFO.
733 */
734 udelay(1);
735 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
736 if (x != 0) {
737 /* there were two bytes with an end-of-packet indication */
738 mp->tx_bad_runt = 1;
739 mace_set_timeout(dev);
740 } else {
741 /*
742 * Either there weren't the two bytes buffered up, or they
743 * didn't have an end-of-packet indication.
744 * We flush the transmit FIFO just in case (by setting the
745 * XMTFWU bit with the transmitter disabled).
746 */
747 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
748 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
749 udelay(1);
750 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
751 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
752 }
753 }
754 /* dma should have finished */
755 if (i == mp->tx_fill) {
756 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
757 fs, xcount, dstat);
758 continue;
759 }
760 /* Update stats */
761 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
762 ++dev->stats.tx_errors;
763 if (fs & LCAR)
764 ++dev->stats.tx_carrier_errors;
765 if (fs & (UFLO|LCOL|RTRY))
766 ++dev->stats.tx_aborted_errors;
767 } else {
768 dev->stats.tx_bytes += mp->tx_bufs[i]->len;
769 ++dev->stats.tx_packets;
770 }
771 dev_consume_skb_irq(mp->tx_bufs[i]);
772 --mp->tx_active;
773 if (++i >= N_TX_RING)
774 i = 0;
775 #if 0
776 mace_last_fs = fs;
777 mace_last_xcount = xcount;
778 #endif
779 }
780
781 if (i != mp->tx_empty) {
782 mp->tx_fullup = 0;
783 netif_wake_queue(dev);
784 }
785 mp->tx_empty = i;
786 i += mp->tx_active;
787 if (i >= N_TX_RING)
788 i -= N_TX_RING;
789 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
790 do {
791 /* set up the next one */
792 cp = mp->tx_cmds + NCMDS_TX * i;
793 out_le16(&cp->xfer_status, 0);
794 out_le16(&cp->command, OUTPUT_LAST);
795 ++mp->tx_active;
796 if (++i >= N_TX_RING)
797 i = 0;
798 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
799 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
800 mace_set_timeout(dev);
801 }
802 spin_unlock_irqrestore(&mp->lock, flags);
803 return IRQ_HANDLED;
804 }
805
mace_tx_timeout(struct timer_list * t)806 static void mace_tx_timeout(struct timer_list *t)
807 {
808 struct mace_data *mp = from_timer(mp, t, tx_timeout);
809 struct net_device *dev = macio_get_drvdata(mp->mdev);
810 volatile struct mace __iomem *mb = mp->mace;
811 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
812 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
813 volatile struct dbdma_cmd *cp;
814 unsigned long flags;
815 int i;
816
817 spin_lock_irqsave(&mp->lock, flags);
818 mp->timeout_active = 0;
819 if (mp->tx_active == 0 && !mp->tx_bad_runt)
820 goto out;
821
822 /* update various counters */
823 mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
824
825 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
826
827 /* turn off both tx and rx and reset the chip */
828 out_8(&mb->maccc, 0);
829 printk(KERN_ERR "mace: transmit timeout - resetting\n");
830 dbdma_reset(td);
831 mace_reset(dev);
832
833 /* restart rx dma */
834 cp = bus_to_virt(le32_to_cpu(rd->cmdptr));
835 dbdma_reset(rd);
836 out_le16(&cp->xfer_status, 0);
837 out_le32(&rd->cmdptr, virt_to_bus(cp));
838 out_le32(&rd->control, (RUN << 16) | RUN);
839
840 /* fix up the transmit side */
841 i = mp->tx_empty;
842 mp->tx_active = 0;
843 ++dev->stats.tx_errors;
844 if (mp->tx_bad_runt) {
845 mp->tx_bad_runt = 0;
846 } else if (i != mp->tx_fill) {
847 dev_kfree_skb_irq(mp->tx_bufs[i]);
848 if (++i >= N_TX_RING)
849 i = 0;
850 mp->tx_empty = i;
851 }
852 mp->tx_fullup = 0;
853 netif_wake_queue(dev);
854 if (i != mp->tx_fill) {
855 cp = mp->tx_cmds + NCMDS_TX * i;
856 out_le16(&cp->xfer_status, 0);
857 out_le16(&cp->command, OUTPUT_LAST);
858 out_le32(&td->cmdptr, virt_to_bus(cp));
859 out_le32(&td->control, (RUN << 16) | RUN);
860 ++mp->tx_active;
861 mace_set_timeout(dev);
862 }
863
864 /* turn it back on */
865 out_8(&mb->imr, RCVINT);
866 out_8(&mb->maccc, mp->maccc);
867
868 out:
869 spin_unlock_irqrestore(&mp->lock, flags);
870 }
871
mace_txdma_intr(int irq,void * dev_id)872 static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
873 {
874 return IRQ_HANDLED;
875 }
876
mace_rxdma_intr(int irq,void * dev_id)877 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
878 {
879 struct net_device *dev = (struct net_device *) dev_id;
880 struct mace_data *mp = netdev_priv(dev);
881 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
882 volatile struct dbdma_cmd *cp, *np;
883 int i, nb, stat, next;
884 struct sk_buff *skb;
885 unsigned frame_status;
886 static int mace_lost_status;
887 unsigned char *data;
888 unsigned long flags;
889
890 spin_lock_irqsave(&mp->lock, flags);
891 for (i = mp->rx_empty; i != mp->rx_fill; ) {
892 cp = mp->rx_cmds + i;
893 stat = le16_to_cpu(cp->xfer_status);
894 if ((stat & ACTIVE) == 0) {
895 next = i + 1;
896 if (next >= N_RX_RING)
897 next = 0;
898 np = mp->rx_cmds + next;
899 if (next != mp->rx_fill &&
900 (le16_to_cpu(np->xfer_status) & ACTIVE) != 0) {
901 printk(KERN_DEBUG "mace: lost a status word\n");
902 ++mace_lost_status;
903 } else
904 break;
905 }
906 nb = le16_to_cpu(cp->req_count) - le16_to_cpu(cp->res_count);
907 out_le16(&cp->command, DBDMA_STOP);
908 /* got a packet, have a look at it */
909 skb = mp->rx_bufs[i];
910 if (!skb) {
911 ++dev->stats.rx_dropped;
912 } else if (nb > 8) {
913 data = skb->data;
914 frame_status = (data[nb-3] << 8) + data[nb-4];
915 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
916 ++dev->stats.rx_errors;
917 if (frame_status & RS_OFLO)
918 ++dev->stats.rx_over_errors;
919 if (frame_status & RS_FRAMERR)
920 ++dev->stats.rx_frame_errors;
921 if (frame_status & RS_FCSERR)
922 ++dev->stats.rx_crc_errors;
923 } else {
924 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
925 * FCS on frames with 802.3 headers. This means that Ethernet
926 * frames have 8 extra octets at the end, while 802.3 frames
927 * have only 4. We need to correctly account for this. */
928 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
929 nb -= 4;
930 else /* Ethernet header; mace includes FCS */
931 nb -= 8;
932 skb_put(skb, nb);
933 skb->protocol = eth_type_trans(skb, dev);
934 dev->stats.rx_bytes += skb->len;
935 netif_rx(skb);
936 mp->rx_bufs[i] = NULL;
937 ++dev->stats.rx_packets;
938 }
939 } else {
940 ++dev->stats.rx_errors;
941 ++dev->stats.rx_length_errors;
942 }
943
944 /* advance to next */
945 if (++i >= N_RX_RING)
946 i = 0;
947 }
948 mp->rx_empty = i;
949
950 i = mp->rx_fill;
951 for (;;) {
952 next = i + 1;
953 if (next >= N_RX_RING)
954 next = 0;
955 if (next == mp->rx_empty)
956 break;
957 cp = mp->rx_cmds + i;
958 skb = mp->rx_bufs[i];
959 if (!skb) {
960 skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
961 if (skb) {
962 skb_reserve(skb, 2);
963 mp->rx_bufs[i] = skb;
964 }
965 }
966 cp->req_count = cpu_to_le16(RX_BUFLEN);
967 data = skb? skb->data: dummy_buf;
968 cp->phy_addr = cpu_to_le32(virt_to_bus(data));
969 out_le16(&cp->xfer_status, 0);
970 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
971 #if 0
972 if ((le32_to_cpu(rd->status) & ACTIVE) != 0) {
973 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
974 while ((in_le32(&rd->status) & ACTIVE) != 0)
975 ;
976 }
977 #endif
978 i = next;
979 }
980 if (i != mp->rx_fill) {
981 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
982 mp->rx_fill = i;
983 }
984 spin_unlock_irqrestore(&mp->lock, flags);
985 return IRQ_HANDLED;
986 }
987
988 static const struct of_device_id mace_match[] =
989 {
990 {
991 .name = "mace",
992 },
993 {},
994 };
995 MODULE_DEVICE_TABLE (of, mace_match);
996
997 static struct macio_driver mace_driver =
998 {
999 .driver = {
1000 .name = "mace",
1001 .owner = THIS_MODULE,
1002 .of_match_table = mace_match,
1003 },
1004 .probe = mace_probe,
1005 .remove = mace_remove,
1006 };
1007
1008
mace_init(void)1009 static int __init mace_init(void)
1010 {
1011 return macio_register_driver(&mace_driver);
1012 }
1013
mace_cleanup(void)1014 static void __exit mace_cleanup(void)
1015 {
1016 macio_unregister_driver(&mace_driver);
1017
1018 kfree(dummy_buf);
1019 dummy_buf = NULL;
1020 }
1021
1022 MODULE_AUTHOR("Paul Mackerras");
1023 MODULE_DESCRIPTION("PowerMac MACE driver.");
1024 module_param(port_aaui, int, 0);
1025 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1026 MODULE_LICENSE("GPL");
1027
1028 module_init(mace_init);
1029 module_exit(mace_cleanup);
1030