1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cadence MACB/GEM Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
28 #include <linux/of.h>
29 #include <linux/of_gpio.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/ip.h>
33 #include <linux/udp.h>
34 #include <linux/tcp.h>
35 #include <linux/iopoll.h>
36 #include <linux/phy/phy.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/ptp_classify.h>
39 #include <linux/reset.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
41 #include <linux/inetdevice.h>
42 #include "macb.h"
43
44 /* This structure is only used for MACB on SiFive FU540 devices */
45 struct sifive_fu540_macb_mgmt {
46 void __iomem *reg;
47 unsigned long rate;
48 struct clk_hw hw;
49 };
50
51 #define MACB_RX_BUFFER_SIZE 128
52 #define RX_BUFFER_MULTIPLE 64 /* bytes */
53
54 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
55 #define MIN_RX_RING_SIZE 64
56 #define MAX_RX_RING_SIZE 8192
57 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
58 * (bp)->rx_ring_size)
59
60 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
61 #define MIN_TX_RING_SIZE 64
62 #define MAX_TX_RING_SIZE 4096
63 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
64 * (bp)->tx_ring_size)
65
66 /* level of occupied TX descriptors under which we wake up TX process */
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
68
69 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
70 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
71 | MACB_BIT(ISR_RLE) \
72 | MACB_BIT(TXERR))
73 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
74 | MACB_BIT(TXUBR))
75
76 /* Max length of transmit frame must be a multiple of 8 bytes */
77 #define MACB_TX_LEN_ALIGN 8
78 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
79 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
80 * false amba_error in TX path from the DMA assuming there is not enough
81 * space in the SRAM (16KB) even when there is.
82 */
83 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
84
85 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
86 #define MACB_NETIF_LSO NETIF_F_TSO
87
88 #define MACB_WOL_ENABLED BIT(0)
89
90 #define HS_SPEED_10000M 4
91 #define MACB_SERDES_RATE_10G 1
92
93 /* Graceful stop timeouts in us. We should allow up to
94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
95 */
96 #define MACB_HALT_TIMEOUT 14000
97 #define MACB_PM_TIMEOUT 100 /* ms */
98
99 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
100
101 /* DMA buffer descriptor might be different size
102 * depends on hardware configuration:
103 *
104 * 1. dma address width 32 bits:
105 * word 1: 32 bit address of Data Buffer
106 * word 2: control
107 *
108 * 2. dma address width 64 bits:
109 * word 1: 32 bit address of Data Buffer
110 * word 2: control
111 * word 3: upper 32 bit address of Data Buffer
112 * word 4: unused
113 *
114 * 3. dma address width 32 bits with hardware timestamping:
115 * word 1: 32 bit address of Data Buffer
116 * word 2: control
117 * word 3: timestamp word 1
118 * word 4: timestamp word 2
119 *
120 * 4. dma address width 64 bits with hardware timestamping:
121 * word 1: 32 bit address of Data Buffer
122 * word 2: control
123 * word 3: upper 32 bit address of Data Buffer
124 * word 4: unused
125 * word 5: timestamp word 1
126 * word 6: timestamp word 2
127 */
macb_dma_desc_get_size(struct macb * bp)128 static unsigned int macb_dma_desc_get_size(struct macb *bp)
129 {
130 #ifdef MACB_EXT_DESC
131 unsigned int desc_size;
132
133 switch (bp->hw_dma_cap) {
134 case HW_DMA_CAP_64B:
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_64);
137 break;
138 case HW_DMA_CAP_PTP:
139 desc_size = sizeof(struct macb_dma_desc)
140 + sizeof(struct macb_dma_desc_ptp);
141 break;
142 case HW_DMA_CAP_64B_PTP:
143 desc_size = sizeof(struct macb_dma_desc)
144 + sizeof(struct macb_dma_desc_64)
145 + sizeof(struct macb_dma_desc_ptp);
146 break;
147 default:
148 desc_size = sizeof(struct macb_dma_desc);
149 }
150 return desc_size;
151 #endif
152 return sizeof(struct macb_dma_desc);
153 }
154
macb_adj_dma_desc_idx(struct macb * bp,unsigned int desc_idx)155 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
156 {
157 #ifdef MACB_EXT_DESC
158 switch (bp->hw_dma_cap) {
159 case HW_DMA_CAP_64B:
160 case HW_DMA_CAP_PTP:
161 desc_idx <<= 1;
162 break;
163 case HW_DMA_CAP_64B_PTP:
164 desc_idx *= 3;
165 break;
166 default:
167 break;
168 }
169 #endif
170 return desc_idx;
171 }
172
173 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
macb_64b_desc(struct macb * bp,struct macb_dma_desc * desc)174 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
175 {
176 return (struct macb_dma_desc_64 *)((void *)desc
177 + sizeof(struct macb_dma_desc));
178 }
179 #endif
180
181 /* Ring buffer accessors */
macb_tx_ring_wrap(struct macb * bp,unsigned int index)182 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
183 {
184 return index & (bp->tx_ring_size - 1);
185 }
186
macb_tx_desc(struct macb_queue * queue,unsigned int index)187 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
188 unsigned int index)
189 {
190 index = macb_tx_ring_wrap(queue->bp, index);
191 index = macb_adj_dma_desc_idx(queue->bp, index);
192 return &queue->tx_ring[index];
193 }
194
macb_tx_skb(struct macb_queue * queue,unsigned int index)195 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
196 unsigned int index)
197 {
198 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
199 }
200
macb_tx_dma(struct macb_queue * queue,unsigned int index)201 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
202 {
203 dma_addr_t offset;
204
205 offset = macb_tx_ring_wrap(queue->bp, index) *
206 macb_dma_desc_get_size(queue->bp);
207
208 return queue->tx_ring_dma + offset;
209 }
210
macb_rx_ring_wrap(struct macb * bp,unsigned int index)211 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
212 {
213 return index & (bp->rx_ring_size - 1);
214 }
215
macb_rx_desc(struct macb_queue * queue,unsigned int index)216 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
217 {
218 index = macb_rx_ring_wrap(queue->bp, index);
219 index = macb_adj_dma_desc_idx(queue->bp, index);
220 return &queue->rx_ring[index];
221 }
222
macb_rx_buffer(struct macb_queue * queue,unsigned int index)223 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
224 {
225 return queue->rx_buffers + queue->bp->rx_buffer_size *
226 macb_rx_ring_wrap(queue->bp, index);
227 }
228
229 /* I/O accessors */
hw_readl_native(struct macb * bp,int offset)230 static u32 hw_readl_native(struct macb *bp, int offset)
231 {
232 return __raw_readl(bp->regs + offset);
233 }
234
hw_writel_native(struct macb * bp,int offset,u32 value)235 static void hw_writel_native(struct macb *bp, int offset, u32 value)
236 {
237 __raw_writel(value, bp->regs + offset);
238 }
239
hw_readl(struct macb * bp,int offset)240 static u32 hw_readl(struct macb *bp, int offset)
241 {
242 return readl_relaxed(bp->regs + offset);
243 }
244
hw_writel(struct macb * bp,int offset,u32 value)245 static void hw_writel(struct macb *bp, int offset, u32 value)
246 {
247 writel_relaxed(value, bp->regs + offset);
248 }
249
250 /* Find the CPU endianness by using the loopback bit of NCR register. When the
251 * CPU is in big endian we need to program swapped mode for management
252 * descriptor access.
253 */
hw_is_native_io(void __iomem * addr)254 static bool hw_is_native_io(void __iomem *addr)
255 {
256 u32 value = MACB_BIT(LLB);
257
258 __raw_writel(value, addr + MACB_NCR);
259 value = __raw_readl(addr + MACB_NCR);
260
261 /* Write 0 back to disable everything */
262 __raw_writel(0, addr + MACB_NCR);
263
264 return value == MACB_BIT(LLB);
265 }
266
hw_is_gem(void __iomem * addr,bool native_io)267 static bool hw_is_gem(void __iomem *addr, bool native_io)
268 {
269 u32 id;
270
271 if (native_io)
272 id = __raw_readl(addr + MACB_MID);
273 else
274 id = readl_relaxed(addr + MACB_MID);
275
276 return MACB_BFEXT(IDNUM, id) >= 0x2;
277 }
278
macb_set_hwaddr(struct macb * bp)279 static void macb_set_hwaddr(struct macb *bp)
280 {
281 u32 bottom;
282 u16 top;
283
284 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
285 macb_or_gem_writel(bp, SA1B, bottom);
286 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
287 macb_or_gem_writel(bp, SA1T, top);
288
289 if (gem_has_ptp(bp)) {
290 gem_writel(bp, RXPTPUNI, bottom);
291 gem_writel(bp, TXPTPUNI, bottom);
292 }
293
294 /* Clear unused address register sets */
295 macb_or_gem_writel(bp, SA2B, 0);
296 macb_or_gem_writel(bp, SA2T, 0);
297 macb_or_gem_writel(bp, SA3B, 0);
298 macb_or_gem_writel(bp, SA3T, 0);
299 macb_or_gem_writel(bp, SA4B, 0);
300 macb_or_gem_writel(bp, SA4T, 0);
301 }
302
macb_get_hwaddr(struct macb * bp)303 static void macb_get_hwaddr(struct macb *bp)
304 {
305 u32 bottom;
306 u16 top;
307 u8 addr[6];
308 int i;
309
310 /* Check all 4 address register for valid address */
311 for (i = 0; i < 4; i++) {
312 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
313 top = macb_or_gem_readl(bp, SA1T + i * 8);
314
315 addr[0] = bottom & 0xff;
316 addr[1] = (bottom >> 8) & 0xff;
317 addr[2] = (bottom >> 16) & 0xff;
318 addr[3] = (bottom >> 24) & 0xff;
319 addr[4] = top & 0xff;
320 addr[5] = (top >> 8) & 0xff;
321
322 if (is_valid_ether_addr(addr)) {
323 eth_hw_addr_set(bp->dev, addr);
324 return;
325 }
326 }
327
328 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
329 eth_hw_addr_random(bp->dev);
330 }
331
macb_mdio_wait_for_idle(struct macb * bp)332 static int macb_mdio_wait_for_idle(struct macb *bp)
333 {
334 u32 val;
335
336 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
337 1, MACB_MDIO_TIMEOUT);
338 }
339
macb_mdio_read_c22(struct mii_bus * bus,int mii_id,int regnum)340 static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
341 {
342 struct macb *bp = bus->priv;
343 int status;
344
345 status = pm_runtime_resume_and_get(&bp->pdev->dev);
346 if (status < 0)
347 goto mdio_pm_exit;
348
349 status = macb_mdio_wait_for_idle(bp);
350 if (status < 0)
351 goto mdio_read_exit;
352
353 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
354 | MACB_BF(RW, MACB_MAN_C22_READ)
355 | MACB_BF(PHYA, mii_id)
356 | MACB_BF(REGA, regnum)
357 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
358
359 status = macb_mdio_wait_for_idle(bp);
360 if (status < 0)
361 goto mdio_read_exit;
362
363 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
364
365 mdio_read_exit:
366 pm_runtime_mark_last_busy(&bp->pdev->dev);
367 pm_runtime_put_autosuspend(&bp->pdev->dev);
368 mdio_pm_exit:
369 return status;
370 }
371
macb_mdio_read_c45(struct mii_bus * bus,int mii_id,int devad,int regnum)372 static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad,
373 int regnum)
374 {
375 struct macb *bp = bus->priv;
376 int status;
377
378 status = pm_runtime_get_sync(&bp->pdev->dev);
379 if (status < 0) {
380 pm_runtime_put_noidle(&bp->pdev->dev);
381 goto mdio_pm_exit;
382 }
383
384 status = macb_mdio_wait_for_idle(bp);
385 if (status < 0)
386 goto mdio_read_exit;
387
388 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
389 | MACB_BF(RW, MACB_MAN_C45_ADDR)
390 | MACB_BF(PHYA, mii_id)
391 | MACB_BF(REGA, devad & 0x1F)
392 | MACB_BF(DATA, regnum & 0xFFFF)
393 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
394
395 status = macb_mdio_wait_for_idle(bp);
396 if (status < 0)
397 goto mdio_read_exit;
398
399 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
400 | MACB_BF(RW, MACB_MAN_C45_READ)
401 | MACB_BF(PHYA, mii_id)
402 | MACB_BF(REGA, devad & 0x1F)
403 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
404
405 status = macb_mdio_wait_for_idle(bp);
406 if (status < 0)
407 goto mdio_read_exit;
408
409 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
410
411 mdio_read_exit:
412 pm_runtime_mark_last_busy(&bp->pdev->dev);
413 pm_runtime_put_autosuspend(&bp->pdev->dev);
414 mdio_pm_exit:
415 return status;
416 }
417
macb_mdio_write_c22(struct mii_bus * bus,int mii_id,int regnum,u16 value)418 static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
419 u16 value)
420 {
421 struct macb *bp = bus->priv;
422 int status;
423
424 status = pm_runtime_resume_and_get(&bp->pdev->dev);
425 if (status < 0)
426 goto mdio_pm_exit;
427
428 status = macb_mdio_wait_for_idle(bp);
429 if (status < 0)
430 goto mdio_write_exit;
431
432 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
433 | MACB_BF(RW, MACB_MAN_C22_WRITE)
434 | MACB_BF(PHYA, mii_id)
435 | MACB_BF(REGA, regnum)
436 | MACB_BF(CODE, MACB_MAN_C22_CODE)
437 | MACB_BF(DATA, value)));
438
439 status = macb_mdio_wait_for_idle(bp);
440 if (status < 0)
441 goto mdio_write_exit;
442
443 mdio_write_exit:
444 pm_runtime_mark_last_busy(&bp->pdev->dev);
445 pm_runtime_put_autosuspend(&bp->pdev->dev);
446 mdio_pm_exit:
447 return status;
448 }
449
macb_mdio_write_c45(struct mii_bus * bus,int mii_id,int devad,int regnum,u16 value)450 static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id,
451 int devad, int regnum,
452 u16 value)
453 {
454 struct macb *bp = bus->priv;
455 int status;
456
457 status = pm_runtime_get_sync(&bp->pdev->dev);
458 if (status < 0) {
459 pm_runtime_put_noidle(&bp->pdev->dev);
460 goto mdio_pm_exit;
461 }
462
463 status = macb_mdio_wait_for_idle(bp);
464 if (status < 0)
465 goto mdio_write_exit;
466
467 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
468 | MACB_BF(RW, MACB_MAN_C45_ADDR)
469 | MACB_BF(PHYA, mii_id)
470 | MACB_BF(REGA, devad & 0x1F)
471 | MACB_BF(DATA, regnum & 0xFFFF)
472 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
473
474 status = macb_mdio_wait_for_idle(bp);
475 if (status < 0)
476 goto mdio_write_exit;
477
478 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
479 | MACB_BF(RW, MACB_MAN_C45_WRITE)
480 | MACB_BF(PHYA, mii_id)
481 | MACB_BF(REGA, devad & 0x1F)
482 | MACB_BF(CODE, MACB_MAN_C45_CODE)
483 | MACB_BF(DATA, value)));
484
485 status = macb_mdio_wait_for_idle(bp);
486 if (status < 0)
487 goto mdio_write_exit;
488
489 mdio_write_exit:
490 pm_runtime_mark_last_busy(&bp->pdev->dev);
491 pm_runtime_put_autosuspend(&bp->pdev->dev);
492 mdio_pm_exit:
493 return status;
494 }
495
macb_init_buffers(struct macb * bp)496 static void macb_init_buffers(struct macb *bp)
497 {
498 struct macb_queue *queue;
499 unsigned int q;
500
501 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
502 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
503 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
504 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
505 queue_writel(queue, RBQPH,
506 upper_32_bits(queue->rx_ring_dma));
507 #endif
508 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
509 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
510 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
511 queue_writel(queue, TBQPH,
512 upper_32_bits(queue->tx_ring_dma));
513 #endif
514 }
515 }
516
517 /**
518 * macb_set_tx_clk() - Set a clock to a new frequency
519 * @bp: pointer to struct macb
520 * @speed: New frequency in Hz
521 */
macb_set_tx_clk(struct macb * bp,int speed)522 static void macb_set_tx_clk(struct macb *bp, int speed)
523 {
524 long ferr, rate, rate_rounded;
525
526 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
527 return;
528
529 /* In case of MII the PHY is the clock master */
530 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
531 return;
532
533 switch (speed) {
534 case SPEED_10:
535 rate = 2500000;
536 break;
537 case SPEED_100:
538 rate = 25000000;
539 break;
540 case SPEED_1000:
541 rate = 125000000;
542 break;
543 default:
544 return;
545 }
546
547 rate_rounded = clk_round_rate(bp->tx_clk, rate);
548 if (rate_rounded < 0)
549 return;
550
551 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
552 * is not satisfied.
553 */
554 ferr = abs(rate_rounded - rate);
555 ferr = DIV_ROUND_UP(ferr, rate / 100000);
556 if (ferr > 5)
557 netdev_warn(bp->dev,
558 "unable to generate target frequency: %ld Hz\n",
559 rate);
560
561 if (clk_set_rate(bp->tx_clk, rate_rounded))
562 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
563 }
564
macb_usx_pcs_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)565 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
566 phy_interface_t interface, int speed,
567 int duplex)
568 {
569 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
570 u32 config;
571
572 config = gem_readl(bp, USX_CONTROL);
573 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
574 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
575 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
576 config |= GEM_BIT(TX_EN);
577 gem_writel(bp, USX_CONTROL, config);
578 }
579
macb_usx_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)580 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
581 struct phylink_link_state *state)
582 {
583 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
584 u32 val;
585
586 state->speed = SPEED_10000;
587 state->duplex = 1;
588 state->an_complete = 1;
589
590 val = gem_readl(bp, USX_STATUS);
591 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
592 val = gem_readl(bp, NCFGR);
593 if (val & GEM_BIT(PAE))
594 state->pause = MLO_PAUSE_RX;
595 }
596
macb_usx_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)597 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
598 unsigned int neg_mode,
599 phy_interface_t interface,
600 const unsigned long *advertising,
601 bool permit_pause_to_mac)
602 {
603 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
604
605 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
606 GEM_BIT(SIGNAL_OK));
607
608 return 0;
609 }
610
macb_pcs_get_state(struct phylink_pcs * pcs,struct phylink_link_state * state)611 static void macb_pcs_get_state(struct phylink_pcs *pcs,
612 struct phylink_link_state *state)
613 {
614 state->link = 0;
615 }
616
macb_pcs_an_restart(struct phylink_pcs * pcs)617 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
618 {
619 /* Not supported */
620 }
621
macb_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)622 static int macb_pcs_config(struct phylink_pcs *pcs,
623 unsigned int neg_mode,
624 phy_interface_t interface,
625 const unsigned long *advertising,
626 bool permit_pause_to_mac)
627 {
628 return 0;
629 }
630
631 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
632 .pcs_get_state = macb_usx_pcs_get_state,
633 .pcs_config = macb_usx_pcs_config,
634 .pcs_link_up = macb_usx_pcs_link_up,
635 };
636
637 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
638 .pcs_get_state = macb_pcs_get_state,
639 .pcs_an_restart = macb_pcs_an_restart,
640 .pcs_config = macb_pcs_config,
641 };
642
macb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)643 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
644 const struct phylink_link_state *state)
645 {
646 struct net_device *ndev = to_net_dev(config->dev);
647 struct macb *bp = netdev_priv(ndev);
648 unsigned long flags;
649 u32 old_ctrl, ctrl;
650 u32 old_ncr, ncr;
651
652 spin_lock_irqsave(&bp->lock, flags);
653
654 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
655 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
656
657 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
658 if (state->interface == PHY_INTERFACE_MODE_RMII)
659 ctrl |= MACB_BIT(RM9200_RMII);
660 } else if (macb_is_gem(bp)) {
661 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
662 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
663
664 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
665 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
666 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
667 ctrl |= GEM_BIT(PCSSEL);
668 ncr |= GEM_BIT(ENABLE_HS_MAC);
669 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
670 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
671 ncr |= MACB_BIT(MIIONRGMII);
672 }
673 }
674
675 /* Apply the new configuration, if any */
676 if (old_ctrl ^ ctrl)
677 macb_or_gem_writel(bp, NCFGR, ctrl);
678
679 if (old_ncr ^ ncr)
680 macb_or_gem_writel(bp, NCR, ncr);
681
682 /* Disable AN for SGMII fixed link configuration, enable otherwise.
683 * Must be written after PCSSEL is set in NCFGR,
684 * otherwise writes will not take effect.
685 */
686 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
687 u32 pcsctrl, old_pcsctrl;
688
689 old_pcsctrl = gem_readl(bp, PCSCNTRL);
690 if (mode == MLO_AN_FIXED)
691 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
692 else
693 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
694 if (old_pcsctrl != pcsctrl)
695 gem_writel(bp, PCSCNTRL, pcsctrl);
696 }
697
698 spin_unlock_irqrestore(&bp->lock, flags);
699 }
700
macb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)701 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
702 phy_interface_t interface)
703 {
704 struct net_device *ndev = to_net_dev(config->dev);
705 struct macb *bp = netdev_priv(ndev);
706 struct macb_queue *queue;
707 unsigned int q;
708 u32 ctrl;
709
710 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
711 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
712 queue_writel(queue, IDR,
713 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
714
715 /* Disable Rx and Tx */
716 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
717 macb_writel(bp, NCR, ctrl);
718
719 netif_tx_stop_all_queues(ndev);
720 }
721
macb_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)722 static void macb_mac_link_up(struct phylink_config *config,
723 struct phy_device *phy,
724 unsigned int mode, phy_interface_t interface,
725 int speed, int duplex,
726 bool tx_pause, bool rx_pause)
727 {
728 struct net_device *ndev = to_net_dev(config->dev);
729 struct macb *bp = netdev_priv(ndev);
730 struct macb_queue *queue;
731 unsigned long flags;
732 unsigned int q;
733 u32 ctrl;
734
735 spin_lock_irqsave(&bp->lock, flags);
736
737 ctrl = macb_or_gem_readl(bp, NCFGR);
738
739 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
740
741 if (speed == SPEED_100)
742 ctrl |= MACB_BIT(SPD);
743
744 if (duplex)
745 ctrl |= MACB_BIT(FD);
746
747 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
748 ctrl &= ~MACB_BIT(PAE);
749 if (macb_is_gem(bp)) {
750 ctrl &= ~GEM_BIT(GBE);
751
752 if (speed == SPEED_1000)
753 ctrl |= GEM_BIT(GBE);
754 }
755
756 if (rx_pause)
757 ctrl |= MACB_BIT(PAE);
758
759 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
760 * cleared the pipeline and control registers.
761 */
762 bp->macbgem_ops.mog_init_rings(bp);
763 macb_init_buffers(bp);
764
765 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
766 queue_writel(queue, IER,
767 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
768 }
769
770 macb_or_gem_writel(bp, NCFGR, ctrl);
771
772 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
773 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
774 gem_readl(bp, HS_MAC_CONFIG)));
775
776 spin_unlock_irqrestore(&bp->lock, flags);
777
778 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
779 macb_set_tx_clk(bp, speed);
780
781 /* Enable Rx and Tx; Enable PTP unicast */
782 ctrl = macb_readl(bp, NCR);
783 if (gem_has_ptp(bp))
784 ctrl |= MACB_BIT(PTPUNI);
785
786 macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));
787
788 netif_tx_wake_all_queues(ndev);
789 }
790
macb_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)791 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
792 phy_interface_t interface)
793 {
794 struct net_device *ndev = to_net_dev(config->dev);
795 struct macb *bp = netdev_priv(ndev);
796
797 if (interface == PHY_INTERFACE_MODE_10GBASER)
798 return &bp->phylink_usx_pcs;
799 else if (interface == PHY_INTERFACE_MODE_SGMII)
800 return &bp->phylink_sgmii_pcs;
801 else
802 return NULL;
803 }
804
805 static const struct phylink_mac_ops macb_phylink_ops = {
806 .mac_select_pcs = macb_mac_select_pcs,
807 .mac_config = macb_mac_config,
808 .mac_link_down = macb_mac_link_down,
809 .mac_link_up = macb_mac_link_up,
810 };
811
macb_phy_handle_exists(struct device_node * dn)812 static bool macb_phy_handle_exists(struct device_node *dn)
813 {
814 dn = of_parse_phandle(dn, "phy-handle", 0);
815 of_node_put(dn);
816 return dn != NULL;
817 }
818
macb_phylink_connect(struct macb * bp)819 static int macb_phylink_connect(struct macb *bp)
820 {
821 struct device_node *dn = bp->pdev->dev.of_node;
822 struct net_device *dev = bp->dev;
823 struct phy_device *phydev;
824 int ret;
825
826 if (dn)
827 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
828
829 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
830 phydev = phy_find_first(bp->mii_bus);
831 if (!phydev) {
832 netdev_err(dev, "no PHY found\n");
833 return -ENXIO;
834 }
835
836 /* attach the mac to the phy */
837 ret = phylink_connect_phy(bp->phylink, phydev);
838 }
839
840 if (ret) {
841 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
842 return ret;
843 }
844
845 phylink_start(bp->phylink);
846
847 return 0;
848 }
849
macb_get_pcs_fixed_state(struct phylink_config * config,struct phylink_link_state * state)850 static void macb_get_pcs_fixed_state(struct phylink_config *config,
851 struct phylink_link_state *state)
852 {
853 struct net_device *ndev = to_net_dev(config->dev);
854 struct macb *bp = netdev_priv(ndev);
855
856 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
857 }
858
859 /* based on au1000_eth. c*/
macb_mii_probe(struct net_device * dev)860 static int macb_mii_probe(struct net_device *dev)
861 {
862 struct macb *bp = netdev_priv(dev);
863
864 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
865 bp->phylink_sgmii_pcs.neg_mode = true;
866 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
867 bp->phylink_usx_pcs.neg_mode = true;
868
869 bp->phylink_config.dev = &dev->dev;
870 bp->phylink_config.type = PHYLINK_NETDEV;
871 bp->phylink_config.mac_managed_pm = true;
872
873 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
874 bp->phylink_config.poll_fixed_state = true;
875 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
876 }
877
878 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
879 MAC_10 | MAC_100;
880
881 __set_bit(PHY_INTERFACE_MODE_MII,
882 bp->phylink_config.supported_interfaces);
883 __set_bit(PHY_INTERFACE_MODE_RMII,
884 bp->phylink_config.supported_interfaces);
885
886 /* Determine what modes are supported */
887 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
888 bp->phylink_config.mac_capabilities |= MAC_1000FD;
889 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
890 bp->phylink_config.mac_capabilities |= MAC_1000HD;
891
892 __set_bit(PHY_INTERFACE_MODE_GMII,
893 bp->phylink_config.supported_interfaces);
894 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
895
896 if (bp->caps & MACB_CAPS_PCS)
897 __set_bit(PHY_INTERFACE_MODE_SGMII,
898 bp->phylink_config.supported_interfaces);
899
900 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
901 __set_bit(PHY_INTERFACE_MODE_10GBASER,
902 bp->phylink_config.supported_interfaces);
903 bp->phylink_config.mac_capabilities |= MAC_10000FD;
904 }
905 }
906
907 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
908 bp->phy_interface, &macb_phylink_ops);
909 if (IS_ERR(bp->phylink)) {
910 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
911 PTR_ERR(bp->phylink));
912 return PTR_ERR(bp->phylink);
913 }
914
915 return 0;
916 }
917
macb_mdiobus_register(struct macb * bp)918 static int macb_mdiobus_register(struct macb *bp)
919 {
920 struct device_node *child, *np = bp->pdev->dev.of_node;
921
922 /* If we have a child named mdio, probe it instead of looking for PHYs
923 * directly under the MAC node
924 */
925 child = of_get_child_by_name(np, "mdio");
926 if (child) {
927 int ret = of_mdiobus_register(bp->mii_bus, child);
928
929 of_node_put(child);
930 return ret;
931 }
932
933 if (of_phy_is_fixed_link(np))
934 return mdiobus_register(bp->mii_bus);
935
936 /* Only create the PHY from the device tree if at least one PHY is
937 * described. Otherwise scan the entire MDIO bus. We do this to support
938 * old device tree that did not follow the best practices and did not
939 * describe their network PHYs.
940 */
941 for_each_available_child_of_node(np, child)
942 if (of_mdiobus_child_is_phy(child)) {
943 /* The loop increments the child refcount,
944 * decrement it before returning.
945 */
946 of_node_put(child);
947
948 return of_mdiobus_register(bp->mii_bus, np);
949 }
950
951 return mdiobus_register(bp->mii_bus);
952 }
953
macb_mii_init(struct macb * bp)954 static int macb_mii_init(struct macb *bp)
955 {
956 int err = -ENXIO;
957
958 /* Enable management port */
959 macb_writel(bp, NCR, MACB_BIT(MPE));
960
961 bp->mii_bus = mdiobus_alloc();
962 if (!bp->mii_bus) {
963 err = -ENOMEM;
964 goto err_out;
965 }
966
967 bp->mii_bus->name = "MACB_mii_bus";
968 bp->mii_bus->read = &macb_mdio_read_c22;
969 bp->mii_bus->write = &macb_mdio_write_c22;
970 bp->mii_bus->read_c45 = &macb_mdio_read_c45;
971 bp->mii_bus->write_c45 = &macb_mdio_write_c45;
972 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
973 bp->pdev->name, bp->pdev->id);
974 bp->mii_bus->priv = bp;
975 bp->mii_bus->parent = &bp->pdev->dev;
976
977 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
978
979 err = macb_mdiobus_register(bp);
980 if (err)
981 goto err_out_free_mdiobus;
982
983 err = macb_mii_probe(bp->dev);
984 if (err)
985 goto err_out_unregister_bus;
986
987 return 0;
988
989 err_out_unregister_bus:
990 mdiobus_unregister(bp->mii_bus);
991 err_out_free_mdiobus:
992 mdiobus_free(bp->mii_bus);
993 err_out:
994 return err;
995 }
996
macb_update_stats(struct macb * bp)997 static void macb_update_stats(struct macb *bp)
998 {
999 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
1000 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
1001 int offset = MACB_PFR;
1002
1003 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
1004
1005 for (; p < end; p++, offset += 4)
1006 *p += bp->macb_reg_readl(bp, offset);
1007 }
1008
macb_halt_tx(struct macb * bp)1009 static int macb_halt_tx(struct macb *bp)
1010 {
1011 unsigned long halt_time, timeout;
1012 u32 status;
1013
1014 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
1015
1016 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
1017 do {
1018 halt_time = jiffies;
1019 status = macb_readl(bp, TSR);
1020 if (!(status & MACB_BIT(TGO)))
1021 return 0;
1022
1023 udelay(250);
1024 } while (time_before(halt_time, timeout));
1025
1026 return -ETIMEDOUT;
1027 }
1028
macb_tx_unmap(struct macb * bp,struct macb_tx_skb * tx_skb,int budget)1029 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
1030 {
1031 if (tx_skb->mapping) {
1032 if (tx_skb->mapped_as_page)
1033 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
1034 tx_skb->size, DMA_TO_DEVICE);
1035 else
1036 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
1037 tx_skb->size, DMA_TO_DEVICE);
1038 tx_skb->mapping = 0;
1039 }
1040
1041 if (tx_skb->skb) {
1042 napi_consume_skb(tx_skb->skb, budget);
1043 tx_skb->skb = NULL;
1044 }
1045 }
1046
macb_set_addr(struct macb * bp,struct macb_dma_desc * desc,dma_addr_t addr)1047 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
1048 {
1049 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1050 struct macb_dma_desc_64 *desc_64;
1051
1052 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1053 desc_64 = macb_64b_desc(bp, desc);
1054 desc_64->addrh = upper_32_bits(addr);
1055 /* The low bits of RX address contain the RX_USED bit, clearing
1056 * of which allows packet RX. Make sure the high bits are also
1057 * visible to HW at that point.
1058 */
1059 dma_wmb();
1060 }
1061 #endif
1062 desc->addr = lower_32_bits(addr);
1063 }
1064
macb_get_addr(struct macb * bp,struct macb_dma_desc * desc)1065 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1066 {
1067 dma_addr_t addr = 0;
1068 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1069 struct macb_dma_desc_64 *desc_64;
1070
1071 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1072 desc_64 = macb_64b_desc(bp, desc);
1073 addr = ((u64)(desc_64->addrh) << 32);
1074 }
1075 #endif
1076 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1077 #ifdef CONFIG_MACB_USE_HWSTAMP
1078 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
1079 addr &= ~GEM_BIT(DMA_RXVALID);
1080 #endif
1081 return addr;
1082 }
1083
macb_tx_error_task(struct work_struct * work)1084 static void macb_tx_error_task(struct work_struct *work)
1085 {
1086 struct macb_queue *queue = container_of(work, struct macb_queue,
1087 tx_error_task);
1088 bool halt_timeout = false;
1089 struct macb *bp = queue->bp;
1090 struct macb_tx_skb *tx_skb;
1091 struct macb_dma_desc *desc;
1092 struct sk_buff *skb;
1093 unsigned int tail;
1094 unsigned long flags;
1095
1096 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1097 (unsigned int)(queue - bp->queues),
1098 queue->tx_tail, queue->tx_head);
1099
1100 /* Prevent the queue NAPI TX poll from running, as it calls
1101 * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1102 * As explained below, we have to halt the transmission before updating
1103 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1104 * network engine about the macb/gem being halted.
1105 */
1106 napi_disable(&queue->napi_tx);
1107 spin_lock_irqsave(&bp->lock, flags);
1108
1109 /* Make sure nobody is trying to queue up new packets */
1110 netif_tx_stop_all_queues(bp->dev);
1111
1112 /* Stop transmission now
1113 * (in case we have just queued new packets)
1114 * macb/gem must be halted to write TBQP register
1115 */
1116 if (macb_halt_tx(bp)) {
1117 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1118 macb_writel(bp, NCR, macb_readl(bp, NCR) & (~MACB_BIT(TE)));
1119 halt_timeout = true;
1120 }
1121
1122 /* Treat frames in TX queue including the ones that caused the error.
1123 * Free transmit buffers in upper layer.
1124 */
1125 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1126 u32 ctrl;
1127
1128 desc = macb_tx_desc(queue, tail);
1129 ctrl = desc->ctrl;
1130 tx_skb = macb_tx_skb(queue, tail);
1131 skb = tx_skb->skb;
1132
1133 if (ctrl & MACB_BIT(TX_USED)) {
1134 /* skb is set for the last buffer of the frame */
1135 while (!skb) {
1136 macb_tx_unmap(bp, tx_skb, 0);
1137 tail++;
1138 tx_skb = macb_tx_skb(queue, tail);
1139 skb = tx_skb->skb;
1140 }
1141
1142 /* ctrl still refers to the first buffer descriptor
1143 * since it's the only one written back by the hardware
1144 */
1145 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1146 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1147 macb_tx_ring_wrap(bp, tail),
1148 skb->data);
1149 bp->dev->stats.tx_packets++;
1150 queue->stats.tx_packets++;
1151 bp->dev->stats.tx_bytes += skb->len;
1152 queue->stats.tx_bytes += skb->len;
1153 }
1154 } else {
1155 /* "Buffers exhausted mid-frame" errors may only happen
1156 * if the driver is buggy, so complain loudly about
1157 * those. Statistics are updated by hardware.
1158 */
1159 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1160 netdev_err(bp->dev,
1161 "BUG: TX buffers exhausted mid-frame\n");
1162
1163 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1164 }
1165
1166 macb_tx_unmap(bp, tx_skb, 0);
1167 }
1168
1169 /* Set end of TX queue */
1170 desc = macb_tx_desc(queue, 0);
1171 macb_set_addr(bp, desc, 0);
1172 desc->ctrl = MACB_BIT(TX_USED);
1173
1174 /* Make descriptor updates visible to hardware */
1175 wmb();
1176
1177 /* Reinitialize the TX desc queue */
1178 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1179 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1180 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1181 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1182 #endif
1183 /* Make TX ring reflect state of hardware */
1184 queue->tx_head = 0;
1185 queue->tx_tail = 0;
1186
1187 /* Housework before enabling TX IRQ */
1188 macb_writel(bp, TSR, macb_readl(bp, TSR));
1189 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1190
1191 if (halt_timeout)
1192 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
1193
1194 /* Now we are ready to start transmission again */
1195 netif_tx_start_all_queues(bp->dev);
1196 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1197
1198 spin_unlock_irqrestore(&bp->lock, flags);
1199 napi_enable(&queue->napi_tx);
1200 }
1201
ptp_one_step_sync(struct sk_buff * skb)1202 static bool ptp_one_step_sync(struct sk_buff *skb)
1203 {
1204 struct ptp_header *hdr;
1205 unsigned int ptp_class;
1206 u8 msgtype;
1207
1208 /* No need to parse packet if PTP TS is not involved */
1209 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1210 goto not_oss;
1211
1212 /* Identify and return whether PTP one step sync is being processed */
1213 ptp_class = ptp_classify_raw(skb);
1214 if (ptp_class == PTP_CLASS_NONE)
1215 goto not_oss;
1216
1217 hdr = ptp_parse_header(skb, ptp_class);
1218 if (!hdr)
1219 goto not_oss;
1220
1221 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
1222 goto not_oss;
1223
1224 msgtype = ptp_get_msgtype(hdr, ptp_class);
1225 if (msgtype == PTP_MSGTYPE_SYNC)
1226 return true;
1227
1228 not_oss:
1229 return false;
1230 }
1231
macb_tx_complete(struct macb_queue * queue,int budget)1232 static int macb_tx_complete(struct macb_queue *queue, int budget)
1233 {
1234 struct macb *bp = queue->bp;
1235 u16 queue_index = queue - bp->queues;
1236 unsigned int tail;
1237 unsigned int head;
1238 int packets = 0;
1239
1240 spin_lock(&queue->tx_ptr_lock);
1241 head = queue->tx_head;
1242 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1243 struct macb_tx_skb *tx_skb;
1244 struct sk_buff *skb;
1245 struct macb_dma_desc *desc;
1246 u32 ctrl;
1247
1248 desc = macb_tx_desc(queue, tail);
1249
1250 /* Make hw descriptor updates visible to CPU */
1251 rmb();
1252
1253 ctrl = desc->ctrl;
1254
1255 /* TX_USED bit is only set by hardware on the very first buffer
1256 * descriptor of the transmitted frame.
1257 */
1258 if (!(ctrl & MACB_BIT(TX_USED)))
1259 break;
1260
1261 /* Process all buffers of the current transmitted frame */
1262 for (;; tail++) {
1263 tx_skb = macb_tx_skb(queue, tail);
1264 skb = tx_skb->skb;
1265
1266 /* First, update TX stats if needed */
1267 if (skb) {
1268 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1269 !ptp_one_step_sync(skb))
1270 gem_ptp_do_txstamp(bp, skb, desc);
1271
1272 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1273 macb_tx_ring_wrap(bp, tail),
1274 skb->data);
1275 bp->dev->stats.tx_packets++;
1276 queue->stats.tx_packets++;
1277 bp->dev->stats.tx_bytes += skb->len;
1278 queue->stats.tx_bytes += skb->len;
1279 packets++;
1280 }
1281
1282 /* Now we can safely release resources */
1283 macb_tx_unmap(bp, tx_skb, budget);
1284
1285 /* skb is set only for the last buffer of the frame.
1286 * WARNING: at this point skb has been freed by
1287 * macb_tx_unmap().
1288 */
1289 if (skb)
1290 break;
1291 }
1292 }
1293
1294 queue->tx_tail = tail;
1295 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1296 CIRC_CNT(queue->tx_head, queue->tx_tail,
1297 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1298 netif_wake_subqueue(bp->dev, queue_index);
1299 spin_unlock(&queue->tx_ptr_lock);
1300
1301 return packets;
1302 }
1303
gem_rx_refill(struct macb_queue * queue)1304 static void gem_rx_refill(struct macb_queue *queue)
1305 {
1306 unsigned int entry;
1307 struct sk_buff *skb;
1308 dma_addr_t paddr;
1309 struct macb *bp = queue->bp;
1310 struct macb_dma_desc *desc;
1311
1312 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1313 bp->rx_ring_size) > 0) {
1314 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1315
1316 /* Make hw descriptor updates visible to CPU */
1317 rmb();
1318
1319 desc = macb_rx_desc(queue, entry);
1320
1321 if (!queue->rx_skbuff[entry]) {
1322 /* allocate sk_buff for this free entry in ring */
1323 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1324 if (unlikely(!skb)) {
1325 netdev_err(bp->dev,
1326 "Unable to allocate sk_buff\n");
1327 break;
1328 }
1329
1330 /* now fill corresponding descriptor entry */
1331 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1332 bp->rx_buffer_size,
1333 DMA_FROM_DEVICE);
1334 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1335 dev_kfree_skb(skb);
1336 break;
1337 }
1338
1339 queue->rx_skbuff[entry] = skb;
1340
1341 if (entry == bp->rx_ring_size - 1)
1342 paddr |= MACB_BIT(RX_WRAP);
1343 desc->ctrl = 0;
1344 /* Setting addr clears RX_USED and allows reception,
1345 * make sure ctrl is cleared first to avoid a race.
1346 */
1347 dma_wmb();
1348 macb_set_addr(bp, desc, paddr);
1349
1350 /* properly align Ethernet header */
1351 skb_reserve(skb, NET_IP_ALIGN);
1352 } else {
1353 desc->ctrl = 0;
1354 dma_wmb();
1355 desc->addr &= ~MACB_BIT(RX_USED);
1356 }
1357 queue->rx_prepared_head++;
1358 }
1359
1360 /* Make descriptor updates visible to hardware */
1361 wmb();
1362
1363 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1364 queue, queue->rx_prepared_head, queue->rx_tail);
1365 }
1366
1367 /* Mark DMA descriptors from begin up to and not including end as unused */
discard_partial_frame(struct macb_queue * queue,unsigned int begin,unsigned int end)1368 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1369 unsigned int end)
1370 {
1371 unsigned int frag;
1372
1373 for (frag = begin; frag != end; frag++) {
1374 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1375
1376 desc->addr &= ~MACB_BIT(RX_USED);
1377 }
1378
1379 /* Make descriptor updates visible to hardware */
1380 wmb();
1381
1382 /* When this happens, the hardware stats registers for
1383 * whatever caused this is updated, so we don't have to record
1384 * anything.
1385 */
1386 }
1387
gem_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)1388 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1389 int budget)
1390 {
1391 struct macb *bp = queue->bp;
1392 unsigned int len;
1393 unsigned int entry;
1394 struct sk_buff *skb;
1395 struct macb_dma_desc *desc;
1396 int count = 0;
1397
1398 while (count < budget) {
1399 u32 ctrl;
1400 dma_addr_t addr;
1401 bool rxused;
1402
1403 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1404 desc = macb_rx_desc(queue, entry);
1405
1406 /* Make hw descriptor updates visible to CPU */
1407 rmb();
1408
1409 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1410 addr = macb_get_addr(bp, desc);
1411
1412 if (!rxused)
1413 break;
1414
1415 /* Ensure ctrl is at least as up-to-date as rxused */
1416 dma_rmb();
1417
1418 ctrl = desc->ctrl;
1419
1420 queue->rx_tail++;
1421 count++;
1422
1423 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1424 netdev_err(bp->dev,
1425 "not whole frame pointed by descriptor\n");
1426 bp->dev->stats.rx_dropped++;
1427 queue->stats.rx_dropped++;
1428 break;
1429 }
1430 skb = queue->rx_skbuff[entry];
1431 if (unlikely(!skb)) {
1432 netdev_err(bp->dev,
1433 "inconsistent Rx descriptor chain\n");
1434 bp->dev->stats.rx_dropped++;
1435 queue->stats.rx_dropped++;
1436 break;
1437 }
1438 /* now everything is ready for receiving packet */
1439 queue->rx_skbuff[entry] = NULL;
1440 len = ctrl & bp->rx_frm_len_mask;
1441
1442 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1443
1444 skb_put(skb, len);
1445 dma_unmap_single(&bp->pdev->dev, addr,
1446 bp->rx_buffer_size, DMA_FROM_DEVICE);
1447
1448 skb->protocol = eth_type_trans(skb, bp->dev);
1449 skb_checksum_none_assert(skb);
1450 if (bp->dev->features & NETIF_F_RXCSUM &&
1451 !(bp->dev->flags & IFF_PROMISC) &&
1452 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1453 skb->ip_summed = CHECKSUM_UNNECESSARY;
1454
1455 bp->dev->stats.rx_packets++;
1456 queue->stats.rx_packets++;
1457 bp->dev->stats.rx_bytes += skb->len;
1458 queue->stats.rx_bytes += skb->len;
1459
1460 gem_ptp_do_rxstamp(bp, skb, desc);
1461
1462 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1463 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1464 skb->len, skb->csum);
1465 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1466 skb_mac_header(skb), 16, true);
1467 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1468 skb->data, 32, true);
1469 #endif
1470
1471 napi_gro_receive(napi, skb);
1472 }
1473
1474 gem_rx_refill(queue);
1475
1476 return count;
1477 }
1478
macb_rx_frame(struct macb_queue * queue,struct napi_struct * napi,unsigned int first_frag,unsigned int last_frag)1479 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1480 unsigned int first_frag, unsigned int last_frag)
1481 {
1482 unsigned int len;
1483 unsigned int frag;
1484 unsigned int offset;
1485 struct sk_buff *skb;
1486 struct macb_dma_desc *desc;
1487 struct macb *bp = queue->bp;
1488
1489 desc = macb_rx_desc(queue, last_frag);
1490 len = desc->ctrl & bp->rx_frm_len_mask;
1491
1492 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1493 macb_rx_ring_wrap(bp, first_frag),
1494 macb_rx_ring_wrap(bp, last_frag), len);
1495
1496 /* The ethernet header starts NET_IP_ALIGN bytes into the
1497 * first buffer. Since the header is 14 bytes, this makes the
1498 * payload word-aligned.
1499 *
1500 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1501 * the two padding bytes into the skb so that we avoid hitting
1502 * the slowpath in memcpy(), and pull them off afterwards.
1503 */
1504 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1505 if (!skb) {
1506 bp->dev->stats.rx_dropped++;
1507 for (frag = first_frag; ; frag++) {
1508 desc = macb_rx_desc(queue, frag);
1509 desc->addr &= ~MACB_BIT(RX_USED);
1510 if (frag == last_frag)
1511 break;
1512 }
1513
1514 /* Make descriptor updates visible to hardware */
1515 wmb();
1516
1517 return 1;
1518 }
1519
1520 offset = 0;
1521 len += NET_IP_ALIGN;
1522 skb_checksum_none_assert(skb);
1523 skb_put(skb, len);
1524
1525 for (frag = first_frag; ; frag++) {
1526 unsigned int frag_len = bp->rx_buffer_size;
1527
1528 if (offset + frag_len > len) {
1529 if (unlikely(frag != last_frag)) {
1530 dev_kfree_skb_any(skb);
1531 return -1;
1532 }
1533 frag_len = len - offset;
1534 }
1535 skb_copy_to_linear_data_offset(skb, offset,
1536 macb_rx_buffer(queue, frag),
1537 frag_len);
1538 offset += bp->rx_buffer_size;
1539 desc = macb_rx_desc(queue, frag);
1540 desc->addr &= ~MACB_BIT(RX_USED);
1541
1542 if (frag == last_frag)
1543 break;
1544 }
1545
1546 /* Make descriptor updates visible to hardware */
1547 wmb();
1548
1549 __skb_pull(skb, NET_IP_ALIGN);
1550 skb->protocol = eth_type_trans(skb, bp->dev);
1551
1552 bp->dev->stats.rx_packets++;
1553 bp->dev->stats.rx_bytes += skb->len;
1554 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1555 skb->len, skb->csum);
1556 napi_gro_receive(napi, skb);
1557
1558 return 0;
1559 }
1560
macb_init_rx_ring(struct macb_queue * queue)1561 static inline void macb_init_rx_ring(struct macb_queue *queue)
1562 {
1563 struct macb *bp = queue->bp;
1564 dma_addr_t addr;
1565 struct macb_dma_desc *desc = NULL;
1566 int i;
1567
1568 addr = queue->rx_buffers_dma;
1569 for (i = 0; i < bp->rx_ring_size; i++) {
1570 desc = macb_rx_desc(queue, i);
1571 macb_set_addr(bp, desc, addr);
1572 desc->ctrl = 0;
1573 addr += bp->rx_buffer_size;
1574 }
1575 desc->addr |= MACB_BIT(RX_WRAP);
1576 queue->rx_tail = 0;
1577 }
1578
macb_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)1579 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1580 int budget)
1581 {
1582 struct macb *bp = queue->bp;
1583 bool reset_rx_queue = false;
1584 int received = 0;
1585 unsigned int tail;
1586 int first_frag = -1;
1587
1588 for (tail = queue->rx_tail; budget > 0; tail++) {
1589 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1590 u32 ctrl;
1591
1592 /* Make hw descriptor updates visible to CPU */
1593 rmb();
1594
1595 if (!(desc->addr & MACB_BIT(RX_USED)))
1596 break;
1597
1598 /* Ensure ctrl is at least as up-to-date as addr */
1599 dma_rmb();
1600
1601 ctrl = desc->ctrl;
1602
1603 if (ctrl & MACB_BIT(RX_SOF)) {
1604 if (first_frag != -1)
1605 discard_partial_frame(queue, first_frag, tail);
1606 first_frag = tail;
1607 }
1608
1609 if (ctrl & MACB_BIT(RX_EOF)) {
1610 int dropped;
1611
1612 if (unlikely(first_frag == -1)) {
1613 reset_rx_queue = true;
1614 continue;
1615 }
1616
1617 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1618 first_frag = -1;
1619 if (unlikely(dropped < 0)) {
1620 reset_rx_queue = true;
1621 continue;
1622 }
1623 if (!dropped) {
1624 received++;
1625 budget--;
1626 }
1627 }
1628 }
1629
1630 if (unlikely(reset_rx_queue)) {
1631 unsigned long flags;
1632 u32 ctrl;
1633
1634 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1635
1636 spin_lock_irqsave(&bp->lock, flags);
1637
1638 ctrl = macb_readl(bp, NCR);
1639 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1640
1641 macb_init_rx_ring(queue);
1642 queue_writel(queue, RBQP, queue->rx_ring_dma);
1643
1644 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1645
1646 spin_unlock_irqrestore(&bp->lock, flags);
1647 return received;
1648 }
1649
1650 if (first_frag != -1)
1651 queue->rx_tail = first_frag;
1652 else
1653 queue->rx_tail = tail;
1654
1655 return received;
1656 }
1657
macb_rx_pending(struct macb_queue * queue)1658 static bool macb_rx_pending(struct macb_queue *queue)
1659 {
1660 struct macb *bp = queue->bp;
1661 unsigned int entry;
1662 struct macb_dma_desc *desc;
1663
1664 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1665 desc = macb_rx_desc(queue, entry);
1666
1667 /* Make hw descriptor updates visible to CPU */
1668 rmb();
1669
1670 return (desc->addr & MACB_BIT(RX_USED)) != 0;
1671 }
1672
macb_rx_poll(struct napi_struct * napi,int budget)1673 static int macb_rx_poll(struct napi_struct *napi, int budget)
1674 {
1675 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1676 struct macb *bp = queue->bp;
1677 int work_done;
1678
1679 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1680
1681 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
1682 (unsigned int)(queue - bp->queues), work_done, budget);
1683
1684 if (work_done < budget && napi_complete_done(napi, work_done)) {
1685 queue_writel(queue, IER, bp->rx_intr_mask);
1686
1687 /* Packet completions only seem to propagate to raise
1688 * interrupts when interrupts are enabled at the time, so if
1689 * packets were received while interrupts were disabled,
1690 * they will not cause another interrupt to be generated when
1691 * interrupts are re-enabled.
1692 * Check for this case here to avoid losing a wakeup. This can
1693 * potentially race with the interrupt handler doing the same
1694 * actions if an interrupt is raised just after enabling them,
1695 * but this should be harmless.
1696 */
1697 if (macb_rx_pending(queue)) {
1698 queue_writel(queue, IDR, bp->rx_intr_mask);
1699 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1700 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1701 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
1702 napi_schedule(napi);
1703 }
1704 }
1705
1706 /* TODO: Handle errors */
1707
1708 return work_done;
1709 }
1710
macb_tx_restart(struct macb_queue * queue)1711 static void macb_tx_restart(struct macb_queue *queue)
1712 {
1713 struct macb *bp = queue->bp;
1714 unsigned int head_idx, tbqp;
1715
1716 spin_lock(&queue->tx_ptr_lock);
1717
1718 if (queue->tx_head == queue->tx_tail)
1719 goto out_tx_ptr_unlock;
1720
1721 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1722 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1723 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head));
1724
1725 if (tbqp == head_idx)
1726 goto out_tx_ptr_unlock;
1727
1728 spin_lock_irq(&bp->lock);
1729 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1730 spin_unlock_irq(&bp->lock);
1731
1732 out_tx_ptr_unlock:
1733 spin_unlock(&queue->tx_ptr_lock);
1734 }
1735
macb_tx_complete_pending(struct macb_queue * queue)1736 static bool macb_tx_complete_pending(struct macb_queue *queue)
1737 {
1738 bool retval = false;
1739
1740 spin_lock(&queue->tx_ptr_lock);
1741 if (queue->tx_head != queue->tx_tail) {
1742 /* Make hw descriptor updates visible to CPU */
1743 rmb();
1744
1745 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1746 retval = true;
1747 }
1748 spin_unlock(&queue->tx_ptr_lock);
1749 return retval;
1750 }
1751
macb_tx_poll(struct napi_struct * napi,int budget)1752 static int macb_tx_poll(struct napi_struct *napi, int budget)
1753 {
1754 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1755 struct macb *bp = queue->bp;
1756 int work_done;
1757
1758 work_done = macb_tx_complete(queue, budget);
1759
1760 rmb(); // ensure txubr_pending is up to date
1761 if (queue->txubr_pending) {
1762 queue->txubr_pending = false;
1763 netdev_vdbg(bp->dev, "poll: tx restart\n");
1764 macb_tx_restart(queue);
1765 }
1766
1767 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1768 (unsigned int)(queue - bp->queues), work_done, budget);
1769
1770 if (work_done < budget && napi_complete_done(napi, work_done)) {
1771 queue_writel(queue, IER, MACB_BIT(TCOMP));
1772
1773 /* Packet completions only seem to propagate to raise
1774 * interrupts when interrupts are enabled at the time, so if
1775 * packets were sent while interrupts were disabled,
1776 * they will not cause another interrupt to be generated when
1777 * interrupts are re-enabled.
1778 * Check for this case here to avoid losing a wakeup. This can
1779 * potentially race with the interrupt handler doing the same
1780 * actions if an interrupt is raised just after enabling them,
1781 * but this should be harmless.
1782 */
1783 if (macb_tx_complete_pending(queue)) {
1784 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1785 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1786 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1787 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1788 napi_schedule(napi);
1789 }
1790 }
1791
1792 return work_done;
1793 }
1794
macb_hresp_error_task(struct work_struct * work)1795 static void macb_hresp_error_task(struct work_struct *work)
1796 {
1797 struct macb *bp = from_work(bp, work, hresp_err_bh_work);
1798 struct net_device *dev = bp->dev;
1799 struct macb_queue *queue;
1800 unsigned int q;
1801 u32 ctrl;
1802
1803 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1804 queue_writel(queue, IDR, bp->rx_intr_mask |
1805 MACB_TX_INT_FLAGS |
1806 MACB_BIT(HRESP));
1807 }
1808 ctrl = macb_readl(bp, NCR);
1809 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1810 macb_writel(bp, NCR, ctrl);
1811
1812 netif_tx_stop_all_queues(dev);
1813 netif_carrier_off(dev);
1814
1815 bp->macbgem_ops.mog_init_rings(bp);
1816
1817 /* Initialize TX and RX buffers */
1818 macb_init_buffers(bp);
1819
1820 /* Enable interrupts */
1821 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1822 queue_writel(queue, IER,
1823 bp->rx_intr_mask |
1824 MACB_TX_INT_FLAGS |
1825 MACB_BIT(HRESP));
1826
1827 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1828 macb_writel(bp, NCR, ctrl);
1829
1830 netif_carrier_on(dev);
1831 netif_tx_start_all_queues(dev);
1832 }
1833
macb_wol_interrupt(int irq,void * dev_id)1834 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1835 {
1836 struct macb_queue *queue = dev_id;
1837 struct macb *bp = queue->bp;
1838 u32 status;
1839
1840 status = queue_readl(queue, ISR);
1841
1842 if (unlikely(!status))
1843 return IRQ_NONE;
1844
1845 spin_lock(&bp->lock);
1846
1847 if (status & MACB_BIT(WOL)) {
1848 queue_writel(queue, IDR, MACB_BIT(WOL));
1849 macb_writel(bp, WOL, 0);
1850 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1851 (unsigned int)(queue - bp->queues),
1852 (unsigned long)status);
1853 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1854 queue_writel(queue, ISR, MACB_BIT(WOL));
1855 pm_wakeup_event(&bp->pdev->dev, 0);
1856 }
1857
1858 spin_unlock(&bp->lock);
1859
1860 return IRQ_HANDLED;
1861 }
1862
gem_wol_interrupt(int irq,void * dev_id)1863 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1864 {
1865 struct macb_queue *queue = dev_id;
1866 struct macb *bp = queue->bp;
1867 u32 status;
1868
1869 status = queue_readl(queue, ISR);
1870
1871 if (unlikely(!status))
1872 return IRQ_NONE;
1873
1874 spin_lock(&bp->lock);
1875
1876 if (status & GEM_BIT(WOL)) {
1877 queue_writel(queue, IDR, GEM_BIT(WOL));
1878 gem_writel(bp, WOL, 0);
1879 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1880 (unsigned int)(queue - bp->queues),
1881 (unsigned long)status);
1882 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1883 queue_writel(queue, ISR, GEM_BIT(WOL));
1884 pm_wakeup_event(&bp->pdev->dev, 0);
1885 }
1886
1887 spin_unlock(&bp->lock);
1888
1889 return IRQ_HANDLED;
1890 }
1891
macb_interrupt(int irq,void * dev_id)1892 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1893 {
1894 struct macb_queue *queue = dev_id;
1895 struct macb *bp = queue->bp;
1896 struct net_device *dev = bp->dev;
1897 u32 status, ctrl;
1898
1899 status = queue_readl(queue, ISR);
1900
1901 if (unlikely(!status))
1902 return IRQ_NONE;
1903
1904 spin_lock(&bp->lock);
1905
1906 while (status) {
1907 /* close possible race with dev_close */
1908 if (unlikely(!netif_running(dev))) {
1909 queue_writel(queue, IDR, -1);
1910 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1911 queue_writel(queue, ISR, -1);
1912 break;
1913 }
1914
1915 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1916 (unsigned int)(queue - bp->queues),
1917 (unsigned long)status);
1918
1919 if (status & bp->rx_intr_mask) {
1920 /* There's no point taking any more interrupts
1921 * until we have processed the buffers. The
1922 * scheduling call may fail if the poll routine
1923 * is already scheduled, so disable interrupts
1924 * now.
1925 */
1926 queue_writel(queue, IDR, bp->rx_intr_mask);
1927 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1928 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1929
1930 if (napi_schedule_prep(&queue->napi_rx)) {
1931 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1932 __napi_schedule(&queue->napi_rx);
1933 }
1934 }
1935
1936 if (status & (MACB_BIT(TCOMP) |
1937 MACB_BIT(TXUBR))) {
1938 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1939 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1940 queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1941 MACB_BIT(TXUBR));
1942
1943 if (status & MACB_BIT(TXUBR)) {
1944 queue->txubr_pending = true;
1945 wmb(); // ensure softirq can see update
1946 }
1947
1948 if (napi_schedule_prep(&queue->napi_tx)) {
1949 netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1950 __napi_schedule(&queue->napi_tx);
1951 }
1952 }
1953
1954 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1955 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1956 schedule_work(&queue->tx_error_task);
1957
1958 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1959 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1960
1961 break;
1962 }
1963
1964 /* Link change detection isn't possible with RMII, so we'll
1965 * add that if/when we get our hands on a full-blown MII PHY.
1966 */
1967
1968 /* There is a hardware issue under heavy load where DMA can
1969 * stop, this causes endless "used buffer descriptor read"
1970 * interrupts but it can be cleared by re-enabling RX. See
1971 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1972 * section 16.7.4 for details. RXUBR is only enabled for
1973 * these two versions.
1974 */
1975 if (status & MACB_BIT(RXUBR)) {
1976 ctrl = macb_readl(bp, NCR);
1977 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1978 wmb();
1979 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1980
1981 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1982 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1983 }
1984
1985 if (status & MACB_BIT(ISR_ROVR)) {
1986 /* We missed at least one packet */
1987 if (macb_is_gem(bp))
1988 bp->hw_stats.gem.rx_overruns++;
1989 else
1990 bp->hw_stats.macb.rx_overruns++;
1991
1992 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1993 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1994 }
1995
1996 if (status & MACB_BIT(HRESP)) {
1997 queue_work(system_bh_wq, &bp->hresp_err_bh_work);
1998 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1999
2000 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2001 queue_writel(queue, ISR, MACB_BIT(HRESP));
2002 }
2003 status = queue_readl(queue, ISR);
2004 }
2005
2006 spin_unlock(&bp->lock);
2007
2008 return IRQ_HANDLED;
2009 }
2010
2011 #ifdef CONFIG_NET_POLL_CONTROLLER
2012 /* Polling receive - used by netconsole and other diagnostic tools
2013 * to allow network i/o with interrupts disabled.
2014 */
macb_poll_controller(struct net_device * dev)2015 static void macb_poll_controller(struct net_device *dev)
2016 {
2017 struct macb *bp = netdev_priv(dev);
2018 struct macb_queue *queue;
2019 unsigned long flags;
2020 unsigned int q;
2021
2022 local_irq_save(flags);
2023 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2024 macb_interrupt(dev->irq, queue);
2025 local_irq_restore(flags);
2026 }
2027 #endif
2028
macb_tx_map(struct macb * bp,struct macb_queue * queue,struct sk_buff * skb,unsigned int hdrlen)2029 static unsigned int macb_tx_map(struct macb *bp,
2030 struct macb_queue *queue,
2031 struct sk_buff *skb,
2032 unsigned int hdrlen)
2033 {
2034 dma_addr_t mapping;
2035 unsigned int len, entry, i, tx_head = queue->tx_head;
2036 struct macb_tx_skb *tx_skb = NULL;
2037 struct macb_dma_desc *desc;
2038 unsigned int offset, size, count = 0;
2039 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
2040 unsigned int eof = 1, mss_mfs = 0;
2041 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
2042
2043 /* LSO */
2044 if (skb_shinfo(skb)->gso_size != 0) {
2045 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2046 /* UDP - UFO */
2047 lso_ctrl = MACB_LSO_UFO_ENABLE;
2048 else
2049 /* TCP - TSO */
2050 lso_ctrl = MACB_LSO_TSO_ENABLE;
2051 }
2052
2053 /* First, map non-paged data */
2054 len = skb_headlen(skb);
2055
2056 /* first buffer length */
2057 size = hdrlen;
2058
2059 offset = 0;
2060 while (len) {
2061 entry = macb_tx_ring_wrap(bp, tx_head);
2062 tx_skb = &queue->tx_skb[entry];
2063
2064 mapping = dma_map_single(&bp->pdev->dev,
2065 skb->data + offset,
2066 size, DMA_TO_DEVICE);
2067 if (dma_mapping_error(&bp->pdev->dev, mapping))
2068 goto dma_error;
2069
2070 /* Save info to properly release resources */
2071 tx_skb->skb = NULL;
2072 tx_skb->mapping = mapping;
2073 tx_skb->size = size;
2074 tx_skb->mapped_as_page = false;
2075
2076 len -= size;
2077 offset += size;
2078 count++;
2079 tx_head++;
2080
2081 size = min(len, bp->max_tx_length);
2082 }
2083
2084 /* Then, map paged data from fragments */
2085 for (f = 0; f < nr_frags; f++) {
2086 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2087
2088 len = skb_frag_size(frag);
2089 offset = 0;
2090 while (len) {
2091 size = min(len, bp->max_tx_length);
2092 entry = macb_tx_ring_wrap(bp, tx_head);
2093 tx_skb = &queue->tx_skb[entry];
2094
2095 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2096 offset, size, DMA_TO_DEVICE);
2097 if (dma_mapping_error(&bp->pdev->dev, mapping))
2098 goto dma_error;
2099
2100 /* Save info to properly release resources */
2101 tx_skb->skb = NULL;
2102 tx_skb->mapping = mapping;
2103 tx_skb->size = size;
2104 tx_skb->mapped_as_page = true;
2105
2106 len -= size;
2107 offset += size;
2108 count++;
2109 tx_head++;
2110 }
2111 }
2112
2113 /* Should never happen */
2114 if (unlikely(!tx_skb)) {
2115 netdev_err(bp->dev, "BUG! empty skb!\n");
2116 return 0;
2117 }
2118
2119 /* This is the last buffer of the frame: save socket buffer */
2120 tx_skb->skb = skb;
2121
2122 /* Update TX ring: update buffer descriptors in reverse order
2123 * to avoid race condition
2124 */
2125
2126 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2127 * to set the end of TX queue
2128 */
2129 i = tx_head;
2130 entry = macb_tx_ring_wrap(bp, i);
2131 ctrl = MACB_BIT(TX_USED);
2132 desc = macb_tx_desc(queue, entry);
2133 desc->ctrl = ctrl;
2134
2135 if (lso_ctrl) {
2136 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2137 /* include header and FCS in value given to h/w */
2138 mss_mfs = skb_shinfo(skb)->gso_size +
2139 skb_transport_offset(skb) +
2140 ETH_FCS_LEN;
2141 else /* TSO */ {
2142 mss_mfs = skb_shinfo(skb)->gso_size;
2143 /* TCP Sequence Number Source Select
2144 * can be set only for TSO
2145 */
2146 seq_ctrl = 0;
2147 }
2148 }
2149
2150 do {
2151 i--;
2152 entry = macb_tx_ring_wrap(bp, i);
2153 tx_skb = &queue->tx_skb[entry];
2154 desc = macb_tx_desc(queue, entry);
2155
2156 ctrl = (u32)tx_skb->size;
2157 if (eof) {
2158 ctrl |= MACB_BIT(TX_LAST);
2159 eof = 0;
2160 }
2161 if (unlikely(entry == (bp->tx_ring_size - 1)))
2162 ctrl |= MACB_BIT(TX_WRAP);
2163
2164 /* First descriptor is header descriptor */
2165 if (i == queue->tx_head) {
2166 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2167 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2168 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2169 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
2170 !ptp_one_step_sync(skb))
2171 ctrl |= MACB_BIT(TX_NOCRC);
2172 } else
2173 /* Only set MSS/MFS on payload descriptors
2174 * (second or later descriptor)
2175 */
2176 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2177
2178 /* Set TX buffer descriptor */
2179 macb_set_addr(bp, desc, tx_skb->mapping);
2180 /* desc->addr must be visible to hardware before clearing
2181 * 'TX_USED' bit in desc->ctrl.
2182 */
2183 wmb();
2184 desc->ctrl = ctrl;
2185 } while (i != queue->tx_head);
2186
2187 queue->tx_head = tx_head;
2188
2189 return count;
2190
2191 dma_error:
2192 netdev_err(bp->dev, "TX DMA map failed\n");
2193
2194 for (i = queue->tx_head; i != tx_head; i++) {
2195 tx_skb = macb_tx_skb(queue, i);
2196
2197 macb_tx_unmap(bp, tx_skb, 0);
2198 }
2199
2200 return 0;
2201 }
2202
macb_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2203 static netdev_features_t macb_features_check(struct sk_buff *skb,
2204 struct net_device *dev,
2205 netdev_features_t features)
2206 {
2207 unsigned int nr_frags, f;
2208 unsigned int hdrlen;
2209
2210 /* Validate LSO compatibility */
2211
2212 /* there is only one buffer or protocol is not UDP */
2213 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2214 return features;
2215
2216 /* length of header */
2217 hdrlen = skb_transport_offset(skb);
2218
2219 /* For UFO only:
2220 * When software supplies two or more payload buffers all payload buffers
2221 * apart from the last must be a multiple of 8 bytes in size.
2222 */
2223 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2224 return features & ~MACB_NETIF_LSO;
2225
2226 nr_frags = skb_shinfo(skb)->nr_frags;
2227 /* No need to check last fragment */
2228 nr_frags--;
2229 for (f = 0; f < nr_frags; f++) {
2230 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2231
2232 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2233 return features & ~MACB_NETIF_LSO;
2234 }
2235 return features;
2236 }
2237
macb_clear_csum(struct sk_buff * skb)2238 static inline int macb_clear_csum(struct sk_buff *skb)
2239 {
2240 /* no change for packets without checksum offloading */
2241 if (skb->ip_summed != CHECKSUM_PARTIAL)
2242 return 0;
2243
2244 /* make sure we can modify the header */
2245 if (unlikely(skb_cow_head(skb, 0)))
2246 return -1;
2247
2248 /* initialize checksum field
2249 * This is required - at least for Zynq, which otherwise calculates
2250 * wrong UDP header checksums for UDP packets with UDP data len <=2
2251 */
2252 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2253 return 0;
2254 }
2255
macb_pad_and_fcs(struct sk_buff ** skb,struct net_device * ndev)2256 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2257 {
2258 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2259 skb_is_nonlinear(*skb);
2260 int padlen = ETH_ZLEN - (*skb)->len;
2261 int tailroom = skb_tailroom(*skb);
2262 struct sk_buff *nskb;
2263 u32 fcs;
2264
2265 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2266 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2267 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb))
2268 return 0;
2269
2270 if (padlen <= 0) {
2271 /* FCS could be appeded to tailroom. */
2272 if (tailroom >= ETH_FCS_LEN)
2273 goto add_fcs;
2274 /* No room for FCS, need to reallocate skb. */
2275 else
2276 padlen = ETH_FCS_LEN;
2277 } else {
2278 /* Add room for FCS. */
2279 padlen += ETH_FCS_LEN;
2280 }
2281
2282 if (cloned || tailroom < padlen) {
2283 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2284 if (!nskb)
2285 return -ENOMEM;
2286
2287 dev_consume_skb_any(*skb);
2288 *skb = nskb;
2289 }
2290
2291 if (padlen > ETH_FCS_LEN)
2292 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2293
2294 add_fcs:
2295 /* set FCS to packet */
2296 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2297 fcs = ~fcs;
2298
2299 skb_put_u8(*skb, fcs & 0xff);
2300 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2301 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2302 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2303
2304 return 0;
2305 }
2306
macb_start_xmit(struct sk_buff * skb,struct net_device * dev)2307 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2308 {
2309 u16 queue_index = skb_get_queue_mapping(skb);
2310 struct macb *bp = netdev_priv(dev);
2311 struct macb_queue *queue = &bp->queues[queue_index];
2312 unsigned int desc_cnt, nr_frags, frag_size, f;
2313 unsigned int hdrlen;
2314 bool is_lso;
2315 netdev_tx_t ret = NETDEV_TX_OK;
2316
2317 if (macb_clear_csum(skb)) {
2318 dev_kfree_skb_any(skb);
2319 return ret;
2320 }
2321
2322 if (macb_pad_and_fcs(&skb, dev)) {
2323 dev_kfree_skb_any(skb);
2324 return ret;
2325 }
2326
2327 #ifdef CONFIG_MACB_USE_HWSTAMP
2328 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2329 (bp->hw_dma_cap & HW_DMA_CAP_PTP))
2330 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2331 #endif
2332
2333 is_lso = (skb_shinfo(skb)->gso_size != 0);
2334
2335 if (is_lso) {
2336 /* length of headers */
2337 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2338 /* only queue eth + ip headers separately for UDP */
2339 hdrlen = skb_transport_offset(skb);
2340 else
2341 hdrlen = skb_tcp_all_headers(skb);
2342 if (skb_headlen(skb) < hdrlen) {
2343 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2344 /* if this is required, would need to copy to single buffer */
2345 return NETDEV_TX_BUSY;
2346 }
2347 } else
2348 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2349
2350 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2351 netdev_vdbg(bp->dev,
2352 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2353 queue_index, skb->len, skb->head, skb->data,
2354 skb_tail_pointer(skb), skb_end_pointer(skb));
2355 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2356 skb->data, 16, true);
2357 #endif
2358
2359 /* Count how many TX buffer descriptors are needed to send this
2360 * socket buffer: skb fragments of jumbo frames may need to be
2361 * split into many buffer descriptors.
2362 */
2363 if (is_lso && (skb_headlen(skb) > hdrlen))
2364 /* extra header descriptor if also payload in first buffer */
2365 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2366 else
2367 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2368 nr_frags = skb_shinfo(skb)->nr_frags;
2369 for (f = 0; f < nr_frags; f++) {
2370 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2371 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2372 }
2373
2374 spin_lock_bh(&queue->tx_ptr_lock);
2375
2376 /* This is a hard error, log it. */
2377 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2378 bp->tx_ring_size) < desc_cnt) {
2379 netif_stop_subqueue(dev, queue_index);
2380 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2381 queue->tx_head, queue->tx_tail);
2382 ret = NETDEV_TX_BUSY;
2383 goto unlock;
2384 }
2385
2386 /* Map socket buffer for DMA transfer */
2387 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2388 dev_kfree_skb_any(skb);
2389 goto unlock;
2390 }
2391
2392 /* Make newly initialized descriptor visible to hardware */
2393 wmb();
2394 skb_tx_timestamp(skb);
2395
2396 spin_lock_irq(&bp->lock);
2397 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2398 spin_unlock_irq(&bp->lock);
2399
2400 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2401 netif_stop_subqueue(dev, queue_index);
2402
2403 unlock:
2404 spin_unlock_bh(&queue->tx_ptr_lock);
2405
2406 return ret;
2407 }
2408
macb_init_rx_buffer_size(struct macb * bp,size_t size)2409 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2410 {
2411 if (!macb_is_gem(bp)) {
2412 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2413 } else {
2414 bp->rx_buffer_size = size;
2415
2416 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2417 netdev_dbg(bp->dev,
2418 "RX buffer must be multiple of %d bytes, expanding\n",
2419 RX_BUFFER_MULTIPLE);
2420 bp->rx_buffer_size =
2421 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2422 }
2423 }
2424
2425 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2426 bp->dev->mtu, bp->rx_buffer_size);
2427 }
2428
gem_free_rx_buffers(struct macb * bp)2429 static void gem_free_rx_buffers(struct macb *bp)
2430 {
2431 struct sk_buff *skb;
2432 struct macb_dma_desc *desc;
2433 struct macb_queue *queue;
2434 dma_addr_t addr;
2435 unsigned int q;
2436 int i;
2437
2438 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2439 if (!queue->rx_skbuff)
2440 continue;
2441
2442 for (i = 0; i < bp->rx_ring_size; i++) {
2443 skb = queue->rx_skbuff[i];
2444
2445 if (!skb)
2446 continue;
2447
2448 desc = macb_rx_desc(queue, i);
2449 addr = macb_get_addr(bp, desc);
2450
2451 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2452 DMA_FROM_DEVICE);
2453 dev_kfree_skb_any(skb);
2454 skb = NULL;
2455 }
2456
2457 kfree(queue->rx_skbuff);
2458 queue->rx_skbuff = NULL;
2459 }
2460 }
2461
macb_free_rx_buffers(struct macb * bp)2462 static void macb_free_rx_buffers(struct macb *bp)
2463 {
2464 struct macb_queue *queue = &bp->queues[0];
2465
2466 if (queue->rx_buffers) {
2467 dma_free_coherent(&bp->pdev->dev,
2468 bp->rx_ring_size * bp->rx_buffer_size,
2469 queue->rx_buffers, queue->rx_buffers_dma);
2470 queue->rx_buffers = NULL;
2471 }
2472 }
2473
macb_free_consistent(struct macb * bp)2474 static void macb_free_consistent(struct macb *bp)
2475 {
2476 struct macb_queue *queue;
2477 unsigned int q;
2478 int size;
2479
2480 if (bp->rx_ring_tieoff) {
2481 dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp),
2482 bp->rx_ring_tieoff, bp->rx_ring_tieoff_dma);
2483 bp->rx_ring_tieoff = NULL;
2484 }
2485
2486 bp->macbgem_ops.mog_free_rx_buffers(bp);
2487
2488 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2489 kfree(queue->tx_skb);
2490 queue->tx_skb = NULL;
2491 if (queue->tx_ring) {
2492 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2493 dma_free_coherent(&bp->pdev->dev, size,
2494 queue->tx_ring, queue->tx_ring_dma);
2495 queue->tx_ring = NULL;
2496 }
2497 if (queue->rx_ring) {
2498 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2499 dma_free_coherent(&bp->pdev->dev, size,
2500 queue->rx_ring, queue->rx_ring_dma);
2501 queue->rx_ring = NULL;
2502 }
2503 }
2504 }
2505
gem_alloc_rx_buffers(struct macb * bp)2506 static int gem_alloc_rx_buffers(struct macb *bp)
2507 {
2508 struct macb_queue *queue;
2509 unsigned int q;
2510 int size;
2511
2512 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2513 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2514 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2515 if (!queue->rx_skbuff)
2516 return -ENOMEM;
2517 else
2518 netdev_dbg(bp->dev,
2519 "Allocated %d RX struct sk_buff entries at %p\n",
2520 bp->rx_ring_size, queue->rx_skbuff);
2521 }
2522 return 0;
2523 }
2524
macb_alloc_rx_buffers(struct macb * bp)2525 static int macb_alloc_rx_buffers(struct macb *bp)
2526 {
2527 struct macb_queue *queue = &bp->queues[0];
2528 int size;
2529
2530 size = bp->rx_ring_size * bp->rx_buffer_size;
2531 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2532 &queue->rx_buffers_dma, GFP_KERNEL);
2533 if (!queue->rx_buffers)
2534 return -ENOMEM;
2535
2536 netdev_dbg(bp->dev,
2537 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2538 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2539 return 0;
2540 }
2541
macb_alloc_consistent(struct macb * bp)2542 static int macb_alloc_consistent(struct macb *bp)
2543 {
2544 struct macb_queue *queue;
2545 unsigned int q;
2546 int size;
2547
2548 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2549 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2550 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2551 &queue->tx_ring_dma,
2552 GFP_KERNEL);
2553 if (!queue->tx_ring)
2554 goto out_err;
2555 netdev_dbg(bp->dev,
2556 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2557 q, size, (unsigned long)queue->tx_ring_dma,
2558 queue->tx_ring);
2559
2560 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2561 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2562 if (!queue->tx_skb)
2563 goto out_err;
2564
2565 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2566 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2567 &queue->rx_ring_dma, GFP_KERNEL);
2568 if (!queue->rx_ring)
2569 goto out_err;
2570 netdev_dbg(bp->dev,
2571 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2572 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2573 }
2574 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2575 goto out_err;
2576
2577 /* Required for tie off descriptor for PM cases */
2578 if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) {
2579 bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev,
2580 macb_dma_desc_get_size(bp),
2581 &bp->rx_ring_tieoff_dma,
2582 GFP_KERNEL);
2583 if (!bp->rx_ring_tieoff)
2584 goto out_err;
2585 }
2586
2587 return 0;
2588
2589 out_err:
2590 macb_free_consistent(bp);
2591 return -ENOMEM;
2592 }
2593
macb_init_tieoff(struct macb * bp)2594 static void macb_init_tieoff(struct macb *bp)
2595 {
2596 struct macb_dma_desc *desc = bp->rx_ring_tieoff;
2597
2598 if (bp->caps & MACB_CAPS_QUEUE_DISABLE)
2599 return;
2600 /* Setup a wrapping descriptor with no free slots
2601 * (WRAP and USED) to tie off/disable unused RX queues.
2602 */
2603 macb_set_addr(bp, desc, MACB_BIT(RX_WRAP) | MACB_BIT(RX_USED));
2604 desc->ctrl = 0;
2605 }
2606
gem_init_rings(struct macb * bp)2607 static void gem_init_rings(struct macb *bp)
2608 {
2609 struct macb_queue *queue;
2610 struct macb_dma_desc *desc = NULL;
2611 unsigned int q;
2612 int i;
2613
2614 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2615 for (i = 0; i < bp->tx_ring_size; i++) {
2616 desc = macb_tx_desc(queue, i);
2617 macb_set_addr(bp, desc, 0);
2618 desc->ctrl = MACB_BIT(TX_USED);
2619 }
2620 desc->ctrl |= MACB_BIT(TX_WRAP);
2621 queue->tx_head = 0;
2622 queue->tx_tail = 0;
2623
2624 queue->rx_tail = 0;
2625 queue->rx_prepared_head = 0;
2626
2627 gem_rx_refill(queue);
2628 }
2629
2630 macb_init_tieoff(bp);
2631 }
2632
macb_init_rings(struct macb * bp)2633 static void macb_init_rings(struct macb *bp)
2634 {
2635 int i;
2636 struct macb_dma_desc *desc = NULL;
2637
2638 macb_init_rx_ring(&bp->queues[0]);
2639
2640 for (i = 0; i < bp->tx_ring_size; i++) {
2641 desc = macb_tx_desc(&bp->queues[0], i);
2642 macb_set_addr(bp, desc, 0);
2643 desc->ctrl = MACB_BIT(TX_USED);
2644 }
2645 bp->queues[0].tx_head = 0;
2646 bp->queues[0].tx_tail = 0;
2647 desc->ctrl |= MACB_BIT(TX_WRAP);
2648
2649 macb_init_tieoff(bp);
2650 }
2651
macb_reset_hw(struct macb * bp)2652 static void macb_reset_hw(struct macb *bp)
2653 {
2654 struct macb_queue *queue;
2655 unsigned int q;
2656 u32 ctrl = macb_readl(bp, NCR);
2657
2658 /* Disable RX and TX (XXX: Should we halt the transmission
2659 * more gracefully?)
2660 */
2661 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2662
2663 /* Clear the stats registers (XXX: Update stats first?) */
2664 ctrl |= MACB_BIT(CLRSTAT);
2665
2666 macb_writel(bp, NCR, ctrl);
2667
2668 /* Clear all status flags */
2669 macb_writel(bp, TSR, -1);
2670 macb_writel(bp, RSR, -1);
2671
2672 /* Disable RX partial store and forward and reset watermark value */
2673 gem_writel(bp, PBUFRXCUT, 0);
2674
2675 /* Disable all interrupts */
2676 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2677 queue_writel(queue, IDR, -1);
2678 queue_readl(queue, ISR);
2679 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2680 queue_writel(queue, ISR, -1);
2681 }
2682 }
2683
gem_mdc_clk_div(struct macb * bp)2684 static u32 gem_mdc_clk_div(struct macb *bp)
2685 {
2686 u32 config;
2687 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2688
2689 if (pclk_hz <= 20000000)
2690 config = GEM_BF(CLK, GEM_CLK_DIV8);
2691 else if (pclk_hz <= 40000000)
2692 config = GEM_BF(CLK, GEM_CLK_DIV16);
2693 else if (pclk_hz <= 80000000)
2694 config = GEM_BF(CLK, GEM_CLK_DIV32);
2695 else if (pclk_hz <= 120000000)
2696 config = GEM_BF(CLK, GEM_CLK_DIV48);
2697 else if (pclk_hz <= 160000000)
2698 config = GEM_BF(CLK, GEM_CLK_DIV64);
2699 else if (pclk_hz <= 240000000)
2700 config = GEM_BF(CLK, GEM_CLK_DIV96);
2701 else if (pclk_hz <= 320000000)
2702 config = GEM_BF(CLK, GEM_CLK_DIV128);
2703 else
2704 config = GEM_BF(CLK, GEM_CLK_DIV224);
2705
2706 return config;
2707 }
2708
macb_mdc_clk_div(struct macb * bp)2709 static u32 macb_mdc_clk_div(struct macb *bp)
2710 {
2711 u32 config;
2712 unsigned long pclk_hz;
2713
2714 if (macb_is_gem(bp))
2715 return gem_mdc_clk_div(bp);
2716
2717 pclk_hz = clk_get_rate(bp->pclk);
2718 if (pclk_hz <= 20000000)
2719 config = MACB_BF(CLK, MACB_CLK_DIV8);
2720 else if (pclk_hz <= 40000000)
2721 config = MACB_BF(CLK, MACB_CLK_DIV16);
2722 else if (pclk_hz <= 80000000)
2723 config = MACB_BF(CLK, MACB_CLK_DIV32);
2724 else
2725 config = MACB_BF(CLK, MACB_CLK_DIV64);
2726
2727 return config;
2728 }
2729
2730 /* Get the DMA bus width field of the network configuration register that we
2731 * should program. We find the width from decoding the design configuration
2732 * register to find the maximum supported data bus width.
2733 */
macb_dbw(struct macb * bp)2734 static u32 macb_dbw(struct macb *bp)
2735 {
2736 if (!macb_is_gem(bp))
2737 return 0;
2738
2739 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2740 case 4:
2741 return GEM_BF(DBW, GEM_DBW128);
2742 case 2:
2743 return GEM_BF(DBW, GEM_DBW64);
2744 case 1:
2745 default:
2746 return GEM_BF(DBW, GEM_DBW32);
2747 }
2748 }
2749
2750 /* Configure the receive DMA engine
2751 * - use the correct receive buffer size
2752 * - set best burst length for DMA operations
2753 * (if not supported by FIFO, it will fallback to default)
2754 * - set both rx/tx packet buffers to full memory size
2755 * These are configurable parameters for GEM.
2756 */
macb_configure_dma(struct macb * bp)2757 static void macb_configure_dma(struct macb *bp)
2758 {
2759 struct macb_queue *queue;
2760 u32 buffer_size;
2761 unsigned int q;
2762 u32 dmacfg;
2763
2764 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2765 if (macb_is_gem(bp)) {
2766 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2767 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2768 if (q)
2769 queue_writel(queue, RBQS, buffer_size);
2770 else
2771 dmacfg |= GEM_BF(RXBS, buffer_size);
2772 }
2773 if (bp->dma_burst_length)
2774 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2775 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2776 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2777
2778 if (bp->native_io)
2779 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2780 else
2781 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2782
2783 if (bp->dev->features & NETIF_F_HW_CSUM)
2784 dmacfg |= GEM_BIT(TXCOEN);
2785 else
2786 dmacfg &= ~GEM_BIT(TXCOEN);
2787
2788 dmacfg &= ~GEM_BIT(ADDR64);
2789 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2790 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2791 dmacfg |= GEM_BIT(ADDR64);
2792 #endif
2793 #ifdef CONFIG_MACB_USE_HWSTAMP
2794 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2795 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2796 #endif
2797 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2798 dmacfg);
2799 gem_writel(bp, DMACFG, dmacfg);
2800 }
2801 }
2802
macb_init_hw(struct macb * bp)2803 static void macb_init_hw(struct macb *bp)
2804 {
2805 u32 config;
2806
2807 macb_reset_hw(bp);
2808 macb_set_hwaddr(bp);
2809
2810 config = macb_mdc_clk_div(bp);
2811 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2812 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2813 if (bp->caps & MACB_CAPS_JUMBO)
2814 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2815 else
2816 config |= MACB_BIT(BIG); /* Receive oversized frames */
2817 if (bp->dev->flags & IFF_PROMISC)
2818 config |= MACB_BIT(CAF); /* Copy All Frames */
2819 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2820 config |= GEM_BIT(RXCOEN);
2821 if (!(bp->dev->flags & IFF_BROADCAST))
2822 config |= MACB_BIT(NBC); /* No BroadCast */
2823 config |= macb_dbw(bp);
2824 macb_writel(bp, NCFGR, config);
2825 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2826 gem_writel(bp, JML, bp->jumbo_max_len);
2827 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2828 if (bp->caps & MACB_CAPS_JUMBO)
2829 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2830
2831 macb_configure_dma(bp);
2832
2833 /* Enable RX partial store and forward and set watermark */
2834 if (bp->rx_watermark)
2835 gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
2836 }
2837
2838 /* The hash address register is 64 bits long and takes up two
2839 * locations in the memory map. The least significant bits are stored
2840 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2841 *
2842 * The unicast hash enable and the multicast hash enable bits in the
2843 * network configuration register enable the reception of hash matched
2844 * frames. The destination address is reduced to a 6 bit index into
2845 * the 64 bit hash register using the following hash function. The
2846 * hash function is an exclusive or of every sixth bit of the
2847 * destination address.
2848 *
2849 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2850 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2851 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2852 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2853 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2854 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2855 *
2856 * da[0] represents the least significant bit of the first byte
2857 * received, that is, the multicast/unicast indicator, and da[47]
2858 * represents the most significant bit of the last byte received. If
2859 * the hash index, hi[n], points to a bit that is set in the hash
2860 * register then the frame will be matched according to whether the
2861 * frame is multicast or unicast. A multicast match will be signalled
2862 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2863 * index points to a bit set in the hash register. A unicast match
2864 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2865 * and the hash index points to a bit set in the hash register. To
2866 * receive all multicast frames, the hash register should be set with
2867 * all ones and the multicast hash enable bit should be set in the
2868 * network configuration register.
2869 */
2870
hash_bit_value(int bitnr,__u8 * addr)2871 static inline int hash_bit_value(int bitnr, __u8 *addr)
2872 {
2873 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2874 return 1;
2875 return 0;
2876 }
2877
2878 /* Return the hash index value for the specified address. */
hash_get_index(__u8 * addr)2879 static int hash_get_index(__u8 *addr)
2880 {
2881 int i, j, bitval;
2882 int hash_index = 0;
2883
2884 for (j = 0; j < 6; j++) {
2885 for (i = 0, bitval = 0; i < 8; i++)
2886 bitval ^= hash_bit_value(i * 6 + j, addr);
2887
2888 hash_index |= (bitval << j);
2889 }
2890
2891 return hash_index;
2892 }
2893
2894 /* Add multicast addresses to the internal multicast-hash table. */
macb_sethashtable(struct net_device * dev)2895 static void macb_sethashtable(struct net_device *dev)
2896 {
2897 struct netdev_hw_addr *ha;
2898 unsigned long mc_filter[2];
2899 unsigned int bitnr;
2900 struct macb *bp = netdev_priv(dev);
2901
2902 mc_filter[0] = 0;
2903 mc_filter[1] = 0;
2904
2905 netdev_for_each_mc_addr(ha, dev) {
2906 bitnr = hash_get_index(ha->addr);
2907 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2908 }
2909
2910 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2911 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2912 }
2913
2914 /* Enable/Disable promiscuous and multicast modes. */
macb_set_rx_mode(struct net_device * dev)2915 static void macb_set_rx_mode(struct net_device *dev)
2916 {
2917 unsigned long cfg;
2918 struct macb *bp = netdev_priv(dev);
2919
2920 cfg = macb_readl(bp, NCFGR);
2921
2922 if (dev->flags & IFF_PROMISC) {
2923 /* Enable promiscuous mode */
2924 cfg |= MACB_BIT(CAF);
2925
2926 /* Disable RX checksum offload */
2927 if (macb_is_gem(bp))
2928 cfg &= ~GEM_BIT(RXCOEN);
2929 } else {
2930 /* Disable promiscuous mode */
2931 cfg &= ~MACB_BIT(CAF);
2932
2933 /* Enable RX checksum offload only if requested */
2934 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2935 cfg |= GEM_BIT(RXCOEN);
2936 }
2937
2938 if (dev->flags & IFF_ALLMULTI) {
2939 /* Enable all multicast mode */
2940 macb_or_gem_writel(bp, HRB, -1);
2941 macb_or_gem_writel(bp, HRT, -1);
2942 cfg |= MACB_BIT(NCFGR_MTI);
2943 } else if (!netdev_mc_empty(dev)) {
2944 /* Enable specific multicasts */
2945 macb_sethashtable(dev);
2946 cfg |= MACB_BIT(NCFGR_MTI);
2947 } else if (dev->flags & (~IFF_ALLMULTI)) {
2948 /* Disable all multicast mode */
2949 macb_or_gem_writel(bp, HRB, 0);
2950 macb_or_gem_writel(bp, HRT, 0);
2951 cfg &= ~MACB_BIT(NCFGR_MTI);
2952 }
2953
2954 macb_writel(bp, NCFGR, cfg);
2955 }
2956
macb_open(struct net_device * dev)2957 static int macb_open(struct net_device *dev)
2958 {
2959 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2960 struct macb *bp = netdev_priv(dev);
2961 struct macb_queue *queue;
2962 unsigned int q;
2963 int err;
2964
2965 netdev_dbg(bp->dev, "open\n");
2966
2967 err = pm_runtime_resume_and_get(&bp->pdev->dev);
2968 if (err < 0)
2969 return err;
2970
2971 /* RX buffers initialization */
2972 macb_init_rx_buffer_size(bp, bufsz);
2973
2974 err = macb_alloc_consistent(bp);
2975 if (err) {
2976 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2977 err);
2978 goto pm_exit;
2979 }
2980
2981 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2982 napi_enable(&queue->napi_rx);
2983 napi_enable(&queue->napi_tx);
2984 }
2985
2986 macb_init_hw(bp);
2987
2988 err = phy_power_on(bp->sgmii_phy);
2989 if (err)
2990 goto reset_hw;
2991
2992 err = macb_phylink_connect(bp);
2993 if (err)
2994 goto phy_off;
2995
2996 netif_tx_start_all_queues(dev);
2997
2998 if (bp->ptp_info)
2999 bp->ptp_info->ptp_init(dev);
3000
3001 return 0;
3002
3003 phy_off:
3004 phy_power_off(bp->sgmii_phy);
3005
3006 reset_hw:
3007 macb_reset_hw(bp);
3008 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3009 napi_disable(&queue->napi_rx);
3010 napi_disable(&queue->napi_tx);
3011 }
3012 macb_free_consistent(bp);
3013 pm_exit:
3014 pm_runtime_put_sync(&bp->pdev->dev);
3015 return err;
3016 }
3017
macb_close(struct net_device * dev)3018 static int macb_close(struct net_device *dev)
3019 {
3020 struct macb *bp = netdev_priv(dev);
3021 struct macb_queue *queue;
3022 unsigned long flags;
3023 unsigned int q;
3024
3025 netif_tx_stop_all_queues(dev);
3026
3027 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3028 napi_disable(&queue->napi_rx);
3029 napi_disable(&queue->napi_tx);
3030 }
3031
3032 phylink_stop(bp->phylink);
3033 phylink_disconnect_phy(bp->phylink);
3034
3035 phy_power_off(bp->sgmii_phy);
3036
3037 spin_lock_irqsave(&bp->lock, flags);
3038 macb_reset_hw(bp);
3039 netif_carrier_off(dev);
3040 spin_unlock_irqrestore(&bp->lock, flags);
3041
3042 macb_free_consistent(bp);
3043
3044 if (bp->ptp_info)
3045 bp->ptp_info->ptp_remove(dev);
3046
3047 pm_runtime_put(&bp->pdev->dev);
3048
3049 return 0;
3050 }
3051
macb_change_mtu(struct net_device * dev,int new_mtu)3052 static int macb_change_mtu(struct net_device *dev, int new_mtu)
3053 {
3054 if (netif_running(dev))
3055 return -EBUSY;
3056
3057 WRITE_ONCE(dev->mtu, new_mtu);
3058
3059 return 0;
3060 }
3061
macb_set_mac_addr(struct net_device * dev,void * addr)3062 static int macb_set_mac_addr(struct net_device *dev, void *addr)
3063 {
3064 int err;
3065
3066 err = eth_mac_addr(dev, addr);
3067 if (err < 0)
3068 return err;
3069
3070 macb_set_hwaddr(netdev_priv(dev));
3071 return 0;
3072 }
3073
gem_update_stats(struct macb * bp)3074 static void gem_update_stats(struct macb *bp)
3075 {
3076 struct macb_queue *queue;
3077 unsigned int i, q, idx;
3078 unsigned long *stat;
3079
3080 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
3081
3082 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
3083 u32 offset = gem_statistics[i].offset;
3084 u64 val = bp->macb_reg_readl(bp, offset);
3085
3086 bp->ethtool_stats[i] += val;
3087 *p += val;
3088
3089 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
3090 /* Add GEM_OCTTXH, GEM_OCTRXH */
3091 val = bp->macb_reg_readl(bp, offset + 4);
3092 bp->ethtool_stats[i] += ((u64)val) << 32;
3093 *(++p) += val;
3094 }
3095 }
3096
3097 idx = GEM_STATS_LEN;
3098 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
3099 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
3100 bp->ethtool_stats[idx++] = *stat;
3101 }
3102
gem_get_stats(struct macb * bp)3103 static struct net_device_stats *gem_get_stats(struct macb *bp)
3104 {
3105 struct gem_stats *hwstat = &bp->hw_stats.gem;
3106 struct net_device_stats *nstat = &bp->dev->stats;
3107
3108 if (!netif_running(bp->dev))
3109 return nstat;
3110
3111 gem_update_stats(bp);
3112
3113 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
3114 hwstat->rx_alignment_errors +
3115 hwstat->rx_resource_errors +
3116 hwstat->rx_overruns +
3117 hwstat->rx_oversize_frames +
3118 hwstat->rx_jabbers +
3119 hwstat->rx_undersized_frames +
3120 hwstat->rx_length_field_frame_errors);
3121 nstat->tx_errors = (hwstat->tx_late_collisions +
3122 hwstat->tx_excessive_collisions +
3123 hwstat->tx_underrun +
3124 hwstat->tx_carrier_sense_errors);
3125 nstat->multicast = hwstat->rx_multicast_frames;
3126 nstat->collisions = (hwstat->tx_single_collision_frames +
3127 hwstat->tx_multiple_collision_frames +
3128 hwstat->tx_excessive_collisions);
3129 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3130 hwstat->rx_jabbers +
3131 hwstat->rx_undersized_frames +
3132 hwstat->rx_length_field_frame_errors);
3133 nstat->rx_over_errors = hwstat->rx_resource_errors;
3134 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3135 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3136 nstat->rx_fifo_errors = hwstat->rx_overruns;
3137 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3138 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3139 nstat->tx_fifo_errors = hwstat->tx_underrun;
3140
3141 return nstat;
3142 }
3143
gem_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)3144 static void gem_get_ethtool_stats(struct net_device *dev,
3145 struct ethtool_stats *stats, u64 *data)
3146 {
3147 struct macb *bp;
3148
3149 bp = netdev_priv(dev);
3150 gem_update_stats(bp);
3151 memcpy(data, &bp->ethtool_stats, sizeof(u64)
3152 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3153 }
3154
gem_get_sset_count(struct net_device * dev,int sset)3155 static int gem_get_sset_count(struct net_device *dev, int sset)
3156 {
3157 struct macb *bp = netdev_priv(dev);
3158
3159 switch (sset) {
3160 case ETH_SS_STATS:
3161 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3162 default:
3163 return -EOPNOTSUPP;
3164 }
3165 }
3166
gem_get_ethtool_strings(struct net_device * dev,u32 sset,u8 * p)3167 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3168 {
3169 char stat_string[ETH_GSTRING_LEN];
3170 struct macb *bp = netdev_priv(dev);
3171 struct macb_queue *queue;
3172 unsigned int i;
3173 unsigned int q;
3174
3175 switch (sset) {
3176 case ETH_SS_STATS:
3177 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3178 memcpy(p, gem_statistics[i].stat_string,
3179 ETH_GSTRING_LEN);
3180
3181 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3182 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3183 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
3184 q, queue_statistics[i].stat_string);
3185 memcpy(p, stat_string, ETH_GSTRING_LEN);
3186 }
3187 }
3188 break;
3189 }
3190 }
3191
macb_get_stats(struct net_device * dev)3192 static struct net_device_stats *macb_get_stats(struct net_device *dev)
3193 {
3194 struct macb *bp = netdev_priv(dev);
3195 struct net_device_stats *nstat = &bp->dev->stats;
3196 struct macb_stats *hwstat = &bp->hw_stats.macb;
3197
3198 if (macb_is_gem(bp))
3199 return gem_get_stats(bp);
3200
3201 /* read stats from hardware */
3202 macb_update_stats(bp);
3203
3204 /* Convert HW stats into netdevice stats */
3205 nstat->rx_errors = (hwstat->rx_fcs_errors +
3206 hwstat->rx_align_errors +
3207 hwstat->rx_resource_errors +
3208 hwstat->rx_overruns +
3209 hwstat->rx_oversize_pkts +
3210 hwstat->rx_jabbers +
3211 hwstat->rx_undersize_pkts +
3212 hwstat->rx_length_mismatch);
3213 nstat->tx_errors = (hwstat->tx_late_cols +
3214 hwstat->tx_excessive_cols +
3215 hwstat->tx_underruns +
3216 hwstat->tx_carrier_errors +
3217 hwstat->sqe_test_errors);
3218 nstat->collisions = (hwstat->tx_single_cols +
3219 hwstat->tx_multiple_cols +
3220 hwstat->tx_excessive_cols);
3221 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3222 hwstat->rx_jabbers +
3223 hwstat->rx_undersize_pkts +
3224 hwstat->rx_length_mismatch);
3225 nstat->rx_over_errors = hwstat->rx_resource_errors +
3226 hwstat->rx_overruns;
3227 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3228 nstat->rx_frame_errors = hwstat->rx_align_errors;
3229 nstat->rx_fifo_errors = hwstat->rx_overruns;
3230 /* XXX: What does "missed" mean? */
3231 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3232 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3233 nstat->tx_fifo_errors = hwstat->tx_underruns;
3234 /* Don't know about heartbeat or window errors... */
3235
3236 return nstat;
3237 }
3238
macb_get_regs_len(struct net_device * netdev)3239 static int macb_get_regs_len(struct net_device *netdev)
3240 {
3241 return MACB_GREGS_NBR * sizeof(u32);
3242 }
3243
macb_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)3244 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3245 void *p)
3246 {
3247 struct macb *bp = netdev_priv(dev);
3248 unsigned int tail, head;
3249 u32 *regs_buff = p;
3250
3251 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3252 | MACB_GREGS_VERSION;
3253
3254 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3255 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3256
3257 regs_buff[0] = macb_readl(bp, NCR);
3258 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3259 regs_buff[2] = macb_readl(bp, NSR);
3260 regs_buff[3] = macb_readl(bp, TSR);
3261 regs_buff[4] = macb_readl(bp, RBQP);
3262 regs_buff[5] = macb_readl(bp, TBQP);
3263 regs_buff[6] = macb_readl(bp, RSR);
3264 regs_buff[7] = macb_readl(bp, IMR);
3265
3266 regs_buff[8] = tail;
3267 regs_buff[9] = head;
3268 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3269 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3270
3271 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3272 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3273 if (macb_is_gem(bp))
3274 regs_buff[13] = gem_readl(bp, DMACFG);
3275 }
3276
macb_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)3277 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3278 {
3279 struct macb *bp = netdev_priv(netdev);
3280
3281 phylink_ethtool_get_wol(bp->phylink, wol);
3282 wol->supported |= (WAKE_MAGIC | WAKE_ARP);
3283
3284 /* Add macb wolopts to phy wolopts */
3285 wol->wolopts |= bp->wolopts;
3286 }
3287
macb_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)3288 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3289 {
3290 struct macb *bp = netdev_priv(netdev);
3291 int ret;
3292
3293 /* Pass the order to phylink layer */
3294 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3295 /* Don't manage WoL on MAC, if PHY set_wol() fails */
3296 if (ret && ret != -EOPNOTSUPP)
3297 return ret;
3298
3299 bp->wolopts = (wol->wolopts & WAKE_MAGIC) ? WAKE_MAGIC : 0;
3300 bp->wolopts |= (wol->wolopts & WAKE_ARP) ? WAKE_ARP : 0;
3301 bp->wol = (wol->wolopts) ? MACB_WOL_ENABLED : 0;
3302
3303 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
3304
3305 return 0;
3306 }
3307
macb_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * kset)3308 static int macb_get_link_ksettings(struct net_device *netdev,
3309 struct ethtool_link_ksettings *kset)
3310 {
3311 struct macb *bp = netdev_priv(netdev);
3312
3313 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3314 }
3315
macb_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * kset)3316 static int macb_set_link_ksettings(struct net_device *netdev,
3317 const struct ethtool_link_ksettings *kset)
3318 {
3319 struct macb *bp = netdev_priv(netdev);
3320
3321 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3322 }
3323
macb_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)3324 static void macb_get_ringparam(struct net_device *netdev,
3325 struct ethtool_ringparam *ring,
3326 struct kernel_ethtool_ringparam *kernel_ring,
3327 struct netlink_ext_ack *extack)
3328 {
3329 struct macb *bp = netdev_priv(netdev);
3330
3331 ring->rx_max_pending = MAX_RX_RING_SIZE;
3332 ring->tx_max_pending = MAX_TX_RING_SIZE;
3333
3334 ring->rx_pending = bp->rx_ring_size;
3335 ring->tx_pending = bp->tx_ring_size;
3336 }
3337
macb_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)3338 static int macb_set_ringparam(struct net_device *netdev,
3339 struct ethtool_ringparam *ring,
3340 struct kernel_ethtool_ringparam *kernel_ring,
3341 struct netlink_ext_ack *extack)
3342 {
3343 struct macb *bp = netdev_priv(netdev);
3344 u32 new_rx_size, new_tx_size;
3345 unsigned int reset = 0;
3346
3347 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3348 return -EINVAL;
3349
3350 new_rx_size = clamp_t(u32, ring->rx_pending,
3351 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3352 new_rx_size = roundup_pow_of_two(new_rx_size);
3353
3354 new_tx_size = clamp_t(u32, ring->tx_pending,
3355 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3356 new_tx_size = roundup_pow_of_two(new_tx_size);
3357
3358 if ((new_tx_size == bp->tx_ring_size) &&
3359 (new_rx_size == bp->rx_ring_size)) {
3360 /* nothing to do */
3361 return 0;
3362 }
3363
3364 if (netif_running(bp->dev)) {
3365 reset = 1;
3366 macb_close(bp->dev);
3367 }
3368
3369 bp->rx_ring_size = new_rx_size;
3370 bp->tx_ring_size = new_tx_size;
3371
3372 if (reset)
3373 macb_open(bp->dev);
3374
3375 return 0;
3376 }
3377
3378 #ifdef CONFIG_MACB_USE_HWSTAMP
gem_get_tsu_rate(struct macb * bp)3379 static unsigned int gem_get_tsu_rate(struct macb *bp)
3380 {
3381 struct clk *tsu_clk;
3382 unsigned int tsu_rate;
3383
3384 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3385 if (!IS_ERR(tsu_clk))
3386 tsu_rate = clk_get_rate(tsu_clk);
3387 /* try pclk instead */
3388 else if (!IS_ERR(bp->pclk)) {
3389 tsu_clk = bp->pclk;
3390 tsu_rate = clk_get_rate(tsu_clk);
3391 } else
3392 return -ENOTSUPP;
3393 return tsu_rate;
3394 }
3395
gem_get_ptp_max_adj(void)3396 static s32 gem_get_ptp_max_adj(void)
3397 {
3398 return 64000000;
3399 }
3400
gem_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)3401 static int gem_get_ts_info(struct net_device *dev,
3402 struct kernel_ethtool_ts_info *info)
3403 {
3404 struct macb *bp = netdev_priv(dev);
3405
3406 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3407 ethtool_op_get_ts_info(dev, info);
3408 return 0;
3409 }
3410
3411 info->so_timestamping =
3412 SOF_TIMESTAMPING_TX_SOFTWARE |
3413 SOF_TIMESTAMPING_TX_HARDWARE |
3414 SOF_TIMESTAMPING_RX_HARDWARE |
3415 SOF_TIMESTAMPING_RAW_HARDWARE;
3416 info->tx_types =
3417 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3418 (1 << HWTSTAMP_TX_OFF) |
3419 (1 << HWTSTAMP_TX_ON);
3420 info->rx_filters =
3421 (1 << HWTSTAMP_FILTER_NONE) |
3422 (1 << HWTSTAMP_FILTER_ALL);
3423
3424 if (bp->ptp_clock)
3425 info->phc_index = ptp_clock_index(bp->ptp_clock);
3426
3427 return 0;
3428 }
3429
3430 static struct macb_ptp_info gem_ptp_info = {
3431 .ptp_init = gem_ptp_init,
3432 .ptp_remove = gem_ptp_remove,
3433 .get_ptp_max_adj = gem_get_ptp_max_adj,
3434 .get_tsu_rate = gem_get_tsu_rate,
3435 .get_ts_info = gem_get_ts_info,
3436 .get_hwtst = gem_get_hwtst,
3437 .set_hwtst = gem_set_hwtst,
3438 };
3439 #endif
3440
macb_get_ts_info(struct net_device * netdev,struct kernel_ethtool_ts_info * info)3441 static int macb_get_ts_info(struct net_device *netdev,
3442 struct kernel_ethtool_ts_info *info)
3443 {
3444 struct macb *bp = netdev_priv(netdev);
3445
3446 if (bp->ptp_info)
3447 return bp->ptp_info->get_ts_info(netdev, info);
3448
3449 return ethtool_op_get_ts_info(netdev, info);
3450 }
3451
gem_enable_flow_filters(struct macb * bp,bool enable)3452 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3453 {
3454 struct net_device *netdev = bp->dev;
3455 struct ethtool_rx_fs_item *item;
3456 u32 t2_scr;
3457 int num_t2_scr;
3458
3459 if (!(netdev->features & NETIF_F_NTUPLE))
3460 return;
3461
3462 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3463
3464 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3465 struct ethtool_rx_flow_spec *fs = &item->fs;
3466 struct ethtool_tcpip4_spec *tp4sp_m;
3467
3468 if (fs->location >= num_t2_scr)
3469 continue;
3470
3471 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3472
3473 /* enable/disable screener regs for the flow entry */
3474 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3475
3476 /* only enable fields with no masking */
3477 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3478
3479 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3480 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3481 else
3482 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3483
3484 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3485 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3486 else
3487 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3488
3489 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3490 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3491 else
3492 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3493
3494 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3495 }
3496 }
3497
gem_prog_cmp_regs(struct macb * bp,struct ethtool_rx_flow_spec * fs)3498 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3499 {
3500 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3501 uint16_t index = fs->location;
3502 u32 w0, w1, t2_scr;
3503 bool cmp_a = false;
3504 bool cmp_b = false;
3505 bool cmp_c = false;
3506
3507 if (!macb_is_gem(bp))
3508 return;
3509
3510 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3511 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3512
3513 /* ignore field if any masking set */
3514 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3515 /* 1st compare reg - IP source address */
3516 w0 = 0;
3517 w1 = 0;
3518 w0 = tp4sp_v->ip4src;
3519 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3520 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3521 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3522 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3523 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3524 cmp_a = true;
3525 }
3526
3527 /* ignore field if any masking set */
3528 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3529 /* 2nd compare reg - IP destination address */
3530 w0 = 0;
3531 w1 = 0;
3532 w0 = tp4sp_v->ip4dst;
3533 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3534 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3535 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3536 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3537 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3538 cmp_b = true;
3539 }
3540
3541 /* ignore both port fields if masking set in both */
3542 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3543 /* 3rd compare reg - source port, destination port */
3544 w0 = 0;
3545 w1 = 0;
3546 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3547 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3548 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3549 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3550 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3551 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3552 } else {
3553 /* only one port definition */
3554 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3555 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3556 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3557 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3558 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3559 } else { /* dst port */
3560 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3561 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3562 }
3563 }
3564 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3565 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3566 cmp_c = true;
3567 }
3568
3569 t2_scr = 0;
3570 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3571 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3572 if (cmp_a)
3573 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3574 if (cmp_b)
3575 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3576 if (cmp_c)
3577 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3578 gem_writel_n(bp, SCRT2, index, t2_scr);
3579 }
3580
gem_add_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3581 static int gem_add_flow_filter(struct net_device *netdev,
3582 struct ethtool_rxnfc *cmd)
3583 {
3584 struct macb *bp = netdev_priv(netdev);
3585 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3586 struct ethtool_rx_fs_item *item, *newfs;
3587 unsigned long flags;
3588 int ret = -EINVAL;
3589 bool added = false;
3590
3591 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3592 if (newfs == NULL)
3593 return -ENOMEM;
3594 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3595
3596 netdev_dbg(netdev,
3597 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3598 fs->flow_type, (int)fs->ring_cookie, fs->location,
3599 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3600 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3601 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3602 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3603
3604 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3605
3606 /* find correct place to add in list */
3607 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3608 if (item->fs.location > newfs->fs.location) {
3609 list_add_tail(&newfs->list, &item->list);
3610 added = true;
3611 break;
3612 } else if (item->fs.location == fs->location) {
3613 netdev_err(netdev, "Rule not added: location %d not free!\n",
3614 fs->location);
3615 ret = -EBUSY;
3616 goto err;
3617 }
3618 }
3619 if (!added)
3620 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3621
3622 gem_prog_cmp_regs(bp, fs);
3623 bp->rx_fs_list.count++;
3624 /* enable filtering if NTUPLE on */
3625 gem_enable_flow_filters(bp, 1);
3626
3627 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3628 return 0;
3629
3630 err:
3631 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3632 kfree(newfs);
3633 return ret;
3634 }
3635
gem_del_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3636 static int gem_del_flow_filter(struct net_device *netdev,
3637 struct ethtool_rxnfc *cmd)
3638 {
3639 struct macb *bp = netdev_priv(netdev);
3640 struct ethtool_rx_fs_item *item;
3641 struct ethtool_rx_flow_spec *fs;
3642 unsigned long flags;
3643
3644 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3645
3646 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3647 if (item->fs.location == cmd->fs.location) {
3648 /* disable screener regs for the flow entry */
3649 fs = &(item->fs);
3650 netdev_dbg(netdev,
3651 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3652 fs->flow_type, (int)fs->ring_cookie, fs->location,
3653 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3654 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3655 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3656 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3657
3658 gem_writel_n(bp, SCRT2, fs->location, 0);
3659
3660 list_del(&item->list);
3661 bp->rx_fs_list.count--;
3662 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3663 kfree(item);
3664 return 0;
3665 }
3666 }
3667
3668 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3669 return -EINVAL;
3670 }
3671
gem_get_flow_entry(struct net_device * netdev,struct ethtool_rxnfc * cmd)3672 static int gem_get_flow_entry(struct net_device *netdev,
3673 struct ethtool_rxnfc *cmd)
3674 {
3675 struct macb *bp = netdev_priv(netdev);
3676 struct ethtool_rx_fs_item *item;
3677
3678 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3679 if (item->fs.location == cmd->fs.location) {
3680 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3681 return 0;
3682 }
3683 }
3684 return -EINVAL;
3685 }
3686
gem_get_all_flow_entries(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3687 static int gem_get_all_flow_entries(struct net_device *netdev,
3688 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3689 {
3690 struct macb *bp = netdev_priv(netdev);
3691 struct ethtool_rx_fs_item *item;
3692 uint32_t cnt = 0;
3693
3694 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3695 if (cnt == cmd->rule_cnt)
3696 return -EMSGSIZE;
3697 rule_locs[cnt] = item->fs.location;
3698 cnt++;
3699 }
3700 cmd->data = bp->max_tuples;
3701 cmd->rule_cnt = cnt;
3702
3703 return 0;
3704 }
3705
gem_get_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3706 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3707 u32 *rule_locs)
3708 {
3709 struct macb *bp = netdev_priv(netdev);
3710 int ret = 0;
3711
3712 switch (cmd->cmd) {
3713 case ETHTOOL_GRXRINGS:
3714 cmd->data = bp->num_queues;
3715 break;
3716 case ETHTOOL_GRXCLSRLCNT:
3717 cmd->rule_cnt = bp->rx_fs_list.count;
3718 break;
3719 case ETHTOOL_GRXCLSRULE:
3720 ret = gem_get_flow_entry(netdev, cmd);
3721 break;
3722 case ETHTOOL_GRXCLSRLALL:
3723 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3724 break;
3725 default:
3726 netdev_err(netdev,
3727 "Command parameter %d is not supported\n", cmd->cmd);
3728 ret = -EOPNOTSUPP;
3729 }
3730
3731 return ret;
3732 }
3733
gem_set_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd)3734 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3735 {
3736 struct macb *bp = netdev_priv(netdev);
3737 int ret;
3738
3739 switch (cmd->cmd) {
3740 case ETHTOOL_SRXCLSRLINS:
3741 if ((cmd->fs.location >= bp->max_tuples)
3742 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3743 ret = -EINVAL;
3744 break;
3745 }
3746 ret = gem_add_flow_filter(netdev, cmd);
3747 break;
3748 case ETHTOOL_SRXCLSRLDEL:
3749 ret = gem_del_flow_filter(netdev, cmd);
3750 break;
3751 default:
3752 netdev_err(netdev,
3753 "Command parameter %d is not supported\n", cmd->cmd);
3754 ret = -EOPNOTSUPP;
3755 }
3756
3757 return ret;
3758 }
3759
3760 static const struct ethtool_ops macb_ethtool_ops = {
3761 .get_regs_len = macb_get_regs_len,
3762 .get_regs = macb_get_regs,
3763 .get_link = ethtool_op_get_link,
3764 .get_ts_info = ethtool_op_get_ts_info,
3765 .get_wol = macb_get_wol,
3766 .set_wol = macb_set_wol,
3767 .get_link_ksettings = macb_get_link_ksettings,
3768 .set_link_ksettings = macb_set_link_ksettings,
3769 .get_ringparam = macb_get_ringparam,
3770 .set_ringparam = macb_set_ringparam,
3771 };
3772
3773 static const struct ethtool_ops gem_ethtool_ops = {
3774 .get_regs_len = macb_get_regs_len,
3775 .get_regs = macb_get_regs,
3776 .get_wol = macb_get_wol,
3777 .set_wol = macb_set_wol,
3778 .get_link = ethtool_op_get_link,
3779 .get_ts_info = macb_get_ts_info,
3780 .get_ethtool_stats = gem_get_ethtool_stats,
3781 .get_strings = gem_get_ethtool_strings,
3782 .get_sset_count = gem_get_sset_count,
3783 .get_link_ksettings = macb_get_link_ksettings,
3784 .set_link_ksettings = macb_set_link_ksettings,
3785 .get_ringparam = macb_get_ringparam,
3786 .set_ringparam = macb_set_ringparam,
3787 .get_rxnfc = gem_get_rxnfc,
3788 .set_rxnfc = gem_set_rxnfc,
3789 };
3790
macb_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)3791 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3792 {
3793 struct macb *bp = netdev_priv(dev);
3794
3795 if (!netif_running(dev))
3796 return -EINVAL;
3797
3798 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3799 }
3800
macb_hwtstamp_get(struct net_device * dev,struct kernel_hwtstamp_config * cfg)3801 static int macb_hwtstamp_get(struct net_device *dev,
3802 struct kernel_hwtstamp_config *cfg)
3803 {
3804 struct macb *bp = netdev_priv(dev);
3805
3806 if (!netif_running(dev))
3807 return -EINVAL;
3808
3809 if (!bp->ptp_info)
3810 return -EOPNOTSUPP;
3811
3812 return bp->ptp_info->get_hwtst(dev, cfg);
3813 }
3814
macb_hwtstamp_set(struct net_device * dev,struct kernel_hwtstamp_config * cfg,struct netlink_ext_ack * extack)3815 static int macb_hwtstamp_set(struct net_device *dev,
3816 struct kernel_hwtstamp_config *cfg,
3817 struct netlink_ext_ack *extack)
3818 {
3819 struct macb *bp = netdev_priv(dev);
3820
3821 if (!netif_running(dev))
3822 return -EINVAL;
3823
3824 if (!bp->ptp_info)
3825 return -EOPNOTSUPP;
3826
3827 return bp->ptp_info->set_hwtst(dev, cfg, extack);
3828 }
3829
macb_set_txcsum_feature(struct macb * bp,netdev_features_t features)3830 static inline void macb_set_txcsum_feature(struct macb *bp,
3831 netdev_features_t features)
3832 {
3833 u32 val;
3834
3835 if (!macb_is_gem(bp))
3836 return;
3837
3838 val = gem_readl(bp, DMACFG);
3839 if (features & NETIF_F_HW_CSUM)
3840 val |= GEM_BIT(TXCOEN);
3841 else
3842 val &= ~GEM_BIT(TXCOEN);
3843
3844 gem_writel(bp, DMACFG, val);
3845 }
3846
macb_set_rxcsum_feature(struct macb * bp,netdev_features_t features)3847 static inline void macb_set_rxcsum_feature(struct macb *bp,
3848 netdev_features_t features)
3849 {
3850 struct net_device *netdev = bp->dev;
3851 u32 val;
3852
3853 if (!macb_is_gem(bp))
3854 return;
3855
3856 val = gem_readl(bp, NCFGR);
3857 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3858 val |= GEM_BIT(RXCOEN);
3859 else
3860 val &= ~GEM_BIT(RXCOEN);
3861
3862 gem_writel(bp, NCFGR, val);
3863 }
3864
macb_set_rxflow_feature(struct macb * bp,netdev_features_t features)3865 static inline void macb_set_rxflow_feature(struct macb *bp,
3866 netdev_features_t features)
3867 {
3868 if (!macb_is_gem(bp))
3869 return;
3870
3871 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3872 }
3873
macb_set_features(struct net_device * netdev,netdev_features_t features)3874 static int macb_set_features(struct net_device *netdev,
3875 netdev_features_t features)
3876 {
3877 struct macb *bp = netdev_priv(netdev);
3878 netdev_features_t changed = features ^ netdev->features;
3879
3880 /* TX checksum offload */
3881 if (changed & NETIF_F_HW_CSUM)
3882 macb_set_txcsum_feature(bp, features);
3883
3884 /* RX checksum offload */
3885 if (changed & NETIF_F_RXCSUM)
3886 macb_set_rxcsum_feature(bp, features);
3887
3888 /* RX Flow Filters */
3889 if (changed & NETIF_F_NTUPLE)
3890 macb_set_rxflow_feature(bp, features);
3891
3892 return 0;
3893 }
3894
macb_restore_features(struct macb * bp)3895 static void macb_restore_features(struct macb *bp)
3896 {
3897 struct net_device *netdev = bp->dev;
3898 netdev_features_t features = netdev->features;
3899 struct ethtool_rx_fs_item *item;
3900
3901 /* TX checksum offload */
3902 macb_set_txcsum_feature(bp, features);
3903
3904 /* RX checksum offload */
3905 macb_set_rxcsum_feature(bp, features);
3906
3907 /* RX Flow Filters */
3908 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3909 gem_prog_cmp_regs(bp, &item->fs);
3910
3911 macb_set_rxflow_feature(bp, features);
3912 }
3913
3914 static const struct net_device_ops macb_netdev_ops = {
3915 .ndo_open = macb_open,
3916 .ndo_stop = macb_close,
3917 .ndo_start_xmit = macb_start_xmit,
3918 .ndo_set_rx_mode = macb_set_rx_mode,
3919 .ndo_get_stats = macb_get_stats,
3920 .ndo_eth_ioctl = macb_ioctl,
3921 .ndo_validate_addr = eth_validate_addr,
3922 .ndo_change_mtu = macb_change_mtu,
3923 .ndo_set_mac_address = macb_set_mac_addr,
3924 #ifdef CONFIG_NET_POLL_CONTROLLER
3925 .ndo_poll_controller = macb_poll_controller,
3926 #endif
3927 .ndo_set_features = macb_set_features,
3928 .ndo_features_check = macb_features_check,
3929 .ndo_hwtstamp_set = macb_hwtstamp_set,
3930 .ndo_hwtstamp_get = macb_hwtstamp_get,
3931 };
3932
3933 /* Configure peripheral capabilities according to device tree
3934 * and integration options used
3935 */
macb_configure_caps(struct macb * bp,const struct macb_config * dt_conf)3936 static void macb_configure_caps(struct macb *bp,
3937 const struct macb_config *dt_conf)
3938 {
3939 u32 dcfg;
3940
3941 if (dt_conf)
3942 bp->caps = dt_conf->caps;
3943
3944 if (hw_is_gem(bp->regs, bp->native_io)) {
3945 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3946
3947 dcfg = gem_readl(bp, DCFG1);
3948 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3949 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3950 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3951 bp->caps |= MACB_CAPS_PCS;
3952 dcfg = gem_readl(bp, DCFG12);
3953 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3954 bp->caps |= MACB_CAPS_HIGH_SPEED;
3955 dcfg = gem_readl(bp, DCFG2);
3956 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3957 bp->caps |= MACB_CAPS_FIFO_MODE;
3958 if (gem_has_ptp(bp)) {
3959 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3960 dev_err(&bp->pdev->dev,
3961 "GEM doesn't support hardware ptp.\n");
3962 else {
3963 #ifdef CONFIG_MACB_USE_HWSTAMP
3964 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3965 bp->ptp_info = &gem_ptp_info;
3966 #endif
3967 }
3968 }
3969 }
3970
3971 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3972 }
3973
macb_probe_queues(void __iomem * mem,bool native_io,unsigned int * queue_mask,unsigned int * num_queues)3974 static void macb_probe_queues(void __iomem *mem,
3975 bool native_io,
3976 unsigned int *queue_mask,
3977 unsigned int *num_queues)
3978 {
3979 *queue_mask = 0x1;
3980 *num_queues = 1;
3981
3982 /* is it macb or gem ?
3983 *
3984 * We need to read directly from the hardware here because
3985 * we are early in the probe process and don't have the
3986 * MACB_CAPS_MACB_IS_GEM flag positioned
3987 */
3988 if (!hw_is_gem(mem, native_io))
3989 return;
3990
3991 /* bit 0 is never set but queue 0 always exists */
3992 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3993 *num_queues = hweight32(*queue_mask);
3994 }
3995
macb_clks_disable(struct clk * pclk,struct clk * hclk,struct clk * tx_clk,struct clk * rx_clk,struct clk * tsu_clk)3996 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3997 struct clk *rx_clk, struct clk *tsu_clk)
3998 {
3999 struct clk_bulk_data clks[] = {
4000 { .clk = tsu_clk, },
4001 { .clk = rx_clk, },
4002 { .clk = pclk, },
4003 { .clk = hclk, },
4004 { .clk = tx_clk },
4005 };
4006
4007 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
4008 }
4009
macb_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4010 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
4011 struct clk **hclk, struct clk **tx_clk,
4012 struct clk **rx_clk, struct clk **tsu_clk)
4013 {
4014 struct macb_platform_data *pdata;
4015 int err;
4016
4017 pdata = dev_get_platdata(&pdev->dev);
4018 if (pdata) {
4019 *pclk = pdata->pclk;
4020 *hclk = pdata->hclk;
4021 } else {
4022 *pclk = devm_clk_get(&pdev->dev, "pclk");
4023 *hclk = devm_clk_get(&pdev->dev, "hclk");
4024 }
4025
4026 if (IS_ERR_OR_NULL(*pclk))
4027 return dev_err_probe(&pdev->dev,
4028 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
4029 "failed to get pclk\n");
4030
4031 if (IS_ERR_OR_NULL(*hclk))
4032 return dev_err_probe(&pdev->dev,
4033 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
4034 "failed to get hclk\n");
4035
4036 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
4037 if (IS_ERR(*tx_clk))
4038 return PTR_ERR(*tx_clk);
4039
4040 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
4041 if (IS_ERR(*rx_clk))
4042 return PTR_ERR(*rx_clk);
4043
4044 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
4045 if (IS_ERR(*tsu_clk))
4046 return PTR_ERR(*tsu_clk);
4047
4048 err = clk_prepare_enable(*pclk);
4049 if (err) {
4050 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4051 return err;
4052 }
4053
4054 err = clk_prepare_enable(*hclk);
4055 if (err) {
4056 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
4057 goto err_disable_pclk;
4058 }
4059
4060 err = clk_prepare_enable(*tx_clk);
4061 if (err) {
4062 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
4063 goto err_disable_hclk;
4064 }
4065
4066 err = clk_prepare_enable(*rx_clk);
4067 if (err) {
4068 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
4069 goto err_disable_txclk;
4070 }
4071
4072 err = clk_prepare_enable(*tsu_clk);
4073 if (err) {
4074 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
4075 goto err_disable_rxclk;
4076 }
4077
4078 return 0;
4079
4080 err_disable_rxclk:
4081 clk_disable_unprepare(*rx_clk);
4082
4083 err_disable_txclk:
4084 clk_disable_unprepare(*tx_clk);
4085
4086 err_disable_hclk:
4087 clk_disable_unprepare(*hclk);
4088
4089 err_disable_pclk:
4090 clk_disable_unprepare(*pclk);
4091
4092 return err;
4093 }
4094
macb_init(struct platform_device * pdev)4095 static int macb_init(struct platform_device *pdev)
4096 {
4097 struct net_device *dev = platform_get_drvdata(pdev);
4098 unsigned int hw_q, q;
4099 struct macb *bp = netdev_priv(dev);
4100 struct macb_queue *queue;
4101 int err;
4102 u32 val, reg;
4103
4104 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
4105 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
4106
4107 /* set the queue register mapping once for all: queue0 has a special
4108 * register mapping but we don't want to test the queue index then
4109 * compute the corresponding register offset at run time.
4110 */
4111 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
4112 if (!(bp->queue_mask & (1 << hw_q)))
4113 continue;
4114
4115 queue = &bp->queues[q];
4116 queue->bp = bp;
4117 spin_lock_init(&queue->tx_ptr_lock);
4118 netif_napi_add(dev, &queue->napi_rx, macb_rx_poll);
4119 netif_napi_add(dev, &queue->napi_tx, macb_tx_poll);
4120 if (hw_q) {
4121 queue->ISR = GEM_ISR(hw_q - 1);
4122 queue->IER = GEM_IER(hw_q - 1);
4123 queue->IDR = GEM_IDR(hw_q - 1);
4124 queue->IMR = GEM_IMR(hw_q - 1);
4125 queue->TBQP = GEM_TBQP(hw_q - 1);
4126 queue->RBQP = GEM_RBQP(hw_q - 1);
4127 queue->RBQS = GEM_RBQS(hw_q - 1);
4128 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4129 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4130 queue->TBQPH = GEM_TBQPH(hw_q - 1);
4131 queue->RBQPH = GEM_RBQPH(hw_q - 1);
4132 }
4133 #endif
4134 } else {
4135 /* queue0 uses legacy registers */
4136 queue->ISR = MACB_ISR;
4137 queue->IER = MACB_IER;
4138 queue->IDR = MACB_IDR;
4139 queue->IMR = MACB_IMR;
4140 queue->TBQP = MACB_TBQP;
4141 queue->RBQP = MACB_RBQP;
4142 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4143 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4144 queue->TBQPH = MACB_TBQPH;
4145 queue->RBQPH = MACB_RBQPH;
4146 }
4147 #endif
4148 }
4149
4150 /* get irq: here we use the linux queue index, not the hardware
4151 * queue index. the queue irq definitions in the device tree
4152 * must remove the optional gaps that could exist in the
4153 * hardware queue mask.
4154 */
4155 queue->irq = platform_get_irq(pdev, q);
4156 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
4157 IRQF_SHARED, dev->name, queue);
4158 if (err) {
4159 dev_err(&pdev->dev,
4160 "Unable to request IRQ %d (error %d)\n",
4161 queue->irq, err);
4162 return err;
4163 }
4164
4165 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4166 q++;
4167 }
4168
4169 dev->netdev_ops = &macb_netdev_ops;
4170
4171 /* setup appropriated routines according to adapter type */
4172 if (macb_is_gem(bp)) {
4173 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4174 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4175 bp->macbgem_ops.mog_init_rings = gem_init_rings;
4176 bp->macbgem_ops.mog_rx = gem_rx;
4177 dev->ethtool_ops = &gem_ethtool_ops;
4178 } else {
4179 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4180 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4181 bp->macbgem_ops.mog_init_rings = macb_init_rings;
4182 bp->macbgem_ops.mog_rx = macb_rx;
4183 dev->ethtool_ops = &macb_ethtool_ops;
4184 }
4185
4186 netdev_sw_irq_coalesce_default_on(dev);
4187
4188 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4189
4190 /* Set features */
4191 dev->hw_features = NETIF_F_SG;
4192
4193 /* Check LSO capability */
4194 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4195 dev->hw_features |= MACB_NETIF_LSO;
4196
4197 /* Checksum offload is only available on gem with packet buffer */
4198 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4199 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4200 if (bp->caps & MACB_CAPS_SG_DISABLED)
4201 dev->hw_features &= ~NETIF_F_SG;
4202 dev->features = dev->hw_features;
4203
4204 /* Check RX Flow Filters support.
4205 * Max Rx flows set by availability of screeners & compare regs:
4206 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4207 */
4208 reg = gem_readl(bp, DCFG8);
4209 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4210 GEM_BFEXT(T2SCR, reg));
4211 INIT_LIST_HEAD(&bp->rx_fs_list.list);
4212 if (bp->max_tuples > 0) {
4213 /* also needs one ethtype match to check IPv4 */
4214 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4215 /* program this reg now */
4216 reg = 0;
4217 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4218 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4219 /* Filtering is supported in hw but don't enable it in kernel now */
4220 dev->hw_features |= NETIF_F_NTUPLE;
4221 /* init Rx flow definitions */
4222 bp->rx_fs_list.count = 0;
4223 spin_lock_init(&bp->rx_fs_lock);
4224 } else
4225 bp->max_tuples = 0;
4226 }
4227
4228 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4229 val = 0;
4230 if (phy_interface_mode_is_rgmii(bp->phy_interface))
4231 val = bp->usrio->rgmii;
4232 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4233 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4234 val = bp->usrio->rmii;
4235 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4236 val = bp->usrio->mii;
4237
4238 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4239 val |= bp->usrio->refclk;
4240
4241 macb_or_gem_writel(bp, USRIO, val);
4242 }
4243
4244 /* Set MII management clock divider */
4245 val = macb_mdc_clk_div(bp);
4246 val |= macb_dbw(bp);
4247 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4248 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4249 macb_writel(bp, NCFGR, val);
4250
4251 return 0;
4252 }
4253
4254 static const struct macb_usrio_config macb_default_usrio = {
4255 .mii = MACB_BIT(MII),
4256 .rmii = MACB_BIT(RMII),
4257 .rgmii = GEM_BIT(RGMII),
4258 .refclk = MACB_BIT(CLKEN),
4259 };
4260
4261 #if defined(CONFIG_OF)
4262 /* 1518 rounded up */
4263 #define AT91ETHER_MAX_RBUFF_SZ 0x600
4264 /* max number of receive buffers */
4265 #define AT91ETHER_MAX_RX_DESCR 9
4266
4267 static struct sifive_fu540_macb_mgmt *mgmt;
4268
at91ether_alloc_coherent(struct macb * lp)4269 static int at91ether_alloc_coherent(struct macb *lp)
4270 {
4271 struct macb_queue *q = &lp->queues[0];
4272
4273 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4274 (AT91ETHER_MAX_RX_DESCR *
4275 macb_dma_desc_get_size(lp)),
4276 &q->rx_ring_dma, GFP_KERNEL);
4277 if (!q->rx_ring)
4278 return -ENOMEM;
4279
4280 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4281 AT91ETHER_MAX_RX_DESCR *
4282 AT91ETHER_MAX_RBUFF_SZ,
4283 &q->rx_buffers_dma, GFP_KERNEL);
4284 if (!q->rx_buffers) {
4285 dma_free_coherent(&lp->pdev->dev,
4286 AT91ETHER_MAX_RX_DESCR *
4287 macb_dma_desc_get_size(lp),
4288 q->rx_ring, q->rx_ring_dma);
4289 q->rx_ring = NULL;
4290 return -ENOMEM;
4291 }
4292
4293 return 0;
4294 }
4295
at91ether_free_coherent(struct macb * lp)4296 static void at91ether_free_coherent(struct macb *lp)
4297 {
4298 struct macb_queue *q = &lp->queues[0];
4299
4300 if (q->rx_ring) {
4301 dma_free_coherent(&lp->pdev->dev,
4302 AT91ETHER_MAX_RX_DESCR *
4303 macb_dma_desc_get_size(lp),
4304 q->rx_ring, q->rx_ring_dma);
4305 q->rx_ring = NULL;
4306 }
4307
4308 if (q->rx_buffers) {
4309 dma_free_coherent(&lp->pdev->dev,
4310 AT91ETHER_MAX_RX_DESCR *
4311 AT91ETHER_MAX_RBUFF_SZ,
4312 q->rx_buffers, q->rx_buffers_dma);
4313 q->rx_buffers = NULL;
4314 }
4315 }
4316
4317 /* Initialize and start the Receiver and Transmit subsystems */
at91ether_start(struct macb * lp)4318 static int at91ether_start(struct macb *lp)
4319 {
4320 struct macb_queue *q = &lp->queues[0];
4321 struct macb_dma_desc *desc;
4322 dma_addr_t addr;
4323 u32 ctl;
4324 int i, ret;
4325
4326 ret = at91ether_alloc_coherent(lp);
4327 if (ret)
4328 return ret;
4329
4330 addr = q->rx_buffers_dma;
4331 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4332 desc = macb_rx_desc(q, i);
4333 macb_set_addr(lp, desc, addr);
4334 desc->ctrl = 0;
4335 addr += AT91ETHER_MAX_RBUFF_SZ;
4336 }
4337
4338 /* Set the Wrap bit on the last descriptor */
4339 desc->addr |= MACB_BIT(RX_WRAP);
4340
4341 /* Reset buffer index */
4342 q->rx_tail = 0;
4343
4344 /* Program address of descriptor list in Rx Buffer Queue register */
4345 macb_writel(lp, RBQP, q->rx_ring_dma);
4346
4347 /* Enable Receive and Transmit */
4348 ctl = macb_readl(lp, NCR);
4349 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4350
4351 /* Enable MAC interrupts */
4352 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4353 MACB_BIT(RXUBR) |
4354 MACB_BIT(ISR_TUND) |
4355 MACB_BIT(ISR_RLE) |
4356 MACB_BIT(TCOMP) |
4357 MACB_BIT(ISR_ROVR) |
4358 MACB_BIT(HRESP));
4359
4360 return 0;
4361 }
4362
at91ether_stop(struct macb * lp)4363 static void at91ether_stop(struct macb *lp)
4364 {
4365 u32 ctl;
4366
4367 /* Disable MAC interrupts */
4368 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4369 MACB_BIT(RXUBR) |
4370 MACB_BIT(ISR_TUND) |
4371 MACB_BIT(ISR_RLE) |
4372 MACB_BIT(TCOMP) |
4373 MACB_BIT(ISR_ROVR) |
4374 MACB_BIT(HRESP));
4375
4376 /* Disable Receiver and Transmitter */
4377 ctl = macb_readl(lp, NCR);
4378 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4379
4380 /* Free resources. */
4381 at91ether_free_coherent(lp);
4382 }
4383
4384 /* Open the ethernet interface */
at91ether_open(struct net_device * dev)4385 static int at91ether_open(struct net_device *dev)
4386 {
4387 struct macb *lp = netdev_priv(dev);
4388 u32 ctl;
4389 int ret;
4390
4391 ret = pm_runtime_resume_and_get(&lp->pdev->dev);
4392 if (ret < 0)
4393 return ret;
4394
4395 /* Clear internal statistics */
4396 ctl = macb_readl(lp, NCR);
4397 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4398
4399 macb_set_hwaddr(lp);
4400
4401 ret = at91ether_start(lp);
4402 if (ret)
4403 goto pm_exit;
4404
4405 ret = macb_phylink_connect(lp);
4406 if (ret)
4407 goto stop;
4408
4409 netif_start_queue(dev);
4410
4411 return 0;
4412
4413 stop:
4414 at91ether_stop(lp);
4415 pm_exit:
4416 pm_runtime_put_sync(&lp->pdev->dev);
4417 return ret;
4418 }
4419
4420 /* Close the interface */
at91ether_close(struct net_device * dev)4421 static int at91ether_close(struct net_device *dev)
4422 {
4423 struct macb *lp = netdev_priv(dev);
4424
4425 netif_stop_queue(dev);
4426
4427 phylink_stop(lp->phylink);
4428 phylink_disconnect_phy(lp->phylink);
4429
4430 at91ether_stop(lp);
4431
4432 return pm_runtime_put(&lp->pdev->dev);
4433 }
4434
4435 /* Transmit packet */
at91ether_start_xmit(struct sk_buff * skb,struct net_device * dev)4436 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4437 struct net_device *dev)
4438 {
4439 struct macb *lp = netdev_priv(dev);
4440
4441 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4442 int desc = 0;
4443
4444 netif_stop_queue(dev);
4445
4446 /* Store packet information (to free when Tx completed) */
4447 lp->rm9200_txq[desc].skb = skb;
4448 lp->rm9200_txq[desc].size = skb->len;
4449 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4450 skb->len, DMA_TO_DEVICE);
4451 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4452 dev_kfree_skb_any(skb);
4453 dev->stats.tx_dropped++;
4454 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4455 return NETDEV_TX_OK;
4456 }
4457
4458 /* Set address of the data in the Transmit Address register */
4459 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4460 /* Set length of the packet in the Transmit Control register */
4461 macb_writel(lp, TCR, skb->len);
4462
4463 } else {
4464 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4465 return NETDEV_TX_BUSY;
4466 }
4467
4468 return NETDEV_TX_OK;
4469 }
4470
4471 /* Extract received frame from buffer descriptors and sent to upper layers.
4472 * (Called from interrupt context)
4473 */
at91ether_rx(struct net_device * dev)4474 static void at91ether_rx(struct net_device *dev)
4475 {
4476 struct macb *lp = netdev_priv(dev);
4477 struct macb_queue *q = &lp->queues[0];
4478 struct macb_dma_desc *desc;
4479 unsigned char *p_recv;
4480 struct sk_buff *skb;
4481 unsigned int pktlen;
4482
4483 desc = macb_rx_desc(q, q->rx_tail);
4484 while (desc->addr & MACB_BIT(RX_USED)) {
4485 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4486 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4487 skb = netdev_alloc_skb(dev, pktlen + 2);
4488 if (skb) {
4489 skb_reserve(skb, 2);
4490 skb_put_data(skb, p_recv, pktlen);
4491
4492 skb->protocol = eth_type_trans(skb, dev);
4493 dev->stats.rx_packets++;
4494 dev->stats.rx_bytes += pktlen;
4495 netif_rx(skb);
4496 } else {
4497 dev->stats.rx_dropped++;
4498 }
4499
4500 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4501 dev->stats.multicast++;
4502
4503 /* reset ownership bit */
4504 desc->addr &= ~MACB_BIT(RX_USED);
4505
4506 /* wrap after last buffer */
4507 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4508 q->rx_tail = 0;
4509 else
4510 q->rx_tail++;
4511
4512 desc = macb_rx_desc(q, q->rx_tail);
4513 }
4514 }
4515
4516 /* MAC interrupt handler */
at91ether_interrupt(int irq,void * dev_id)4517 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4518 {
4519 struct net_device *dev = dev_id;
4520 struct macb *lp = netdev_priv(dev);
4521 u32 intstatus, ctl;
4522 unsigned int desc;
4523
4524 /* MAC Interrupt Status register indicates what interrupts are pending.
4525 * It is automatically cleared once read.
4526 */
4527 intstatus = macb_readl(lp, ISR);
4528
4529 /* Receive complete */
4530 if (intstatus & MACB_BIT(RCOMP))
4531 at91ether_rx(dev);
4532
4533 /* Transmit complete */
4534 if (intstatus & MACB_BIT(TCOMP)) {
4535 /* The TCOM bit is set even if the transmission failed */
4536 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4537 dev->stats.tx_errors++;
4538
4539 desc = 0;
4540 if (lp->rm9200_txq[desc].skb) {
4541 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4542 lp->rm9200_txq[desc].skb = NULL;
4543 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4544 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4545 dev->stats.tx_packets++;
4546 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4547 }
4548 netif_wake_queue(dev);
4549 }
4550
4551 /* Work-around for EMAC Errata section 41.3.1 */
4552 if (intstatus & MACB_BIT(RXUBR)) {
4553 ctl = macb_readl(lp, NCR);
4554 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4555 wmb();
4556 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4557 }
4558
4559 if (intstatus & MACB_BIT(ISR_ROVR))
4560 netdev_err(dev, "ROVR error\n");
4561
4562 return IRQ_HANDLED;
4563 }
4564
4565 #ifdef CONFIG_NET_POLL_CONTROLLER
at91ether_poll_controller(struct net_device * dev)4566 static void at91ether_poll_controller(struct net_device *dev)
4567 {
4568 unsigned long flags;
4569
4570 local_irq_save(flags);
4571 at91ether_interrupt(dev->irq, dev);
4572 local_irq_restore(flags);
4573 }
4574 #endif
4575
4576 static const struct net_device_ops at91ether_netdev_ops = {
4577 .ndo_open = at91ether_open,
4578 .ndo_stop = at91ether_close,
4579 .ndo_start_xmit = at91ether_start_xmit,
4580 .ndo_get_stats = macb_get_stats,
4581 .ndo_set_rx_mode = macb_set_rx_mode,
4582 .ndo_set_mac_address = eth_mac_addr,
4583 .ndo_eth_ioctl = macb_ioctl,
4584 .ndo_validate_addr = eth_validate_addr,
4585 #ifdef CONFIG_NET_POLL_CONTROLLER
4586 .ndo_poll_controller = at91ether_poll_controller,
4587 #endif
4588 .ndo_hwtstamp_set = macb_hwtstamp_set,
4589 .ndo_hwtstamp_get = macb_hwtstamp_get,
4590 };
4591
at91ether_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4592 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4593 struct clk **hclk, struct clk **tx_clk,
4594 struct clk **rx_clk, struct clk **tsu_clk)
4595 {
4596 int err;
4597
4598 *hclk = NULL;
4599 *tx_clk = NULL;
4600 *rx_clk = NULL;
4601 *tsu_clk = NULL;
4602
4603 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4604 if (IS_ERR(*pclk))
4605 return PTR_ERR(*pclk);
4606
4607 err = clk_prepare_enable(*pclk);
4608 if (err) {
4609 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4610 return err;
4611 }
4612
4613 return 0;
4614 }
4615
at91ether_init(struct platform_device * pdev)4616 static int at91ether_init(struct platform_device *pdev)
4617 {
4618 struct net_device *dev = platform_get_drvdata(pdev);
4619 struct macb *bp = netdev_priv(dev);
4620 int err;
4621
4622 bp->queues[0].bp = bp;
4623
4624 dev->netdev_ops = &at91ether_netdev_ops;
4625 dev->ethtool_ops = &macb_ethtool_ops;
4626
4627 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4628 0, dev->name, dev);
4629 if (err)
4630 return err;
4631
4632 macb_writel(bp, NCR, 0);
4633
4634 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4635
4636 return 0;
4637 }
4638
fu540_macb_tx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)4639 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4640 unsigned long parent_rate)
4641 {
4642 return mgmt->rate;
4643 }
4644
fu540_macb_tx_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)4645 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4646 unsigned long *parent_rate)
4647 {
4648 if (WARN_ON(rate < 2500000))
4649 return 2500000;
4650 else if (rate == 2500000)
4651 return 2500000;
4652 else if (WARN_ON(rate < 13750000))
4653 return 2500000;
4654 else if (WARN_ON(rate < 25000000))
4655 return 25000000;
4656 else if (rate == 25000000)
4657 return 25000000;
4658 else if (WARN_ON(rate < 75000000))
4659 return 25000000;
4660 else if (WARN_ON(rate < 125000000))
4661 return 125000000;
4662 else if (rate == 125000000)
4663 return 125000000;
4664
4665 WARN_ON(rate > 125000000);
4666
4667 return 125000000;
4668 }
4669
fu540_macb_tx_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)4670 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4671 unsigned long parent_rate)
4672 {
4673 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4674 if (rate != 125000000)
4675 iowrite32(1, mgmt->reg);
4676 else
4677 iowrite32(0, mgmt->reg);
4678 mgmt->rate = rate;
4679
4680 return 0;
4681 }
4682
4683 static const struct clk_ops fu540_c000_ops = {
4684 .recalc_rate = fu540_macb_tx_recalc_rate,
4685 .round_rate = fu540_macb_tx_round_rate,
4686 .set_rate = fu540_macb_tx_set_rate,
4687 };
4688
fu540_c000_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4689 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4690 struct clk **hclk, struct clk **tx_clk,
4691 struct clk **rx_clk, struct clk **tsu_clk)
4692 {
4693 struct clk_init_data init;
4694 int err = 0;
4695
4696 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4697 if (err)
4698 return err;
4699
4700 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4701 if (!mgmt) {
4702 err = -ENOMEM;
4703 goto err_disable_clks;
4704 }
4705
4706 init.name = "sifive-gemgxl-mgmt";
4707 init.ops = &fu540_c000_ops;
4708 init.flags = 0;
4709 init.num_parents = 0;
4710
4711 mgmt->rate = 0;
4712 mgmt->hw.init = &init;
4713
4714 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4715 if (IS_ERR(*tx_clk)) {
4716 err = PTR_ERR(*tx_clk);
4717 goto err_disable_clks;
4718 }
4719
4720 err = clk_prepare_enable(*tx_clk);
4721 if (err) {
4722 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4723 *tx_clk = NULL;
4724 goto err_disable_clks;
4725 } else {
4726 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4727 }
4728
4729 return 0;
4730
4731 err_disable_clks:
4732 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4733
4734 return err;
4735 }
4736
fu540_c000_init(struct platform_device * pdev)4737 static int fu540_c000_init(struct platform_device *pdev)
4738 {
4739 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4740 if (IS_ERR(mgmt->reg))
4741 return PTR_ERR(mgmt->reg);
4742
4743 return macb_init(pdev);
4744 }
4745
init_reset_optional(struct platform_device * pdev)4746 static int init_reset_optional(struct platform_device *pdev)
4747 {
4748 struct net_device *dev = platform_get_drvdata(pdev);
4749 struct macb *bp = netdev_priv(dev);
4750 int ret;
4751
4752 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4753 /* Ensure PHY device used in SGMII mode is ready */
4754 bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
4755
4756 if (IS_ERR(bp->sgmii_phy))
4757 return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
4758 "failed to get SGMII PHY\n");
4759
4760 ret = phy_init(bp->sgmii_phy);
4761 if (ret)
4762 return dev_err_probe(&pdev->dev, ret,
4763 "failed to init SGMII PHY\n");
4764
4765 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG);
4766 if (!ret) {
4767 u32 pm_info[2];
4768
4769 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
4770 pm_info, ARRAY_SIZE(pm_info));
4771 if (ret) {
4772 dev_err(&pdev->dev, "Failed to read power management information\n");
4773 goto err_out_phy_exit;
4774 }
4775 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0);
4776 if (ret)
4777 goto err_out_phy_exit;
4778
4779 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1);
4780 if (ret)
4781 goto err_out_phy_exit;
4782 }
4783
4784 }
4785
4786 /* Fully reset controller at hardware level if mapped in device tree */
4787 ret = device_reset_optional(&pdev->dev);
4788 if (ret) {
4789 phy_exit(bp->sgmii_phy);
4790 return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
4791 }
4792
4793 ret = macb_init(pdev);
4794
4795 err_out_phy_exit:
4796 if (ret)
4797 phy_exit(bp->sgmii_phy);
4798
4799 return ret;
4800 }
4801
4802 static const struct macb_usrio_config sama7g5_usrio = {
4803 .mii = 0,
4804 .rmii = 1,
4805 .rgmii = 2,
4806 .refclk = BIT(2),
4807 .hdfctlen = BIT(6),
4808 };
4809
4810 static const struct macb_config fu540_c000_config = {
4811 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4812 MACB_CAPS_GEM_HAS_PTP,
4813 .dma_burst_length = 16,
4814 .clk_init = fu540_c000_clk_init,
4815 .init = fu540_c000_init,
4816 .jumbo_max_len = 10240,
4817 .usrio = &macb_default_usrio,
4818 };
4819
4820 static const struct macb_config at91sam9260_config = {
4821 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4822 .clk_init = macb_clk_init,
4823 .init = macb_init,
4824 .usrio = &macb_default_usrio,
4825 };
4826
4827 static const struct macb_config sama5d3macb_config = {
4828 .caps = MACB_CAPS_SG_DISABLED |
4829 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4830 .clk_init = macb_clk_init,
4831 .init = macb_init,
4832 .usrio = &macb_default_usrio,
4833 };
4834
4835 static const struct macb_config pc302gem_config = {
4836 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4837 .dma_burst_length = 16,
4838 .clk_init = macb_clk_init,
4839 .init = macb_init,
4840 .usrio = &macb_default_usrio,
4841 };
4842
4843 static const struct macb_config sama5d2_config = {
4844 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4845 .dma_burst_length = 16,
4846 .clk_init = macb_clk_init,
4847 .init = macb_init,
4848 .usrio = &macb_default_usrio,
4849 };
4850
4851 static const struct macb_config sama5d29_config = {
4852 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
4853 .dma_burst_length = 16,
4854 .clk_init = macb_clk_init,
4855 .init = macb_init,
4856 .usrio = &macb_default_usrio,
4857 };
4858
4859 static const struct macb_config sama5d3_config = {
4860 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4861 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4862 .dma_burst_length = 16,
4863 .clk_init = macb_clk_init,
4864 .init = macb_init,
4865 .jumbo_max_len = 10240,
4866 .usrio = &macb_default_usrio,
4867 };
4868
4869 static const struct macb_config sama5d4_config = {
4870 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4871 .dma_burst_length = 4,
4872 .clk_init = macb_clk_init,
4873 .init = macb_init,
4874 .usrio = &macb_default_usrio,
4875 };
4876
4877 static const struct macb_config emac_config = {
4878 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4879 .clk_init = at91ether_clk_init,
4880 .init = at91ether_init,
4881 .usrio = &macb_default_usrio,
4882 };
4883
4884 static const struct macb_config np4_config = {
4885 .caps = MACB_CAPS_USRIO_DISABLED,
4886 .clk_init = macb_clk_init,
4887 .init = macb_init,
4888 .usrio = &macb_default_usrio,
4889 };
4890
4891 static const struct macb_config zynqmp_config = {
4892 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4893 MACB_CAPS_JUMBO |
4894 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4895 .dma_burst_length = 16,
4896 .clk_init = macb_clk_init,
4897 .init = init_reset_optional,
4898 .jumbo_max_len = 10240,
4899 .usrio = &macb_default_usrio,
4900 };
4901
4902 static const struct macb_config zynq_config = {
4903 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4904 MACB_CAPS_NEEDS_RSTONUBR,
4905 .dma_burst_length = 16,
4906 .clk_init = macb_clk_init,
4907 .init = macb_init,
4908 .usrio = &macb_default_usrio,
4909 };
4910
4911 static const struct macb_config mpfs_config = {
4912 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4913 MACB_CAPS_JUMBO |
4914 MACB_CAPS_GEM_HAS_PTP,
4915 .dma_burst_length = 16,
4916 .clk_init = macb_clk_init,
4917 .init = init_reset_optional,
4918 .usrio = &macb_default_usrio,
4919 .max_tx_length = 4040, /* Cadence Erratum 1686 */
4920 .jumbo_max_len = 4040,
4921 };
4922
4923 static const struct macb_config sama7g5_gem_config = {
4924 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4925 MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP,
4926 .dma_burst_length = 16,
4927 .clk_init = macb_clk_init,
4928 .init = macb_init,
4929 .usrio = &sama7g5_usrio,
4930 };
4931
4932 static const struct macb_config sama7g5_emac_config = {
4933 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
4934 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII |
4935 MACB_CAPS_GEM_HAS_PTP,
4936 .dma_burst_length = 16,
4937 .clk_init = macb_clk_init,
4938 .init = macb_init,
4939 .usrio = &sama7g5_usrio,
4940 };
4941
4942 static const struct macb_config versal_config = {
4943 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4944 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK |
4945 MACB_CAPS_QUEUE_DISABLE,
4946 .dma_burst_length = 16,
4947 .clk_init = macb_clk_init,
4948 .init = init_reset_optional,
4949 .jumbo_max_len = 10240,
4950 .usrio = &macb_default_usrio,
4951 };
4952
4953 static const struct of_device_id macb_dt_ids[] = {
4954 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4955 { .compatible = "cdns,macb" },
4956 { .compatible = "cdns,np4-macb", .data = &np4_config },
4957 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4958 { .compatible = "cdns,gem", .data = &pc302gem_config },
4959 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4960 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4961 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4962 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4963 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4964 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4965 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4966 { .compatible = "cdns,emac", .data = &emac_config },
4967 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
4968 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
4969 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4970 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
4971 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4972 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4973 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
4974 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
4975 { .compatible = "xlnx,versal-gem", .data = &versal_config},
4976 { /* sentinel */ }
4977 };
4978 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4979 #endif /* CONFIG_OF */
4980
4981 static const struct macb_config default_gem_config = {
4982 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4983 MACB_CAPS_JUMBO |
4984 MACB_CAPS_GEM_HAS_PTP,
4985 .dma_burst_length = 16,
4986 .clk_init = macb_clk_init,
4987 .init = macb_init,
4988 .usrio = &macb_default_usrio,
4989 .jumbo_max_len = 10240,
4990 };
4991
macb_probe(struct platform_device * pdev)4992 static int macb_probe(struct platform_device *pdev)
4993 {
4994 const struct macb_config *macb_config = &default_gem_config;
4995 int (*clk_init)(struct platform_device *, struct clk **,
4996 struct clk **, struct clk **, struct clk **,
4997 struct clk **) = macb_config->clk_init;
4998 int (*init)(struct platform_device *) = macb_config->init;
4999 struct device_node *np = pdev->dev.of_node;
5000 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
5001 struct clk *tsu_clk = NULL;
5002 unsigned int queue_mask, num_queues;
5003 bool native_io;
5004 phy_interface_t interface;
5005 struct net_device *dev;
5006 struct resource *regs;
5007 u32 wtrmrk_rst_val;
5008 void __iomem *mem;
5009 struct macb *bp;
5010 int err, val;
5011
5012 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
5013 if (IS_ERR(mem))
5014 return PTR_ERR(mem);
5015
5016 if (np) {
5017 const struct of_device_id *match;
5018
5019 match = of_match_node(macb_dt_ids, np);
5020 if (match && match->data) {
5021 macb_config = match->data;
5022 clk_init = macb_config->clk_init;
5023 init = macb_config->init;
5024 }
5025 }
5026
5027 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
5028 if (err)
5029 return err;
5030
5031 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
5032 pm_runtime_use_autosuspend(&pdev->dev);
5033 pm_runtime_get_noresume(&pdev->dev);
5034 pm_runtime_set_active(&pdev->dev);
5035 pm_runtime_enable(&pdev->dev);
5036 native_io = hw_is_native_io(mem);
5037
5038 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
5039 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
5040 if (!dev) {
5041 err = -ENOMEM;
5042 goto err_disable_clocks;
5043 }
5044
5045 dev->base_addr = regs->start;
5046
5047 SET_NETDEV_DEV(dev, &pdev->dev);
5048
5049 bp = netdev_priv(dev);
5050 bp->pdev = pdev;
5051 bp->dev = dev;
5052 bp->regs = mem;
5053 bp->native_io = native_io;
5054 if (native_io) {
5055 bp->macb_reg_readl = hw_readl_native;
5056 bp->macb_reg_writel = hw_writel_native;
5057 } else {
5058 bp->macb_reg_readl = hw_readl;
5059 bp->macb_reg_writel = hw_writel;
5060 }
5061 bp->num_queues = num_queues;
5062 bp->queue_mask = queue_mask;
5063 if (macb_config)
5064 bp->dma_burst_length = macb_config->dma_burst_length;
5065 bp->pclk = pclk;
5066 bp->hclk = hclk;
5067 bp->tx_clk = tx_clk;
5068 bp->rx_clk = rx_clk;
5069 bp->tsu_clk = tsu_clk;
5070 if (macb_config)
5071 bp->jumbo_max_len = macb_config->jumbo_max_len;
5072
5073 if (!hw_is_gem(bp->regs, bp->native_io))
5074 bp->max_tx_length = MACB_MAX_TX_LEN;
5075 else if (macb_config->max_tx_length)
5076 bp->max_tx_length = macb_config->max_tx_length;
5077 else
5078 bp->max_tx_length = GEM_MAX_TX_LEN;
5079
5080 bp->wol = 0;
5081 device_set_wakeup_capable(&pdev->dev, 1);
5082
5083 bp->usrio = macb_config->usrio;
5084
5085 /* By default we set to partial store and forward mode for zynqmp.
5086 * Disable if not set in devicetree.
5087 */
5088 if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
5089 err = of_property_read_u32(bp->pdev->dev.of_node,
5090 "cdns,rx-watermark",
5091 &bp->rx_watermark);
5092
5093 if (!err) {
5094 /* Disable partial store and forward in case of error or
5095 * invalid watermark value
5096 */
5097 wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
5098 if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
5099 dev_info(&bp->pdev->dev, "Invalid watermark value\n");
5100 bp->rx_watermark = 0;
5101 }
5102 }
5103 }
5104 spin_lock_init(&bp->lock);
5105
5106 /* setup capabilities */
5107 macb_configure_caps(bp, macb_config);
5108
5109 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5110 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
5111 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
5112 bp->hw_dma_cap |= HW_DMA_CAP_64B;
5113 }
5114 #endif
5115 platform_set_drvdata(pdev, dev);
5116
5117 dev->irq = platform_get_irq(pdev, 0);
5118 if (dev->irq < 0) {
5119 err = dev->irq;
5120 goto err_out_free_netdev;
5121 }
5122
5123 /* MTU range: 68 - 1518 or 10240 */
5124 dev->min_mtu = GEM_MTU_MIN_SIZE;
5125 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
5126 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
5127 else
5128 dev->max_mtu = 1536 - ETH_HLEN - ETH_FCS_LEN;
5129
5130 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
5131 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
5132 if (val)
5133 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
5134 macb_dma_desc_get_size(bp);
5135
5136 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
5137 if (val)
5138 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
5139 macb_dma_desc_get_size(bp);
5140 }
5141
5142 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
5143 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
5144 bp->rx_intr_mask |= MACB_BIT(RXUBR);
5145
5146 err = of_get_ethdev_address(np, bp->dev);
5147 if (err == -EPROBE_DEFER)
5148 goto err_out_free_netdev;
5149 else if (err)
5150 macb_get_hwaddr(bp);
5151
5152 err = of_get_phy_mode(np, &interface);
5153 if (err)
5154 /* not found in DT, MII by default */
5155 bp->phy_interface = PHY_INTERFACE_MODE_MII;
5156 else
5157 bp->phy_interface = interface;
5158
5159 /* IP specific init */
5160 err = init(pdev);
5161 if (err)
5162 goto err_out_free_netdev;
5163
5164 err = macb_mii_init(bp);
5165 if (err)
5166 goto err_out_phy_exit;
5167
5168 netif_carrier_off(dev);
5169
5170 err = register_netdev(dev);
5171 if (err) {
5172 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5173 goto err_out_unregister_mdio;
5174 }
5175
5176 INIT_WORK(&bp->hresp_err_bh_work, macb_hresp_error_task);
5177
5178 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
5179 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
5180 dev->base_addr, dev->irq, dev->dev_addr);
5181
5182 pm_runtime_mark_last_busy(&bp->pdev->dev);
5183 pm_runtime_put_autosuspend(&bp->pdev->dev);
5184
5185 return 0;
5186
5187 err_out_unregister_mdio:
5188 mdiobus_unregister(bp->mii_bus);
5189 mdiobus_free(bp->mii_bus);
5190
5191 err_out_phy_exit:
5192 phy_exit(bp->sgmii_phy);
5193
5194 err_out_free_netdev:
5195 free_netdev(dev);
5196
5197 err_disable_clocks:
5198 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5199 pm_runtime_disable(&pdev->dev);
5200 pm_runtime_set_suspended(&pdev->dev);
5201 pm_runtime_dont_use_autosuspend(&pdev->dev);
5202
5203 return err;
5204 }
5205
macb_remove(struct platform_device * pdev)5206 static void macb_remove(struct platform_device *pdev)
5207 {
5208 struct net_device *dev;
5209 struct macb *bp;
5210
5211 dev = platform_get_drvdata(pdev);
5212
5213 if (dev) {
5214 bp = netdev_priv(dev);
5215 phy_exit(bp->sgmii_phy);
5216 mdiobus_unregister(bp->mii_bus);
5217 mdiobus_free(bp->mii_bus);
5218
5219 unregister_netdev(dev);
5220 cancel_work_sync(&bp->hresp_err_bh_work);
5221 pm_runtime_disable(&pdev->dev);
5222 pm_runtime_dont_use_autosuspend(&pdev->dev);
5223 if (!pm_runtime_suspended(&pdev->dev)) {
5224 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
5225 bp->rx_clk, bp->tsu_clk);
5226 pm_runtime_set_suspended(&pdev->dev);
5227 }
5228 phylink_destroy(bp->phylink);
5229 free_netdev(dev);
5230 }
5231 }
5232
macb_suspend(struct device * dev)5233 static int __maybe_unused macb_suspend(struct device *dev)
5234 {
5235 struct net_device *netdev = dev_get_drvdata(dev);
5236 struct macb *bp = netdev_priv(netdev);
5237 struct in_ifaddr *ifa = NULL;
5238 struct macb_queue *queue;
5239 struct in_device *idev;
5240 unsigned long flags;
5241 unsigned int q;
5242 int err;
5243 u32 tmp;
5244
5245 if (!device_may_wakeup(&bp->dev->dev))
5246 phy_exit(bp->sgmii_phy);
5247
5248 if (!netif_running(netdev))
5249 return 0;
5250
5251 if (bp->wol & MACB_WOL_ENABLED) {
5252 /* Check for IP address in WOL ARP mode */
5253 idev = __in_dev_get_rcu(bp->dev);
5254 if (idev)
5255 ifa = rcu_dereference(idev->ifa_list);
5256 if ((bp->wolopts & WAKE_ARP) && !ifa) {
5257 netdev_err(netdev, "IP address not assigned as required by WoL walk ARP\n");
5258 return -EOPNOTSUPP;
5259 }
5260 spin_lock_irqsave(&bp->lock, flags);
5261
5262 /* Disable Tx and Rx engines before disabling the queues,
5263 * this is mandatory as per the IP spec sheet
5264 */
5265 tmp = macb_readl(bp, NCR);
5266 macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE)));
5267 for (q = 0, queue = bp->queues; q < bp->num_queues;
5268 ++q, ++queue) {
5269 /* Disable RX queues */
5270 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) {
5271 queue_writel(queue, RBQP, MACB_BIT(QUEUE_DISABLE));
5272 } else {
5273 /* Tie off RX queues */
5274 queue_writel(queue, RBQP,
5275 lower_32_bits(bp->rx_ring_tieoff_dma));
5276 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5277 queue_writel(queue, RBQPH,
5278 upper_32_bits(bp->rx_ring_tieoff_dma));
5279 #endif
5280 }
5281 /* Disable all interrupts */
5282 queue_writel(queue, IDR, -1);
5283 queue_readl(queue, ISR);
5284 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5285 queue_writel(queue, ISR, -1);
5286 }
5287 /* Enable Receive engine */
5288 macb_writel(bp, NCR, tmp | MACB_BIT(RE));
5289 /* Flush all status bits */
5290 macb_writel(bp, TSR, -1);
5291 macb_writel(bp, RSR, -1);
5292
5293 tmp = (bp->wolopts & WAKE_MAGIC) ? MACB_BIT(MAG) : 0;
5294 if (bp->wolopts & WAKE_ARP) {
5295 tmp |= MACB_BIT(ARP);
5296 /* write IP address into register */
5297 tmp |= MACB_BFEXT(IP, be32_to_cpu(ifa->ifa_local));
5298 }
5299
5300 /* Change interrupt handler and
5301 * Enable WoL IRQ on queue 0
5302 */
5303 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5304 if (macb_is_gem(bp)) {
5305 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
5306 IRQF_SHARED, netdev->name, bp->queues);
5307 if (err) {
5308 dev_err(dev,
5309 "Unable to request IRQ %d (error %d)\n",
5310 bp->queues[0].irq, err);
5311 spin_unlock_irqrestore(&bp->lock, flags);
5312 return err;
5313 }
5314 queue_writel(bp->queues, IER, GEM_BIT(WOL));
5315 gem_writel(bp, WOL, tmp);
5316 } else {
5317 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
5318 IRQF_SHARED, netdev->name, bp->queues);
5319 if (err) {
5320 dev_err(dev,
5321 "Unable to request IRQ %d (error %d)\n",
5322 bp->queues[0].irq, err);
5323 spin_unlock_irqrestore(&bp->lock, flags);
5324 return err;
5325 }
5326 queue_writel(bp->queues, IER, MACB_BIT(WOL));
5327 macb_writel(bp, WOL, tmp);
5328 }
5329 spin_unlock_irqrestore(&bp->lock, flags);
5330
5331 enable_irq_wake(bp->queues[0].irq);
5332 }
5333
5334 netif_device_detach(netdev);
5335 for (q = 0, queue = bp->queues; q < bp->num_queues;
5336 ++q, ++queue) {
5337 napi_disable(&queue->napi_rx);
5338 napi_disable(&queue->napi_tx);
5339 }
5340
5341 if (!(bp->wol & MACB_WOL_ENABLED)) {
5342 rtnl_lock();
5343 phylink_stop(bp->phylink);
5344 rtnl_unlock();
5345 spin_lock_irqsave(&bp->lock, flags);
5346 macb_reset_hw(bp);
5347 spin_unlock_irqrestore(&bp->lock, flags);
5348 }
5349
5350 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5351 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5352
5353 if (netdev->hw_features & NETIF_F_NTUPLE)
5354 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5355
5356 if (bp->ptp_info)
5357 bp->ptp_info->ptp_remove(netdev);
5358 if (!device_may_wakeup(dev))
5359 pm_runtime_force_suspend(dev);
5360
5361 return 0;
5362 }
5363
macb_resume(struct device * dev)5364 static int __maybe_unused macb_resume(struct device *dev)
5365 {
5366 struct net_device *netdev = dev_get_drvdata(dev);
5367 struct macb *bp = netdev_priv(netdev);
5368 struct macb_queue *queue;
5369 unsigned long flags;
5370 unsigned int q;
5371 int err;
5372
5373 if (!device_may_wakeup(&bp->dev->dev))
5374 phy_init(bp->sgmii_phy);
5375
5376 if (!netif_running(netdev))
5377 return 0;
5378
5379 if (!device_may_wakeup(dev))
5380 pm_runtime_force_resume(dev);
5381
5382 if (bp->wol & MACB_WOL_ENABLED) {
5383 spin_lock_irqsave(&bp->lock, flags);
5384 /* Disable WoL */
5385 if (macb_is_gem(bp)) {
5386 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5387 gem_writel(bp, WOL, 0);
5388 } else {
5389 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5390 macb_writel(bp, WOL, 0);
5391 }
5392 /* Clear ISR on queue 0 */
5393 queue_readl(bp->queues, ISR);
5394 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5395 queue_writel(bp->queues, ISR, -1);
5396 /* Replace interrupt handler on queue 0 */
5397 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5398 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5399 IRQF_SHARED, netdev->name, bp->queues);
5400 if (err) {
5401 dev_err(dev,
5402 "Unable to request IRQ %d (error %d)\n",
5403 bp->queues[0].irq, err);
5404 spin_unlock_irqrestore(&bp->lock, flags);
5405 return err;
5406 }
5407 spin_unlock_irqrestore(&bp->lock, flags);
5408
5409 disable_irq_wake(bp->queues[0].irq);
5410
5411 /* Now make sure we disable phy before moving
5412 * to common restore path
5413 */
5414 rtnl_lock();
5415 phylink_stop(bp->phylink);
5416 rtnl_unlock();
5417 }
5418
5419 for (q = 0, queue = bp->queues; q < bp->num_queues;
5420 ++q, ++queue) {
5421 napi_enable(&queue->napi_rx);
5422 napi_enable(&queue->napi_tx);
5423 }
5424
5425 if (netdev->hw_features & NETIF_F_NTUPLE)
5426 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5427
5428 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5429 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5430
5431 macb_writel(bp, NCR, MACB_BIT(MPE));
5432 macb_init_hw(bp);
5433 macb_set_rx_mode(netdev);
5434 macb_restore_features(bp);
5435 rtnl_lock();
5436
5437 phylink_start(bp->phylink);
5438 rtnl_unlock();
5439
5440 netif_device_attach(netdev);
5441 if (bp->ptp_info)
5442 bp->ptp_info->ptp_init(netdev);
5443
5444 return 0;
5445 }
5446
macb_runtime_suspend(struct device * dev)5447 static int __maybe_unused macb_runtime_suspend(struct device *dev)
5448 {
5449 struct net_device *netdev = dev_get_drvdata(dev);
5450 struct macb *bp = netdev_priv(netdev);
5451
5452 if (!(device_may_wakeup(dev)))
5453 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5454 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
5455 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5456
5457 return 0;
5458 }
5459
macb_runtime_resume(struct device * dev)5460 static int __maybe_unused macb_runtime_resume(struct device *dev)
5461 {
5462 struct net_device *netdev = dev_get_drvdata(dev);
5463 struct macb *bp = netdev_priv(netdev);
5464
5465 if (!(device_may_wakeup(dev))) {
5466 clk_prepare_enable(bp->pclk);
5467 clk_prepare_enable(bp->hclk);
5468 clk_prepare_enable(bp->tx_clk);
5469 clk_prepare_enable(bp->rx_clk);
5470 clk_prepare_enable(bp->tsu_clk);
5471 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
5472 clk_prepare_enable(bp->tsu_clk);
5473 }
5474
5475 return 0;
5476 }
5477
5478 static const struct dev_pm_ops macb_pm_ops = {
5479 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5480 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5481 };
5482
5483 static struct platform_driver macb_driver = {
5484 .probe = macb_probe,
5485 .remove_new = macb_remove,
5486 .driver = {
5487 .name = "macb",
5488 .of_match_table = of_match_ptr(macb_dt_ids),
5489 .pm = &macb_pm_ops,
5490 },
5491 };
5492
5493 module_platform_driver(macb_driver);
5494
5495 MODULE_LICENSE("GPL");
5496 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5497 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5498 MODULE_ALIAS("platform:macb");
5499